1 /* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90 /*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105 #include <sys/cdefs.h> 106 __FBSDID("$FreeBSD$"); 107 108 #include "opt_wlan.h" 109 110 #include <sys/param.h> 111 #include <sys/bus.h> 112 #include <sys/conf.h> 113 #include <sys/endian.h> 114 #include <sys/firmware.h> 115 #include <sys/kernel.h> 116 #include <sys/malloc.h> 117 #include <sys/mbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/module.h> 120 #include <sys/proc.h> 121 #include <sys/rman.h> 122 #include <sys/socket.h> 123 #include <sys/sockio.h> 124 #include <sys/sysctl.h> 125 #include <sys/linker.h> 126 127 #include <machine/bus.h> 128 #include <machine/endian.h> 129 #include <machine/resource.h> 130 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/pcireg.h> 133 134 #include <net/bpf.h> 135 136 #include <net/if.h> 137 #include <net/if_var.h> 138 #include <net/if_arp.h> 139 #include <net/if_dl.h> 140 #include <net/if_media.h> 141 #include <net/if_types.h> 142 143 #include <netinet/in.h> 144 #include <netinet/in_systm.h> 145 #include <netinet/if_ether.h> 146 #include <netinet/ip.h> 147 148 #include <net80211/ieee80211_var.h> 149 #include <net80211/ieee80211_regdomain.h> 150 #include <net80211/ieee80211_ratectl.h> 151 #include <net80211/ieee80211_radiotap.h> 152 153 #include <dev/iwm/if_iwmreg.h> 154 #include <dev/iwm/if_iwmvar.h> 155 #include <dev/iwm/if_iwm_config.h> 156 #include <dev/iwm/if_iwm_debug.h> 157 #include <dev/iwm/if_iwm_pcie_trans.h> 158 159 /* 160 * This is a subset of what's in linux iwlwifi/pcie/trans.c. 161 * The rest can be migrated out into here once they're no longer in 162 * if_iwm.c. 163 */ 164 165 /* 166 * basic device access 167 */ 168 169 uint32_t 170 iwm_read_prph(struct iwm_softc *sc, uint32_t addr) 171 { 172 IWM_WRITE(sc, 173 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24))); 174 IWM_BARRIER_READ_WRITE(sc); 175 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT); 176 } 177 178 void 179 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val) 180 { 181 IWM_WRITE(sc, 182 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24))); 183 IWM_BARRIER_WRITE(sc); 184 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val); 185 } 186 187 #ifdef IWM_DEBUG 188 /* iwlwifi: pcie/trans.c */ 189 int 190 iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) 191 { 192 int offs, ret = 0; 193 uint32_t *vals = buf; 194 195 if (iwm_nic_lock(sc)) { 196 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr); 197 for (offs = 0; offs < dwords; offs++) 198 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT); 199 iwm_nic_unlock(sc); 200 } else { 201 ret = EBUSY; 202 } 203 return ret; 204 } 205 #endif 206 207 /* iwlwifi: pcie/trans.c */ 208 int 209 iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) 210 { 211 int offs; 212 const uint32_t *vals = buf; 213 214 if (iwm_nic_lock(sc)) { 215 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr); 216 /* WADDR auto-increments */ 217 for (offs = 0; offs < dwords; offs++) { 218 uint32_t val = vals ? vals[offs] : 0; 219 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val); 220 } 221 iwm_nic_unlock(sc); 222 } else { 223 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, 224 "%s: write_mem failed\n", __func__); 225 return EBUSY; 226 } 227 return 0; 228 } 229 230 int 231 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val) 232 { 233 return iwm_write_mem(sc, addr, &val, 1); 234 } 235 236 int 237 iwm_poll_bit(struct iwm_softc *sc, int reg, 238 uint32_t bits, uint32_t mask, int timo) 239 { 240 for (;;) { 241 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) { 242 return 1; 243 } 244 if (timo < 10) { 245 return 0; 246 } 247 timo -= 10; 248 DELAY(10); 249 } 250 } 251 252 int 253 iwm_nic_lock(struct iwm_softc *sc) 254 { 255 int rv = 0; 256 257 if (sc->cmd_hold_nic_awake) 258 return 1; 259 260 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 261 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 262 263 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_8000) 264 DELAY(2); 265 266 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 267 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 268 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 269 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 270 rv = 1; 271 } else { 272 /* jolt */ 273 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 274 "%s: resetting device via NMI\n", __func__); 275 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 276 } 277 278 return rv; 279 } 280 281 void 282 iwm_nic_unlock(struct iwm_softc *sc) 283 { 284 if (sc->cmd_hold_nic_awake) 285 return; 286 287 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 288 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 289 } 290 291 void 292 iwm_set_bits_mask_prph(struct iwm_softc *sc, 293 uint32_t reg, uint32_t bits, uint32_t mask) 294 { 295 uint32_t val; 296 297 /* XXX: no error path? */ 298 if (iwm_nic_lock(sc)) { 299 val = iwm_read_prph(sc, reg) & mask; 300 val |= bits; 301 iwm_write_prph(sc, reg, val); 302 iwm_nic_unlock(sc); 303 } 304 } 305 306 void 307 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 308 { 309 iwm_set_bits_mask_prph(sc, reg, bits, ~0); 310 } 311 312 void 313 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 314 { 315 iwm_set_bits_mask_prph(sc, reg, 0, ~bits); 316 } 317 318 /* 319 * High-level hardware frobbing routines 320 */ 321 322 void 323 iwm_enable_rfkill_int(struct iwm_softc *sc) 324 { 325 sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL; 326 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 327 } 328 329 int 330 iwm_check_rfkill(struct iwm_softc *sc) 331 { 332 uint32_t v; 333 int rv; 334 335 /* 336 * "documentation" is not really helpful here: 337 * 27: HW_RF_KILL_SW 338 * Indicates state of (platform's) hardware RF-Kill switch 339 * 340 * But apparently when it's off, it's on ... 341 */ 342 v = IWM_READ(sc, IWM_CSR_GP_CNTRL); 343 rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0; 344 if (rv) { 345 sc->sc_flags |= IWM_FLAG_RFKILL; 346 } else { 347 sc->sc_flags &= ~IWM_FLAG_RFKILL; 348 } 349 350 return rv; 351 } 352 353 354 #define IWM_HW_READY_TIMEOUT 50 355 int 356 iwm_set_hw_ready(struct iwm_softc *sc) 357 { 358 int ready; 359 360 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 361 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 362 363 ready = iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG, 364 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 365 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 366 IWM_HW_READY_TIMEOUT); 367 if (ready) { 368 IWM_SETBITS(sc, IWM_CSR_MBOX_SET_REG, 369 IWM_CSR_MBOX_SET_REG_OS_ALIVE); 370 } 371 return ready; 372 } 373 #undef IWM_HW_READY_TIMEOUT 374 375 int 376 iwm_prepare_card_hw(struct iwm_softc *sc) 377 { 378 int rv = 0; 379 int t = 0; 380 381 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__); 382 if (iwm_set_hw_ready(sc)) 383 goto out; 384 385 DELAY(100); 386 387 /* If HW is not ready, prepare the conditions to check again */ 388 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 389 IWM_CSR_HW_IF_CONFIG_REG_PREPARE); 390 391 do { 392 if (iwm_set_hw_ready(sc)) 393 goto out; 394 DELAY(200); 395 t += 200; 396 } while (t < 150000); 397 398 rv = ETIMEDOUT; 399 400 out: 401 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__); 402 return rv; 403 } 404 405 void 406 iwm_apm_config(struct iwm_softc *sc) 407 { 408 uint16_t reg; 409 410 reg = pci_read_config(sc->sc_dev, PCIER_LINK_CTL, sizeof(reg)); 411 if (reg & PCIEM_LINK_CTL_ASPMC_L1) { 412 /* Um the Linux driver prints "Disabling L0S for this one ... */ 413 IWM_SETBITS(sc, IWM_CSR_GIO_REG, 414 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 415 } else { 416 /* ... and "Enabling" here */ 417 IWM_CLRBITS(sc, IWM_CSR_GIO_REG, 418 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 419 } 420 } 421 422 /* 423 * Start up NIC's basic functionality after it has been reset 424 * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop()) 425 * NOTE: This does not load uCode nor start the embedded processor 426 */ 427 int 428 iwm_apm_init(struct iwm_softc *sc) 429 { 430 int error = 0; 431 432 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n"); 433 434 /* Disable L0S exit timer (platform NMI Work/Around) */ 435 if (sc->cfg->device_family != IWM_DEVICE_FAMILY_8000) { 436 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 437 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 438 } 439 440 /* 441 * Disable L0s without affecting L1; 442 * don't wait for ICH L0s (ICH bug W/A) 443 */ 444 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 445 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 446 447 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 448 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL); 449 450 /* 451 * Enable HAP INTA (interrupt from management bus) to 452 * wake device's PCI Express link L1a -> L0s 453 */ 454 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 455 IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 456 457 iwm_apm_config(sc); 458 459 #if 0 /* not for 7k/8k */ 460 /* Configure analog phase-lock-loop before activating to D0A */ 461 if (trans->cfg->base_params->pll_cfg_val) 462 IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG, 463 trans->cfg->base_params->pll_cfg_val); 464 #endif 465 466 /* 467 * Set "initialization complete" bit to move adapter from 468 * D0U* --> D0A* (powered-up active) state. 469 */ 470 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 471 472 /* 473 * Wait for clock stabilization; once stabilized, access to 474 * device-internal resources is supported, e.g. iwm_write_prph() 475 * and accesses to uCode SRAM. 476 */ 477 if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 478 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 479 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) { 480 device_printf(sc->sc_dev, 481 "timeout waiting for clock stabilization\n"); 482 error = ETIMEDOUT; 483 goto out; 484 } 485 486 if (sc->cfg->host_interrupt_operation_mode) { 487 /* 488 * This is a bit of an abuse - This is needed for 7260 / 3160 489 * only check host_interrupt_operation_mode even if this is 490 * not related to host_interrupt_operation_mode. 491 * 492 * Enable the oscillator to count wake up time for L1 exit. This 493 * consumes slightly more power (100uA) - but allows to be sure 494 * that we wake up from L1 on time. 495 * 496 * This looks weird: read twice the same register, discard the 497 * value, set a bit, and yet again, read that same register 498 * just to discard the value. But that's the way the hardware 499 * seems to like it. 500 */ 501 iwm_read_prph(sc, IWM_OSC_CLK); 502 iwm_read_prph(sc, IWM_OSC_CLK); 503 iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL); 504 iwm_read_prph(sc, IWM_OSC_CLK); 505 iwm_read_prph(sc, IWM_OSC_CLK); 506 } 507 508 /* 509 * Enable DMA clock and wait for it to stabilize. 510 * 511 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits 512 * do not disable clocks. This preserves any hardware bits already 513 * set by default in "CLK_CTRL_REG" after reset. 514 */ 515 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 516 iwm_write_prph(sc, IWM_APMG_CLK_EN_REG, 517 IWM_APMG_CLK_VAL_DMA_CLK_RQT); 518 DELAY(20); 519 520 /* Disable L1-Active */ 521 iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 522 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 523 524 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 525 iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG, 526 IWM_APMG_RTC_INT_STT_RFKILL); 527 } 528 out: 529 if (error) 530 device_printf(sc->sc_dev, "apm init error %d\n", error); 531 return error; 532 } 533 534 /* iwlwifi/pcie/trans.c */ 535 void 536 iwm_apm_stop(struct iwm_softc *sc) 537 { 538 /* stop device's busmaster DMA activity */ 539 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER); 540 541 if (!iwm_poll_bit(sc, IWM_CSR_RESET, 542 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 543 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100)) 544 device_printf(sc->sc_dev, "timeout waiting for master\n"); 545 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__); 546 } 547 548 /* iwlwifi pcie/trans.c */ 549 int 550 iwm_start_hw(struct iwm_softc *sc) 551 { 552 int error; 553 554 if ((error = iwm_prepare_card_hw(sc)) != 0) 555 return error; 556 557 /* Reset the entire device */ 558 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET); 559 DELAY(10); 560 561 if ((error = iwm_apm_init(sc)) != 0) 562 return error; 563 564 iwm_enable_rfkill_int(sc); 565 iwm_check_rfkill(sc); 566 567 return 0; 568 } 569 570 /* iwlwifi pcie/trans.c (always main power) */ 571 void 572 iwm_set_pwr(struct iwm_softc *sc) 573 { 574 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 575 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC); 576 } 577 578 /* iwlwifi pcie/rx.c */ 579 int 580 iwm_pcie_rx_stop(struct iwm_softc *sc) 581 { 582 int ret = 0; 583 if (iwm_nic_lock(sc)) { 584 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 585 ret = iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG, 586 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 587 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 588 1000); 589 iwm_nic_unlock(sc); 590 } 591 return ret; 592 } 593 594 void 595 iwm_pcie_clear_cmd_in_flight(struct iwm_softc *sc) 596 { 597 if (!sc->cfg->apmg_wake_up_wa) 598 return; 599 600 if (!sc->cmd_hold_nic_awake) { 601 device_printf(sc->sc_dev, 602 "%s: cmd_hold_nic_awake not set\n", __func__); 603 return; 604 } 605 606 sc->cmd_hold_nic_awake = 0; 607 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 608 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 609 } 610 611 int 612 iwm_pcie_set_cmd_in_flight(struct iwm_softc *sc) 613 { 614 int ret; 615 616 /* 617 * wake up the NIC to make sure that the firmware will see the host 618 * command - we will let the NIC sleep once all the host commands 619 * returned. This needs to be done only on NICs that have 620 * apmg_wake_up_wa set. 621 */ 622 if (sc->cfg->apmg_wake_up_wa && 623 !sc->cmd_hold_nic_awake) { 624 625 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 626 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 627 628 ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 629 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 630 (IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 631 IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 632 15000); 633 if (ret == 0) { 634 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 635 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 636 device_printf(sc->sc_dev, 637 "%s: Failed to wake NIC for hcmd\n", __func__); 638 return EIO; 639 } 640 sc->cmd_hold_nic_awake = 1; 641 } 642 643 return 0; 644 } 645