1 /* $OpenBSD: if_iwm.c,v 1.167 2017/04/04 00:40:52 claudio Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90 /*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105 #include <sys/cdefs.h> 106 #include "opt_wlan.h" 107 #include "opt_iwm.h" 108 109 #include <sys/param.h> 110 #include <sys/bus.h> 111 #include <sys/conf.h> 112 #include <sys/endian.h> 113 #include <sys/firmware.h> 114 #include <sys/kernel.h> 115 #include <sys/malloc.h> 116 #include <sys/mbuf.h> 117 #include <sys/mutex.h> 118 #include <sys/module.h> 119 #include <sys/proc.h> 120 #include <sys/rman.h> 121 #include <sys/socket.h> 122 #include <sys/sockio.h> 123 #include <sys/sysctl.h> 124 #include <sys/linker.h> 125 126 #include <machine/bus.h> 127 #include <machine/endian.h> 128 #include <machine/resource.h> 129 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/pcireg.h> 132 133 #include <net/bpf.h> 134 135 #include <net/if.h> 136 #include <net/if_var.h> 137 #include <net/if_arp.h> 138 #include <net/if_dl.h> 139 #include <net/if_media.h> 140 #include <net/if_types.h> 141 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/if_ether.h> 145 #include <netinet/ip.h> 146 147 #include <net80211/ieee80211_var.h> 148 #include <net80211/ieee80211_regdomain.h> 149 #include <net80211/ieee80211_ratectl.h> 150 #include <net80211/ieee80211_radiotap.h> 151 152 #include <dev/iwm/if_iwmreg.h> 153 #include <dev/iwm/if_iwmvar.h> 154 #include <dev/iwm/if_iwm_config.h> 155 #include <dev/iwm/if_iwm_debug.h> 156 #include <dev/iwm/if_iwm_notif_wait.h> 157 #include <dev/iwm/if_iwm_util.h> 158 #include <dev/iwm/if_iwm_binding.h> 159 #include <dev/iwm/if_iwm_phy_db.h> 160 #include <dev/iwm/if_iwm_mac_ctxt.h> 161 #include <dev/iwm/if_iwm_phy_ctxt.h> 162 #include <dev/iwm/if_iwm_time_event.h> 163 #include <dev/iwm/if_iwm_power.h> 164 #include <dev/iwm/if_iwm_scan.h> 165 #include <dev/iwm/if_iwm_sf.h> 166 #include <dev/iwm/if_iwm_sta.h> 167 168 #include <dev/iwm/if_iwm_pcie_trans.h> 169 #include <dev/iwm/if_iwm_led.h> 170 #include <dev/iwm/if_iwm_fw.h> 171 172 /* From DragonflyBSD */ 173 #define mtodoff(m, t, off) ((t)((m)->m_data + (off))) 174 175 const uint8_t iwm_nvm_channels[] = { 176 /* 2.4 GHz */ 177 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 178 /* 5 GHz */ 179 36, 40, 44, 48, 52, 56, 60, 64, 180 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 181 149, 153, 157, 161, 165 182 }; 183 _Static_assert(nitems(iwm_nvm_channels) <= IWM_NUM_CHANNELS, 184 "IWM_NUM_CHANNELS is too small"); 185 186 const uint8_t iwm_nvm_channels_8000[] = { 187 /* 2.4 GHz */ 188 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 189 /* 5 GHz */ 190 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 191 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 192 149, 153, 157, 161, 165, 169, 173, 177, 181 193 }; 194 _Static_assert(nitems(iwm_nvm_channels_8000) <= IWM_NUM_CHANNELS_8000, 195 "IWM_NUM_CHANNELS_8000 is too small"); 196 197 #define IWM_NUM_2GHZ_CHANNELS 14 198 #define IWM_N_HW_ADDR_MASK 0xF 199 200 const struct iwm_rate { 201 uint16_t rate; 202 uint8_t plcp; 203 uint8_t ht_plcp; 204 } iwm_rates[] = { 205 /* Legacy */ /* HT */ 206 { 2, IWM_RATE_1M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 207 { 4, IWM_RATE_2M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 208 { 11, IWM_RATE_5M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 209 { 22, IWM_RATE_11M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 210 { 12, IWM_RATE_6M_PLCP, IWM_RATE_HT_SISO_MCS_0_PLCP }, 211 { 18, IWM_RATE_9M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 212 { 24, IWM_RATE_12M_PLCP, IWM_RATE_HT_SISO_MCS_1_PLCP }, 213 { 26, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_8_PLCP }, 214 { 36, IWM_RATE_18M_PLCP, IWM_RATE_HT_SISO_MCS_2_PLCP }, 215 { 48, IWM_RATE_24M_PLCP, IWM_RATE_HT_SISO_MCS_3_PLCP }, 216 { 52, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_9_PLCP }, 217 { 72, IWM_RATE_36M_PLCP, IWM_RATE_HT_SISO_MCS_4_PLCP }, 218 { 78, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_10_PLCP }, 219 { 96, IWM_RATE_48M_PLCP, IWM_RATE_HT_SISO_MCS_5_PLCP }, 220 { 104, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_11_PLCP }, 221 { 108, IWM_RATE_54M_PLCP, IWM_RATE_HT_SISO_MCS_6_PLCP }, 222 { 128, IWM_RATE_INVM_PLCP, IWM_RATE_HT_SISO_MCS_7_PLCP }, 223 { 156, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_12_PLCP }, 224 { 208, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_13_PLCP }, 225 { 234, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_14_PLCP }, 226 { 260, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_15_PLCP }, 227 }; 228 #define IWM_RIDX_CCK 0 229 #define IWM_RIDX_OFDM 4 230 #define IWM_RIDX_MAX (nitems(iwm_rates)-1) 231 #define IWM_RIDX_IS_CCK(_i_) ((_i_) < IWM_RIDX_OFDM) 232 #define IWM_RIDX_IS_OFDM(_i_) ((_i_) >= IWM_RIDX_OFDM) 233 #define IWM_RVAL_IS_OFDM(_i_) ((_i_) >= 12 && (_i_) != 22) 234 235 /* Convert an MCS index into an iwm_rates[] index. */ 236 const int iwm_mcs2ridx[] = { 237 IWM_RATE_MCS_0_INDEX, 238 IWM_RATE_MCS_1_INDEX, 239 IWM_RATE_MCS_2_INDEX, 240 IWM_RATE_MCS_3_INDEX, 241 IWM_RATE_MCS_4_INDEX, 242 IWM_RATE_MCS_5_INDEX, 243 IWM_RATE_MCS_6_INDEX, 244 IWM_RATE_MCS_7_INDEX, 245 IWM_RATE_MCS_8_INDEX, 246 IWM_RATE_MCS_9_INDEX, 247 IWM_RATE_MCS_10_INDEX, 248 IWM_RATE_MCS_11_INDEX, 249 IWM_RATE_MCS_12_INDEX, 250 IWM_RATE_MCS_13_INDEX, 251 IWM_RATE_MCS_14_INDEX, 252 IWM_RATE_MCS_15_INDEX, 253 }; 254 255 struct iwm_nvm_section { 256 uint16_t length; 257 uint8_t *data; 258 }; 259 260 #define IWM_UCODE_ALIVE_TIMEOUT hz 261 #define IWM_UCODE_CALIB_TIMEOUT (2*hz) 262 263 struct iwm_alive_data { 264 int valid; 265 uint32_t scd_base_addr; 266 }; 267 268 static int iwm_store_cscheme(struct iwm_softc *, const uint8_t *, size_t); 269 static int iwm_firmware_store_section(struct iwm_softc *, 270 enum iwm_ucode_type, 271 const uint8_t *, size_t); 272 static int iwm_set_default_calib(struct iwm_softc *, const void *); 273 static void iwm_fw_info_free(struct iwm_fw_info *); 274 static int iwm_read_firmware(struct iwm_softc *); 275 static int iwm_alloc_fwmem(struct iwm_softc *); 276 static int iwm_alloc_sched(struct iwm_softc *); 277 static int iwm_alloc_kw(struct iwm_softc *); 278 static int iwm_alloc_ict(struct iwm_softc *); 279 static int iwm_alloc_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 280 static void iwm_reset_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 281 static void iwm_free_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 282 static int iwm_alloc_tx_ring(struct iwm_softc *, struct iwm_tx_ring *, 283 int); 284 static void iwm_reset_tx_ring(struct iwm_softc *, struct iwm_tx_ring *); 285 static void iwm_free_tx_ring(struct iwm_softc *, struct iwm_tx_ring *); 286 static void iwm_enable_interrupts(struct iwm_softc *); 287 static void iwm_restore_interrupts(struct iwm_softc *); 288 static void iwm_disable_interrupts(struct iwm_softc *); 289 static void iwm_ict_reset(struct iwm_softc *); 290 static int iwm_allow_mcast(struct ieee80211vap *, struct iwm_softc *); 291 static void iwm_stop_device(struct iwm_softc *); 292 static void iwm_nic_config(struct iwm_softc *); 293 static int iwm_nic_rx_init(struct iwm_softc *); 294 static int iwm_nic_tx_init(struct iwm_softc *); 295 static int iwm_nic_init(struct iwm_softc *); 296 static int iwm_trans_pcie_fw_alive(struct iwm_softc *, uint32_t); 297 static int iwm_nvm_read_chunk(struct iwm_softc *, uint16_t, uint16_t, 298 uint16_t, uint8_t *, uint16_t *); 299 static int iwm_nvm_read_section(struct iwm_softc *, uint16_t, uint8_t *, 300 uint16_t *, uint32_t); 301 static uint32_t iwm_eeprom_channel_flags(uint16_t); 302 static void iwm_add_channel_band(struct iwm_softc *, 303 struct ieee80211_channel[], int, int *, int, size_t, 304 const uint8_t[]); 305 static void iwm_init_channel_map(struct ieee80211com *, int, int *, 306 struct ieee80211_channel[]); 307 static struct iwm_nvm_data * 308 iwm_parse_nvm_data(struct iwm_softc *, const uint16_t *, 309 const uint16_t *, const uint16_t *, 310 const uint16_t *, const uint16_t *, 311 const uint16_t *); 312 static void iwm_free_nvm_data(struct iwm_nvm_data *); 313 static void iwm_set_hw_address_family_8000(struct iwm_softc *, 314 struct iwm_nvm_data *, 315 const uint16_t *, 316 const uint16_t *); 317 static int iwm_get_sku(const struct iwm_softc *, const uint16_t *, 318 const uint16_t *); 319 static int iwm_get_nvm_version(const struct iwm_softc *, const uint16_t *); 320 static int iwm_get_radio_cfg(const struct iwm_softc *, const uint16_t *, 321 const uint16_t *); 322 static int iwm_get_n_hw_addrs(const struct iwm_softc *, 323 const uint16_t *); 324 static void iwm_set_radio_cfg(const struct iwm_softc *, 325 struct iwm_nvm_data *, uint32_t); 326 static struct iwm_nvm_data * 327 iwm_parse_nvm_sections(struct iwm_softc *, struct iwm_nvm_section *); 328 static int iwm_nvm_init(struct iwm_softc *); 329 static int iwm_pcie_load_section(struct iwm_softc *, uint8_t, 330 const struct iwm_fw_desc *); 331 static int iwm_pcie_load_firmware_chunk(struct iwm_softc *, uint32_t, 332 bus_addr_t, uint32_t); 333 static int iwm_pcie_load_cpu_sections_8000(struct iwm_softc *sc, 334 const struct iwm_fw_img *, 335 int, int *); 336 static int iwm_pcie_load_cpu_sections(struct iwm_softc *, 337 const struct iwm_fw_img *, 338 int, int *); 339 static int iwm_pcie_load_given_ucode_8000(struct iwm_softc *, 340 const struct iwm_fw_img *); 341 static int iwm_pcie_load_given_ucode(struct iwm_softc *, 342 const struct iwm_fw_img *); 343 static int iwm_start_fw(struct iwm_softc *, const struct iwm_fw_img *); 344 static int iwm_send_tx_ant_cfg(struct iwm_softc *, uint8_t); 345 static int iwm_send_phy_cfg_cmd(struct iwm_softc *); 346 static int iwm_load_ucode_wait_alive(struct iwm_softc *, 347 enum iwm_ucode_type); 348 static int iwm_run_init_ucode(struct iwm_softc *, int); 349 static int iwm_config_ltr(struct iwm_softc *sc); 350 static int iwm_rx_addbuf(struct iwm_softc *, int, int); 351 static void iwm_rx_rx_phy_cmd(struct iwm_softc *, 352 struct iwm_rx_packet *); 353 static int iwm_get_noise(struct iwm_softc *, 354 const struct iwm_statistics_rx_non_phy *); 355 static void iwm_handle_rx_statistics(struct iwm_softc *, 356 struct iwm_rx_packet *); 357 static bool iwm_rx_mpdu(struct iwm_softc *, struct mbuf *, 358 uint32_t, bool); 359 static int iwm_rx_tx_cmd_single(struct iwm_softc *, 360 struct iwm_rx_packet *, 361 struct iwm_node *); 362 static void iwm_rx_tx_cmd(struct iwm_softc *, struct iwm_rx_packet *); 363 static void iwm_cmd_done(struct iwm_softc *, struct iwm_rx_packet *); 364 #if 0 365 static void iwm_update_sched(struct iwm_softc *, int, int, uint8_t, 366 uint16_t); 367 #endif 368 static const struct iwm_rate * 369 iwm_tx_fill_cmd(struct iwm_softc *, struct iwm_node *, 370 struct mbuf *, struct iwm_tx_cmd *); 371 static int iwm_tx(struct iwm_softc *, struct mbuf *, 372 struct ieee80211_node *, int); 373 static int iwm_raw_xmit(struct ieee80211_node *, struct mbuf *, 374 const struct ieee80211_bpf_params *); 375 static int iwm_update_quotas(struct iwm_softc *, struct iwm_vap *); 376 static int iwm_auth(struct ieee80211vap *, struct iwm_softc *); 377 static struct ieee80211_node * 378 iwm_node_alloc(struct ieee80211vap *, 379 const uint8_t[IEEE80211_ADDR_LEN]); 380 static uint8_t iwm_rate_from_ucode_rate(uint32_t); 381 static int iwm_rate2ridx(struct iwm_softc *, uint8_t); 382 static void iwm_setrates(struct iwm_softc *, struct iwm_node *, int); 383 static int iwm_newstate(struct ieee80211vap *, enum ieee80211_state, int); 384 static void iwm_endscan_cb(void *, int); 385 static int iwm_send_bt_init_conf(struct iwm_softc *); 386 static boolean_t iwm_is_lar_supported(struct iwm_softc *); 387 static boolean_t iwm_is_wifi_mcc_supported(struct iwm_softc *); 388 static int iwm_send_update_mcc_cmd(struct iwm_softc *, const char *); 389 static void iwm_tt_tx_backoff(struct iwm_softc *, uint32_t); 390 static int iwm_init_hw(struct iwm_softc *); 391 static void iwm_init(struct iwm_softc *); 392 static void iwm_start(struct iwm_softc *); 393 static void iwm_stop(struct iwm_softc *); 394 static void iwm_watchdog(void *); 395 static void iwm_parent(struct ieee80211com *); 396 #ifdef IWM_DEBUG 397 static const char * 398 iwm_desc_lookup(uint32_t); 399 static void iwm_nic_error(struct iwm_softc *); 400 static void iwm_nic_umac_error(struct iwm_softc *); 401 #endif 402 static void iwm_handle_rxb(struct iwm_softc *, struct mbuf *); 403 static void iwm_notif_intr(struct iwm_softc *); 404 static void iwm_intr(void *); 405 static void iwm_intr_msix(void *); 406 static int iwm_attach(device_t); 407 static int iwm_is_valid_ether_addr(uint8_t *); 408 static void iwm_preinit(void *); 409 static int iwm_detach_local(struct iwm_softc *sc, int); 410 static void iwm_init_task(void *); 411 static void iwm_radiotap_attach(struct iwm_softc *); 412 static struct ieee80211vap * 413 iwm_vap_create(struct ieee80211com *, 414 const char [IFNAMSIZ], int, 415 enum ieee80211_opmode, int, 416 const uint8_t [IEEE80211_ADDR_LEN], 417 const uint8_t [IEEE80211_ADDR_LEN]); 418 static void iwm_vap_delete(struct ieee80211vap *); 419 static void iwm_xmit_queue_drain(struct iwm_softc *); 420 static void iwm_scan_start(struct ieee80211com *); 421 static void iwm_scan_end(struct ieee80211com *); 422 static void iwm_update_mcast(struct ieee80211com *); 423 static void iwm_set_channel(struct ieee80211com *); 424 static void iwm_scan_curchan(struct ieee80211_scan_state *, unsigned long); 425 static void iwm_scan_mindwell(struct ieee80211_scan_state *); 426 static int iwm_detach(device_t); 427 428 static int iwm_lar_disable = 0; 429 TUNABLE_INT("hw.iwm.lar.disable", &iwm_lar_disable); 430 431 /* 432 * Firmware parser. 433 */ 434 435 static int 436 iwm_store_cscheme(struct iwm_softc *sc, const uint8_t *data, size_t dlen) 437 { 438 const struct iwm_fw_cscheme_list *l = (const void *)data; 439 440 if (dlen < sizeof(*l) || 441 dlen < sizeof(l->size) + l->size * sizeof(*l->cs)) 442 return EINVAL; 443 444 /* we don't actually store anything for now, always use s/w crypto */ 445 446 return 0; 447 } 448 449 static int 450 iwm_firmware_store_section(struct iwm_softc *sc, 451 enum iwm_ucode_type type, const uint8_t *data, size_t dlen) 452 { 453 struct iwm_fw_img *fws; 454 struct iwm_fw_desc *fwone; 455 456 if (type >= IWM_UCODE_TYPE_MAX) 457 return EINVAL; 458 if (dlen < sizeof(uint32_t)) 459 return EINVAL; 460 461 fws = &sc->sc_fw.img[type]; 462 if (fws->fw_count >= IWM_UCODE_SECTION_MAX) 463 return EINVAL; 464 465 fwone = &fws->sec[fws->fw_count]; 466 467 /* first 32bit are device load offset */ 468 memcpy(&fwone->offset, data, sizeof(uint32_t)); 469 470 /* rest is data */ 471 fwone->data = data + sizeof(uint32_t); 472 fwone->len = dlen - sizeof(uint32_t); 473 474 fws->fw_count++; 475 476 return 0; 477 } 478 479 #define IWM_DEFAULT_SCAN_CHANNELS 40 480 481 /* iwlwifi: iwl-drv.c */ 482 struct iwm_tlv_calib_data { 483 uint32_t ucode_type; 484 struct iwm_tlv_calib_ctrl calib; 485 } __packed; 486 487 static int 488 iwm_set_default_calib(struct iwm_softc *sc, const void *data) 489 { 490 const struct iwm_tlv_calib_data *def_calib = data; 491 uint32_t ucode_type = le32toh(def_calib->ucode_type); 492 493 if (ucode_type >= IWM_UCODE_TYPE_MAX) { 494 device_printf(sc->sc_dev, 495 "Wrong ucode_type %u for default " 496 "calibration.\n", ucode_type); 497 return EINVAL; 498 } 499 500 sc->sc_default_calib[ucode_type].flow_trigger = 501 def_calib->calib.flow_trigger; 502 sc->sc_default_calib[ucode_type].event_trigger = 503 def_calib->calib.event_trigger; 504 505 return 0; 506 } 507 508 static int 509 iwm_set_ucode_api_flags(struct iwm_softc *sc, const uint8_t *data, 510 struct iwm_ucode_capabilities *capa) 511 { 512 const struct iwm_ucode_api *ucode_api = (const void *)data; 513 uint32_t api_index = le32toh(ucode_api->api_index); 514 uint32_t api_flags = le32toh(ucode_api->api_flags); 515 int i; 516 517 if (api_index >= howmany(IWM_NUM_UCODE_TLV_API, 32)) { 518 device_printf(sc->sc_dev, 519 "api flags index %d larger than supported by driver\n", 520 api_index); 521 /* don't return an error so we can load FW that has more bits */ 522 return 0; 523 } 524 525 for (i = 0; i < 32; i++) { 526 if (api_flags & (1U << i)) 527 setbit(capa->enabled_api, i + 32 * api_index); 528 } 529 530 return 0; 531 } 532 533 static int 534 iwm_set_ucode_capabilities(struct iwm_softc *sc, const uint8_t *data, 535 struct iwm_ucode_capabilities *capa) 536 { 537 const struct iwm_ucode_capa *ucode_capa = (const void *)data; 538 uint32_t api_index = le32toh(ucode_capa->api_index); 539 uint32_t api_flags = le32toh(ucode_capa->api_capa); 540 int i; 541 542 if (api_index >= howmany(IWM_NUM_UCODE_TLV_CAPA, 32)) { 543 device_printf(sc->sc_dev, 544 "capa flags index %d larger than supported by driver\n", 545 api_index); 546 /* don't return an error so we can load FW that has more bits */ 547 return 0; 548 } 549 550 for (i = 0; i < 32; i++) { 551 if (api_flags & (1U << i)) 552 setbit(capa->enabled_capa, i + 32 * api_index); 553 } 554 555 return 0; 556 } 557 558 static void 559 iwm_fw_info_free(struct iwm_fw_info *fw) 560 { 561 firmware_put(fw->fw_fp, FIRMWARE_UNLOAD); 562 fw->fw_fp = NULL; 563 memset(fw->img, 0, sizeof(fw->img)); 564 } 565 566 static uint8_t 567 iwm_lookup_cmd_ver(struct iwm_softc *sc, uint8_t grp, uint8_t cmd) 568 { 569 const struct iwm_fw_cmd_version *entry; 570 int i; 571 572 for (i = 0; i < sc->n_cmd_versions; i++) { 573 entry = &sc->cmd_versions[i]; 574 if (entry->group == grp && entry->cmd == cmd) 575 return entry->cmd_ver; 576 } 577 578 return IWM_FW_CMD_VER_UNKNOWN; 579 } 580 581 static int 582 iwm_read_firmware(struct iwm_softc *sc) 583 { 584 struct iwm_fw_info *fw = &sc->sc_fw; 585 const struct iwm_tlv_ucode_header *uhdr; 586 const struct iwm_ucode_tlv *tlv; 587 struct iwm_ucode_capabilities *capa = &sc->sc_fw.ucode_capa; 588 enum iwm_ucode_tlv_type tlv_type; 589 const struct firmware *fwp; 590 const uint8_t *data; 591 uint32_t tlv_len; 592 uint32_t usniffer_img; 593 const uint8_t *tlv_data; 594 uint32_t paging_mem_size; 595 int num_of_cpus; 596 int error = 0; 597 size_t len; 598 599 /* 600 * Load firmware into driver memory. 601 * fw_fp will be set. 602 */ 603 fwp = firmware_get(sc->cfg->fw_name); 604 if (fwp == NULL) { 605 device_printf(sc->sc_dev, 606 "could not read firmware %s (error %d)\n", 607 sc->cfg->fw_name, error); 608 goto out; 609 } 610 fw->fw_fp = fwp; 611 612 /* (Re-)Initialize default values. */ 613 capa->flags = 0; 614 capa->max_probe_length = IWM_DEFAULT_MAX_PROBE_LENGTH; 615 capa->n_scan_channels = IWM_DEFAULT_SCAN_CHANNELS; 616 memset(capa->enabled_capa, 0, sizeof(capa->enabled_capa)); 617 memset(capa->enabled_api, 0, sizeof(capa->enabled_api)); 618 memset(sc->sc_fw_mcc, 0, sizeof(sc->sc_fw_mcc)); 619 620 /* 621 * Parse firmware contents 622 */ 623 624 uhdr = (const void *)fw->fw_fp->data; 625 if (*(const uint32_t *)fw->fw_fp->data != 0 626 || le32toh(uhdr->magic) != IWM_TLV_UCODE_MAGIC) { 627 device_printf(sc->sc_dev, "invalid firmware %s\n", 628 sc->cfg->fw_name); 629 error = EINVAL; 630 goto out; 631 } 632 633 snprintf(sc->sc_fwver, sizeof(sc->sc_fwver), "%u.%u (API ver %u)", 634 IWM_UCODE_MAJOR(le32toh(uhdr->ver)), 635 IWM_UCODE_MINOR(le32toh(uhdr->ver)), 636 IWM_UCODE_API(le32toh(uhdr->ver))); 637 data = uhdr->data; 638 len = fw->fw_fp->datasize - sizeof(*uhdr); 639 640 while (len >= sizeof(*tlv)) { 641 len -= sizeof(*tlv); 642 tlv = (const void *)data; 643 644 tlv_len = le32toh(tlv->length); 645 tlv_type = le32toh(tlv->type); 646 tlv_data = tlv->data; 647 648 if (len < tlv_len) { 649 device_printf(sc->sc_dev, 650 "firmware too short: %zu bytes\n", 651 len); 652 error = EINVAL; 653 goto parse_out; 654 } 655 len -= roundup2(tlv_len, 4); 656 data += sizeof(*tlv) + roundup2(tlv_len, 4); 657 658 switch ((int)tlv_type) { 659 case IWM_UCODE_TLV_PROBE_MAX_LEN: 660 if (tlv_len != sizeof(uint32_t)) { 661 device_printf(sc->sc_dev, 662 "%s: PROBE_MAX_LEN (%u) != sizeof(uint32_t)\n", 663 __func__, tlv_len); 664 error = EINVAL; 665 goto parse_out; 666 } 667 capa->max_probe_length = 668 le32_to_cpup((const uint32_t *)tlv_data); 669 /* limit it to something sensible */ 670 if (capa->max_probe_length > 671 IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE) { 672 IWM_DPRINTF(sc, IWM_DEBUG_FIRMWARE_TLV, 673 "%s: IWM_UCODE_TLV_PROBE_MAX_LEN " 674 "ridiculous\n", __func__); 675 error = EINVAL; 676 goto parse_out; 677 } 678 break; 679 case IWM_UCODE_TLV_PAN: 680 if (tlv_len) { 681 device_printf(sc->sc_dev, 682 "%s: IWM_UCODE_TLV_PAN: tlv_len (%u) > 0\n", 683 __func__, tlv_len); 684 error = EINVAL; 685 goto parse_out; 686 } 687 capa->flags |= IWM_UCODE_TLV_FLAGS_PAN; 688 break; 689 case IWM_UCODE_TLV_FLAGS: 690 if (tlv_len < sizeof(uint32_t)) { 691 device_printf(sc->sc_dev, 692 "%s: IWM_UCODE_TLV_FLAGS: tlv_len (%u) < sizeof(uint32_t)\n", 693 __func__, tlv_len); 694 error = EINVAL; 695 goto parse_out; 696 } 697 if (tlv_len % sizeof(uint32_t)) { 698 device_printf(sc->sc_dev, 699 "%s: IWM_UCODE_TLV_FLAGS: tlv_len (%u) %% sizeof(uint32_t)\n", 700 __func__, tlv_len); 701 error = EINVAL; 702 goto parse_out; 703 } 704 /* 705 * Apparently there can be many flags, but Linux driver 706 * parses only the first one, and so do we. 707 * 708 * XXX: why does this override IWM_UCODE_TLV_PAN? 709 * Intentional or a bug? Observations from 710 * current firmware file: 711 * 1) TLV_PAN is parsed first 712 * 2) TLV_FLAGS contains TLV_FLAGS_PAN 713 * ==> this resets TLV_PAN to itself... hnnnk 714 */ 715 capa->flags = le32_to_cpup((const uint32_t *)tlv_data); 716 break; 717 case IWM_UCODE_TLV_CSCHEME: 718 if ((error = iwm_store_cscheme(sc, 719 tlv_data, tlv_len)) != 0) { 720 device_printf(sc->sc_dev, 721 "%s: iwm_store_cscheme(): returned %d\n", 722 __func__, error); 723 goto parse_out; 724 } 725 break; 726 case IWM_UCODE_TLV_NUM_OF_CPU: 727 if (tlv_len != sizeof(uint32_t)) { 728 device_printf(sc->sc_dev, 729 "%s: IWM_UCODE_TLV_NUM_OF_CPU: tlv_len (%u) != sizeof(uint32_t)\n", 730 __func__, tlv_len); 731 error = EINVAL; 732 goto parse_out; 733 } 734 num_of_cpus = le32_to_cpup((const uint32_t *)tlv_data); 735 if (num_of_cpus == 2) { 736 fw->img[IWM_UCODE_REGULAR].is_dual_cpus = 737 TRUE; 738 fw->img[IWM_UCODE_INIT].is_dual_cpus = 739 TRUE; 740 fw->img[IWM_UCODE_WOWLAN].is_dual_cpus = 741 TRUE; 742 } else if ((num_of_cpus > 2) || (num_of_cpus < 1)) { 743 device_printf(sc->sc_dev, 744 "%s: Driver supports only 1 or 2 CPUs\n", 745 __func__); 746 error = EINVAL; 747 goto parse_out; 748 } 749 break; 750 case IWM_UCODE_TLV_SEC_RT: 751 if ((error = iwm_firmware_store_section(sc, 752 IWM_UCODE_REGULAR, tlv_data, tlv_len)) != 0) { 753 device_printf(sc->sc_dev, 754 "%s: IWM_UCODE_REGULAR: iwm_firmware_store_section() failed; %d\n", 755 __func__, error); 756 goto parse_out; 757 } 758 break; 759 case IWM_UCODE_TLV_SEC_INIT: 760 if ((error = iwm_firmware_store_section(sc, 761 IWM_UCODE_INIT, tlv_data, tlv_len)) != 0) { 762 device_printf(sc->sc_dev, 763 "%s: IWM_UCODE_INIT: iwm_firmware_store_section() failed; %d\n", 764 __func__, error); 765 goto parse_out; 766 } 767 break; 768 case IWM_UCODE_TLV_SEC_WOWLAN: 769 if ((error = iwm_firmware_store_section(sc, 770 IWM_UCODE_WOWLAN, tlv_data, tlv_len)) != 0) { 771 device_printf(sc->sc_dev, 772 "%s: IWM_UCODE_WOWLAN: iwm_firmware_store_section() failed; %d\n", 773 __func__, error); 774 goto parse_out; 775 } 776 break; 777 case IWM_UCODE_TLV_DEF_CALIB: 778 if (tlv_len != sizeof(struct iwm_tlv_calib_data)) { 779 device_printf(sc->sc_dev, 780 "%s: IWM_UCODE_TLV_DEV_CALIB: tlv_len (%u) < sizeof(iwm_tlv_calib_data) (%zu)\n", 781 __func__, tlv_len, 782 sizeof(struct iwm_tlv_calib_data)); 783 error = EINVAL; 784 goto parse_out; 785 } 786 if ((error = iwm_set_default_calib(sc, tlv_data)) != 0) { 787 device_printf(sc->sc_dev, 788 "%s: iwm_set_default_calib() failed: %d\n", 789 __func__, error); 790 goto parse_out; 791 } 792 break; 793 case IWM_UCODE_TLV_PHY_SKU: 794 if (tlv_len != sizeof(uint32_t)) { 795 error = EINVAL; 796 device_printf(sc->sc_dev, 797 "%s: IWM_UCODE_TLV_PHY_SKU: tlv_len (%u) < sizeof(uint32_t)\n", 798 __func__, tlv_len); 799 goto parse_out; 800 } 801 sc->sc_fw.phy_config = 802 le32_to_cpup((const uint32_t *)tlv_data); 803 sc->sc_fw.valid_tx_ant = (sc->sc_fw.phy_config & 804 IWM_FW_PHY_CFG_TX_CHAIN) >> 805 IWM_FW_PHY_CFG_TX_CHAIN_POS; 806 sc->sc_fw.valid_rx_ant = (sc->sc_fw.phy_config & 807 IWM_FW_PHY_CFG_RX_CHAIN) >> 808 IWM_FW_PHY_CFG_RX_CHAIN_POS; 809 break; 810 811 case IWM_UCODE_TLV_API_CHANGES_SET: { 812 if (tlv_len != sizeof(struct iwm_ucode_api)) { 813 error = EINVAL; 814 goto parse_out; 815 } 816 if (iwm_set_ucode_api_flags(sc, tlv_data, capa)) { 817 error = EINVAL; 818 goto parse_out; 819 } 820 break; 821 } 822 823 case IWM_UCODE_TLV_ENABLED_CAPABILITIES: { 824 if (tlv_len != sizeof(struct iwm_ucode_capa)) { 825 error = EINVAL; 826 goto parse_out; 827 } 828 if (iwm_set_ucode_capabilities(sc, tlv_data, capa)) { 829 error = EINVAL; 830 goto parse_out; 831 } 832 break; 833 } 834 835 case IWM_UCODE_TLV_CMD_VERSIONS: 836 if (tlv_len % sizeof(struct iwm_fw_cmd_version)) { 837 tlv_len /= sizeof(struct iwm_fw_cmd_version); 838 tlv_len *= sizeof(struct iwm_fw_cmd_version); 839 } 840 if (sc->n_cmd_versions != 0) { 841 error = EINVAL; 842 goto parse_out; 843 } 844 if (tlv_len > sizeof(sc->cmd_versions)) { 845 error = EINVAL; 846 goto parse_out; 847 } 848 memcpy(&sc->cmd_versions[0], tlv_data, tlv_len); 849 sc->n_cmd_versions = tlv_len / sizeof(struct iwm_fw_cmd_version); 850 break; 851 852 case IWM_UCODE_TLV_SDIO_ADMA_ADDR: 853 case IWM_UCODE_TLV_FW_GSCAN_CAPA: 854 /* ignore, not used by current driver */ 855 break; 856 857 case IWM_UCODE_TLV_SEC_RT_USNIFFER: 858 if ((error = iwm_firmware_store_section(sc, 859 IWM_UCODE_REGULAR_USNIFFER, tlv_data, 860 tlv_len)) != 0) 861 goto parse_out; 862 break; 863 864 case IWM_UCODE_TLV_PAGING: 865 if (tlv_len != sizeof(uint32_t)) { 866 error = EINVAL; 867 goto parse_out; 868 } 869 paging_mem_size = le32_to_cpup((const uint32_t *)tlv_data); 870 871 IWM_DPRINTF(sc, IWM_DEBUG_FIRMWARE_TLV, 872 "%s: Paging: paging enabled (size = %u bytes)\n", 873 __func__, paging_mem_size); 874 if (paging_mem_size > IWM_MAX_PAGING_IMAGE_SIZE) { 875 device_printf(sc->sc_dev, 876 "%s: Paging: driver supports up to %u bytes for paging image\n", 877 __func__, IWM_MAX_PAGING_IMAGE_SIZE); 878 error = EINVAL; 879 goto out; 880 } 881 if (paging_mem_size & (IWM_FW_PAGING_SIZE - 1)) { 882 device_printf(sc->sc_dev, 883 "%s: Paging: image isn't multiple %u\n", 884 __func__, IWM_FW_PAGING_SIZE); 885 error = EINVAL; 886 goto out; 887 } 888 889 sc->sc_fw.img[IWM_UCODE_REGULAR].paging_mem_size = 890 paging_mem_size; 891 usniffer_img = IWM_UCODE_REGULAR_USNIFFER; 892 sc->sc_fw.img[usniffer_img].paging_mem_size = 893 paging_mem_size; 894 break; 895 896 case IWM_UCODE_TLV_N_SCAN_CHANNELS: 897 if (tlv_len != sizeof(uint32_t)) { 898 error = EINVAL; 899 goto parse_out; 900 } 901 capa->n_scan_channels = 902 le32_to_cpup((const uint32_t *)tlv_data); 903 break; 904 905 case IWM_UCODE_TLV_FW_VERSION: 906 if (tlv_len != sizeof(uint32_t) * 3) { 907 error = EINVAL; 908 goto parse_out; 909 } 910 snprintf(sc->sc_fwver, sizeof(sc->sc_fwver), 911 "%u.%u.%u", 912 le32toh(((const uint32_t *)tlv_data)[0]), 913 le32toh(((const uint32_t *)tlv_data)[1]), 914 le32toh(((const uint32_t *)tlv_data)[2])); 915 break; 916 917 case IWM_UCODE_TLV_FW_MEM_SEG: 918 break; 919 920 default: 921 device_printf(sc->sc_dev, 922 "%s: unknown firmware section %d, abort\n", 923 __func__, tlv_type); 924 error = EINVAL; 925 goto parse_out; 926 } 927 } 928 929 KASSERT(error == 0, ("unhandled error")); 930 931 parse_out: 932 if (error) { 933 device_printf(sc->sc_dev, "firmware parse error %d, " 934 "section type %d\n", error, tlv_type); 935 } 936 937 out: 938 if (error) { 939 if (fw->fw_fp != NULL) 940 iwm_fw_info_free(fw); 941 } 942 943 return error; 944 } 945 946 /* 947 * DMA resource routines 948 */ 949 950 /* fwmem is used to load firmware onto the card */ 951 static int 952 iwm_alloc_fwmem(struct iwm_softc *sc) 953 { 954 /* Must be aligned on a 16-byte boundary. */ 955 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, 956 IWM_FH_MEM_TB_MAX_LENGTH, 16); 957 } 958 959 /* tx scheduler rings. not used? */ 960 static int 961 iwm_alloc_sched(struct iwm_softc *sc) 962 { 963 /* TX scheduler rings must be aligned on a 1KB boundary. */ 964 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 965 nitems(sc->txq) * sizeof(struct iwm_agn_scd_bc_tbl), 1024); 966 } 967 968 /* keep-warm page is used internally by the card. see iwl-fh.h for more info */ 969 static int 970 iwm_alloc_kw(struct iwm_softc *sc) 971 { 972 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, 4096, 4096); 973 } 974 975 /* interrupt cause table */ 976 static int 977 iwm_alloc_ict(struct iwm_softc *sc) 978 { 979 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 980 IWM_ICT_SIZE, 1<<IWM_ICT_PADDR_SHIFT); 981 } 982 983 static int 984 iwm_alloc_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 985 { 986 bus_size_t size; 987 size_t descsz; 988 int count, i, error; 989 990 ring->cur = 0; 991 if (sc->cfg->mqrx_supported) { 992 count = IWM_RX_MQ_RING_COUNT; 993 descsz = sizeof(uint64_t); 994 } else { 995 count = IWM_RX_LEGACY_RING_COUNT; 996 descsz = sizeof(uint32_t); 997 } 998 999 /* Allocate RX descriptors (256-byte aligned). */ 1000 size = count * descsz; 1001 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->free_desc_dma, size, 1002 256); 1003 if (error != 0) { 1004 device_printf(sc->sc_dev, 1005 "could not allocate RX ring DMA memory\n"); 1006 goto fail; 1007 } 1008 ring->desc = ring->free_desc_dma.vaddr; 1009 1010 /* Allocate RX status area (16-byte aligned). */ 1011 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1012 sizeof(*ring->stat), 16); 1013 if (error != 0) { 1014 device_printf(sc->sc_dev, 1015 "could not allocate RX status DMA memory\n"); 1016 goto fail; 1017 } 1018 ring->stat = ring->stat_dma.vaddr; 1019 1020 if (sc->cfg->mqrx_supported) { 1021 size = count * sizeof(uint32_t); 1022 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->used_desc_dma, 1023 size, 256); 1024 if (error != 0) { 1025 device_printf(sc->sc_dev, 1026 "could not allocate RX ring DMA memory\n"); 1027 goto fail; 1028 } 1029 } 1030 1031 /* Create RX buffer DMA tag. */ 1032 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1033 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1034 IWM_RBUF_SIZE, 1, IWM_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat); 1035 if (error != 0) { 1036 device_printf(sc->sc_dev, 1037 "%s: could not create RX buf DMA tag, error %d\n", 1038 __func__, error); 1039 goto fail; 1040 } 1041 1042 /* Allocate spare bus_dmamap_t for iwm_rx_addbuf() */ 1043 error = bus_dmamap_create(ring->data_dmat, 0, &ring->spare_map); 1044 if (error != 0) { 1045 device_printf(sc->sc_dev, 1046 "%s: could not create RX buf DMA map, error %d\n", 1047 __func__, error); 1048 goto fail; 1049 } 1050 1051 /* 1052 * Allocate and map RX buffers. 1053 */ 1054 for (i = 0; i < count; i++) { 1055 struct iwm_rx_data *data = &ring->data[i]; 1056 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1057 if (error != 0) { 1058 device_printf(sc->sc_dev, 1059 "%s: could not create RX buf DMA map, error %d\n", 1060 __func__, error); 1061 goto fail; 1062 } 1063 data->m = NULL; 1064 1065 if ((error = iwm_rx_addbuf(sc, IWM_RBUF_SIZE, i)) != 0) { 1066 goto fail; 1067 } 1068 } 1069 return 0; 1070 1071 fail: iwm_free_rx_ring(sc, ring); 1072 return error; 1073 } 1074 1075 static void 1076 iwm_reset_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 1077 { 1078 /* Reset the ring state */ 1079 ring->cur = 0; 1080 1081 /* 1082 * The hw rx ring index in shared memory must also be cleared, 1083 * otherwise the discrepancy can cause reprocessing chaos. 1084 */ 1085 if (sc->rxq.stat) 1086 memset(sc->rxq.stat, 0, sizeof(*sc->rxq.stat)); 1087 } 1088 1089 static void 1090 iwm_free_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 1091 { 1092 int count, i; 1093 1094 iwm_dma_contig_free(&ring->free_desc_dma); 1095 iwm_dma_contig_free(&ring->stat_dma); 1096 iwm_dma_contig_free(&ring->used_desc_dma); 1097 1098 count = sc->cfg->mqrx_supported ? IWM_RX_MQ_RING_COUNT : 1099 IWM_RX_LEGACY_RING_COUNT; 1100 1101 for (i = 0; i < count; i++) { 1102 struct iwm_rx_data *data = &ring->data[i]; 1103 1104 if (data->m != NULL) { 1105 bus_dmamap_sync(ring->data_dmat, data->map, 1106 BUS_DMASYNC_POSTREAD); 1107 bus_dmamap_unload(ring->data_dmat, data->map); 1108 m_freem(data->m); 1109 data->m = NULL; 1110 } 1111 if (data->map != NULL) { 1112 bus_dmamap_destroy(ring->data_dmat, data->map); 1113 data->map = NULL; 1114 } 1115 } 1116 if (ring->spare_map != NULL) { 1117 bus_dmamap_destroy(ring->data_dmat, ring->spare_map); 1118 ring->spare_map = NULL; 1119 } 1120 if (ring->data_dmat != NULL) { 1121 bus_dma_tag_destroy(ring->data_dmat); 1122 ring->data_dmat = NULL; 1123 } 1124 } 1125 1126 static int 1127 iwm_alloc_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring, int qid) 1128 { 1129 bus_addr_t paddr; 1130 bus_size_t size; 1131 size_t maxsize; 1132 int nsegments; 1133 int i, error; 1134 1135 ring->qid = qid; 1136 ring->queued = 0; 1137 ring->cur = 0; 1138 1139 /* Allocate TX descriptors (256-byte aligned). */ 1140 size = IWM_TX_RING_COUNT * sizeof (struct iwm_tfd); 1141 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, size, 256); 1142 if (error != 0) { 1143 device_printf(sc->sc_dev, 1144 "could not allocate TX ring DMA memory\n"); 1145 goto fail; 1146 } 1147 ring->desc = ring->desc_dma.vaddr; 1148 1149 /* 1150 * There is no need to allocate DMA buffers for unused rings. 1151 * 7k/8k/9k hardware supports up to 31 Tx rings which is more 1152 * than we currently need. 1153 * 1154 * In DQA mode we use 1 command queue + 4 DQA mgmt/data queues. 1155 * The command is queue 0 (sc->txq[0]), and 4 mgmt/data frame queues 1156 * are sc->tqx[IWM_DQA_MIN_MGMT_QUEUE + ac], i.e. sc->txq[5:8], 1157 * in order to provide one queue per EDCA category. 1158 * Tx aggregation requires additional queues, one queue per TID for 1159 * which aggregation is enabled. We map TID 0-7 to sc->txq[10:17]. 1160 * 1161 * In non-DQA mode, we use rings 0 through 9 (0-3 are EDCA, 9 is cmd), 1162 * and Tx aggregation is not supported. 1163 * 1164 * Unfortunately, we cannot tell if DQA will be used until the 1165 * firmware gets loaded later, so just allocate sufficient rings 1166 * in order to satisfy both cases. 1167 */ 1168 if (qid > IWM_LAST_AGG_TX_QUEUE) 1169 return 0; 1170 1171 size = IWM_TX_RING_COUNT * sizeof(struct iwm_device_cmd); 1172 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, size, 4); 1173 if (error != 0) { 1174 device_printf(sc->sc_dev, 1175 "could not allocate TX cmd DMA memory\n"); 1176 goto fail; 1177 } 1178 ring->cmd = ring->cmd_dma.vaddr; 1179 1180 /* 1181 * FW commands may require more mapped space than packets. The 1182 * DQA command queue is ring 0 and we can't tell at allocation 1183 * time which command queue id will be used, so give both the 1184 * command-sized DMA tag. 1185 */ 1186 if (qid == IWM_CMD_QUEUE || qid == IWM_DQA_CMD_QUEUE) { 1187 maxsize = IWM_RBUF_SIZE; 1188 nsegments = 1; 1189 } else { 1190 maxsize = MCLBYTES; 1191 nsegments = IWM_MAX_SCATTER - 2; 1192 } 1193 1194 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1195 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1196 nsegments, maxsize, 0, NULL, NULL, &ring->data_dmat); 1197 if (error != 0) { 1198 device_printf(sc->sc_dev, "could not create TX buf DMA tag\n"); 1199 goto fail; 1200 } 1201 1202 paddr = ring->cmd_dma.paddr; 1203 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1204 struct iwm_tx_data *data = &ring->data[i]; 1205 1206 data->cmd_paddr = paddr; 1207 data->scratch_paddr = paddr + sizeof(struct iwm_cmd_header) 1208 + offsetof(struct iwm_tx_cmd, scratch); 1209 paddr += sizeof(struct iwm_device_cmd); 1210 1211 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1212 if (error != 0) { 1213 device_printf(sc->sc_dev, 1214 "could not create TX buf DMA map\n"); 1215 goto fail; 1216 } 1217 } 1218 KASSERT(paddr == ring->cmd_dma.paddr + size, 1219 ("invalid physical address")); 1220 return 0; 1221 1222 fail: iwm_free_tx_ring(sc, ring); 1223 return error; 1224 } 1225 1226 static void 1227 iwm_reset_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring) 1228 { 1229 int i; 1230 1231 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1232 struct iwm_tx_data *data = &ring->data[i]; 1233 1234 if (data->m != NULL) { 1235 bus_dmamap_sync(ring->data_dmat, data->map, 1236 BUS_DMASYNC_POSTWRITE); 1237 bus_dmamap_unload(ring->data_dmat, data->map); 1238 m_freem(data->m); 1239 data->m = NULL; 1240 } 1241 } 1242 /* Clear TX descriptors. */ 1243 memset(ring->desc, 0, ring->desc_dma.size); 1244 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1245 BUS_DMASYNC_PREWRITE); 1246 sc->qfullmsk &= ~(1 << ring->qid); 1247 ring->queued = 0; 1248 ring->cur = 0; 1249 1250 if (ring->qid == sc->cmdqid && sc->cmd_hold_nic_awake) 1251 iwm_pcie_clear_cmd_in_flight(sc); 1252 } 1253 1254 static void 1255 iwm_free_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring) 1256 { 1257 int i; 1258 1259 iwm_dma_contig_free(&ring->desc_dma); 1260 iwm_dma_contig_free(&ring->cmd_dma); 1261 1262 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1263 struct iwm_tx_data *data = &ring->data[i]; 1264 1265 if (data->m != NULL) { 1266 bus_dmamap_sync(ring->data_dmat, data->map, 1267 BUS_DMASYNC_POSTWRITE); 1268 bus_dmamap_unload(ring->data_dmat, data->map); 1269 m_freem(data->m); 1270 data->m = NULL; 1271 } 1272 if (data->map != NULL) { 1273 bus_dmamap_destroy(ring->data_dmat, data->map); 1274 data->map = NULL; 1275 } 1276 } 1277 if (ring->data_dmat != NULL) { 1278 bus_dma_tag_destroy(ring->data_dmat); 1279 ring->data_dmat = NULL; 1280 } 1281 } 1282 1283 /* 1284 * High-level hardware frobbing routines 1285 */ 1286 1287 static void 1288 iwm_enable_interrupts(struct iwm_softc *sc) 1289 { 1290 if (!sc->sc_msix) { 1291 sc->sc_intmask = IWM_CSR_INI_SET_MASK; 1292 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 1293 } else { 1294 /* 1295 * fh/hw_mask keeps all the unmasked causes. 1296 * Unlike msi, in msix cause is enabled when it is unset. 1297 */ 1298 sc->sc_hw_mask = sc->sc_hw_init_mask; 1299 sc->sc_fh_mask = sc->sc_fh_init_mask; 1300 IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD, 1301 ~sc->sc_fh_mask); 1302 IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD, 1303 ~sc->sc_hw_mask); 1304 } 1305 } 1306 1307 static void 1308 iwm_restore_interrupts(struct iwm_softc *sc) 1309 { 1310 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 1311 } 1312 1313 static void 1314 iwm_disable_interrupts(struct iwm_softc *sc) 1315 { 1316 if (!sc->sc_msix) { 1317 /* disable interrupts */ 1318 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0); 1319 1320 /* acknowledge all interrupts */ 1321 IWM_WRITE(sc, IWM_CSR_INT, ~0); 1322 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, ~0); 1323 } else { 1324 IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD, 1325 sc->sc_fh_init_mask); 1326 IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD, 1327 sc->sc_hw_init_mask); 1328 } 1329 } 1330 1331 static void 1332 iwm_ict_reset(struct iwm_softc *sc) 1333 { 1334 iwm_disable_interrupts(sc); 1335 1336 /* Reset ICT table. */ 1337 memset(sc->ict_dma.vaddr, 0, IWM_ICT_SIZE); 1338 sc->ict_cur = 0; 1339 1340 /* Set physical address of ICT table (4KB aligned). */ 1341 IWM_WRITE(sc, IWM_CSR_DRAM_INT_TBL_REG, 1342 IWM_CSR_DRAM_INT_TBL_ENABLE 1343 | IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER 1344 | IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK 1345 | sc->ict_dma.paddr >> IWM_ICT_PADDR_SHIFT); 1346 1347 /* Switch to ICT interrupt mode in driver. */ 1348 sc->sc_flags |= IWM_FLAG_USE_ICT; 1349 1350 /* Re-enable interrupts. */ 1351 IWM_WRITE(sc, IWM_CSR_INT, ~0); 1352 iwm_enable_interrupts(sc); 1353 } 1354 1355 /* iwlwifi pcie/trans.c */ 1356 1357 /* 1358 * Since this .. hard-resets things, it's time to actually 1359 * mark the first vap (if any) as having no mac context. 1360 * It's annoying, but since the driver is potentially being 1361 * stop/start'ed whilst active (thanks openbsd port!) we 1362 * have to correctly track this. 1363 */ 1364 static void 1365 iwm_stop_device(struct iwm_softc *sc) 1366 { 1367 struct ieee80211com *ic = &sc->sc_ic; 1368 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1369 int chnl, qid; 1370 uint32_t mask = 0; 1371 1372 /* tell the device to stop sending interrupts */ 1373 iwm_disable_interrupts(sc); 1374 1375 /* 1376 * FreeBSD-local: mark the first vap as not-uploaded, 1377 * so the next transition through auth/assoc 1378 * will correctly populate the MAC context. 1379 */ 1380 if (vap) { 1381 struct iwm_vap *iv = IWM_VAP(vap); 1382 iv->phy_ctxt = NULL; 1383 iv->is_uploaded = 0; 1384 } 1385 sc->sc_firmware_state = 0; 1386 sc->sc_flags &= ~IWM_FLAG_TE_ACTIVE; 1387 1388 /* device going down, Stop using ICT table */ 1389 sc->sc_flags &= ~IWM_FLAG_USE_ICT; 1390 1391 /* stop tx and rx. tx and rx bits, as usual, are from if_iwn */ 1392 1393 if (iwm_nic_lock(sc)) { 1394 iwm_write_prph(sc, IWM_SCD_TXFACT, 0); 1395 1396 /* Stop each Tx DMA channel */ 1397 for (chnl = 0; chnl < IWM_FH_TCSR_CHNL_NUM; chnl++) { 1398 IWM_WRITE(sc, 1399 IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl), 0); 1400 mask |= IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(chnl); 1401 } 1402 1403 /* Wait for DMA channels to be idle */ 1404 if (!iwm_poll_bit(sc, IWM_FH_TSSR_TX_STATUS_REG, mask, mask, 1405 5000)) { 1406 device_printf(sc->sc_dev, 1407 "Failing on timeout while stopping DMA channel: [0x%08x]\n", 1408 IWM_READ(sc, IWM_FH_TSSR_TX_STATUS_REG)); 1409 } 1410 iwm_nic_unlock(sc); 1411 } 1412 iwm_pcie_rx_stop(sc); 1413 1414 /* Stop RX ring. */ 1415 iwm_reset_rx_ring(sc, &sc->rxq); 1416 1417 /* Reset all TX rings. */ 1418 for (qid = 0; qid < nitems(sc->txq); qid++) 1419 iwm_reset_tx_ring(sc, &sc->txq[qid]); 1420 1421 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 1422 /* Power-down device's busmaster DMA clocks */ 1423 if (iwm_nic_lock(sc)) { 1424 iwm_write_prph(sc, IWM_APMG_CLK_DIS_REG, 1425 IWM_APMG_CLK_VAL_DMA_CLK_RQT); 1426 iwm_nic_unlock(sc); 1427 } 1428 DELAY(5); 1429 } 1430 1431 /* Make sure (redundant) we've released our request to stay awake */ 1432 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 1433 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1434 1435 /* Stop the device, and put it in low power state */ 1436 iwm_apm_stop(sc); 1437 1438 /* stop and reset the on-board processor */ 1439 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET); 1440 DELAY(5000); 1441 1442 /* 1443 * Upon stop, the IVAR table gets erased, so msi-x won't 1444 * work. This causes a bug in RF-KILL flows, since the interrupt 1445 * that enables radio won't fire on the correct irq, and the 1446 * driver won't be able to handle the interrupt. 1447 * Configure the IVAR table again after reset. 1448 */ 1449 iwm_conf_msix_hw(sc, 1); 1450 1451 /* 1452 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1453 * Clear the interrupt again. 1454 */ 1455 iwm_disable_interrupts(sc); 1456 1457 /* 1458 * Even if we stop the HW, we still want the RF kill 1459 * interrupt 1460 */ 1461 iwm_enable_rfkill_int(sc); 1462 iwm_check_rfkill(sc); 1463 1464 iwm_prepare_card_hw(sc); 1465 } 1466 1467 /* iwlwifi: mvm/ops.c */ 1468 static void 1469 iwm_nic_config(struct iwm_softc *sc) 1470 { 1471 uint8_t radio_cfg_type, radio_cfg_step, radio_cfg_dash; 1472 uint32_t mask, val, reg_val = 0; 1473 uint32_t phy_config = iwm_get_phy_config(sc); 1474 1475 radio_cfg_type = (phy_config & IWM_FW_PHY_CFG_RADIO_TYPE) >> 1476 IWM_FW_PHY_CFG_RADIO_TYPE_POS; 1477 radio_cfg_step = (phy_config & IWM_FW_PHY_CFG_RADIO_STEP) >> 1478 IWM_FW_PHY_CFG_RADIO_STEP_POS; 1479 radio_cfg_dash = (phy_config & IWM_FW_PHY_CFG_RADIO_DASH) >> 1480 IWM_FW_PHY_CFG_RADIO_DASH_POS; 1481 1482 /* SKU control */ 1483 reg_val |= IWM_CSR_HW_REV_STEP(sc->sc_hw_rev) << 1484 IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP; 1485 reg_val |= IWM_CSR_HW_REV_DASH(sc->sc_hw_rev) << 1486 IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH; 1487 1488 /* radio configuration */ 1489 reg_val |= radio_cfg_type << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE; 1490 reg_val |= radio_cfg_step << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP; 1491 reg_val |= radio_cfg_dash << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH; 1492 1493 mask = IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH | 1494 IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP | 1495 IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP | 1496 IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH | 1497 IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE | 1498 IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 1499 IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI; 1500 1501 val = IWM_READ(sc, IWM_CSR_HW_IF_CONFIG_REG); 1502 val &= ~mask; 1503 val |= reg_val; 1504 IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, val); 1505 1506 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1507 "Radio type=0x%x-0x%x-0x%x\n", radio_cfg_type, 1508 radio_cfg_step, radio_cfg_dash); 1509 1510 /* 1511 * W/A : NIC is stuck in a reset state after Early PCIe power off 1512 * (PCIe power is lost before PERST# is asserted), causing ME FW 1513 * to lose ownership and not being able to obtain it back. 1514 */ 1515 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 1516 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 1517 IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 1518 ~IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 1519 } 1520 } 1521 1522 static int 1523 iwm_nic_rx_mq_init(struct iwm_softc *sc) 1524 { 1525 int enabled; 1526 1527 if (!iwm_nic_lock(sc)) 1528 return EBUSY; 1529 1530 /* Stop RX DMA. */ 1531 iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG, 0); 1532 /* Disable RX used and free queue operation. */ 1533 iwm_write_prph(sc, IWM_RFH_RXF_RXQ_ACTIVE, 0); 1534 1535 iwm_write_prph64(sc, IWM_RFH_Q0_FRBDCB_BA_LSB, 1536 sc->rxq.free_desc_dma.paddr); 1537 iwm_write_prph64(sc, IWM_RFH_Q0_URBDCB_BA_LSB, 1538 sc->rxq.used_desc_dma.paddr); 1539 iwm_write_prph64(sc, IWM_RFH_Q0_URBD_STTS_WPTR_LSB, 1540 sc->rxq.stat_dma.paddr); 1541 iwm_write_prph(sc, IWM_RFH_Q0_FRBDCB_WIDX, 0); 1542 iwm_write_prph(sc, IWM_RFH_Q0_FRBDCB_RIDX, 0); 1543 iwm_write_prph(sc, IWM_RFH_Q0_URBDCB_WIDX, 0); 1544 1545 /* We configure only queue 0 for now. */ 1546 enabled = ((1 << 0) << 16) | (1 << 0); 1547 1548 /* Enable RX DMA, 4KB buffer size. */ 1549 iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG, 1550 IWM_RFH_DMA_EN_ENABLE_VAL | 1551 IWM_RFH_RXF_DMA_RB_SIZE_4K | 1552 IWM_RFH_RXF_DMA_MIN_RB_4_8 | 1553 IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 1554 IWM_RFH_RXF_DMA_RBDCB_SIZE_512); 1555 1556 /* Enable RX DMA snooping. */ 1557 iwm_write_prph(sc, IWM_RFH_GEN_CFG, 1558 IWM_RFH_GEN_CFG_RFH_DMA_SNOOP | 1559 IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP | 1560 (sc->cfg->integrated ? IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 1561 IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 1562 1563 /* Enable the configured queue(s). */ 1564 iwm_write_prph(sc, IWM_RFH_RXF_RXQ_ACTIVE, enabled); 1565 1566 iwm_nic_unlock(sc); 1567 1568 IWM_WRITE_1(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_TIMEOUT_DEF); 1569 1570 IWM_WRITE(sc, IWM_RFH_Q0_FRBDCB_WIDX_TRG, 8); 1571 1572 return (0); 1573 } 1574 1575 static int 1576 iwm_nic_rx_legacy_init(struct iwm_softc *sc) 1577 { 1578 1579 /* Stop Rx DMA */ 1580 iwm_pcie_rx_stop(sc); 1581 1582 if (!iwm_nic_lock(sc)) 1583 return EBUSY; 1584 1585 /* reset and flush pointers */ 1586 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 1587 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 1588 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RDPTR, 0); 1589 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 1590 1591 /* Set physical address of RX ring (256-byte aligned). */ 1592 IWM_WRITE(sc, 1593 IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG, 1594 sc->rxq.free_desc_dma.paddr >> 8); 1595 1596 /* Set physical address of RX status (16-byte aligned). */ 1597 IWM_WRITE(sc, 1598 IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG, sc->rxq.stat_dma.paddr >> 4); 1599 1600 /* Enable Rx DMA 1601 * XXX 5000 HW isn't supported by the iwm(4) driver. 1602 * IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 1603 * the credit mechanism in 5000 HW RX FIFO 1604 * Direct rx interrupts to hosts 1605 * Rx buffer size 4 or 8k or 12k 1606 * RB timeout 0x10 1607 * 256 RBDs 1608 */ 1609 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 1610 IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 1611 IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | /* HW bug */ 1612 IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 1613 IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K | 1614 (IWM_RX_RB_TIMEOUT << IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 1615 IWM_RX_QUEUE_SIZE_LOG << IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS); 1616 1617 IWM_WRITE_1(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_TIMEOUT_DEF); 1618 1619 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 1620 if (sc->cfg->host_interrupt_operation_mode) 1621 IWM_SETBITS(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_OPER_MODE); 1622 1623 iwm_nic_unlock(sc); 1624 1625 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, 8); 1626 1627 return 0; 1628 } 1629 1630 static int 1631 iwm_nic_rx_init(struct iwm_softc *sc) 1632 { 1633 if (sc->cfg->mqrx_supported) 1634 return iwm_nic_rx_mq_init(sc); 1635 else 1636 return iwm_nic_rx_legacy_init(sc); 1637 } 1638 1639 static int 1640 iwm_nic_tx_init(struct iwm_softc *sc) 1641 { 1642 int qid; 1643 1644 if (!iwm_nic_lock(sc)) 1645 return EBUSY; 1646 1647 /* Deactivate TX scheduler. */ 1648 iwm_write_prph(sc, IWM_SCD_TXFACT, 0); 1649 1650 /* Set physical address of "keep warm" page (16-byte aligned). */ 1651 IWM_WRITE(sc, IWM_FH_KW_MEM_ADDR_REG, sc->kw_dma.paddr >> 4); 1652 1653 /* Initialize TX rings. */ 1654 for (qid = 0; qid < nitems(sc->txq); qid++) { 1655 struct iwm_tx_ring *txq = &sc->txq[qid]; 1656 1657 /* Set physical address of TX ring (256-byte aligned). */ 1658 IWM_WRITE(sc, IWM_FH_MEM_CBBC_QUEUE(qid), 1659 txq->desc_dma.paddr >> 8); 1660 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 1661 "%s: loading ring %d descriptors (%p) at %lx\n", 1662 __func__, 1663 qid, txq->desc, 1664 (unsigned long) (txq->desc_dma.paddr >> 8)); 1665 } 1666 1667 iwm_set_bits_prph(sc, IWM_SCD_GP_CTRL, 1668 IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE | 1669 IWM_SCD_GP_CTRL_ENABLE_31_QUEUES); 1670 1671 iwm_nic_unlock(sc); 1672 1673 return 0; 1674 } 1675 1676 static int 1677 iwm_nic_init(struct iwm_softc *sc) 1678 { 1679 int error; 1680 1681 iwm_apm_init(sc); 1682 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) 1683 iwm_set_pwr(sc); 1684 1685 iwm_nic_config(sc); 1686 1687 if ((error = iwm_nic_rx_init(sc)) != 0) 1688 return error; 1689 1690 /* 1691 * Ditto for TX, from iwn 1692 */ 1693 if ((error = iwm_nic_tx_init(sc)) != 0) 1694 return error; 1695 1696 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1697 "%s: shadow registers enabled\n", __func__); 1698 IWM_SETBITS(sc, IWM_CSR_MAC_SHADOW_REG_CTRL, 0x800fffff); 1699 1700 return 0; 1701 } 1702 1703 int 1704 iwm_enable_txq(struct iwm_softc *sc, int sta_id, int qid, int fifo) 1705 { 1706 int qmsk; 1707 1708 qmsk = 1 << qid; 1709 1710 if (!iwm_nic_lock(sc)) { 1711 device_printf(sc->sc_dev, "%s: cannot enable txq %d\n", 1712 __func__, qid); 1713 return EBUSY; 1714 } 1715 1716 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | 0); 1717 1718 if (qid == sc->cmdqid) { 1719 #if 0 1720 /* Disable the scheduler. */ 1721 iwm_write_prph(sc, IWM_SCD_EN_CTRL, 0); 1722 #endif 1723 1724 /* Stop the TX queue prior to configuration. */ 1725 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1726 (0 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1727 (1 << IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 1728 1729 iwm_nic_unlock(sc); 1730 1731 /* Disable aggregations for this queue. */ 1732 iwm_clear_bits_prph(sc, IWM_SCD_AGGR_SEL, qmsk); 1733 1734 if (!iwm_nic_lock(sc)) { 1735 device_printf(sc->sc_dev, 1736 "%s: cannot enable txq %d\n", __func__, qid); 1737 return EBUSY; 1738 } 1739 iwm_write_prph(sc, IWM_SCD_QUEUE_RDPTR(qid), 0); 1740 iwm_nic_unlock(sc); 1741 1742 iwm_write_mem32(sc, 1743 sc->scd_base_addr + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid), 0); 1744 /* Set scheduler window size and frame limit. */ 1745 iwm_write_mem32(sc, 1746 sc->scd_base_addr + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid) + 1747 sizeof(uint32_t), 1748 ((IWM_FRAME_LIMIT << IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1749 IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1750 ((IWM_FRAME_LIMIT << IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1751 IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1752 1753 if (!iwm_nic_lock(sc)) { 1754 device_printf(sc->sc_dev, 1755 "%s: cannot enable txq %d\n", __func__, qid); 1756 return EBUSY; 1757 } 1758 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1759 (1 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1760 (fifo << IWM_SCD_QUEUE_STTS_REG_POS_TXF) | 1761 (1 << IWM_SCD_QUEUE_STTS_REG_POS_WSL) | 1762 IWM_SCD_QUEUE_STTS_REG_MSK); 1763 1764 /* Enable the scheduler for this queue. */ 1765 iwm_write_prph(sc, IWM_SCD_EN_CTRL, 1766 iwm_read_prph(sc, IWM_SCD_EN_CTRL) | qmsk); 1767 } else { 1768 struct iwm_scd_txq_cfg_cmd cmd; 1769 int error; 1770 1771 iwm_nic_unlock(sc); 1772 1773 memset(&cmd, 0, sizeof(cmd)); 1774 cmd.scd_queue = qid; 1775 cmd.enable = 1; 1776 cmd.sta_id = sta_id; 1777 cmd.tx_fifo = fifo; 1778 cmd.aggregate = 0; 1779 cmd.window = IWM_FRAME_LIMIT; 1780 1781 error = iwm_send_cmd_pdu(sc, IWM_SCD_QUEUE_CFG, IWM_CMD_SYNC, 1782 sizeof(cmd), &cmd); 1783 if (error) { 1784 device_printf(sc->sc_dev, 1785 "cannot enable txq %d\n", qid); 1786 return error; 1787 } 1788 1789 if (!iwm_nic_lock(sc)) 1790 return EBUSY; 1791 } 1792 1793 iwm_nic_unlock(sc); 1794 1795 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, "%s: enabled txq %d FIFO %d\n", 1796 __func__, qid, fifo); 1797 1798 return 0; 1799 } 1800 1801 static int 1802 iwm_trans_pcie_fw_alive(struct iwm_softc *sc, uint32_t scd_base_addr) 1803 { 1804 int error, chnl; 1805 1806 int clear_dwords = (IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND - 1807 IWM_SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(uint32_t); 1808 1809 if (!iwm_nic_lock(sc)) 1810 return EBUSY; 1811 1812 iwm_ict_reset(sc); 1813 1814 sc->scd_base_addr = iwm_read_prph(sc, IWM_SCD_SRAM_BASE_ADDR); 1815 if (scd_base_addr != 0 && 1816 scd_base_addr != sc->scd_base_addr) { 1817 device_printf(sc->sc_dev, 1818 "%s: sched addr mismatch: alive: 0x%x prph: 0x%x\n", 1819 __func__, sc->scd_base_addr, scd_base_addr); 1820 } 1821 1822 iwm_nic_unlock(sc); 1823 1824 /* reset context data, TX status and translation data */ 1825 error = iwm_write_mem(sc, 1826 sc->scd_base_addr + IWM_SCD_CONTEXT_MEM_LOWER_BOUND, 1827 NULL, clear_dwords); 1828 if (error) 1829 return EBUSY; 1830 1831 if (!iwm_nic_lock(sc)) 1832 return EBUSY; 1833 1834 /* Set physical address of TX scheduler rings (1KB aligned). */ 1835 iwm_write_prph(sc, IWM_SCD_DRAM_BASE_ADDR, sc->sched_dma.paddr >> 10); 1836 1837 iwm_write_prph(sc, IWM_SCD_CHAINEXT_EN, 0); 1838 1839 iwm_nic_unlock(sc); 1840 1841 /* enable command channel */ 1842 error = iwm_enable_txq(sc, 0 /* unused */, sc->cmdqid, 1843 IWM_TX_FIFO_CMD); 1844 if (error) 1845 return error; 1846 1847 if (!iwm_nic_lock(sc)) 1848 return EBUSY; 1849 1850 iwm_write_prph(sc, IWM_SCD_TXFACT, 0xff); 1851 1852 /* Enable DMA channels. */ 1853 for (chnl = 0; chnl < IWM_FH_TCSR_CHNL_NUM; chnl++) { 1854 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl), 1855 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1856 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 1857 } 1858 1859 IWM_SETBITS(sc, IWM_FH_TX_CHICKEN_BITS_REG, 1860 IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 1861 1862 iwm_nic_unlock(sc); 1863 1864 /* Enable L1-Active */ 1865 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 1866 iwm_clear_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 1867 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 1868 } 1869 1870 return error; 1871 } 1872 1873 /* 1874 * NVM read access and content parsing. We do not support 1875 * external NVM or writing NVM. 1876 * iwlwifi/mvm/nvm.c 1877 */ 1878 1879 /* Default NVM size to read */ 1880 #define IWM_NVM_DEFAULT_CHUNK_SIZE (2*1024) 1881 1882 #define IWM_NVM_WRITE_OPCODE 1 1883 #define IWM_NVM_READ_OPCODE 0 1884 1885 /* load nvm chunk response */ 1886 enum { 1887 IWM_READ_NVM_CHUNK_SUCCEED = 0, 1888 IWM_READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 1889 }; 1890 1891 static int 1892 iwm_nvm_read_chunk(struct iwm_softc *sc, uint16_t section, 1893 uint16_t offset, uint16_t length, uint8_t *data, uint16_t *len) 1894 { 1895 struct iwm_nvm_access_cmd nvm_access_cmd = { 1896 .offset = htole16(offset), 1897 .length = htole16(length), 1898 .type = htole16(section), 1899 .op_code = IWM_NVM_READ_OPCODE, 1900 }; 1901 struct iwm_nvm_access_resp *nvm_resp; 1902 struct iwm_rx_packet *pkt; 1903 struct iwm_host_cmd cmd = { 1904 .id = IWM_NVM_ACCESS_CMD, 1905 .flags = IWM_CMD_WANT_SKB | IWM_CMD_SEND_IN_RFKILL, 1906 .data = { &nvm_access_cmd, }, 1907 }; 1908 int ret, bytes_read, offset_read; 1909 uint8_t *resp_data; 1910 1911 cmd.len[0] = sizeof(struct iwm_nvm_access_cmd); 1912 1913 ret = iwm_send_cmd(sc, &cmd); 1914 if (ret) { 1915 device_printf(sc->sc_dev, 1916 "Could not send NVM_ACCESS command (error=%d)\n", ret); 1917 return ret; 1918 } 1919 1920 pkt = cmd.resp_pkt; 1921 1922 /* Extract NVM response */ 1923 nvm_resp = (void *)pkt->data; 1924 ret = le16toh(nvm_resp->status); 1925 bytes_read = le16toh(nvm_resp->length); 1926 offset_read = le16toh(nvm_resp->offset); 1927 resp_data = nvm_resp->data; 1928 if (ret) { 1929 if ((offset != 0) && 1930 (ret == IWM_READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { 1931 /* 1932 * meaning of NOT_VALID_ADDRESS: 1933 * driver try to read chunk from address that is 1934 * multiple of 2K and got an error since addr is empty. 1935 * meaning of (offset != 0): driver already 1936 * read valid data from another chunk so this case 1937 * is not an error. 1938 */ 1939 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 1940 "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", 1941 offset); 1942 *len = 0; 1943 ret = 0; 1944 } else { 1945 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 1946 "NVM access command failed with status %d\n", ret); 1947 ret = EIO; 1948 } 1949 goto exit; 1950 } 1951 1952 if (offset_read != offset) { 1953 device_printf(sc->sc_dev, 1954 "NVM ACCESS response with invalid offset %d\n", 1955 offset_read); 1956 ret = EINVAL; 1957 goto exit; 1958 } 1959 1960 if (bytes_read > length) { 1961 device_printf(sc->sc_dev, 1962 "NVM ACCESS response with too much data " 1963 "(%d bytes requested, %d bytes received)\n", 1964 length, bytes_read); 1965 ret = EINVAL; 1966 goto exit; 1967 } 1968 1969 /* Write data to NVM */ 1970 memcpy(data + offset, resp_data, bytes_read); 1971 *len = bytes_read; 1972 1973 exit: 1974 iwm_free_resp(sc, &cmd); 1975 return ret; 1976 } 1977 1978 /* 1979 * Reads an NVM section completely. 1980 * NICs prior to 7000 family don't have a real NVM, but just read 1981 * section 0 which is the EEPROM. Because the EEPROM reading is unlimited 1982 * by uCode, we need to manually check in this case that we don't 1983 * overflow and try to read more than the EEPROM size. 1984 * For 7000 family NICs, we supply the maximal size we can read, and 1985 * the uCode fills the response with as much data as we can, 1986 * without overflowing, so no check is needed. 1987 */ 1988 static int 1989 iwm_nvm_read_section(struct iwm_softc *sc, 1990 uint16_t section, uint8_t *data, uint16_t *len, uint32_t size_read) 1991 { 1992 uint16_t seglen, length, offset = 0; 1993 int ret; 1994 1995 /* Set nvm section read length */ 1996 length = IWM_NVM_DEFAULT_CHUNK_SIZE; 1997 1998 seglen = length; 1999 2000 /* Read the NVM until exhausted (reading less than requested) */ 2001 while (seglen == length) { 2002 /* Check no memory assumptions fail and cause an overflow */ 2003 if ((size_read + offset + length) > 2004 sc->cfg->eeprom_size) { 2005 device_printf(sc->sc_dev, 2006 "EEPROM size is too small for NVM\n"); 2007 return ENOBUFS; 2008 } 2009 2010 ret = iwm_nvm_read_chunk(sc, section, offset, length, data, &seglen); 2011 if (ret) { 2012 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 2013 "Cannot read NVM from section %d offset %d, length %d\n", 2014 section, offset, length); 2015 return ret; 2016 } 2017 offset += seglen; 2018 } 2019 2020 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 2021 "NVM section %d read completed\n", section); 2022 *len = offset; 2023 return 0; 2024 } 2025 2026 /* 2027 * BEGIN IWM_NVM_PARSE 2028 */ 2029 2030 /* iwlwifi/iwl-nvm-parse.c */ 2031 2032 /* 2033 * Translate EEPROM flags to net80211. 2034 */ 2035 static uint32_t 2036 iwm_eeprom_channel_flags(uint16_t ch_flags) 2037 { 2038 uint32_t nflags; 2039 2040 nflags = 0; 2041 if ((ch_flags & IWM_NVM_CHANNEL_ACTIVE) == 0) 2042 nflags |= IEEE80211_CHAN_PASSIVE; 2043 if ((ch_flags & IWM_NVM_CHANNEL_IBSS) == 0) 2044 nflags |= IEEE80211_CHAN_NOADHOC; 2045 if (ch_flags & IWM_NVM_CHANNEL_RADAR) { 2046 nflags |= IEEE80211_CHAN_DFS; 2047 /* Just in case. */ 2048 nflags |= IEEE80211_CHAN_NOADHOC; 2049 } 2050 2051 return (nflags); 2052 } 2053 2054 static void 2055 iwm_add_channel_band(struct iwm_softc *sc, struct ieee80211_channel chans[], 2056 int maxchans, int *nchans, int ch_idx, size_t ch_num, 2057 const uint8_t bands[]) 2058 { 2059 const uint16_t * const nvm_ch_flags = sc->nvm_data->nvm_ch_flags; 2060 uint32_t nflags; 2061 uint16_t ch_flags; 2062 uint8_t ieee; 2063 int error; 2064 2065 for (; ch_idx < ch_num; ch_idx++) { 2066 ch_flags = le16_to_cpup(nvm_ch_flags + ch_idx); 2067 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) 2068 ieee = iwm_nvm_channels[ch_idx]; 2069 else 2070 ieee = iwm_nvm_channels_8000[ch_idx]; 2071 2072 if (!(ch_flags & IWM_NVM_CHANNEL_VALID)) { 2073 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM, 2074 "Ch. %d Flags %x [%sGHz] - No traffic\n", 2075 ieee, ch_flags, 2076 (ch_idx >= IWM_NUM_2GHZ_CHANNELS) ? 2077 "5.2" : "2.4"); 2078 continue; 2079 } 2080 2081 nflags = iwm_eeprom_channel_flags(ch_flags); 2082 error = ieee80211_add_channel(chans, maxchans, nchans, 2083 ieee, 0, 0, nflags, bands); 2084 if (error != 0) 2085 break; 2086 2087 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM, 2088 "Ch. %d Flags %x [%sGHz] - Added\n", 2089 ieee, ch_flags, 2090 (ch_idx >= IWM_NUM_2GHZ_CHANNELS) ? 2091 "5.2" : "2.4"); 2092 } 2093 } 2094 2095 /* TODO: HT20 */ 2096 /* TODO: HT40 */ 2097 /* TODO: VHT20 */ 2098 /* TODO: VHT40, VHT80 */ 2099 2100 static void 2101 iwm_init_channel_map(struct ieee80211com *ic, int maxchans, int *nchans, 2102 struct ieee80211_channel chans[]) 2103 { 2104 struct iwm_softc *sc = ic->ic_softc; 2105 struct iwm_nvm_data *data = sc->nvm_data; 2106 uint8_t bands[IEEE80211_MODE_BYTES]; 2107 size_t ch_num; 2108 2109 memset(bands, 0, sizeof(bands)); 2110 /* 1-13: 11b/g channels. */ 2111 setbit(bands, IEEE80211_MODE_11B); 2112 setbit(bands, IEEE80211_MODE_11G); 2113 iwm_add_channel_band(sc, chans, maxchans, nchans, 0, 2114 IWM_NUM_2GHZ_CHANNELS - 1, bands); 2115 2116 /* 14: 11b channel only. */ 2117 clrbit(bands, IEEE80211_MODE_11G); 2118 iwm_add_channel_band(sc, chans, maxchans, nchans, 2119 IWM_NUM_2GHZ_CHANNELS - 1, IWM_NUM_2GHZ_CHANNELS, bands); 2120 2121 if (data->sku_cap_band_52GHz_enable) { 2122 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) 2123 ch_num = nitems(iwm_nvm_channels); 2124 else 2125 ch_num = nitems(iwm_nvm_channels_8000); 2126 memset(bands, 0, sizeof(bands)); 2127 setbit(bands, IEEE80211_MODE_11A); 2128 iwm_add_channel_band(sc, chans, maxchans, nchans, 2129 IWM_NUM_2GHZ_CHANNELS, ch_num, bands); 2130 } 2131 } 2132 2133 static int 2134 iwm_mimo_enabled(struct iwm_softc *sc) 2135 { 2136 return (!sc->nvm_data->sku_cap_mimo_disable); 2137 } 2138 2139 static void 2140 iwm_setup_ht_rates(struct iwm_softc *sc) 2141 { 2142 /* XXX TODO MCS0..7 */ 2143 2144 if (!iwm_mimo_enabled(sc)) 2145 return; 2146 2147 /* XXX TODO: MCS8..15 if >1 antenna and mimo enabled */ 2148 } 2149 2150 static void 2151 iwm_set_hw_address_family_8000(struct iwm_softc *sc, struct iwm_nvm_data *data, 2152 const uint16_t *mac_override, const uint16_t *nvm_hw) 2153 { 2154 const uint8_t *hw_addr; 2155 2156 if (mac_override) { 2157 static const uint8_t reserved_mac[] = { 2158 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 2159 }; 2160 2161 hw_addr = (const uint8_t *)(mac_override + 2162 IWM_MAC_ADDRESS_OVERRIDE_8000); 2163 2164 /* 2165 * Store the MAC address from MAO section. 2166 * No byte swapping is required in MAO section 2167 */ 2168 IEEE80211_ADDR_COPY(data->hw_addr, hw_addr); 2169 2170 /* 2171 * Force the use of the OTP MAC address in case of reserved MAC 2172 * address in the NVM, or if address is given but invalid. 2173 */ 2174 if (!IEEE80211_ADDR_EQ(reserved_mac, hw_addr) && 2175 !IEEE80211_ADDR_EQ(ieee80211broadcastaddr, data->hw_addr) && 2176 iwm_is_valid_ether_addr(data->hw_addr) && 2177 !IEEE80211_IS_MULTICAST(data->hw_addr)) 2178 return; 2179 2180 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2181 "%s: mac address from nvm override section invalid\n", 2182 __func__); 2183 } 2184 2185 if (nvm_hw) { 2186 /* read the mac address from WFMP registers */ 2187 uint32_t mac_addr0 = 2188 htole32(iwm_read_prph(sc, IWM_WFMP_MAC_ADDR_0)); 2189 uint32_t mac_addr1 = 2190 htole32(iwm_read_prph(sc, IWM_WFMP_MAC_ADDR_1)); 2191 2192 hw_addr = (const uint8_t *)&mac_addr0; 2193 data->hw_addr[0] = hw_addr[3]; 2194 data->hw_addr[1] = hw_addr[2]; 2195 data->hw_addr[2] = hw_addr[1]; 2196 data->hw_addr[3] = hw_addr[0]; 2197 2198 hw_addr = (const uint8_t *)&mac_addr1; 2199 data->hw_addr[4] = hw_addr[1]; 2200 data->hw_addr[5] = hw_addr[0]; 2201 2202 return; 2203 } 2204 2205 device_printf(sc->sc_dev, "%s: mac address not found\n", __func__); 2206 memset(data->hw_addr, 0, sizeof(data->hw_addr)); 2207 } 2208 2209 static int 2210 iwm_get_sku(const struct iwm_softc *sc, const uint16_t *nvm_sw, 2211 const uint16_t *phy_sku) 2212 { 2213 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) 2214 return le16_to_cpup(nvm_sw + IWM_SKU); 2215 2216 return le32_to_cpup((const uint32_t *)(phy_sku + IWM_SKU_8000)); 2217 } 2218 2219 static int 2220 iwm_get_nvm_version(const struct iwm_softc *sc, const uint16_t *nvm_sw) 2221 { 2222 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) 2223 return le16_to_cpup(nvm_sw + IWM_NVM_VERSION); 2224 else 2225 return le32_to_cpup((const uint32_t *)(nvm_sw + 2226 IWM_NVM_VERSION_8000)); 2227 } 2228 2229 static int 2230 iwm_get_radio_cfg(const struct iwm_softc *sc, const uint16_t *nvm_sw, 2231 const uint16_t *phy_sku) 2232 { 2233 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) 2234 return le16_to_cpup(nvm_sw + IWM_RADIO_CFG); 2235 2236 return le32_to_cpup((const uint32_t *)(phy_sku + IWM_RADIO_CFG_8000)); 2237 } 2238 2239 static int 2240 iwm_get_n_hw_addrs(const struct iwm_softc *sc, const uint16_t *nvm_sw) 2241 { 2242 int n_hw_addr; 2243 2244 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) 2245 return le16_to_cpup(nvm_sw + IWM_N_HW_ADDRS); 2246 2247 n_hw_addr = le32_to_cpup((const uint32_t *)(nvm_sw + IWM_N_HW_ADDRS_8000)); 2248 2249 return n_hw_addr & IWM_N_HW_ADDR_MASK; 2250 } 2251 2252 static void 2253 iwm_set_radio_cfg(const struct iwm_softc *sc, struct iwm_nvm_data *data, 2254 uint32_t radio_cfg) 2255 { 2256 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 2257 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK(radio_cfg); 2258 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK(radio_cfg); 2259 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK(radio_cfg); 2260 data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK(radio_cfg); 2261 return; 2262 } 2263 2264 /* set the radio configuration for family 8000 */ 2265 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK_8000(radio_cfg); 2266 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK_8000(radio_cfg); 2267 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK_8000(radio_cfg); 2268 data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK_8000(radio_cfg); 2269 data->valid_tx_ant = IWM_NVM_RF_CFG_TX_ANT_MSK_8000(radio_cfg); 2270 data->valid_rx_ant = IWM_NVM_RF_CFG_RX_ANT_MSK_8000(radio_cfg); 2271 } 2272 2273 static int 2274 iwm_set_hw_address(struct iwm_softc *sc, struct iwm_nvm_data *data, 2275 const uint16_t *nvm_hw, const uint16_t *mac_override) 2276 { 2277 #ifdef notyet /* for FAMILY 9000 */ 2278 if (cfg->mac_addr_from_csr) { 2279 iwm_set_hw_address_from_csr(sc, data); 2280 } else 2281 #endif 2282 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 2283 const uint8_t *hw_addr = (const uint8_t *)(nvm_hw + IWM_HW_ADDR); 2284 2285 /* The byte order is little endian 16 bit, meaning 214365 */ 2286 data->hw_addr[0] = hw_addr[1]; 2287 data->hw_addr[1] = hw_addr[0]; 2288 data->hw_addr[2] = hw_addr[3]; 2289 data->hw_addr[3] = hw_addr[2]; 2290 data->hw_addr[4] = hw_addr[5]; 2291 data->hw_addr[5] = hw_addr[4]; 2292 } else { 2293 iwm_set_hw_address_family_8000(sc, data, mac_override, nvm_hw); 2294 } 2295 2296 if (!iwm_is_valid_ether_addr(data->hw_addr)) { 2297 device_printf(sc->sc_dev, "no valid mac address was found\n"); 2298 return EINVAL; 2299 } 2300 2301 return 0; 2302 } 2303 2304 static struct iwm_nvm_data * 2305 iwm_parse_nvm_data(struct iwm_softc *sc, 2306 const uint16_t *nvm_hw, const uint16_t *nvm_sw, 2307 const uint16_t *nvm_calib, const uint16_t *mac_override, 2308 const uint16_t *phy_sku, const uint16_t *regulatory) 2309 { 2310 struct iwm_nvm_data *data; 2311 uint32_t sku, radio_cfg; 2312 uint16_t lar_config; 2313 2314 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 2315 data = malloc(sizeof(*data) + 2316 IWM_NUM_CHANNELS * sizeof(uint16_t), 2317 M_DEVBUF, M_NOWAIT | M_ZERO); 2318 } else { 2319 data = malloc(sizeof(*data) + 2320 IWM_NUM_CHANNELS_8000 * sizeof(uint16_t), 2321 M_DEVBUF, M_NOWAIT | M_ZERO); 2322 } 2323 if (!data) 2324 return NULL; 2325 2326 data->nvm_version = iwm_get_nvm_version(sc, nvm_sw); 2327 2328 radio_cfg = iwm_get_radio_cfg(sc, nvm_sw, phy_sku); 2329 iwm_set_radio_cfg(sc, data, radio_cfg); 2330 2331 sku = iwm_get_sku(sc, nvm_sw, phy_sku); 2332 data->sku_cap_band_24GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_24GHZ; 2333 data->sku_cap_band_52GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_52GHZ; 2334 data->sku_cap_11n_enable = sku & IWM_NVM_SKU_CAP_11N_ENABLE; 2335 data->sku_cap_mimo_disable = sku & IWM_NVM_SKU_CAP_MIMO_DISABLE; 2336 2337 data->n_hw_addrs = iwm_get_n_hw_addrs(sc, nvm_sw); 2338 2339 data->calib_version = 255; /* TODO: 2340 this value will prevent some checks from 2341 failing, we need to check if this 2342 field is still needed, and if it does, 2343 where is it in the NVM */ 2344 2345 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) { 2346 /* TODO: use IWL_NVM_EXT */ 2347 uint16_t lar_offset = data->nvm_version < 0xE39 ? 2348 IWM_NVM_LAR_OFFSET_8000_OLD : 2349 IWM_NVM_LAR_OFFSET_8000; 2350 2351 lar_config = le16_to_cpup(regulatory + lar_offset); 2352 data->lar_enabled = !!(lar_config & 2353 IWM_NVM_LAR_ENABLED_8000); 2354 } 2355 2356 /* If no valid mac address was found - bail out */ 2357 if (iwm_set_hw_address(sc, data, nvm_hw, mac_override)) { 2358 free(data, M_DEVBUF); 2359 return NULL; 2360 } 2361 2362 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 2363 memcpy(data->nvm_ch_flags, sc->cfg->nvm_type == IWM_NVM_SDP ? 2364 ®ulatory[0] : &nvm_sw[IWM_NVM_CHANNELS], 2365 IWM_NUM_CHANNELS * sizeof(uint16_t)); 2366 } else { 2367 memcpy(data->nvm_ch_flags, ®ulatory[IWM_NVM_CHANNELS_8000], 2368 IWM_NUM_CHANNELS_8000 * sizeof(uint16_t)); 2369 } 2370 2371 return data; 2372 } 2373 2374 static void 2375 iwm_free_nvm_data(struct iwm_nvm_data *data) 2376 { 2377 if (data != NULL) 2378 free(data, M_DEVBUF); 2379 } 2380 2381 static struct iwm_nvm_data * 2382 iwm_parse_nvm_sections(struct iwm_softc *sc, struct iwm_nvm_section *sections) 2383 { 2384 const uint16_t *hw, *sw, *calib, *regulatory, *mac_override, *phy_sku; 2385 2386 /* Checking for required sections */ 2387 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 2388 if (!sections[IWM_NVM_SECTION_TYPE_SW].data || 2389 !sections[sc->cfg->nvm_hw_section_num].data) { 2390 device_printf(sc->sc_dev, 2391 "Can't parse empty OTP/NVM sections\n"); 2392 return NULL; 2393 } 2394 } else if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) { 2395 /* SW and REGULATORY sections are mandatory */ 2396 if (!sections[IWM_NVM_SECTION_TYPE_SW].data || 2397 !sections[IWM_NVM_SECTION_TYPE_REGULATORY].data) { 2398 device_printf(sc->sc_dev, 2399 "Can't parse empty OTP/NVM sections\n"); 2400 return NULL; 2401 } 2402 /* MAC_OVERRIDE or at least HW section must exist */ 2403 if (!sections[sc->cfg->nvm_hw_section_num].data && 2404 !sections[IWM_NVM_SECTION_TYPE_MAC_OVERRIDE].data) { 2405 device_printf(sc->sc_dev, 2406 "Can't parse mac_address, empty sections\n"); 2407 return NULL; 2408 } 2409 2410 /* PHY_SKU section is mandatory in B0 */ 2411 if (!sections[IWM_NVM_SECTION_TYPE_PHY_SKU].data) { 2412 device_printf(sc->sc_dev, 2413 "Can't parse phy_sku in B0, empty sections\n"); 2414 return NULL; 2415 } 2416 } else { 2417 panic("unknown device family %d\n", sc->cfg->device_family); 2418 } 2419 2420 hw = (const uint16_t *) sections[sc->cfg->nvm_hw_section_num].data; 2421 sw = (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_SW].data; 2422 calib = (const uint16_t *) 2423 sections[IWM_NVM_SECTION_TYPE_CALIBRATION].data; 2424 regulatory = sc->cfg->nvm_type == IWM_NVM_SDP ? 2425 (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_REGULATORY_SDP].data : 2426 (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_REGULATORY].data; 2427 mac_override = (const uint16_t *) 2428 sections[IWM_NVM_SECTION_TYPE_MAC_OVERRIDE].data; 2429 phy_sku = (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_PHY_SKU].data; 2430 2431 return iwm_parse_nvm_data(sc, hw, sw, calib, mac_override, 2432 phy_sku, regulatory); 2433 } 2434 2435 static int 2436 iwm_nvm_init(struct iwm_softc *sc) 2437 { 2438 struct iwm_nvm_section nvm_sections[IWM_NVM_NUM_OF_SECTIONS]; 2439 int i, ret, section; 2440 uint32_t size_read = 0; 2441 uint8_t *nvm_buffer, *temp; 2442 uint16_t len; 2443 2444 memset(nvm_sections, 0, sizeof(nvm_sections)); 2445 2446 if (sc->cfg->nvm_hw_section_num >= IWM_NVM_NUM_OF_SECTIONS) 2447 return EINVAL; 2448 2449 /* load NVM values from nic */ 2450 /* Read From FW NVM */ 2451 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM, "Read from NVM\n"); 2452 2453 nvm_buffer = malloc(sc->cfg->eeprom_size, M_DEVBUF, M_NOWAIT | M_ZERO); 2454 if (!nvm_buffer) 2455 return ENOMEM; 2456 for (section = 0; section < IWM_NVM_NUM_OF_SECTIONS; section++) { 2457 /* we override the constness for initial read */ 2458 ret = iwm_nvm_read_section(sc, section, nvm_buffer, 2459 &len, size_read); 2460 if (ret) 2461 continue; 2462 size_read += len; 2463 temp = malloc(len, M_DEVBUF, M_NOWAIT); 2464 if (!temp) { 2465 ret = ENOMEM; 2466 break; 2467 } 2468 memcpy(temp, nvm_buffer, len); 2469 2470 nvm_sections[section].data = temp; 2471 nvm_sections[section].length = len; 2472 } 2473 if (!size_read) 2474 device_printf(sc->sc_dev, "OTP is blank\n"); 2475 free(nvm_buffer, M_DEVBUF); 2476 2477 sc->nvm_data = iwm_parse_nvm_sections(sc, nvm_sections); 2478 if (!sc->nvm_data) 2479 return EINVAL; 2480 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 2481 "nvm version = %x\n", sc->nvm_data->nvm_version); 2482 2483 for (i = 0; i < IWM_NVM_NUM_OF_SECTIONS; i++) { 2484 if (nvm_sections[i].data != NULL) 2485 free(nvm_sections[i].data, M_DEVBUF); 2486 } 2487 2488 return 0; 2489 } 2490 2491 static int 2492 iwm_pcie_load_section(struct iwm_softc *sc, uint8_t section_num, 2493 const struct iwm_fw_desc *section) 2494 { 2495 struct iwm_dma_info *dma = &sc->fw_dma; 2496 uint8_t *v_addr; 2497 bus_addr_t p_addr; 2498 uint32_t offset, chunk_sz = MIN(IWM_FH_MEM_TB_MAX_LENGTH, section->len); 2499 int ret = 0; 2500 2501 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2502 "%s: [%d] uCode section being loaded...\n", 2503 __func__, section_num); 2504 2505 v_addr = dma->vaddr; 2506 p_addr = dma->paddr; 2507 2508 for (offset = 0; offset < section->len; offset += chunk_sz) { 2509 uint32_t copy_size, dst_addr; 2510 int extended_addr = FALSE; 2511 2512 copy_size = MIN(chunk_sz, section->len - offset); 2513 dst_addr = section->offset + offset; 2514 2515 if (dst_addr >= IWM_FW_MEM_EXTENDED_START && 2516 dst_addr <= IWM_FW_MEM_EXTENDED_END) 2517 extended_addr = TRUE; 2518 2519 if (extended_addr) 2520 iwm_set_bits_prph(sc, IWM_LMPM_CHICK, 2521 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE); 2522 2523 memcpy(v_addr, (const uint8_t *)section->data + offset, 2524 copy_size); 2525 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 2526 ret = iwm_pcie_load_firmware_chunk(sc, dst_addr, p_addr, 2527 copy_size); 2528 2529 if (extended_addr) 2530 iwm_clear_bits_prph(sc, IWM_LMPM_CHICK, 2531 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE); 2532 2533 if (ret) { 2534 device_printf(sc->sc_dev, 2535 "%s: Could not load the [%d] uCode section\n", 2536 __func__, section_num); 2537 break; 2538 } 2539 } 2540 2541 return ret; 2542 } 2543 2544 /* 2545 * ucode 2546 */ 2547 static int 2548 iwm_pcie_load_firmware_chunk(struct iwm_softc *sc, uint32_t dst_addr, 2549 bus_addr_t phy_addr, uint32_t byte_cnt) 2550 { 2551 sc->sc_fw_chunk_done = 0; 2552 2553 if (!iwm_nic_lock(sc)) 2554 return EBUSY; 2555 2556 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL), 2557 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 2558 2559 IWM_WRITE(sc, IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(IWM_FH_SRVC_CHNL), 2560 dst_addr); 2561 2562 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL0_REG(IWM_FH_SRVC_CHNL), 2563 phy_addr & IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 2564 2565 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL1_REG(IWM_FH_SRVC_CHNL), 2566 (iwm_get_dma_hi_addr(phy_addr) 2567 << IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 2568 2569 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(IWM_FH_SRVC_CHNL), 2570 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 2571 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 2572 IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 2573 2574 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL), 2575 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 2576 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 2577 IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 2578 2579 iwm_nic_unlock(sc); 2580 2581 /* wait up to 5s for this segment to load */ 2582 msleep(&sc->sc_fw, &sc->sc_mtx, 0, "iwmfw", hz * 5); 2583 2584 if (!sc->sc_fw_chunk_done) { 2585 device_printf(sc->sc_dev, 2586 "fw chunk addr 0x%x len %d failed to load\n", 2587 dst_addr, byte_cnt); 2588 return ETIMEDOUT; 2589 } 2590 2591 return 0; 2592 } 2593 2594 static int 2595 iwm_pcie_load_cpu_sections_8000(struct iwm_softc *sc, 2596 const struct iwm_fw_img *image, int cpu, int *first_ucode_section) 2597 { 2598 int shift_param; 2599 int i, ret = 0, sec_num = 0x1; 2600 uint32_t val, last_read_idx = 0; 2601 2602 if (cpu == 1) { 2603 shift_param = 0; 2604 *first_ucode_section = 0; 2605 } else { 2606 shift_param = 16; 2607 (*first_ucode_section)++; 2608 } 2609 2610 for (i = *first_ucode_section; i < IWM_UCODE_SECTION_MAX; i++) { 2611 last_read_idx = i; 2612 2613 /* 2614 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 2615 * CPU1 to CPU2. 2616 * PAGING_SEPARATOR_SECTION delimiter - separate between 2617 * CPU2 non paged to CPU2 paging sec. 2618 */ 2619 if (!image->sec[i].data || 2620 image->sec[i].offset == IWM_CPU1_CPU2_SEPARATOR_SECTION || 2621 image->sec[i].offset == IWM_PAGING_SEPARATOR_SECTION) { 2622 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2623 "Break since Data not valid or Empty section, sec = %d\n", 2624 i); 2625 break; 2626 } 2627 ret = iwm_pcie_load_section(sc, i, &image->sec[i]); 2628 if (ret) 2629 return ret; 2630 2631 /* Notify the ucode of the loaded section number and status */ 2632 if (iwm_nic_lock(sc)) { 2633 val = IWM_READ(sc, IWM_FH_UCODE_LOAD_STATUS); 2634 val = val | (sec_num << shift_param); 2635 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, val); 2636 sec_num = (sec_num << 1) | 0x1; 2637 iwm_nic_unlock(sc); 2638 } 2639 } 2640 2641 *first_ucode_section = last_read_idx; 2642 2643 iwm_enable_interrupts(sc); 2644 2645 if (iwm_nic_lock(sc)) { 2646 if (cpu == 1) 2647 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFF); 2648 else 2649 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); 2650 iwm_nic_unlock(sc); 2651 } 2652 2653 return 0; 2654 } 2655 2656 static int 2657 iwm_pcie_load_cpu_sections(struct iwm_softc *sc, 2658 const struct iwm_fw_img *image, int cpu, int *first_ucode_section) 2659 { 2660 int i, ret = 0; 2661 uint32_t last_read_idx = 0; 2662 2663 if (cpu == 1) { 2664 *first_ucode_section = 0; 2665 } else { 2666 (*first_ucode_section)++; 2667 } 2668 2669 for (i = *first_ucode_section; i < IWM_UCODE_SECTION_MAX; i++) { 2670 last_read_idx = i; 2671 2672 /* 2673 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 2674 * CPU1 to CPU2. 2675 * PAGING_SEPARATOR_SECTION delimiter - separate between 2676 * CPU2 non paged to CPU2 paging sec. 2677 */ 2678 if (!image->sec[i].data || 2679 image->sec[i].offset == IWM_CPU1_CPU2_SEPARATOR_SECTION || 2680 image->sec[i].offset == IWM_PAGING_SEPARATOR_SECTION) { 2681 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2682 "Break since Data not valid or Empty section, sec = %d\n", 2683 i); 2684 break; 2685 } 2686 2687 ret = iwm_pcie_load_section(sc, i, &image->sec[i]); 2688 if (ret) 2689 return ret; 2690 } 2691 2692 *first_ucode_section = last_read_idx; 2693 2694 return 0; 2695 2696 } 2697 2698 static int 2699 iwm_pcie_load_given_ucode(struct iwm_softc *sc, const struct iwm_fw_img *image) 2700 { 2701 int ret = 0; 2702 int first_ucode_section; 2703 2704 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "working with %s CPU\n", 2705 image->is_dual_cpus ? "Dual" : "Single"); 2706 2707 /* load to FW the binary non secured sections of CPU1 */ 2708 ret = iwm_pcie_load_cpu_sections(sc, image, 1, &first_ucode_section); 2709 if (ret) 2710 return ret; 2711 2712 if (image->is_dual_cpus) { 2713 /* set CPU2 header address */ 2714 if (iwm_nic_lock(sc)) { 2715 iwm_write_prph(sc, 2716 IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 2717 IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE); 2718 iwm_nic_unlock(sc); 2719 } 2720 2721 /* load to FW the binary sections of CPU2 */ 2722 ret = iwm_pcie_load_cpu_sections(sc, image, 2, 2723 &first_ucode_section); 2724 if (ret) 2725 return ret; 2726 } 2727 2728 iwm_enable_interrupts(sc); 2729 2730 /* release CPU reset */ 2731 IWM_WRITE(sc, IWM_CSR_RESET, 0); 2732 2733 return 0; 2734 } 2735 2736 int 2737 iwm_pcie_load_given_ucode_8000(struct iwm_softc *sc, 2738 const struct iwm_fw_img *image) 2739 { 2740 int ret = 0; 2741 int first_ucode_section; 2742 2743 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "working with %s CPU\n", 2744 image->is_dual_cpus ? "Dual" : "Single"); 2745 2746 /* configure the ucode to be ready to get the secured image */ 2747 /* release CPU reset */ 2748 if (iwm_nic_lock(sc)) { 2749 iwm_write_prph(sc, IWM_RELEASE_CPU_RESET, 2750 IWM_RELEASE_CPU_RESET_BIT); 2751 iwm_nic_unlock(sc); 2752 } 2753 2754 /* load to FW the binary Secured sections of CPU1 */ 2755 ret = iwm_pcie_load_cpu_sections_8000(sc, image, 1, 2756 &first_ucode_section); 2757 if (ret) 2758 return ret; 2759 2760 /* load to FW the binary sections of CPU2 */ 2761 return iwm_pcie_load_cpu_sections_8000(sc, image, 2, 2762 &first_ucode_section); 2763 } 2764 2765 /* XXX Get rid of this definition */ 2766 static inline void 2767 iwm_enable_fw_load_int(struct iwm_softc *sc) 2768 { 2769 IWM_DPRINTF(sc, IWM_DEBUG_INTR, "Enabling FW load interrupt\n"); 2770 2771 if (!sc->sc_msix) { 2772 sc->sc_intmask = IWM_CSR_INT_BIT_FH_TX; 2773 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 2774 } else { 2775 IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD, 2776 sc->sc_hw_init_mask); 2777 IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD, 2778 ~IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 2779 sc->sc_fh_mask = IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM; 2780 } 2781 } 2782 2783 /* XXX Add proper rfkill support code */ 2784 static int 2785 iwm_start_fw(struct iwm_softc *sc, const struct iwm_fw_img *fw) 2786 { 2787 int ret; 2788 2789 /* This may fail if AMT took ownership of the device */ 2790 if (iwm_prepare_card_hw(sc)) { 2791 device_printf(sc->sc_dev, 2792 "%s: Exit HW not ready\n", __func__); 2793 ret = EIO; 2794 goto out; 2795 } 2796 2797 IWM_WRITE(sc, IWM_CSR_INT, 0xFFFFFFFF); 2798 2799 iwm_disable_interrupts(sc); 2800 2801 /* make sure rfkill handshake bits are cleared */ 2802 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL); 2803 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, 2804 IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 2805 2806 /* clear (again), then enable host interrupts */ 2807 IWM_WRITE(sc, IWM_CSR_INT, 0xFFFFFFFF); 2808 2809 ret = iwm_nic_init(sc); 2810 if (ret) { 2811 device_printf(sc->sc_dev, "%s: Unable to init nic\n", __func__); 2812 goto out; 2813 } 2814 2815 /* 2816 * Now, we load the firmware and don't want to be interrupted, even 2817 * by the RF-Kill interrupt (hence mask all the interrupt besides the 2818 * FH_TX interrupt which is needed to load the firmware). If the 2819 * RF-Kill switch is toggled, we will find out after having loaded 2820 * the firmware and return the proper value to the caller. 2821 */ 2822 iwm_enable_fw_load_int(sc); 2823 2824 /* really make sure rfkill handshake bits are cleared */ 2825 /* maybe we should write a few times more? just to make sure */ 2826 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL); 2827 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL); 2828 2829 /* Load the given image to the HW */ 2830 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) 2831 ret = iwm_pcie_load_given_ucode_8000(sc, fw); 2832 else 2833 ret = iwm_pcie_load_given_ucode(sc, fw); 2834 2835 /* XXX re-check RF-Kill state */ 2836 2837 out: 2838 return ret; 2839 } 2840 2841 static int 2842 iwm_send_tx_ant_cfg(struct iwm_softc *sc, uint8_t valid_tx_ant) 2843 { 2844 struct iwm_tx_ant_cfg_cmd tx_ant_cmd = { 2845 .valid = htole32(valid_tx_ant), 2846 }; 2847 2848 return iwm_send_cmd_pdu(sc, IWM_TX_ANT_CONFIGURATION_CMD, 2849 IWM_CMD_SYNC, sizeof(tx_ant_cmd), &tx_ant_cmd); 2850 } 2851 2852 /* iwlwifi: mvm/fw.c */ 2853 static int 2854 iwm_send_phy_cfg_cmd(struct iwm_softc *sc) 2855 { 2856 struct iwm_phy_cfg_cmd phy_cfg_cmd; 2857 enum iwm_ucode_type ucode_type = sc->cur_ucode; 2858 2859 /* Set parameters */ 2860 phy_cfg_cmd.phy_cfg = htole32(iwm_get_phy_config(sc)); 2861 phy_cfg_cmd.calib_control.event_trigger = 2862 sc->sc_default_calib[ucode_type].event_trigger; 2863 phy_cfg_cmd.calib_control.flow_trigger = 2864 sc->sc_default_calib[ucode_type].flow_trigger; 2865 2866 IWM_DPRINTF(sc, IWM_DEBUG_CMD | IWM_DEBUG_RESET, 2867 "Sending Phy CFG command: 0x%x\n", phy_cfg_cmd.phy_cfg); 2868 return iwm_send_cmd_pdu(sc, IWM_PHY_CONFIGURATION_CMD, IWM_CMD_SYNC, 2869 sizeof(phy_cfg_cmd), &phy_cfg_cmd); 2870 } 2871 2872 static int 2873 iwm_alive_fn(struct iwm_softc *sc, struct iwm_rx_packet *pkt, void *data) 2874 { 2875 struct iwm_alive_data *alive_data = data; 2876 struct iwm_alive_resp_v3 *palive3; 2877 struct iwm_alive_resp *palive; 2878 struct iwm_umac_alive *umac; 2879 struct iwm_lmac_alive *lmac1; 2880 struct iwm_lmac_alive *lmac2 = NULL; 2881 uint16_t status; 2882 2883 if (iwm_rx_packet_payload_len(pkt) == sizeof(*palive)) { 2884 palive = (void *)pkt->data; 2885 umac = &palive->umac_data; 2886 lmac1 = &palive->lmac_data[0]; 2887 lmac2 = &palive->lmac_data[1]; 2888 status = le16toh(palive->status); 2889 } else { 2890 palive3 = (void *)pkt->data; 2891 umac = &palive3->umac_data; 2892 lmac1 = &palive3->lmac_data; 2893 status = le16toh(palive3->status); 2894 } 2895 2896 sc->error_event_table[0] = le32toh(lmac1->error_event_table_ptr); 2897 if (lmac2) 2898 sc->error_event_table[1] = 2899 le32toh(lmac2->error_event_table_ptr); 2900 sc->log_event_table = le32toh(lmac1->log_event_table_ptr); 2901 sc->umac_error_event_table = le32toh(umac->error_info_addr); 2902 alive_data->scd_base_addr = le32toh(lmac1->scd_base_ptr); 2903 alive_data->valid = status == IWM_ALIVE_STATUS_OK; 2904 if (sc->umac_error_event_table) 2905 sc->support_umac_log = TRUE; 2906 2907 IWM_DPRINTF(sc, IWM_DEBUG_FW, 2908 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n", 2909 status, lmac1->ver_type, lmac1->ver_subtype); 2910 2911 if (lmac2) 2912 IWM_DPRINTF(sc, IWM_DEBUG_FW, "Alive ucode CDB\n"); 2913 2914 IWM_DPRINTF(sc, IWM_DEBUG_FW, 2915 "UMAC version: Major - 0x%x, Minor - 0x%x\n", 2916 le32toh(umac->umac_major), 2917 le32toh(umac->umac_minor)); 2918 2919 return TRUE; 2920 } 2921 2922 static int 2923 iwm_wait_phy_db_entry(struct iwm_softc *sc, 2924 struct iwm_rx_packet *pkt, void *data) 2925 { 2926 struct iwm_phy_db *phy_db = data; 2927 2928 if (pkt->hdr.code != IWM_CALIB_RES_NOTIF_PHY_DB) { 2929 if(pkt->hdr.code != IWM_INIT_COMPLETE_NOTIF) { 2930 device_printf(sc->sc_dev, "%s: Unexpected cmd: %d\n", 2931 __func__, pkt->hdr.code); 2932 } 2933 return TRUE; 2934 } 2935 2936 if (iwm_phy_db_set_section(phy_db, pkt)) { 2937 device_printf(sc->sc_dev, 2938 "%s: iwm_phy_db_set_section failed\n", __func__); 2939 } 2940 2941 return FALSE; 2942 } 2943 2944 static int 2945 iwm_load_ucode_wait_alive(struct iwm_softc *sc, 2946 enum iwm_ucode_type ucode_type) 2947 { 2948 struct iwm_notification_wait alive_wait; 2949 struct iwm_alive_data alive_data; 2950 const struct iwm_fw_img *fw; 2951 enum iwm_ucode_type old_type = sc->cur_ucode; 2952 int error; 2953 static const uint16_t alive_cmd[] = { IWM_ALIVE }; 2954 2955 fw = &sc->sc_fw.img[ucode_type]; 2956 sc->cur_ucode = ucode_type; 2957 sc->ucode_loaded = FALSE; 2958 2959 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_DQA_SUPPORT)) 2960 sc->cmdqid = IWM_DQA_CMD_QUEUE; 2961 else 2962 sc->cmdqid = IWM_CMD_QUEUE; 2963 2964 memset(&alive_data, 0, sizeof(alive_data)); 2965 iwm_init_notification_wait(sc->sc_notif_wait, &alive_wait, 2966 alive_cmd, nitems(alive_cmd), 2967 iwm_alive_fn, &alive_data); 2968 2969 error = iwm_start_fw(sc, fw); 2970 if (error) { 2971 device_printf(sc->sc_dev, "iwm_start_fw: failed %d\n", error); 2972 sc->cur_ucode = old_type; 2973 iwm_remove_notification(sc->sc_notif_wait, &alive_wait); 2974 return error; 2975 } 2976 2977 /* 2978 * Some things may run in the background now, but we 2979 * just wait for the ALIVE notification here. 2980 */ 2981 IWM_UNLOCK(sc); 2982 error = iwm_wait_notification(sc->sc_notif_wait, &alive_wait, 2983 IWM_UCODE_ALIVE_TIMEOUT); 2984 IWM_LOCK(sc); 2985 if (error) { 2986 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) { 2987 uint32_t a = 0x5a5a5a5a, b = 0x5a5a5a5a; 2988 if (iwm_nic_lock(sc)) { 2989 a = iwm_read_prph(sc, IWM_SB_CPU_1_STATUS); 2990 b = iwm_read_prph(sc, IWM_SB_CPU_2_STATUS); 2991 iwm_nic_unlock(sc); 2992 } 2993 device_printf(sc->sc_dev, 2994 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 2995 a, b); 2996 } 2997 sc->cur_ucode = old_type; 2998 return error; 2999 } 3000 3001 if (!alive_data.valid) { 3002 device_printf(sc->sc_dev, "%s: Loaded ucode is not valid\n", 3003 __func__); 3004 sc->cur_ucode = old_type; 3005 return EIO; 3006 } 3007 3008 iwm_trans_pcie_fw_alive(sc, alive_data.scd_base_addr); 3009 3010 /* 3011 * configure and operate fw paging mechanism. 3012 * driver configures the paging flow only once, CPU2 paging image 3013 * included in the IWM_UCODE_INIT image. 3014 */ 3015 if (fw->paging_mem_size) { 3016 error = iwm_save_fw_paging(sc, fw); 3017 if (error) { 3018 device_printf(sc->sc_dev, 3019 "%s: failed to save the FW paging image\n", 3020 __func__); 3021 return error; 3022 } 3023 3024 error = iwm_send_paging_cmd(sc, fw); 3025 if (error) { 3026 device_printf(sc->sc_dev, 3027 "%s: failed to send the paging cmd\n", __func__); 3028 iwm_free_fw_paging(sc); 3029 return error; 3030 } 3031 } 3032 3033 if (!error) 3034 sc->ucode_loaded = TRUE; 3035 return error; 3036 } 3037 3038 /* 3039 * mvm misc bits 3040 */ 3041 3042 /* 3043 * follows iwlwifi/fw.c 3044 */ 3045 static int 3046 iwm_run_init_ucode(struct iwm_softc *sc, int justnvm) 3047 { 3048 struct iwm_notification_wait calib_wait; 3049 static const uint16_t init_complete[] = { 3050 IWM_INIT_COMPLETE_NOTIF, 3051 IWM_CALIB_RES_NOTIF_PHY_DB 3052 }; 3053 int ret; 3054 3055 /* do not operate with rfkill switch turned on */ 3056 if ((sc->sc_flags & IWM_FLAG_RFKILL) && !justnvm) { 3057 device_printf(sc->sc_dev, 3058 "radio is disabled by hardware switch\n"); 3059 return EPERM; 3060 } 3061 3062 iwm_init_notification_wait(sc->sc_notif_wait, 3063 &calib_wait, 3064 init_complete, 3065 nitems(init_complete), 3066 iwm_wait_phy_db_entry, 3067 sc->sc_phy_db); 3068 3069 /* Will also start the device */ 3070 ret = iwm_load_ucode_wait_alive(sc, IWM_UCODE_INIT); 3071 if (ret) { 3072 device_printf(sc->sc_dev, "Failed to start INIT ucode: %d\n", 3073 ret); 3074 goto error; 3075 } 3076 3077 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 3078 ret = iwm_send_bt_init_conf(sc); 3079 if (ret) { 3080 device_printf(sc->sc_dev, 3081 "failed to send bt coex configuration: %d\n", ret); 3082 goto error; 3083 } 3084 } 3085 3086 if (justnvm) { 3087 /* Read nvm */ 3088 ret = iwm_nvm_init(sc); 3089 if (ret) { 3090 device_printf(sc->sc_dev, "failed to read nvm\n"); 3091 goto error; 3092 } 3093 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, sc->nvm_data->hw_addr); 3094 goto error; 3095 } 3096 3097 /* Send TX valid antennas before triggering calibrations */ 3098 ret = iwm_send_tx_ant_cfg(sc, iwm_get_valid_tx_ant(sc)); 3099 if (ret) { 3100 device_printf(sc->sc_dev, 3101 "failed to send antennas before calibration: %d\n", ret); 3102 goto error; 3103 } 3104 3105 /* 3106 * Send phy configurations command to init uCode 3107 * to start the 16.0 uCode init image internal calibrations. 3108 */ 3109 ret = iwm_send_phy_cfg_cmd(sc); 3110 if (ret) { 3111 device_printf(sc->sc_dev, 3112 "%s: Failed to run INIT calibrations: %d\n", 3113 __func__, ret); 3114 goto error; 3115 } 3116 3117 /* 3118 * Nothing to do but wait for the init complete notification 3119 * from the firmware. 3120 */ 3121 IWM_UNLOCK(sc); 3122 ret = iwm_wait_notification(sc->sc_notif_wait, &calib_wait, 3123 IWM_UCODE_CALIB_TIMEOUT); 3124 IWM_LOCK(sc); 3125 3126 3127 goto out; 3128 3129 error: 3130 iwm_remove_notification(sc->sc_notif_wait, &calib_wait); 3131 out: 3132 return ret; 3133 } 3134 3135 static int 3136 iwm_config_ltr(struct iwm_softc *sc) 3137 { 3138 struct iwm_ltr_config_cmd cmd = { 3139 .flags = htole32(IWM_LTR_CFG_FLAG_FEATURE_ENABLE), 3140 }; 3141 3142 if (!sc->sc_ltr_enabled) 3143 return 0; 3144 3145 return iwm_send_cmd_pdu(sc, IWM_LTR_CONFIG, 0, sizeof(cmd), &cmd); 3146 } 3147 3148 /* 3149 * receive side 3150 */ 3151 3152 /* (re)stock rx ring, called at init-time and at runtime */ 3153 static int 3154 iwm_rx_addbuf(struct iwm_softc *sc, int size, int idx) 3155 { 3156 struct iwm_rx_ring *ring = &sc->rxq; 3157 struct iwm_rx_data *data = &ring->data[idx]; 3158 struct mbuf *m; 3159 bus_dmamap_t dmamap; 3160 bus_dma_segment_t seg; 3161 int nsegs, error; 3162 3163 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWM_RBUF_SIZE); 3164 if (m == NULL) 3165 return ENOBUFS; 3166 3167 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3168 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, ring->spare_map, m, 3169 &seg, &nsegs, BUS_DMA_NOWAIT); 3170 if (error != 0) { 3171 device_printf(sc->sc_dev, 3172 "%s: can't map mbuf, error %d\n", __func__, error); 3173 m_freem(m); 3174 return error; 3175 } 3176 3177 if (data->m != NULL) 3178 bus_dmamap_unload(ring->data_dmat, data->map); 3179 3180 /* Swap ring->spare_map with data->map */ 3181 dmamap = data->map; 3182 data->map = ring->spare_map; 3183 ring->spare_map = dmamap; 3184 3185 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREREAD); 3186 data->m = m; 3187 3188 /* Update RX descriptor. */ 3189 KASSERT((seg.ds_addr & 255) == 0, ("seg.ds_addr not aligned")); 3190 if (sc->cfg->mqrx_supported) 3191 ((uint64_t *)ring->desc)[idx] = htole64(seg.ds_addr); 3192 else 3193 ((uint32_t *)ring->desc)[idx] = htole32(seg.ds_addr >> 8); 3194 bus_dmamap_sync(ring->free_desc_dma.tag, ring->free_desc_dma.map, 3195 BUS_DMASYNC_PREWRITE); 3196 3197 return 0; 3198 } 3199 3200 static void 3201 iwm_rx_rx_phy_cmd(struct iwm_softc *sc, struct iwm_rx_packet *pkt) 3202 { 3203 struct iwm_rx_phy_info *phy_info = (void *)pkt->data; 3204 3205 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "received PHY stats\n"); 3206 3207 memcpy(&sc->sc_last_phy_info, phy_info, sizeof(sc->sc_last_phy_info)); 3208 } 3209 3210 /* 3211 * Retrieve the average noise (in dBm) among receivers. 3212 */ 3213 static int 3214 iwm_get_noise(struct iwm_softc *sc, 3215 const struct iwm_statistics_rx_non_phy *stats) 3216 { 3217 int i, noise; 3218 #ifdef IWM_DEBUG 3219 int nbant, total; 3220 #else 3221 int nbant __unused, total __unused; 3222 #endif 3223 3224 total = nbant = noise = 0; 3225 for (i = 0; i < 3; i++) { 3226 noise = le32toh(stats->beacon_silence_rssi[i]) & 0xff; 3227 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "%s: i=%d, noise=%d\n", 3228 __func__, 3229 i, 3230 noise); 3231 3232 if (noise) { 3233 total += noise; 3234 nbant++; 3235 } 3236 } 3237 3238 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "%s: nbant=%d, total=%d\n", 3239 __func__, nbant, total); 3240 #if 0 3241 /* There should be at least one antenna but check anyway. */ 3242 return (nbant == 0) ? -127 : (total / nbant) - 107; 3243 #else 3244 /* For now, just hard-code it to -96 to be safe */ 3245 return (-96); 3246 #endif 3247 } 3248 3249 static void 3250 iwm_handle_rx_statistics(struct iwm_softc *sc, struct iwm_rx_packet *pkt) 3251 { 3252 struct iwm_notif_statistics *stats = (void *)&pkt->data; 3253 3254 memcpy(&sc->sc_stats, stats, sizeof(sc->sc_stats)); 3255 sc->sc_noise = iwm_get_noise(sc, &stats->rx.general); 3256 } 3257 3258 /* iwlwifi: mvm/rx.c */ 3259 /* 3260 * iwm_get_signal_strength - use new rx PHY INFO API 3261 * values are reported by the fw as positive values - need to negate 3262 * to obtain their dBM. Account for missing antennas by replacing 0 3263 * values by -256dBm: practically 0 power and a non-feasible 8 bit value. 3264 */ 3265 static int 3266 iwm_rx_get_signal_strength(struct iwm_softc *sc, 3267 struct iwm_rx_phy_info *phy_info) 3268 { 3269 int energy_a, energy_b, energy_c, max_energy; 3270 uint32_t val; 3271 3272 val = le32toh(phy_info->non_cfg_phy[IWM_RX_INFO_ENERGY_ANT_ABC_IDX]); 3273 energy_a = (val & IWM_RX_INFO_ENERGY_ANT_A_MSK) >> 3274 IWM_RX_INFO_ENERGY_ANT_A_POS; 3275 energy_a = energy_a ? -energy_a : -256; 3276 energy_b = (val & IWM_RX_INFO_ENERGY_ANT_B_MSK) >> 3277 IWM_RX_INFO_ENERGY_ANT_B_POS; 3278 energy_b = energy_b ? -energy_b : -256; 3279 energy_c = (val & IWM_RX_INFO_ENERGY_ANT_C_MSK) >> 3280 IWM_RX_INFO_ENERGY_ANT_C_POS; 3281 energy_c = energy_c ? -energy_c : -256; 3282 max_energy = MAX(energy_a, energy_b); 3283 max_energy = MAX(max_energy, energy_c); 3284 3285 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3286 "energy In A %d B %d C %d , and max %d\n", 3287 energy_a, energy_b, energy_c, max_energy); 3288 3289 return max_energy; 3290 } 3291 3292 static int 3293 iwm_rxmq_get_signal_strength(struct iwm_softc *sc, 3294 struct iwm_rx_mpdu_desc *desc) 3295 { 3296 int energy_a, energy_b; 3297 3298 energy_a = desc->v1.energy_a; 3299 energy_b = desc->v1.energy_b; 3300 energy_a = energy_a ? -energy_a : -256; 3301 energy_b = energy_b ? -energy_b : -256; 3302 return MAX(energy_a, energy_b); 3303 } 3304 3305 /* 3306 * iwm_rx_rx_mpdu - IWM_REPLY_RX_MPDU_CMD handler 3307 * 3308 * Handles the actual data of the Rx packet from the fw 3309 */ 3310 static bool 3311 iwm_rx_rx_mpdu(struct iwm_softc *sc, struct mbuf *m, uint32_t offset, 3312 bool stolen) 3313 { 3314 struct ieee80211com *ic = &sc->sc_ic; 3315 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3316 struct ieee80211_rx_stats rxs; 3317 struct iwm_rx_phy_info *phy_info; 3318 struct iwm_rx_mpdu_res_start *rx_res; 3319 struct iwm_rx_packet *pkt = mtodoff(m, struct iwm_rx_packet *, offset); 3320 uint32_t len; 3321 uint32_t rx_pkt_status; 3322 int rssi; 3323 3324 phy_info = &sc->sc_last_phy_info; 3325 rx_res = (struct iwm_rx_mpdu_res_start *)pkt->data; 3326 len = le16toh(rx_res->byte_count); 3327 rx_pkt_status = le32toh(*(uint32_t *)(pkt->data + sizeof(*rx_res) + len)); 3328 3329 if (__predict_false(phy_info->cfg_phy_cnt > 20)) { 3330 device_printf(sc->sc_dev, 3331 "dsp size out of range [0,20]: %d\n", 3332 phy_info->cfg_phy_cnt); 3333 return false; 3334 } 3335 3336 if (!(rx_pkt_status & IWM_RX_MPDU_RES_STATUS_CRC_OK) || 3337 !(rx_pkt_status & IWM_RX_MPDU_RES_STATUS_OVERRUN_OK)) { 3338 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3339 "Bad CRC or FIFO: 0x%08X.\n", rx_pkt_status); 3340 return false; 3341 } 3342 3343 rssi = iwm_rx_get_signal_strength(sc, phy_info); 3344 3345 /* Map it to relative value */ 3346 rssi = rssi - sc->sc_noise; 3347 3348 /* replenish ring for the buffer we're going to feed to the sharks */ 3349 if (!stolen && iwm_rx_addbuf(sc, IWM_RBUF_SIZE, sc->rxq.cur) != 0) { 3350 device_printf(sc->sc_dev, "%s: unable to add more buffers\n", 3351 __func__); 3352 return false; 3353 } 3354 3355 m->m_data = pkt->data + sizeof(*rx_res); 3356 m->m_pkthdr.len = m->m_len = len; 3357 3358 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3359 "%s: rssi=%d, noise=%d\n", __func__, rssi, sc->sc_noise); 3360 3361 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3362 "%s: phy_info: channel=%d, flags=0x%08x\n", 3363 __func__, 3364 le16toh(phy_info->channel), 3365 le16toh(phy_info->phy_flags)); 3366 3367 /* 3368 * Populate an RX state struct with the provided information. 3369 */ 3370 bzero(&rxs, sizeof(rxs)); 3371 rxs.r_flags |= IEEE80211_R_IEEE | IEEE80211_R_FREQ; 3372 rxs.r_flags |= IEEE80211_R_BAND; 3373 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI; 3374 rxs.c_ieee = le16toh(phy_info->channel); 3375 if (le16toh(phy_info->phy_flags & IWM_RX_RES_PHY_FLAGS_BAND_24)) { 3376 rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, IEEE80211_CHAN_2GHZ); 3377 rxs.c_band = IEEE80211_CHAN_2GHZ; 3378 } else { 3379 rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, IEEE80211_CHAN_5GHZ); 3380 rxs.c_band = IEEE80211_CHAN_5GHZ; 3381 } 3382 3383 /* rssi is in 1/2db units */ 3384 rxs.c_rssi = rssi * 2; 3385 rxs.c_nf = sc->sc_noise; 3386 if (ieee80211_add_rx_params(m, &rxs) == 0) 3387 return false; 3388 3389 if (ieee80211_radiotap_active_vap(vap)) { 3390 struct iwm_rx_radiotap_header *tap = &sc->sc_rxtap; 3391 3392 tap->wr_flags = 0; 3393 if (phy_info->phy_flags & htole16(IWM_PHY_INFO_FLAG_SHPREAMBLE)) 3394 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3395 tap->wr_chan_freq = htole16(rxs.c_freq); 3396 /* XXX only if ic->ic_curchan->ic_ieee == rxs.c_ieee */ 3397 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 3398 tap->wr_dbm_antsignal = (int8_t)rssi; 3399 tap->wr_dbm_antnoise = (int8_t)sc->sc_noise; 3400 tap->wr_tsft = phy_info->system_timestamp; 3401 switch (phy_info->rate) { 3402 /* CCK rates. */ 3403 case 10: tap->wr_rate = 2; break; 3404 case 20: tap->wr_rate = 4; break; 3405 case 55: tap->wr_rate = 11; break; 3406 case 110: tap->wr_rate = 22; break; 3407 /* OFDM rates. */ 3408 case 0xd: tap->wr_rate = 12; break; 3409 case 0xf: tap->wr_rate = 18; break; 3410 case 0x5: tap->wr_rate = 24; break; 3411 case 0x7: tap->wr_rate = 36; break; 3412 case 0x9: tap->wr_rate = 48; break; 3413 case 0xb: tap->wr_rate = 72; break; 3414 case 0x1: tap->wr_rate = 96; break; 3415 case 0x3: tap->wr_rate = 108; break; 3416 /* Unknown rate: should not happen. */ 3417 default: tap->wr_rate = 0; 3418 } 3419 } 3420 3421 return true; 3422 } 3423 3424 static bool 3425 iwm_rx_mpdu_mq(struct iwm_softc *sc, struct mbuf *m, uint32_t offset, 3426 bool stolen) 3427 { 3428 struct ieee80211com *ic = &sc->sc_ic; 3429 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3430 struct ieee80211_frame *wh; 3431 struct ieee80211_rx_stats rxs; 3432 struct iwm_rx_mpdu_desc *desc; 3433 struct iwm_rx_packet *pkt; 3434 int rssi; 3435 uint32_t hdrlen, len, rate_n_flags; 3436 uint16_t phy_info; 3437 uint8_t channel; 3438 3439 pkt = mtodo(m, offset); 3440 desc = (void *)pkt->data; 3441 3442 if (!(desc->status & htole16(IWM_RX_MPDU_RES_STATUS_CRC_OK)) || 3443 !(desc->status & htole16(IWM_RX_MPDU_RES_STATUS_OVERRUN_OK))) { 3444 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3445 "Bad CRC or FIFO: 0x%08X.\n", desc->status); 3446 return false; 3447 } 3448 3449 channel = desc->v1.channel; 3450 len = le16toh(desc->mpdu_len); 3451 phy_info = le16toh(desc->phy_info); 3452 rate_n_flags = desc->v1.rate_n_flags; 3453 3454 wh = mtodo(m, sizeof(*desc)); 3455 m->m_data = pkt->data + sizeof(*desc); 3456 m->m_pkthdr.len = m->m_len = len; 3457 m->m_len = len; 3458 3459 /* Account for padding following the frame header. */ 3460 if ((desc->mac_flags2 & IWM_RX_MPDU_MFLG2_PAD)) { 3461 hdrlen = ieee80211_anyhdrsize(wh); 3462 memmove(mtodo(m, 2), mtodo(m, 0), hdrlen); 3463 m->m_data = mtodo(m, 2); 3464 wh = mtod(m, struct ieee80211_frame *); 3465 } 3466 3467 /* Map it to relative value */ 3468 rssi = iwm_rxmq_get_signal_strength(sc, desc); 3469 rssi = rssi - sc->sc_noise; 3470 3471 /* replenish ring for the buffer we're going to feed to the sharks */ 3472 if (!stolen && iwm_rx_addbuf(sc, IWM_RBUF_SIZE, sc->rxq.cur) != 0) { 3473 device_printf(sc->sc_dev, "%s: unable to add more buffers\n", 3474 __func__); 3475 return false; 3476 } 3477 3478 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3479 "%s: rssi=%d, noise=%d\n", __func__, rssi, sc->sc_noise); 3480 3481 /* 3482 * Populate an RX state struct with the provided information. 3483 */ 3484 bzero(&rxs, sizeof(rxs)); 3485 rxs.r_flags |= IEEE80211_R_IEEE | IEEE80211_R_FREQ; 3486 rxs.r_flags |= IEEE80211_R_BAND; 3487 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI; 3488 rxs.c_ieee = channel; 3489 rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, 3490 channel <= 14 ? IEEE80211_CHAN_2GHZ : IEEE80211_CHAN_5GHZ); 3491 rxs.c_band = channel <= 14 ? IEEE80211_CHAN_2GHZ : IEEE80211_CHAN_5GHZ; 3492 3493 /* rssi is in 1/2db units */ 3494 rxs.c_rssi = rssi * 2; 3495 rxs.c_nf = sc->sc_noise; 3496 if (ieee80211_add_rx_params(m, &rxs) == 0) 3497 return false; 3498 3499 if (ieee80211_radiotap_active_vap(vap)) { 3500 struct iwm_rx_radiotap_header *tap = &sc->sc_rxtap; 3501 3502 tap->wr_flags = 0; 3503 if ((phy_info & IWM_RX_MPDU_PHY_SHORT_PREAMBLE) != 0) 3504 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3505 tap->wr_chan_freq = htole16(rxs.c_freq); 3506 /* XXX only if ic->ic_curchan->ic_ieee == rxs.c_ieee */ 3507 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 3508 tap->wr_dbm_antsignal = (int8_t)rssi; 3509 tap->wr_dbm_antnoise = (int8_t)sc->sc_noise; 3510 tap->wr_tsft = desc->v1.gp2_on_air_rise; 3511 switch ((rate_n_flags & 0xff)) { 3512 /* CCK rates. */ 3513 case 10: tap->wr_rate = 2; break; 3514 case 20: tap->wr_rate = 4; break; 3515 case 55: tap->wr_rate = 11; break; 3516 case 110: tap->wr_rate = 22; break; 3517 /* OFDM rates. */ 3518 case 0xd: tap->wr_rate = 12; break; 3519 case 0xf: tap->wr_rate = 18; break; 3520 case 0x5: tap->wr_rate = 24; break; 3521 case 0x7: tap->wr_rate = 36; break; 3522 case 0x9: tap->wr_rate = 48; break; 3523 case 0xb: tap->wr_rate = 72; break; 3524 case 0x1: tap->wr_rate = 96; break; 3525 case 0x3: tap->wr_rate = 108; break; 3526 /* Unknown rate: should not happen. */ 3527 default: tap->wr_rate = 0; 3528 } 3529 } 3530 3531 return true; 3532 } 3533 3534 static bool 3535 iwm_rx_mpdu(struct iwm_softc *sc, struct mbuf *m, uint32_t offset, 3536 bool stolen) 3537 { 3538 struct ieee80211com *ic; 3539 struct ieee80211_frame *wh; 3540 struct ieee80211_node *ni; 3541 bool ret; 3542 3543 ic = &sc->sc_ic; 3544 3545 ret = sc->cfg->mqrx_supported ? 3546 iwm_rx_mpdu_mq(sc, m, offset, stolen) : 3547 iwm_rx_rx_mpdu(sc, m, offset, stolen); 3548 if (!ret) { 3549 counter_u64_add(ic->ic_ierrors, 1); 3550 return (ret); 3551 } 3552 3553 wh = mtod(m, struct ieee80211_frame *); 3554 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3555 3556 IWM_UNLOCK(sc); 3557 if (ni != NULL) { 3558 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "input m %p\n", m); 3559 ieee80211_input_mimo(ni, m); 3560 ieee80211_free_node(ni); 3561 } else { 3562 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "inputall m %p\n", m); 3563 ieee80211_input_mimo_all(ic, m); 3564 } 3565 IWM_LOCK(sc); 3566 3567 return true; 3568 } 3569 3570 static int 3571 iwm_rx_tx_cmd_single(struct iwm_softc *sc, struct iwm_rx_packet *pkt, 3572 struct iwm_node *in) 3573 { 3574 struct iwm_tx_resp *tx_resp = (void *)pkt->data; 3575 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3576 struct ieee80211_node *ni = &in->in_ni; 3577 struct ieee80211vap *vap = ni->ni_vap; 3578 int status = le16toh(tx_resp->status.status) & IWM_TX_STATUS_MSK; 3579 int new_rate, cur_rate; 3580 boolean_t rate_matched; 3581 uint8_t tx_resp_rate; 3582 3583 KASSERT(tx_resp->frame_count == 1, ("too many frames")); 3584 3585 /* Update rate control statistics. */ 3586 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, "%s: status=0x%04x, seq=%d, fc=%d, btc=%d, frts=%d, ff=%d, irate=%08x, wmt=%d\n", 3587 __func__, 3588 (int) le16toh(tx_resp->status.status), 3589 (int) le16toh(tx_resp->status.sequence), 3590 tx_resp->frame_count, 3591 tx_resp->bt_kill_count, 3592 tx_resp->failure_rts, 3593 tx_resp->failure_frame, 3594 le32toh(tx_resp->initial_rate), 3595 (int) le16toh(tx_resp->wireless_media_time)); 3596 3597 cur_rate = ieee80211_node_get_txrate_dot11rate(vap->iv_bss); 3598 tx_resp_rate = iwm_rate_from_ucode_rate(le32toh(tx_resp->initial_rate)); 3599 3600 /* For rate control, ignore frames sent at different initial rate */ 3601 rate_matched = (tx_resp_rate != 0 && tx_resp_rate == cur_rate); 3602 3603 if (tx_resp_rate != 0 && cur_rate != 0 && !rate_matched) { 3604 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3605 "tx_resp_rate doesn't match ni_txrate (tx_resp_rate=%u " 3606 "ni_txrate=%d)\n", tx_resp_rate, cur_rate); 3607 } 3608 3609 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3610 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3611 txs->short_retries = tx_resp->failure_rts; 3612 txs->long_retries = tx_resp->failure_frame; 3613 if (status != IWM_TX_STATUS_SUCCESS && 3614 status != IWM_TX_STATUS_DIRECT_DONE) { 3615 switch (status) { 3616 case IWM_TX_STATUS_FAIL_SHORT_LIMIT: 3617 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT; 3618 break; 3619 case IWM_TX_STATUS_FAIL_LONG_LIMIT: 3620 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG; 3621 break; 3622 case IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 3623 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED; 3624 break; 3625 default: 3626 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3627 break; 3628 } 3629 } else { 3630 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3631 } 3632 3633 if (rate_matched) { 3634 ieee80211_ratectl_tx_complete(ni, txs); 3635 3636 ieee80211_ratectl_rate(vap->iv_bss, NULL, 0); 3637 new_rate = ieee80211_node_get_txrate_dot11rate(vap->iv_bss); 3638 if (new_rate != 0 && new_rate != cur_rate) { 3639 struct iwm_node *in = IWM_NODE(vap->iv_bss); 3640 iwm_setrates(sc, in, new_rate); 3641 iwm_send_lq_cmd(sc, &in->in_lq, FALSE); 3642 } 3643 } 3644 3645 return (txs->status != IEEE80211_RATECTL_TX_SUCCESS); 3646 } 3647 3648 static void 3649 iwm_rx_tx_cmd(struct iwm_softc *sc, struct iwm_rx_packet *pkt) 3650 { 3651 struct iwm_cmd_header *cmd_hdr; 3652 struct iwm_tx_ring *ring; 3653 struct iwm_tx_data *txd; 3654 struct iwm_node *in; 3655 struct mbuf *m; 3656 int idx, qid, qmsk, status; 3657 3658 cmd_hdr = &pkt->hdr; 3659 idx = cmd_hdr->idx; 3660 qid = cmd_hdr->qid; 3661 3662 ring = &sc->txq[qid]; 3663 txd = &ring->data[idx]; 3664 in = txd->in; 3665 m = txd->m; 3666 3667 KASSERT(txd->done == 0, ("txd not done")); 3668 KASSERT(txd->in != NULL, ("txd without node")); 3669 KASSERT(txd->m != NULL, ("txd without mbuf")); 3670 3671 sc->sc_tx_timer = 0; 3672 3673 status = iwm_rx_tx_cmd_single(sc, pkt, in); 3674 3675 /* Unmap and free mbuf. */ 3676 bus_dmamap_sync(ring->data_dmat, txd->map, BUS_DMASYNC_POSTWRITE); 3677 bus_dmamap_unload(ring->data_dmat, txd->map); 3678 3679 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 3680 "free txd %p, in %p\n", txd, txd->in); 3681 txd->done = 1; 3682 txd->m = NULL; 3683 txd->in = NULL; 3684 3685 ieee80211_tx_complete(&in->in_ni, m, status); 3686 3687 qmsk = 1 << qid; 3688 if (--ring->queued < IWM_TX_RING_LOMARK && (sc->qfullmsk & qmsk) != 0) { 3689 sc->qfullmsk &= ~qmsk; 3690 if (sc->qfullmsk == 0) 3691 iwm_start(sc); 3692 } 3693 } 3694 3695 /* 3696 * transmit side 3697 */ 3698 3699 /* 3700 * Process a "command done" firmware notification. This is where we wakeup 3701 * processes waiting for a synchronous command completion. 3702 * from if_iwn 3703 */ 3704 static void 3705 iwm_cmd_done(struct iwm_softc *sc, struct iwm_rx_packet *pkt) 3706 { 3707 struct iwm_tx_ring *ring = &sc->txq[sc->cmdqid]; 3708 struct iwm_tx_data *data; 3709 3710 if (pkt->hdr.qid != sc->cmdqid) { 3711 return; /* Not a command ack. */ 3712 } 3713 3714 /* XXX wide commands? */ 3715 IWM_DPRINTF(sc, IWM_DEBUG_CMD, 3716 "cmd notification type 0x%x qid %d idx %d\n", 3717 pkt->hdr.code, pkt->hdr.qid, pkt->hdr.idx); 3718 3719 data = &ring->data[pkt->hdr.idx]; 3720 3721 /* If the command was mapped in an mbuf, free it. */ 3722 if (data->m != NULL) { 3723 bus_dmamap_sync(ring->data_dmat, data->map, 3724 BUS_DMASYNC_POSTWRITE); 3725 bus_dmamap_unload(ring->data_dmat, data->map); 3726 m_freem(data->m); 3727 data->m = NULL; 3728 } 3729 wakeup(&ring->desc[pkt->hdr.idx]); 3730 3731 if (((pkt->hdr.idx + ring->queued) % IWM_TX_RING_COUNT) != ring->cur) { 3732 device_printf(sc->sc_dev, 3733 "%s: Some HCMDs skipped?: idx=%d queued=%d cur=%d\n", 3734 __func__, pkt->hdr.idx, ring->queued, ring->cur); 3735 /* XXX call iwm_force_nmi() */ 3736 } 3737 3738 KASSERT(ring->queued > 0, ("ring->queued is empty?")); 3739 ring->queued--; 3740 if (ring->queued == 0) 3741 iwm_pcie_clear_cmd_in_flight(sc); 3742 } 3743 3744 #if 0 3745 /* 3746 * necessary only for block ack mode 3747 */ 3748 void 3749 iwm_update_sched(struct iwm_softc *sc, int qid, int idx, uint8_t sta_id, 3750 uint16_t len) 3751 { 3752 struct iwm_agn_scd_bc_tbl *scd_bc_tbl; 3753 uint16_t w_val; 3754 3755 scd_bc_tbl = sc->sched_dma.vaddr; 3756 3757 len += 8; /* magic numbers came naturally from paris */ 3758 len = roundup(len, 4) / 4; 3759 3760 w_val = htole16(sta_id << 12 | len); 3761 3762 /* Update TX scheduler. */ 3763 scd_bc_tbl[qid].tfd_offset[idx] = w_val; 3764 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3765 BUS_DMASYNC_PREWRITE); 3766 3767 /* I really wonder what this is ?!? */ 3768 if (idx < IWM_TFD_QUEUE_SIZE_BC_DUP) { 3769 scd_bc_tbl[qid].tfd_offset[IWM_TFD_QUEUE_SIZE_MAX + idx] = w_val; 3770 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3771 BUS_DMASYNC_PREWRITE); 3772 } 3773 } 3774 #endif 3775 3776 static int 3777 iwm_tx_rateidx_global_lookup(struct iwm_softc *sc, uint8_t rate) 3778 { 3779 int i; 3780 3781 for (i = 0; i < nitems(iwm_rates); i++) { 3782 if (iwm_rates[i].rate == rate) 3783 return (i); 3784 } 3785 /* XXX error? */ 3786 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE, 3787 "%s: couldn't find an entry for rate=%d\n", 3788 __func__, 3789 rate); 3790 return (0); 3791 } 3792 3793 /* 3794 * Fill in the rate related information for a transmit command. 3795 */ 3796 static const struct iwm_rate * 3797 iwm_tx_fill_cmd(struct iwm_softc *sc, struct iwm_node *in, 3798 struct mbuf *m, struct iwm_tx_cmd *tx) 3799 { 3800 struct ieee80211_node *ni = &in->in_ni; 3801 struct ieee80211_frame *wh; 3802 const struct ieee80211_txparam *tp = ni->ni_txparms; 3803 const struct iwm_rate *rinfo; 3804 int type; 3805 int ridx, rate_flags; 3806 3807 wh = mtod(m, struct ieee80211_frame *); 3808 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3809 3810 tx->rts_retry_limit = IWM_RTS_DFAULT_RETRY_LIMIT; 3811 tx->data_retry_limit = IWM_DEFAULT_TX_RETRY; 3812 3813 if (type == IEEE80211_FC0_TYPE_MGT || 3814 type == IEEE80211_FC0_TYPE_CTL || 3815 (m->m_flags & M_EAPOL) != 0) { 3816 ridx = iwm_tx_rateidx_global_lookup(sc, tp->mgmtrate); 3817 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3818 "%s: MGT (%d)\n", __func__, tp->mgmtrate); 3819 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3820 ridx = iwm_tx_rateidx_global_lookup(sc, tp->mcastrate); 3821 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3822 "%s: MCAST (%d)\n", __func__, tp->mcastrate); 3823 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 3824 ridx = iwm_tx_rateidx_global_lookup(sc, tp->ucastrate); 3825 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3826 "%s: FIXED_RATE (%d)\n", __func__, tp->ucastrate); 3827 } else { 3828 /* for data frames, use RS table */ 3829 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: DATA\n", __func__); 3830 ridx = iwm_rate2ridx(sc, 3831 ieee80211_node_get_txrate_dot11rate(ni)); 3832 if (ridx == -1) 3833 ridx = 0; 3834 3835 /* This is the index into the programmed table */ 3836 tx->initial_rate_index = 0; 3837 tx->tx_flags |= htole32(IWM_TX_CMD_FLG_STA_RATE); 3838 } 3839 3840 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE, 3841 "%s: frame type=%d txrate %d\n", 3842 __func__, type, iwm_rates[ridx].rate); 3843 3844 rinfo = &iwm_rates[ridx]; 3845 3846 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: ridx=%d; rate=%d, CCK=%d\n", 3847 __func__, ridx, 3848 rinfo->rate, 3849 !! (IWM_RIDX_IS_CCK(ridx)) 3850 ); 3851 3852 /* XXX TODO: hard-coded TX antenna? */ 3853 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_9000) 3854 rate_flags = IWM_RATE_MCS_ANT_B_MSK; 3855 else 3856 rate_flags = IWM_RATE_MCS_ANT_A_MSK; 3857 if (IWM_RIDX_IS_CCK(ridx)) 3858 rate_flags |= IWM_RATE_MCS_CCK_MSK; 3859 tx->rate_n_flags = htole32(rate_flags | rinfo->plcp); 3860 3861 return rinfo; 3862 } 3863 3864 #define TB0_SIZE 16 3865 static int 3866 iwm_tx(struct iwm_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 3867 { 3868 struct ieee80211com *ic = &sc->sc_ic; 3869 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3870 struct iwm_node *in = IWM_NODE(ni); 3871 struct iwm_tx_ring *ring; 3872 struct iwm_tx_data *data; 3873 struct iwm_tfd *desc; 3874 struct iwm_device_cmd *cmd; 3875 struct iwm_tx_cmd *tx; 3876 struct ieee80211_frame *wh; 3877 struct ieee80211_key *k = NULL; 3878 struct mbuf *m1; 3879 const struct iwm_rate *rinfo; 3880 uint32_t flags; 3881 u_int hdrlen; 3882 bus_dma_segment_t *seg, segs[IWM_MAX_SCATTER]; 3883 int nsegs; 3884 uint8_t tid, type; 3885 int i, totlen, error, pad; 3886 int qid; 3887 3888 wh = mtod(m, struct ieee80211_frame *); 3889 hdrlen = ieee80211_anyhdrsize(wh); 3890 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3891 tid = 0; 3892 3893 /* Map EDCA categories to Tx data queues. */ 3894 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_DQA_SUPPORT)) 3895 qid = IWM_DQA_MIN_MGMT_QUEUE + ac; 3896 else 3897 qid = ac; 3898 3899 ring = &sc->txq[qid]; 3900 desc = &ring->desc[ring->cur]; 3901 memset(desc, 0, sizeof(*desc)); 3902 data = &ring->data[ring->cur]; 3903 3904 /* Fill out iwm_tx_cmd to send to the firmware */ 3905 cmd = &ring->cmd[ring->cur]; 3906 cmd->hdr.code = IWM_TX_CMD; 3907 cmd->hdr.flags = 0; 3908 cmd->hdr.qid = ring->qid; 3909 cmd->hdr.idx = ring->cur; 3910 3911 tx = (void *)cmd->data; 3912 memset(tx, 0, sizeof(*tx)); 3913 3914 rinfo = iwm_tx_fill_cmd(sc, in, m, tx); 3915 3916 /* Offloaded sequence number assignment; non-AMPDU case */ 3917 if ((m->m_flags & M_AMPDU_MPDU) == 0) 3918 ieee80211_output_seqno_assign(ni, -1, m); 3919 3920 /* Encrypt the frame if need be. */ 3921 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3922 /* Retrieve key for TX && do software encryption. */ 3923 k = ieee80211_crypto_encap(ni, m); 3924 if (k == NULL) { 3925 m_freem(m); 3926 return (ENOBUFS); 3927 } 3928 /* 802.11 header may have moved. */ 3929 wh = mtod(m, struct ieee80211_frame *); 3930 } 3931 3932 if (ieee80211_radiotap_active_vap(vap)) { 3933 struct iwm_tx_radiotap_header *tap = &sc->sc_txtap; 3934 3935 tap->wt_flags = 0; 3936 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 3937 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 3938 tap->wt_rate = rinfo->rate; 3939 if (k != NULL) 3940 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3941 ieee80211_radiotap_tx(vap, m); 3942 } 3943 3944 flags = 0; 3945 totlen = m->m_pkthdr.len; 3946 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3947 flags |= IWM_TX_CMD_FLG_ACK; 3948 } 3949 3950 if (type == IEEE80211_FC0_TYPE_DATA && 3951 totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold && 3952 !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3953 flags |= IWM_TX_CMD_FLG_PROT_REQUIRE; 3954 } 3955 3956 tx->sta_id = IWM_STATION_ID; 3957 3958 if (type == IEEE80211_FC0_TYPE_MGT) { 3959 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3960 3961 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3962 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) { 3963 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_ASSOC); 3964 } else if (subtype == IEEE80211_FC0_SUBTYPE_ACTION) { 3965 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_NONE); 3966 } else { 3967 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_MGMT); 3968 } 3969 } else { 3970 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_NONE); 3971 } 3972 3973 if (hdrlen & 3) { 3974 /* First segment length must be a multiple of 4. */ 3975 flags |= IWM_TX_CMD_FLG_MH_PAD; 3976 tx->offload_assist |= htole16(IWM_TX_CMD_OFFLD_PAD); 3977 pad = 4 - (hdrlen & 3); 3978 } else { 3979 tx->offload_assist = 0; 3980 pad = 0; 3981 } 3982 3983 tx->len = htole16(totlen); 3984 tx->tid_tspec = tid; 3985 tx->life_time = htole32(IWM_TX_CMD_LIFE_TIME_INFINITE); 3986 3987 /* Set physical address of "scratch area". */ 3988 tx->dram_lsb_ptr = htole32(data->scratch_paddr); 3989 tx->dram_msb_ptr = iwm_get_dma_hi_addr(data->scratch_paddr); 3990 3991 /* Copy 802.11 header in TX command. */ 3992 memcpy((uint8_t *)tx + sizeof(*tx), wh, hdrlen); 3993 3994 flags |= IWM_TX_CMD_FLG_BT_DIS | IWM_TX_CMD_FLG_SEQ_CTL; 3995 3996 tx->sec_ctl = 0; 3997 tx->tx_flags |= htole32(flags); 3998 3999 /* Trim 802.11 header. */ 4000 m_adj(m, hdrlen); 4001 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4002 segs, &nsegs, BUS_DMA_NOWAIT); 4003 if (error != 0) { 4004 if (error != EFBIG) { 4005 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 4006 error); 4007 m_freem(m); 4008 return error; 4009 } 4010 /* Too many DMA segments, linearize mbuf. */ 4011 m1 = m_collapse(m, M_NOWAIT, IWM_MAX_SCATTER - 2); 4012 if (m1 == NULL) { 4013 device_printf(sc->sc_dev, 4014 "%s: could not defrag mbuf\n", __func__); 4015 m_freem(m); 4016 return (ENOBUFS); 4017 } 4018 m = m1; 4019 4020 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4021 segs, &nsegs, BUS_DMA_NOWAIT); 4022 if (error != 0) { 4023 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 4024 error); 4025 m_freem(m); 4026 return error; 4027 } 4028 } 4029 data->m = m; 4030 data->in = in; 4031 data->done = 0; 4032 4033 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 4034 "sending txd %p, in %p\n", data, data->in); 4035 KASSERT(data->in != NULL, ("node is NULL")); 4036 4037 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 4038 "sending data: qid=%d idx=%d len=%d nsegs=%d txflags=0x%08x rate_n_flags=0x%08x rateidx=%u\n", 4039 ring->qid, ring->cur, totlen, nsegs, 4040 le32toh(tx->tx_flags), 4041 le32toh(tx->rate_n_flags), 4042 tx->initial_rate_index 4043 ); 4044 4045 /* Fill TX descriptor. */ 4046 memset(desc, 0, sizeof(*desc)); 4047 desc->num_tbs = 2 + nsegs; 4048 4049 desc->tbs[0].lo = htole32(data->cmd_paddr); 4050 desc->tbs[0].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr) | 4051 (TB0_SIZE << 4)); 4052 desc->tbs[1].lo = htole32(data->cmd_paddr + TB0_SIZE); 4053 desc->tbs[1].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr) | 4054 ((sizeof(struct iwm_cmd_header) + sizeof(*tx) + 4055 hdrlen + pad - TB0_SIZE) << 4)); 4056 4057 /* Other DMA segments are for data payload. */ 4058 for (i = 0; i < nsegs; i++) { 4059 seg = &segs[i]; 4060 desc->tbs[i + 2].lo = htole32(seg->ds_addr); 4061 desc->tbs[i + 2].hi_n_len = 4062 htole16(iwm_get_dma_hi_addr(seg->ds_addr)) | 4063 (seg->ds_len << 4); 4064 } 4065 4066 bus_dmamap_sync(ring->data_dmat, data->map, 4067 BUS_DMASYNC_PREWRITE); 4068 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 4069 BUS_DMASYNC_PREWRITE); 4070 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4071 BUS_DMASYNC_PREWRITE); 4072 4073 #if 0 4074 iwm_update_sched(sc, ring->qid, ring->cur, tx->sta_id, le16toh(tx->len)); 4075 #endif 4076 4077 /* Kick TX ring. */ 4078 ring->cur = (ring->cur + 1) % IWM_TX_RING_COUNT; 4079 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4080 4081 /* Mark TX ring as full if we reach a certain threshold. */ 4082 if (++ring->queued > IWM_TX_RING_HIMARK) { 4083 sc->qfullmsk |= 1 << ring->qid; 4084 } 4085 4086 return 0; 4087 } 4088 4089 static int 4090 iwm_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4091 const struct ieee80211_bpf_params *params) 4092 { 4093 struct ieee80211com *ic = ni->ni_ic; 4094 struct iwm_softc *sc = ic->ic_softc; 4095 int error = 0; 4096 4097 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 4098 "->%s begin\n", __func__); 4099 4100 if ((sc->sc_flags & IWM_FLAG_HW_INITED) == 0) { 4101 m_freem(m); 4102 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 4103 "<-%s not RUNNING\n", __func__); 4104 return (ENETDOWN); 4105 } 4106 4107 IWM_LOCK(sc); 4108 /* XXX fix this */ 4109 if (params == NULL) { 4110 error = iwm_tx(sc, m, ni, 0); 4111 } else { 4112 error = iwm_tx(sc, m, ni, 0); 4113 } 4114 if (sc->sc_tx_timer == 0) 4115 callout_reset(&sc->sc_watchdog_to, hz, iwm_watchdog, sc); 4116 sc->sc_tx_timer = 5; 4117 IWM_UNLOCK(sc); 4118 4119 return (error); 4120 } 4121 4122 /* 4123 * mvm/tx.c 4124 */ 4125 4126 /* 4127 * Note that there are transports that buffer frames before they reach 4128 * the firmware. This means that after flush_tx_path is called, the 4129 * queue might not be empty. The race-free way to handle this is to: 4130 * 1) set the station as draining 4131 * 2) flush the Tx path 4132 * 3) wait for the transport queues to be empty 4133 */ 4134 int 4135 iwm_flush_tx_path(struct iwm_softc *sc, uint32_t tfd_msk, uint32_t flags) 4136 { 4137 int ret; 4138 struct iwm_tx_path_flush_cmd_v1 flush_cmd = { 4139 .queues_ctl = htole32(tfd_msk), 4140 .flush_ctl = htole16(IWM_DUMP_TX_FIFO_FLUSH), 4141 }; 4142 4143 ret = iwm_send_cmd_pdu(sc, IWM_TXPATH_FLUSH, flags, 4144 sizeof(flush_cmd), &flush_cmd); 4145 if (ret) 4146 device_printf(sc->sc_dev, 4147 "Flushing tx queue failed: %d\n", ret); 4148 return ret; 4149 } 4150 4151 /* 4152 * BEGIN mvm/quota.c 4153 */ 4154 4155 static int 4156 iwm_update_quotas(struct iwm_softc *sc, struct iwm_vap *ivp) 4157 { 4158 struct iwm_time_quota_cmd_v1 cmd; 4159 int i, idx, ret, num_active_macs, quota, quota_rem; 4160 int colors[IWM_MAX_BINDINGS] = { -1, -1, -1, -1, }; 4161 int n_ifs[IWM_MAX_BINDINGS] = {0, }; 4162 uint16_t id; 4163 4164 memset(&cmd, 0, sizeof(cmd)); 4165 4166 /* currently, PHY ID == binding ID */ 4167 if (ivp) { 4168 id = ivp->phy_ctxt->id; 4169 KASSERT(id < IWM_MAX_BINDINGS, ("invalid id")); 4170 colors[id] = ivp->phy_ctxt->color; 4171 4172 if (1) 4173 n_ifs[id] = 1; 4174 } 4175 4176 /* 4177 * The FW's scheduling session consists of 4178 * IWM_MAX_QUOTA fragments. Divide these fragments 4179 * equally between all the bindings that require quota 4180 */ 4181 num_active_macs = 0; 4182 for (i = 0; i < IWM_MAX_BINDINGS; i++) { 4183 cmd.quotas[i].id_and_color = htole32(IWM_FW_CTXT_INVALID); 4184 num_active_macs += n_ifs[i]; 4185 } 4186 4187 quota = 0; 4188 quota_rem = 0; 4189 if (num_active_macs) { 4190 quota = IWM_MAX_QUOTA / num_active_macs; 4191 quota_rem = IWM_MAX_QUOTA % num_active_macs; 4192 } 4193 4194 for (idx = 0, i = 0; i < IWM_MAX_BINDINGS; i++) { 4195 if (colors[i] < 0) 4196 continue; 4197 4198 cmd.quotas[idx].id_and_color = 4199 htole32(IWM_FW_CMD_ID_AND_COLOR(i, colors[i])); 4200 4201 if (n_ifs[i] <= 0) { 4202 cmd.quotas[idx].quota = htole32(0); 4203 cmd.quotas[idx].max_duration = htole32(0); 4204 } else { 4205 cmd.quotas[idx].quota = htole32(quota * n_ifs[i]); 4206 cmd.quotas[idx].max_duration = htole32(0); 4207 } 4208 idx++; 4209 } 4210 4211 /* Give the remainder of the session to the first binding */ 4212 cmd.quotas[0].quota = htole32(le32toh(cmd.quotas[0].quota) + quota_rem); 4213 4214 ret = iwm_send_cmd_pdu(sc, IWM_TIME_QUOTA_CMD, IWM_CMD_SYNC, 4215 sizeof(cmd), &cmd); 4216 if (ret) 4217 device_printf(sc->sc_dev, 4218 "%s: Failed to send quota: %d\n", __func__, ret); 4219 return ret; 4220 } 4221 4222 /* 4223 * END mvm/quota.c 4224 */ 4225 4226 /* 4227 * ieee80211 routines 4228 */ 4229 4230 /* 4231 * Change to AUTH state in 80211 state machine. Roughly matches what 4232 * Linux does in bss_info_changed(). 4233 */ 4234 static int 4235 iwm_auth(struct ieee80211vap *vap, struct iwm_softc *sc) 4236 { 4237 struct ieee80211_node *ni; 4238 struct iwm_node *in; 4239 struct iwm_vap *iv = IWM_VAP(vap); 4240 uint32_t duration; 4241 int error; 4242 4243 /* 4244 * XXX i have a feeling that the vap node is being 4245 * freed from underneath us. Grr. 4246 */ 4247 ni = ieee80211_ref_node(vap->iv_bss); 4248 in = IWM_NODE(ni); 4249 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_STATE, 4250 "%s: called; vap=%p, bss ni=%p\n", 4251 __func__, 4252 vap, 4253 ni); 4254 IWM_DPRINTF(sc, IWM_DEBUG_STATE, "%s: Current node bssid: %s\n", 4255 __func__, ether_sprintf(ni->ni_bssid)); 4256 4257 in->in_assoc = 0; 4258 iv->iv_auth = 1; 4259 4260 /* 4261 * Firmware bug - it'll crash if the beacon interval is less 4262 * than 16. We can't avoid connecting at all, so refuse the 4263 * station state change, this will cause net80211 to abandon 4264 * attempts to connect to this AP, and eventually wpa_s will 4265 * blacklist the AP... 4266 */ 4267 if (ni->ni_intval < 16) { 4268 device_printf(sc->sc_dev, 4269 "AP %s beacon interval is %d, refusing due to firmware bug!\n", 4270 ether_sprintf(ni->ni_bssid), ni->ni_intval); 4271 error = EINVAL; 4272 goto out; 4273 } 4274 4275 error = iwm_allow_mcast(vap, sc); 4276 if (error) { 4277 device_printf(sc->sc_dev, 4278 "%s: failed to set multicast\n", __func__); 4279 goto out; 4280 } 4281 4282 /* 4283 * This is where it deviates from what Linux does. 4284 * 4285 * Linux iwlwifi doesn't reset the nic each time, nor does it 4286 * call ctxt_add() here. Instead, it adds it during vap creation, 4287 * and always does a mac_ctx_changed(). 4288 * 4289 * The openbsd port doesn't attempt to do that - it reset things 4290 * at odd states and does the add here. 4291 * 4292 * So, until the state handling is fixed (ie, we never reset 4293 * the NIC except for a firmware failure, which should drag 4294 * the NIC back to IDLE, re-setup and re-add all the mac/phy 4295 * contexts that are required), let's do a dirty hack here. 4296 */ 4297 if (iv->is_uploaded) { 4298 if ((error = iwm_mac_ctxt_changed(sc, vap)) != 0) { 4299 device_printf(sc->sc_dev, 4300 "%s: failed to update MAC\n", __func__); 4301 goto out; 4302 } 4303 } else { 4304 if ((error = iwm_mac_ctxt_add(sc, vap)) != 0) { 4305 device_printf(sc->sc_dev, 4306 "%s: failed to add MAC\n", __func__); 4307 goto out; 4308 } 4309 } 4310 sc->sc_firmware_state = 1; 4311 4312 if ((error = iwm_phy_ctxt_changed(sc, &sc->sc_phyctxt[0], 4313 in->in_ni.ni_chan, 1, 1)) != 0) { 4314 device_printf(sc->sc_dev, 4315 "%s: failed update phy ctxt\n", __func__); 4316 goto out; 4317 } 4318 iv->phy_ctxt = &sc->sc_phyctxt[0]; 4319 4320 if ((error = iwm_binding_add_vif(sc, iv)) != 0) { 4321 device_printf(sc->sc_dev, 4322 "%s: binding update cmd\n", __func__); 4323 goto out; 4324 } 4325 sc->sc_firmware_state = 2; 4326 /* 4327 * Authentication becomes unreliable when powersaving is left enabled 4328 * here. Powersaving will be activated again when association has 4329 * finished or is aborted. 4330 */ 4331 iv->ps_disabled = TRUE; 4332 error = iwm_power_update_mac(sc); 4333 iv->ps_disabled = FALSE; 4334 if (error != 0) { 4335 device_printf(sc->sc_dev, 4336 "%s: failed to update power management\n", 4337 __func__); 4338 goto out; 4339 } 4340 if ((error = iwm_add_sta(sc, in)) != 0) { 4341 device_printf(sc->sc_dev, 4342 "%s: failed to add sta\n", __func__); 4343 goto out; 4344 } 4345 sc->sc_firmware_state = 3; 4346 4347 /* 4348 * Prevent the FW from wandering off channel during association 4349 * by "protecting" the session with a time event. 4350 */ 4351 /* XXX duration is in units of TU, not MS */ 4352 duration = IWM_TE_SESSION_PROTECTION_MAX_TIME_MS; 4353 iwm_protect_session(sc, iv, duration, 500 /* XXX magic number */, TRUE); 4354 4355 error = 0; 4356 out: 4357 if (error != 0) 4358 iv->iv_auth = 0; 4359 ieee80211_free_node(ni); 4360 return (error); 4361 } 4362 4363 static struct ieee80211_node * 4364 iwm_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 4365 { 4366 return malloc(sizeof (struct iwm_node), M_80211_NODE, 4367 M_NOWAIT | M_ZERO); 4368 } 4369 4370 static uint8_t 4371 iwm_rate_from_ucode_rate(uint32_t rate_n_flags) 4372 { 4373 uint8_t plcp = rate_n_flags & 0xff; 4374 int i; 4375 4376 for (i = 0; i <= IWM_RIDX_MAX; i++) { 4377 if (iwm_rates[i].plcp == plcp) 4378 return iwm_rates[i].rate; 4379 } 4380 return 0; 4381 } 4382 4383 uint8_t 4384 iwm_ridx2rate(struct ieee80211_rateset *rs, int ridx) 4385 { 4386 int i; 4387 uint8_t rval; 4388 4389 for (i = 0; i < rs->rs_nrates; i++) { 4390 rval = (rs->rs_rates[i] & IEEE80211_RATE_VAL); 4391 if (rval == iwm_rates[ridx].rate) 4392 return rs->rs_rates[i]; 4393 } 4394 4395 return 0; 4396 } 4397 4398 static int 4399 iwm_rate2ridx(struct iwm_softc *sc, uint8_t rate) 4400 { 4401 int i; 4402 4403 for (i = 0; i <= IWM_RIDX_MAX; i++) { 4404 if (iwm_rates[i].rate == rate) 4405 return i; 4406 } 4407 4408 device_printf(sc->sc_dev, 4409 "%s: WARNING: device rate for %u not found!\n", 4410 __func__, rate); 4411 4412 return -1; 4413 } 4414 4415 4416 static void 4417 iwm_setrates(struct iwm_softc *sc, struct iwm_node *in, int dot11rate) 4418 { 4419 struct ieee80211_node *ni = &in->in_ni; 4420 struct iwm_lq_cmd *lq = &in->in_lq; 4421 struct ieee80211_rateset *rs = &ni->ni_rates; 4422 int nrates = rs->rs_nrates; 4423 int i, ridx, tab = 0; 4424 // int txant = 0; 4425 int rix; 4426 4427 /* 4428 * Look up the rate index for the given legacy rate from 4429 * the rs_rates table. Default to the lowest rate if it's 4430 * not found (which is obviously hugely problematic.) 4431 */ 4432 rix = -1; 4433 for (i = 0; i < nrates; i++) { 4434 int rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 4435 if (rate == dot11rate) { 4436 rix = i; 4437 break; 4438 } 4439 } 4440 if (rix < 0) { 4441 device_printf(sc->sc_dev, 4442 "%s: failed to lookup dot11rate (%d)\n", 4443 __func__, dot11rate); 4444 rix = 0; 4445 } 4446 4447 if (nrates > nitems(lq->rs_table)) { 4448 device_printf(sc->sc_dev, 4449 "%s: node supports %d rates, driver handles " 4450 "only %zu\n", __func__, nrates, nitems(lq->rs_table)); 4451 return; 4452 } 4453 if (nrates == 0) { 4454 device_printf(sc->sc_dev, 4455 "%s: node supports 0 rates, odd!\n", __func__); 4456 return; 4457 } 4458 nrates = imin(rix + 1, nrates); 4459 4460 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 4461 "%s: nrates=%d\n", __func__, nrates); 4462 4463 /* then construct a lq_cmd based on those */ 4464 memset(lq, 0, sizeof(*lq)); 4465 lq->sta_id = IWM_STATION_ID; 4466 4467 /* For HT, always enable RTS/CTS to avoid excessive retries. */ 4468 if (ni->ni_flags & IEEE80211_NODE_HT) 4469 lq->flags |= IWM_LQ_FLAG_USE_RTS_MSK; 4470 4471 /* 4472 * are these used? (we don't do SISO or MIMO) 4473 * need to set them to non-zero, though, or we get an error. 4474 */ 4475 lq->single_stream_ant_msk = 1; 4476 lq->dual_stream_ant_msk = 1; 4477 4478 /* 4479 * Build the actual rate selection table. 4480 * The lowest bits are the rates. Additionally, 4481 * CCK needs bit 9 to be set. The rest of the bits 4482 * we add to the table select the tx antenna 4483 * Note that we add the rates in the highest rate first 4484 * (opposite of ni_rates). 4485 */ 4486 for (i = 0; i < nrates; i++) { 4487 int rate = rs->rs_rates[rix - i] & IEEE80211_RATE_VAL; 4488 int nextant; 4489 4490 /* Map 802.11 rate to HW rate index. */ 4491 ridx = iwm_rate2ridx(sc, rate); 4492 if (ridx == -1) 4493 continue; 4494 4495 #if 0 4496 if (txant == 0) 4497 txant = iwm_get_valid_tx_ant(sc); 4498 nextant = 1<<(ffs(txant)-1); 4499 txant &= ~nextant; 4500 #else 4501 nextant = iwm_get_valid_tx_ant(sc); 4502 #endif 4503 tab = iwm_rates[ridx].plcp; 4504 tab |= nextant << IWM_RATE_MCS_ANT_POS; 4505 if (IWM_RIDX_IS_CCK(ridx)) 4506 tab |= IWM_RATE_MCS_CCK_MSK; 4507 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 4508 "station rate i=%d, rate=%d, hw=%x\n", 4509 i, iwm_rates[ridx].rate, tab); 4510 lq->rs_table[i] = htole32(tab); 4511 } 4512 /* then fill the rest with the lowest possible rate */ 4513 for (i = nrates; i < nitems(lq->rs_table); i++) { 4514 KASSERT(tab != 0, ("invalid tab")); 4515 lq->rs_table[i] = htole32(tab); 4516 } 4517 } 4518 4519 static void 4520 iwm_bring_down_firmware(struct iwm_softc *sc, struct ieee80211vap *vap) 4521 { 4522 struct iwm_vap *ivp = IWM_VAP(vap); 4523 int error; 4524 4525 /* Avoid Tx watchdog triggering, when transfers get dropped here. */ 4526 sc->sc_tx_timer = 0; 4527 4528 ivp->iv_auth = 0; 4529 if (sc->sc_firmware_state == 3) { 4530 iwm_xmit_queue_drain(sc); 4531 // iwm_flush_tx_path(sc, 0xf, IWM_CMD_SYNC); 4532 error = iwm_rm_sta(sc, vap, TRUE); 4533 if (error) { 4534 device_printf(sc->sc_dev, 4535 "%s: Failed to remove station: %d\n", 4536 __func__, error); 4537 } 4538 } 4539 if (sc->sc_firmware_state == 3) { 4540 error = iwm_mac_ctxt_changed(sc, vap); 4541 if (error) { 4542 device_printf(sc->sc_dev, 4543 "%s: Failed to change mac context: %d\n", 4544 __func__, error); 4545 } 4546 } 4547 if (sc->sc_firmware_state == 3) { 4548 error = iwm_sf_update(sc, vap, FALSE); 4549 if (error) { 4550 device_printf(sc->sc_dev, 4551 "%s: Failed to update smart FIFO: %d\n", 4552 __func__, error); 4553 } 4554 } 4555 if (sc->sc_firmware_state == 3) { 4556 error = iwm_rm_sta_id(sc, vap); 4557 if (error) { 4558 device_printf(sc->sc_dev, 4559 "%s: Failed to remove station id: %d\n", 4560 __func__, error); 4561 } 4562 } 4563 if (sc->sc_firmware_state == 3) { 4564 error = iwm_update_quotas(sc, NULL); 4565 if (error) { 4566 device_printf(sc->sc_dev, 4567 "%s: Failed to update PHY quota: %d\n", 4568 __func__, error); 4569 } 4570 } 4571 if (sc->sc_firmware_state == 3) { 4572 /* XXX Might need to specify bssid correctly. */ 4573 error = iwm_mac_ctxt_changed(sc, vap); 4574 if (error) { 4575 device_printf(sc->sc_dev, 4576 "%s: Failed to change mac context: %d\n", 4577 __func__, error); 4578 } 4579 } 4580 if (sc->sc_firmware_state == 3) { 4581 sc->sc_firmware_state = 2; 4582 } 4583 if (sc->sc_firmware_state > 1) { 4584 error = iwm_binding_remove_vif(sc, ivp); 4585 if (error) { 4586 device_printf(sc->sc_dev, 4587 "%s: Failed to remove channel ctx: %d\n", 4588 __func__, error); 4589 } 4590 } 4591 if (sc->sc_firmware_state > 1) { 4592 sc->sc_firmware_state = 1; 4593 } 4594 ivp->phy_ctxt = NULL; 4595 if (sc->sc_firmware_state > 0) { 4596 error = iwm_mac_ctxt_changed(sc, vap); 4597 if (error) { 4598 device_printf(sc->sc_dev, 4599 "%s: Failed to change mac context: %d\n", 4600 __func__, error); 4601 } 4602 } 4603 if (sc->sc_firmware_state > 0) { 4604 error = iwm_power_update_mac(sc); 4605 if (error != 0) { 4606 device_printf(sc->sc_dev, 4607 "%s: failed to update power management\n", 4608 __func__); 4609 } 4610 } 4611 sc->sc_firmware_state = 0; 4612 } 4613 4614 static int 4615 iwm_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4616 { 4617 struct iwm_vap *ivp = IWM_VAP(vap); 4618 struct ieee80211com *ic = vap->iv_ic; 4619 struct iwm_softc *sc = ic->ic_softc; 4620 struct iwm_node *in; 4621 int error; 4622 4623 IWM_DPRINTF(sc, IWM_DEBUG_STATE, 4624 "switching state %s -> %s arg=0x%x\n", 4625 ieee80211_state_name[vap->iv_state], 4626 ieee80211_state_name[nstate], 4627 arg); 4628 4629 IEEE80211_UNLOCK(ic); 4630 IWM_LOCK(sc); 4631 4632 if ((sc->sc_flags & IWM_FLAG_SCAN_RUNNING) && 4633 (nstate == IEEE80211_S_AUTH || 4634 nstate == IEEE80211_S_ASSOC || 4635 nstate == IEEE80211_S_RUN)) { 4636 /* Stop blinking for a scan, when authenticating. */ 4637 iwm_led_blink_stop(sc); 4638 } 4639 4640 if (vap->iv_state == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 4641 iwm_led_disable(sc); 4642 /* disable beacon filtering if we're hopping out of RUN */ 4643 iwm_disable_beacon_filter(sc); 4644 if (((in = IWM_NODE(vap->iv_bss)) != NULL)) 4645 in->in_assoc = 0; 4646 } 4647 4648 if ((vap->iv_state == IEEE80211_S_AUTH || 4649 vap->iv_state == IEEE80211_S_ASSOC || 4650 vap->iv_state == IEEE80211_S_RUN) && 4651 (nstate == IEEE80211_S_INIT || 4652 nstate == IEEE80211_S_SCAN || 4653 nstate == IEEE80211_S_AUTH)) { 4654 iwm_stop_session_protection(sc, ivp); 4655 } 4656 4657 if ((vap->iv_state == IEEE80211_S_RUN || 4658 vap->iv_state == IEEE80211_S_ASSOC) && 4659 nstate == IEEE80211_S_INIT) { 4660 /* 4661 * In this case, iv_newstate() wants to send an 80211 frame on 4662 * the network that we are leaving. So we need to call it, 4663 * before tearing down all the firmware state. 4664 */ 4665 IWM_UNLOCK(sc); 4666 IEEE80211_LOCK(ic); 4667 ivp->iv_newstate(vap, nstate, arg); 4668 IEEE80211_UNLOCK(ic); 4669 IWM_LOCK(sc); 4670 iwm_bring_down_firmware(sc, vap); 4671 IWM_UNLOCK(sc); 4672 IEEE80211_LOCK(ic); 4673 return 0; 4674 } 4675 4676 switch (nstate) { 4677 case IEEE80211_S_INIT: 4678 case IEEE80211_S_SCAN: 4679 break; 4680 4681 case IEEE80211_S_AUTH: 4682 iwm_bring_down_firmware(sc, vap); 4683 if ((error = iwm_auth(vap, sc)) != 0) { 4684 device_printf(sc->sc_dev, 4685 "%s: could not move to auth state: %d\n", 4686 __func__, error); 4687 iwm_bring_down_firmware(sc, vap); 4688 IWM_UNLOCK(sc); 4689 IEEE80211_LOCK(ic); 4690 return 1; 4691 } 4692 break; 4693 4694 case IEEE80211_S_ASSOC: 4695 /* 4696 * EBS may be disabled due to previous failures reported by FW. 4697 * Reset EBS status here assuming environment has been changed. 4698 */ 4699 sc->last_ebs_successful = TRUE; 4700 break; 4701 4702 case IEEE80211_S_RUN: 4703 in = IWM_NODE(vap->iv_bss); 4704 /* Update the association state, now we have it all */ 4705 /* (eg associd comes in at this point */ 4706 error = iwm_update_sta(sc, in); 4707 if (error != 0) { 4708 device_printf(sc->sc_dev, 4709 "%s: failed to update STA\n", __func__); 4710 IWM_UNLOCK(sc); 4711 IEEE80211_LOCK(ic); 4712 return error; 4713 } 4714 in->in_assoc = 1; 4715 error = iwm_mac_ctxt_changed(sc, vap); 4716 if (error != 0) { 4717 device_printf(sc->sc_dev, 4718 "%s: failed to update MAC: %d\n", __func__, error); 4719 } 4720 4721 iwm_sf_update(sc, vap, FALSE); 4722 iwm_enable_beacon_filter(sc, ivp); 4723 iwm_power_update_mac(sc); 4724 iwm_update_quotas(sc, ivp); 4725 ieee80211_ratectl_rate(&in->in_ni, NULL, 0); 4726 iwm_setrates(sc, in, 4727 ieee80211_node_get_txrate_dot11rate(&in->in_ni)); 4728 4729 if ((error = iwm_send_lq_cmd(sc, &in->in_lq, TRUE)) != 0) { 4730 device_printf(sc->sc_dev, 4731 "%s: IWM_LQ_CMD failed: %d\n", __func__, error); 4732 } 4733 4734 iwm_led_enable(sc); 4735 break; 4736 4737 default: 4738 break; 4739 } 4740 IWM_UNLOCK(sc); 4741 IEEE80211_LOCK(ic); 4742 4743 return (ivp->iv_newstate(vap, nstate, arg)); 4744 } 4745 4746 void 4747 iwm_endscan_cb(void *arg, int pending) 4748 { 4749 struct iwm_softc *sc = arg; 4750 struct ieee80211com *ic = &sc->sc_ic; 4751 4752 IWM_DPRINTF(sc, IWM_DEBUG_SCAN | IWM_DEBUG_TRACE, 4753 "%s: scan ended\n", 4754 __func__); 4755 4756 ieee80211_scan_done(TAILQ_FIRST(&ic->ic_vaps)); 4757 } 4758 4759 static int 4760 iwm_send_bt_init_conf(struct iwm_softc *sc) 4761 { 4762 struct iwm_bt_coex_cmd bt_cmd; 4763 4764 bt_cmd.mode = htole32(IWM_BT_COEX_WIFI); 4765 bt_cmd.enabled_modules = htole32(IWM_BT_COEX_HIGH_BAND_RET); 4766 4767 return iwm_send_cmd_pdu(sc, IWM_BT_CONFIG, 0, sizeof(bt_cmd), 4768 &bt_cmd); 4769 } 4770 4771 static int 4772 iwm_send_soc_conf(struct iwm_softc *sc) 4773 { 4774 struct iwm_soc_configuration_cmd cmd; 4775 int err; 4776 uint32_t cmd_id, flags = 0; 4777 4778 memset(&cmd, 0, sizeof(cmd)); 4779 4780 /* 4781 * In VER_1 of this command, the discrete value is considered 4782 * an integer; In VER_2, it's a bitmask. Since we have only 2 4783 * values in VER_1, this is backwards-compatible with VER_2, 4784 * as long as we don't set any other flag bits. 4785 */ 4786 if (!sc->cfg->integrated) { /* VER_1 */ 4787 flags = IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE; 4788 } else { /* VER_2 */ 4789 uint8_t scan_cmd_ver; 4790 if (sc->cfg->ltr_delay != IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE) 4791 flags |= (sc->cfg->ltr_delay & 4792 IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK); 4793 scan_cmd_ver = iwm_lookup_cmd_ver(sc, IWM_LONG_GROUP, 4794 IWM_SCAN_REQ_UMAC); 4795 if (scan_cmd_ver != IWM_FW_CMD_VER_UNKNOWN && 4796 scan_cmd_ver >= 2 && sc->cfg->low_latency_xtal) 4797 flags |= IWM_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY; 4798 } 4799 cmd.flags = htole32(flags); 4800 4801 cmd.latency = htole32(sc->cfg->xtal_latency); 4802 4803 cmd_id = iwm_cmd_id(IWM_SOC_CONFIGURATION_CMD, IWM_SYSTEM_GROUP, 0); 4804 err = iwm_send_cmd_pdu(sc, cmd_id, 0, sizeof(cmd), &cmd); 4805 if (err) 4806 device_printf(sc->sc_dev, "failed to set soc latency: %d\n", 4807 err); 4808 return err; 4809 } 4810 4811 static int 4812 iwm_send_dqa_cmd(struct iwm_softc *sc) 4813 { 4814 struct iwm_dqa_enable_cmd dqa_cmd; 4815 uint32_t cmd_id; 4816 4817 dqa_cmd.cmd_queue = htole32(IWM_DQA_CMD_QUEUE); 4818 cmd_id = iwm_cmd_id(IWM_DQA_ENABLE_CMD, IWM_DATA_PATH_GROUP, 0); 4819 return iwm_send_cmd_pdu(sc, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); 4820 } 4821 4822 static int 4823 iwm_send_temp_report_ths_cmd(struct iwm_softc *sc) 4824 { 4825 struct iwm_temp_report_ths_cmd cmd; 4826 int err; 4827 4828 /* 4829 * In order to give responsibility for critical-temperature-kill 4830 * and TX backoff to FW we need to send an empty temperature 4831 * reporting command at init time. 4832 */ 4833 memset(&cmd, 0, sizeof(cmd)); 4834 4835 err = iwm_send_cmd_pdu(sc, 4836 IWM_WIDE_ID(IWM_PHY_OPS_GROUP, IWM_TEMP_REPORTING_THRESHOLDS_CMD), 4837 0, sizeof(cmd), &cmd); 4838 if (err) 4839 device_printf(sc->sc_dev, 4840 "TEMP_REPORT_THS_CMD command failed (error %d)\n", err); 4841 4842 return err; 4843 } 4844 4845 static boolean_t 4846 iwm_is_lar_supported(struct iwm_softc *sc) 4847 { 4848 boolean_t nvm_lar = sc->nvm_data->lar_enabled; 4849 boolean_t tlv_lar = iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_LAR_SUPPORT); 4850 4851 if (iwm_lar_disable) 4852 return FALSE; 4853 4854 /* 4855 * Enable LAR only if it is supported by the FW (TLV) && 4856 * enabled in the NVM 4857 */ 4858 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) 4859 return nvm_lar && tlv_lar; 4860 else 4861 return tlv_lar; 4862 } 4863 4864 static boolean_t 4865 iwm_is_wifi_mcc_supported(struct iwm_softc *sc) 4866 { 4867 return iwm_fw_has_api(sc, IWM_UCODE_TLV_API_WIFI_MCC_UPDATE) || 4868 iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC); 4869 } 4870 4871 static int 4872 iwm_send_update_mcc_cmd(struct iwm_softc *sc, const char *alpha2) 4873 { 4874 struct iwm_mcc_update_cmd mcc_cmd; 4875 struct iwm_host_cmd hcmd = { 4876 .id = IWM_MCC_UPDATE_CMD, 4877 .flags = (IWM_CMD_SYNC | IWM_CMD_WANT_SKB), 4878 .data = { &mcc_cmd }, 4879 }; 4880 int ret; 4881 #ifdef IWM_DEBUG 4882 struct iwm_rx_packet *pkt; 4883 struct iwm_mcc_update_resp_v1 *mcc_resp_v1 = NULL; 4884 struct iwm_mcc_update_resp_v2 *mcc_resp; 4885 int n_channels; 4886 uint16_t mcc; 4887 #endif 4888 int resp_v3 = iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V3); 4889 4890 if (!iwm_is_lar_supported(sc)) { 4891 IWM_DPRINTF(sc, IWM_DEBUG_LAR, "%s: no LAR support\n", 4892 __func__); 4893 return 0; 4894 } 4895 4896 memset(&mcc_cmd, 0, sizeof(mcc_cmd)); 4897 mcc_cmd.mcc = htole16(alpha2[0] << 8 | alpha2[1]); 4898 if (iwm_is_wifi_mcc_supported(sc)) 4899 mcc_cmd.source_id = IWM_MCC_SOURCE_GET_CURRENT; 4900 else 4901 mcc_cmd.source_id = IWM_MCC_SOURCE_OLD_FW; 4902 4903 if (resp_v3) 4904 hcmd.len[0] = sizeof(struct iwm_mcc_update_cmd); 4905 else 4906 hcmd.len[0] = sizeof(struct iwm_mcc_update_cmd_v1); 4907 4908 IWM_DPRINTF(sc, IWM_DEBUG_LAR, 4909 "send MCC update to FW with '%c%c' src = %d\n", 4910 alpha2[0], alpha2[1], mcc_cmd.source_id); 4911 4912 ret = iwm_send_cmd(sc, &hcmd); 4913 if (ret) 4914 return ret; 4915 4916 #ifdef IWM_DEBUG 4917 pkt = hcmd.resp_pkt; 4918 4919 /* Extract MCC response */ 4920 if (resp_v3) { 4921 mcc_resp = (void *)pkt->data; 4922 mcc = mcc_resp->mcc; 4923 n_channels = le32toh(mcc_resp->n_channels); 4924 } else { 4925 mcc_resp_v1 = (void *)pkt->data; 4926 mcc = mcc_resp_v1->mcc; 4927 n_channels = le32toh(mcc_resp_v1->n_channels); 4928 } 4929 4930 /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ 4931 if (mcc == 0) 4932 mcc = 0x3030; /* "00" - world */ 4933 4934 IWM_DPRINTF(sc, IWM_DEBUG_LAR, 4935 "regulatory domain '%c%c' (%d channels available)\n", 4936 mcc >> 8, mcc & 0xff, n_channels); 4937 #endif 4938 iwm_free_resp(sc, &hcmd); 4939 4940 return 0; 4941 } 4942 4943 static void 4944 iwm_tt_tx_backoff(struct iwm_softc *sc, uint32_t backoff) 4945 { 4946 struct iwm_host_cmd cmd = { 4947 .id = IWM_REPLY_THERMAL_MNG_BACKOFF, 4948 .len = { sizeof(uint32_t), }, 4949 .data = { &backoff, }, 4950 }; 4951 4952 if (iwm_send_cmd(sc, &cmd) != 0) { 4953 device_printf(sc->sc_dev, 4954 "failed to change thermal tx backoff\n"); 4955 } 4956 } 4957 4958 static int 4959 iwm_init_hw(struct iwm_softc *sc) 4960 { 4961 struct ieee80211com *ic = &sc->sc_ic; 4962 int error, i, ac, qid; 4963 4964 sc->sf_state = IWM_SF_UNINIT; 4965 4966 if ((error = iwm_start_hw(sc)) != 0) { 4967 printf("iwm_start_hw: failed %d\n", error); 4968 return error; 4969 } 4970 4971 if ((error = iwm_run_init_ucode(sc, 0)) != 0) { 4972 printf("iwm_run_init_ucode: failed %d\n", error); 4973 return error; 4974 } 4975 4976 /* 4977 * should stop and start HW since that INIT 4978 * image just loaded 4979 */ 4980 iwm_stop_device(sc); 4981 sc->sc_ps_disabled = FALSE; 4982 if ((error = iwm_start_hw(sc)) != 0) { 4983 device_printf(sc->sc_dev, "could not initialize hardware\n"); 4984 return error; 4985 } 4986 4987 /* omstart, this time with the regular firmware */ 4988 error = iwm_load_ucode_wait_alive(sc, IWM_UCODE_REGULAR); 4989 if (error) { 4990 device_printf(sc->sc_dev, "could not load firmware\n"); 4991 goto error; 4992 } 4993 4994 error = iwm_sf_update(sc, NULL, FALSE); 4995 if (error) 4996 device_printf(sc->sc_dev, "Failed to initialize Smart Fifo\n"); 4997 4998 if ((error = iwm_send_bt_init_conf(sc)) != 0) { 4999 device_printf(sc->sc_dev, "bt init conf failed\n"); 5000 goto error; 5001 } 5002 5003 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) { 5004 if ((error = iwm_send_soc_conf(sc)) != 0) 5005 goto error; 5006 } 5007 5008 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW)) { 5009 if ((error = iwm_send_temp_report_ths_cmd(sc)) != 0) 5010 goto error; 5011 } 5012 5013 error = iwm_send_tx_ant_cfg(sc, iwm_get_valid_tx_ant(sc)); 5014 if (error != 0) { 5015 device_printf(sc->sc_dev, "antenna config failed\n"); 5016 goto error; 5017 } 5018 5019 /* Send phy db control command and then phy db calibration */ 5020 if ((error = iwm_send_phy_db_data(sc->sc_phy_db)) != 0) 5021 goto error; 5022 5023 if ((error = iwm_send_phy_cfg_cmd(sc)) != 0) { 5024 device_printf(sc->sc_dev, "phy_cfg_cmd failed\n"); 5025 goto error; 5026 } 5027 5028 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_DQA_SUPPORT)) { 5029 if ((error = iwm_send_dqa_cmd(sc)) != 0) 5030 goto error; 5031 } 5032 5033 /* Add auxiliary station for scanning */ 5034 if ((error = iwm_add_aux_sta(sc)) != 0) { 5035 device_printf(sc->sc_dev, "add_aux_sta failed\n"); 5036 goto error; 5037 } 5038 5039 for (i = 0; i < IWM_NUM_PHY_CTX; i++) { 5040 /* 5041 * The channel used here isn't relevant as it's 5042 * going to be overwritten in the other flows. 5043 * For now use the first channel we have. 5044 */ 5045 sc->sc_phyctxt[i].id = i; 5046 sc->sc_phyctxt[i].channel = &ic->ic_channels[1]; 5047 error = iwm_phy_ctxt_cmd(sc, &sc->sc_phyctxt[i], 1, 1, 5048 IWM_FW_CTXT_ACTION_ADD, 0, IEEE80211_HTINFO_2NDCHAN_NONE); 5049 if (error) 5050 goto error; 5051 } 5052 5053 /* Initialize tx backoffs to the minimum. */ 5054 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) 5055 iwm_tt_tx_backoff(sc, 0); 5056 5057 if (iwm_config_ltr(sc) != 0) 5058 device_printf(sc->sc_dev, "PCIe LTR configuration failed\n"); 5059 5060 error = iwm_power_update_device(sc); 5061 if (error) 5062 goto error; 5063 5064 if ((error = iwm_send_update_mcc_cmd(sc, "ZZ")) != 0) 5065 goto error; 5066 5067 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_UMAC_SCAN)) { 5068 if ((error = iwm_config_umac_scan(sc)) != 0) 5069 goto error; 5070 } 5071 5072 /* Enable Tx queues. */ 5073 for (ac = 0; ac < WME_NUM_AC; ac++) { 5074 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_DQA_SUPPORT)) 5075 qid = ac + IWM_DQA_MIN_MGMT_QUEUE; 5076 else 5077 qid = ac; 5078 5079 error = iwm_enable_txq(sc, IWM_STATION_ID, qid, 5080 iwm_ac_to_tx_fifo[ac]); 5081 if (error) 5082 goto error; 5083 } 5084 5085 if ((error = iwm_disable_beacon_filter(sc)) != 0) { 5086 device_printf(sc->sc_dev, "failed to disable beacon filter\n"); 5087 goto error; 5088 } 5089 5090 return 0; 5091 5092 error: 5093 iwm_stop_device(sc); 5094 return error; 5095 } 5096 5097 /* Allow multicast from our BSSID. */ 5098 static int 5099 iwm_allow_mcast(struct ieee80211vap *vap, struct iwm_softc *sc) 5100 { 5101 struct ieee80211_node *ni = vap->iv_bss; 5102 struct iwm_mcast_filter_cmd *cmd; 5103 size_t size; 5104 int error; 5105 5106 size = roundup(sizeof(*cmd), 4); 5107 cmd = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 5108 if (cmd == NULL) 5109 return ENOMEM; 5110 cmd->filter_own = 1; 5111 cmd->port_id = 0; 5112 cmd->count = 0; 5113 cmd->pass_all = 1; 5114 IEEE80211_ADDR_COPY(cmd->bssid, ni->ni_bssid); 5115 5116 error = iwm_send_cmd_pdu(sc, IWM_MCAST_FILTER_CMD, 5117 IWM_CMD_SYNC, size, cmd); 5118 free(cmd, M_DEVBUF); 5119 5120 return (error); 5121 } 5122 5123 /* 5124 * ifnet interfaces 5125 */ 5126 5127 static void 5128 iwm_init(struct iwm_softc *sc) 5129 { 5130 int error; 5131 5132 IWM_LOCK_ASSERT_LOCKED(sc); 5133 5134 if (sc->sc_flags & IWM_FLAG_HW_INITED) { 5135 return; 5136 } 5137 sc->sc_generation++; 5138 sc->sc_flags &= ~IWM_FLAG_STOPPED; 5139 5140 if ((error = iwm_init_hw(sc)) != 0) { 5141 printf("iwm_init_hw failed %d\n", error); 5142 iwm_stop(sc); 5143 return; 5144 } 5145 5146 if (sc->nvm_data->sku_cap_11n_enable) 5147 iwm_setup_ht_rates(sc); 5148 5149 /* 5150 * Ok, firmware loaded and we are jogging 5151 */ 5152 sc->sc_flags |= IWM_FLAG_HW_INITED; 5153 } 5154 5155 static int 5156 iwm_transmit(struct ieee80211com *ic, struct mbuf *m) 5157 { 5158 struct iwm_softc *sc; 5159 int error; 5160 5161 sc = ic->ic_softc; 5162 5163 IWM_LOCK(sc); 5164 if ((sc->sc_flags & IWM_FLAG_HW_INITED) == 0) { 5165 IWM_UNLOCK(sc); 5166 return (ENXIO); 5167 } 5168 error = mbufq_enqueue(&sc->sc_snd, m); 5169 if (error) { 5170 IWM_UNLOCK(sc); 5171 return (error); 5172 } 5173 iwm_start(sc); 5174 IWM_UNLOCK(sc); 5175 return (0); 5176 } 5177 5178 /* 5179 * Dequeue packets from sendq and call send. 5180 */ 5181 static void 5182 iwm_start(struct iwm_softc *sc) 5183 { 5184 struct ieee80211_node *ni; 5185 struct mbuf *m; 5186 int ac = 0; 5187 5188 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TRACE, "->%s\n", __func__); 5189 while (sc->qfullmsk == 0 && 5190 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 5191 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 5192 if (iwm_tx(sc, m, ni, ac) != 0) { 5193 if_inc_counter(ni->ni_vap->iv_ifp, 5194 IFCOUNTER_OERRORS, 1); 5195 ieee80211_free_node(ni); 5196 continue; 5197 } 5198 if (sc->sc_tx_timer == 0) { 5199 callout_reset(&sc->sc_watchdog_to, hz, iwm_watchdog, 5200 sc); 5201 } 5202 sc->sc_tx_timer = 15; 5203 } 5204 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TRACE, "<-%s\n", __func__); 5205 } 5206 5207 static void 5208 iwm_stop(struct iwm_softc *sc) 5209 { 5210 5211 sc->sc_flags &= ~IWM_FLAG_HW_INITED; 5212 sc->sc_flags |= IWM_FLAG_STOPPED; 5213 sc->sc_generation++; 5214 iwm_led_blink_stop(sc); 5215 sc->sc_tx_timer = 0; 5216 iwm_stop_device(sc); 5217 sc->sc_flags &= ~IWM_FLAG_SCAN_RUNNING; 5218 } 5219 5220 static void 5221 iwm_watchdog(void *arg) 5222 { 5223 struct iwm_softc *sc = arg; 5224 struct ieee80211com *ic = &sc->sc_ic; 5225 5226 if (sc->sc_attached == 0) 5227 return; 5228 5229 if (sc->sc_tx_timer > 0) { 5230 if (--sc->sc_tx_timer == 0) { 5231 device_printf(sc->sc_dev, "device timeout\n"); 5232 #ifdef IWM_DEBUG 5233 iwm_nic_error(sc); 5234 #endif 5235 ieee80211_restart_all(ic); 5236 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 5237 return; 5238 } 5239 callout_reset(&sc->sc_watchdog_to, hz, iwm_watchdog, sc); 5240 } 5241 } 5242 5243 static void 5244 iwm_parent(struct ieee80211com *ic) 5245 { 5246 struct iwm_softc *sc = ic->ic_softc; 5247 int startall = 0; 5248 int rfkill = 0; 5249 5250 IWM_LOCK(sc); 5251 if (ic->ic_nrunning > 0) { 5252 if (!(sc->sc_flags & IWM_FLAG_HW_INITED)) { 5253 iwm_init(sc); 5254 rfkill = iwm_check_rfkill(sc); 5255 if (!rfkill) 5256 startall = 1; 5257 } 5258 } else if (sc->sc_flags & IWM_FLAG_HW_INITED) 5259 iwm_stop(sc); 5260 IWM_UNLOCK(sc); 5261 if (startall) 5262 ieee80211_start_all(ic); 5263 else if (rfkill) 5264 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 5265 } 5266 5267 static void 5268 iwm_rftoggle_task(void *arg, int npending __unused) 5269 { 5270 struct iwm_softc *sc = arg; 5271 struct ieee80211com *ic = &sc->sc_ic; 5272 int rfkill; 5273 5274 IWM_LOCK(sc); 5275 rfkill = iwm_check_rfkill(sc); 5276 IWM_UNLOCK(sc); 5277 if (rfkill) { 5278 device_printf(sc->sc_dev, 5279 "%s: rfkill switch, disabling interface\n", __func__); 5280 ieee80211_suspend_all(ic); 5281 ieee80211_notify_radio(ic, 0); 5282 } else { 5283 device_printf(sc->sc_dev, 5284 "%s: rfkill cleared, re-enabling interface\n", __func__); 5285 ieee80211_resume_all(ic); 5286 ieee80211_notify_radio(ic, 1); 5287 } 5288 } 5289 5290 /* 5291 * The interrupt side of things 5292 */ 5293 5294 /* 5295 * error dumping routines are from iwlwifi/mvm/utils.c 5296 */ 5297 5298 /* 5299 * Note: This structure is read from the device with IO accesses, 5300 * and the reading already does the endian conversion. As it is 5301 * read with uint32_t-sized accesses, any members with a different size 5302 * need to be ordered correctly though! 5303 */ 5304 struct iwm_error_event_table { 5305 uint32_t valid; /* (nonzero) valid, (0) log is empty */ 5306 uint32_t error_id; /* type of error */ 5307 uint32_t trm_hw_status0; /* TRM HW status */ 5308 uint32_t trm_hw_status1; /* TRM HW status */ 5309 uint32_t blink2; /* branch link */ 5310 uint32_t ilink1; /* interrupt link */ 5311 uint32_t ilink2; /* interrupt link */ 5312 uint32_t data1; /* error-specific data */ 5313 uint32_t data2; /* error-specific data */ 5314 uint32_t data3; /* error-specific data */ 5315 uint32_t bcon_time; /* beacon timer */ 5316 uint32_t tsf_low; /* network timestamp function timer */ 5317 uint32_t tsf_hi; /* network timestamp function timer */ 5318 uint32_t gp1; /* GP1 timer register */ 5319 uint32_t gp2; /* GP2 timer register */ 5320 uint32_t fw_rev_type; /* firmware revision type */ 5321 uint32_t major; /* uCode version major */ 5322 uint32_t minor; /* uCode version minor */ 5323 uint32_t hw_ver; /* HW Silicon version */ 5324 uint32_t brd_ver; /* HW board version */ 5325 uint32_t log_pc; /* log program counter */ 5326 uint32_t frame_ptr; /* frame pointer */ 5327 uint32_t stack_ptr; /* stack pointer */ 5328 uint32_t hcmd; /* last host command header */ 5329 uint32_t isr0; /* isr status register LMPM_NIC_ISR0: 5330 * rxtx_flag */ 5331 uint32_t isr1; /* isr status register LMPM_NIC_ISR1: 5332 * host_flag */ 5333 uint32_t isr2; /* isr status register LMPM_NIC_ISR2: 5334 * enc_flag */ 5335 uint32_t isr3; /* isr status register LMPM_NIC_ISR3: 5336 * time_flag */ 5337 uint32_t isr4; /* isr status register LMPM_NIC_ISR4: 5338 * wico interrupt */ 5339 uint32_t last_cmd_id; /* last HCMD id handled by the firmware */ 5340 uint32_t wait_event; /* wait event() caller address */ 5341 uint32_t l2p_control; /* L2pControlField */ 5342 uint32_t l2p_duration; /* L2pDurationField */ 5343 uint32_t l2p_mhvalid; /* L2pMhValidBits */ 5344 uint32_t l2p_addr_match; /* L2pAddrMatchStat */ 5345 uint32_t lmpm_pmg_sel; /* indicate which clocks are turned on 5346 * (LMPM_PMG_SEL) */ 5347 uint32_t u_timestamp; /* indicate when the date and time of the 5348 * compilation */ 5349 uint32_t flow_handler; /* FH read/write pointers, RX credit */ 5350 } __packed /* LOG_ERROR_TABLE_API_S_VER_3 */; 5351 5352 /* 5353 * UMAC error struct - relevant starting from family 8000 chip. 5354 * Note: This structure is read from the device with IO accesses, 5355 * and the reading already does the endian conversion. As it is 5356 * read with u32-sized accesses, any members with a different size 5357 * need to be ordered correctly though! 5358 */ 5359 struct iwm_umac_error_event_table { 5360 uint32_t valid; /* (nonzero) valid, (0) log is empty */ 5361 uint32_t error_id; /* type of error */ 5362 uint32_t blink1; /* branch link */ 5363 uint32_t blink2; /* branch link */ 5364 uint32_t ilink1; /* interrupt link */ 5365 uint32_t ilink2; /* interrupt link */ 5366 uint32_t data1; /* error-specific data */ 5367 uint32_t data2; /* error-specific data */ 5368 uint32_t data3; /* error-specific data */ 5369 uint32_t umac_major; 5370 uint32_t umac_minor; 5371 uint32_t frame_pointer; /* core register 27*/ 5372 uint32_t stack_pointer; /* core register 28 */ 5373 uint32_t cmd_header; /* latest host cmd sent to UMAC */ 5374 uint32_t nic_isr_pref; /* ISR status register */ 5375 } __packed; 5376 5377 #define ERROR_START_OFFSET (1 * sizeof(uint32_t)) 5378 #define ERROR_ELEM_SIZE (7 * sizeof(uint32_t)) 5379 5380 #ifdef IWM_DEBUG 5381 struct { 5382 const char *name; 5383 uint8_t num; 5384 } advanced_lookup[] = { 5385 { "NMI_INTERRUPT_WDG", 0x34 }, 5386 { "SYSASSERT", 0x35 }, 5387 { "UCODE_VERSION_MISMATCH", 0x37 }, 5388 { "BAD_COMMAND", 0x38 }, 5389 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, 5390 { "FATAL_ERROR", 0x3D }, 5391 { "NMI_TRM_HW_ERR", 0x46 }, 5392 { "NMI_INTERRUPT_TRM", 0x4C }, 5393 { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, 5394 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, 5395 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, 5396 { "NMI_INTERRUPT_HOST", 0x66 }, 5397 { "NMI_INTERRUPT_ACTION_PT", 0x7C }, 5398 { "NMI_INTERRUPT_UNKNOWN", 0x84 }, 5399 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, 5400 { "ADVANCED_SYSASSERT", 0 }, 5401 }; 5402 5403 static const char * 5404 iwm_desc_lookup(uint32_t num) 5405 { 5406 int i; 5407 5408 for (i = 0; i < nitems(advanced_lookup) - 1; i++) 5409 if (advanced_lookup[i].num == num) 5410 return advanced_lookup[i].name; 5411 5412 /* No entry matches 'num', so it is the last: ADVANCED_SYSASSERT */ 5413 return advanced_lookup[i].name; 5414 } 5415 5416 static void 5417 iwm_nic_umac_error(struct iwm_softc *sc) 5418 { 5419 struct iwm_umac_error_event_table table; 5420 uint32_t base; 5421 5422 base = sc->umac_error_event_table; 5423 5424 if (base < 0x800000) { 5425 device_printf(sc->sc_dev, "Invalid error log pointer 0x%08x\n", 5426 base); 5427 return; 5428 } 5429 5430 if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) { 5431 device_printf(sc->sc_dev, "reading errlog failed\n"); 5432 return; 5433 } 5434 5435 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 5436 device_printf(sc->sc_dev, "Start UMAC Error Log Dump:\n"); 5437 device_printf(sc->sc_dev, "Status: 0x%x, count: %d\n", 5438 sc->sc_flags, table.valid); 5439 } 5440 5441 device_printf(sc->sc_dev, "0x%08X | %s\n", table.error_id, 5442 iwm_desc_lookup(table.error_id)); 5443 device_printf(sc->sc_dev, "0x%08X | umac branchlink1\n", table.blink1); 5444 device_printf(sc->sc_dev, "0x%08X | umac branchlink2\n", table.blink2); 5445 device_printf(sc->sc_dev, "0x%08X | umac interruptlink1\n", 5446 table.ilink1); 5447 device_printf(sc->sc_dev, "0x%08X | umac interruptlink2\n", 5448 table.ilink2); 5449 device_printf(sc->sc_dev, "0x%08X | umac data1\n", table.data1); 5450 device_printf(sc->sc_dev, "0x%08X | umac data2\n", table.data2); 5451 device_printf(sc->sc_dev, "0x%08X | umac data3\n", table.data3); 5452 device_printf(sc->sc_dev, "0x%08X | umac major\n", table.umac_major); 5453 device_printf(sc->sc_dev, "0x%08X | umac minor\n", table.umac_minor); 5454 device_printf(sc->sc_dev, "0x%08X | frame pointer\n", 5455 table.frame_pointer); 5456 device_printf(sc->sc_dev, "0x%08X | stack pointer\n", 5457 table.stack_pointer); 5458 device_printf(sc->sc_dev, "0x%08X | last host cmd\n", table.cmd_header); 5459 device_printf(sc->sc_dev, "0x%08X | isr status reg\n", 5460 table.nic_isr_pref); 5461 } 5462 5463 /* 5464 * Support for dumping the error log seemed like a good idea ... 5465 * but it's mostly hex junk and the only sensible thing is the 5466 * hw/ucode revision (which we know anyway). Since it's here, 5467 * I'll just leave it in, just in case e.g. the Intel guys want to 5468 * help us decipher some "ADVANCED_SYSASSERT" later. 5469 */ 5470 static void 5471 iwm_nic_error(struct iwm_softc *sc) 5472 { 5473 struct iwm_error_event_table table; 5474 uint32_t base; 5475 5476 device_printf(sc->sc_dev, "dumping device error log\n"); 5477 base = sc->error_event_table[0]; 5478 if (base < 0x800000) { 5479 device_printf(sc->sc_dev, 5480 "Invalid error log pointer 0x%08x\n", base); 5481 return; 5482 } 5483 5484 if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) { 5485 device_printf(sc->sc_dev, "reading errlog failed\n"); 5486 return; 5487 } 5488 5489 if (!table.valid) { 5490 device_printf(sc->sc_dev, "errlog not found, skipping\n"); 5491 return; 5492 } 5493 5494 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 5495 device_printf(sc->sc_dev, "Start Error Log Dump:\n"); 5496 device_printf(sc->sc_dev, "Status: 0x%x, count: %d\n", 5497 sc->sc_flags, table.valid); 5498 } 5499 5500 device_printf(sc->sc_dev, "0x%08X | %-28s\n", table.error_id, 5501 iwm_desc_lookup(table.error_id)); 5502 device_printf(sc->sc_dev, "%08X | trm_hw_status0\n", 5503 table.trm_hw_status0); 5504 device_printf(sc->sc_dev, "%08X | trm_hw_status1\n", 5505 table.trm_hw_status1); 5506 device_printf(sc->sc_dev, "%08X | branchlink2\n", table.blink2); 5507 device_printf(sc->sc_dev, "%08X | interruptlink1\n", table.ilink1); 5508 device_printf(sc->sc_dev, "%08X | interruptlink2\n", table.ilink2); 5509 device_printf(sc->sc_dev, "%08X | data1\n", table.data1); 5510 device_printf(sc->sc_dev, "%08X | data2\n", table.data2); 5511 device_printf(sc->sc_dev, "%08X | data3\n", table.data3); 5512 device_printf(sc->sc_dev, "%08X | beacon time\n", table.bcon_time); 5513 device_printf(sc->sc_dev, "%08X | tsf low\n", table.tsf_low); 5514 device_printf(sc->sc_dev, "%08X | tsf hi\n", table.tsf_hi); 5515 device_printf(sc->sc_dev, "%08X | time gp1\n", table.gp1); 5516 device_printf(sc->sc_dev, "%08X | time gp2\n", table.gp2); 5517 device_printf(sc->sc_dev, "%08X | uCode revision type\n", 5518 table.fw_rev_type); 5519 device_printf(sc->sc_dev, "%08X | uCode version major\n", table.major); 5520 device_printf(sc->sc_dev, "%08X | uCode version minor\n", table.minor); 5521 device_printf(sc->sc_dev, "%08X | hw version\n", table.hw_ver); 5522 device_printf(sc->sc_dev, "%08X | board version\n", table.brd_ver); 5523 device_printf(sc->sc_dev, "%08X | hcmd\n", table.hcmd); 5524 device_printf(sc->sc_dev, "%08X | isr0\n", table.isr0); 5525 device_printf(sc->sc_dev, "%08X | isr1\n", table.isr1); 5526 device_printf(sc->sc_dev, "%08X | isr2\n", table.isr2); 5527 device_printf(sc->sc_dev, "%08X | isr3\n", table.isr3); 5528 device_printf(sc->sc_dev, "%08X | isr4\n", table.isr4); 5529 device_printf(sc->sc_dev, "%08X | last cmd Id\n", table.last_cmd_id); 5530 device_printf(sc->sc_dev, "%08X | wait_event\n", table.wait_event); 5531 device_printf(sc->sc_dev, "%08X | l2p_control\n", table.l2p_control); 5532 device_printf(sc->sc_dev, "%08X | l2p_duration\n", table.l2p_duration); 5533 device_printf(sc->sc_dev, "%08X | l2p_mhvalid\n", table.l2p_mhvalid); 5534 device_printf(sc->sc_dev, "%08X | l2p_addr_match\n", table.l2p_addr_match); 5535 device_printf(sc->sc_dev, "%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel); 5536 device_printf(sc->sc_dev, "%08X | timestamp\n", table.u_timestamp); 5537 device_printf(sc->sc_dev, "%08X | flow_handler\n", table.flow_handler); 5538 5539 if (sc->umac_error_event_table) 5540 iwm_nic_umac_error(sc); 5541 } 5542 #endif 5543 5544 static void 5545 iwm_handle_rxb(struct iwm_softc *sc, struct mbuf *m) 5546 { 5547 struct ieee80211com *ic = &sc->sc_ic; 5548 struct iwm_cmd_response *cresp; 5549 struct mbuf *m1; 5550 uint32_t offset = 0; 5551 uint32_t maxoff = IWM_RBUF_SIZE; 5552 uint32_t nextoff; 5553 boolean_t stolen = FALSE; 5554 5555 #define HAVEROOM(a) \ 5556 ((a) + sizeof(uint32_t) + sizeof(struct iwm_cmd_header) < maxoff) 5557 5558 while (HAVEROOM(offset)) { 5559 struct iwm_rx_packet *pkt = mtodoff(m, struct iwm_rx_packet *, 5560 offset); 5561 int qid, idx, code, len; 5562 5563 qid = pkt->hdr.qid; 5564 idx = pkt->hdr.idx; 5565 5566 code = IWM_WIDE_ID(pkt->hdr.flags, pkt->hdr.code); 5567 5568 /* 5569 * randomly get these from the firmware, no idea why. 5570 * they at least seem harmless, so just ignore them for now 5571 */ 5572 if ((pkt->hdr.code == 0 && (qid & ~0x80) == 0 && idx == 0) || 5573 pkt->len_n_flags == htole32(IWM_FH_RSCSR_FRAME_INVALID)) { 5574 break; 5575 } 5576 5577 IWM_DPRINTF(sc, IWM_DEBUG_INTR, 5578 "rx packet qid=%d idx=%d type=%x\n", 5579 qid & ~0x80, pkt->hdr.idx, code); 5580 5581 len = iwm_rx_packet_len(pkt); 5582 len += sizeof(uint32_t); /* account for status word */ 5583 nextoff = offset + roundup2(len, IWM_FH_RSCSR_FRAME_ALIGN); 5584 5585 iwm_notification_wait_notify(sc->sc_notif_wait, code, pkt); 5586 5587 switch (code) { 5588 case IWM_REPLY_RX_PHY_CMD: 5589 iwm_rx_rx_phy_cmd(sc, pkt); 5590 break; 5591 5592 case IWM_REPLY_RX_MPDU_CMD: { 5593 /* 5594 * If this is the last frame in the RX buffer, we 5595 * can directly feed the mbuf to the sharks here. 5596 */ 5597 struct iwm_rx_packet *nextpkt = mtodoff(m, 5598 struct iwm_rx_packet *, nextoff); 5599 if (!HAVEROOM(nextoff) || 5600 (nextpkt->hdr.code == 0 && 5601 (nextpkt->hdr.qid & ~0x80) == 0 && 5602 nextpkt->hdr.idx == 0) || 5603 (nextpkt->len_n_flags == 5604 htole32(IWM_FH_RSCSR_FRAME_INVALID))) { 5605 if (iwm_rx_mpdu(sc, m, offset, stolen)) { 5606 stolen = FALSE; 5607 /* Make sure we abort the loop */ 5608 nextoff = maxoff; 5609 } 5610 break; 5611 } 5612 5613 /* 5614 * Use m_copym instead of m_split, because that 5615 * makes it easier to keep a valid rx buffer in 5616 * the ring, when iwm_rx_mpdu() fails. 5617 * 5618 * We need to start m_copym() at offset 0, to get the 5619 * M_PKTHDR flag preserved. 5620 */ 5621 m1 = m_copym(m, 0, M_COPYALL, M_NOWAIT); 5622 if (m1) { 5623 if (iwm_rx_mpdu(sc, m1, offset, stolen)) 5624 stolen = TRUE; 5625 else 5626 m_freem(m1); 5627 } 5628 break; 5629 } 5630 5631 case IWM_TX_CMD: 5632 iwm_rx_tx_cmd(sc, pkt); 5633 break; 5634 5635 case IWM_MISSED_BEACONS_NOTIFICATION: { 5636 struct iwm_missed_beacons_notif *resp; 5637 int missed; 5638 5639 /* XXX look at mac_id to determine interface ID */ 5640 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5641 5642 resp = (void *)pkt->data; 5643 missed = le32toh(resp->consec_missed_beacons); 5644 5645 IWM_DPRINTF(sc, IWM_DEBUG_BEACON | IWM_DEBUG_STATE, 5646 "%s: MISSED_BEACON: mac_id=%d, " 5647 "consec_since_last_rx=%d, consec=%d, num_expect=%d " 5648 "num_rx=%d\n", 5649 __func__, 5650 le32toh(resp->mac_id), 5651 le32toh(resp->consec_missed_beacons_since_last_rx), 5652 le32toh(resp->consec_missed_beacons), 5653 le32toh(resp->num_expected_beacons), 5654 le32toh(resp->num_recvd_beacons)); 5655 5656 /* Be paranoid */ 5657 if (vap == NULL) 5658 break; 5659 5660 /* XXX no net80211 locking? */ 5661 if (vap->iv_state == IEEE80211_S_RUN && 5662 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 5663 if (missed > vap->iv_bmissthreshold) { 5664 /* XXX bad locking; turn into task */ 5665 IWM_UNLOCK(sc); 5666 ieee80211_beacon_miss(ic); 5667 IWM_LOCK(sc); 5668 } 5669 } 5670 5671 break; 5672 } 5673 5674 case IWM_MFUART_LOAD_NOTIFICATION: 5675 break; 5676 5677 case IWM_ALIVE: 5678 break; 5679 5680 case IWM_CALIB_RES_NOTIF_PHY_DB: 5681 break; 5682 5683 case IWM_STATISTICS_NOTIFICATION: 5684 iwm_handle_rx_statistics(sc, pkt); 5685 break; 5686 5687 case IWM_NVM_ACCESS_CMD: 5688 case IWM_MCC_UPDATE_CMD: 5689 if (sc->sc_wantresp == (((qid & ~0x80) << 16) | idx)) { 5690 memcpy(sc->sc_cmd_resp, 5691 pkt, sizeof(sc->sc_cmd_resp)); 5692 } 5693 break; 5694 5695 case IWM_MCC_CHUB_UPDATE_CMD: { 5696 struct iwm_mcc_chub_notif *notif; 5697 notif = (void *)pkt->data; 5698 5699 sc->sc_fw_mcc[0] = (notif->mcc & 0xff00) >> 8; 5700 sc->sc_fw_mcc[1] = notif->mcc & 0xff; 5701 sc->sc_fw_mcc[2] = '\0'; 5702 IWM_DPRINTF(sc, IWM_DEBUG_LAR, 5703 "fw source %d sent CC '%s'\n", 5704 notif->source_id, sc->sc_fw_mcc); 5705 break; 5706 } 5707 5708 case IWM_DTS_MEASUREMENT_NOTIFICATION: 5709 case IWM_WIDE_ID(IWM_PHY_OPS_GROUP, 5710 IWM_DTS_MEASUREMENT_NOTIF_WIDE): { 5711 struct iwm_dts_measurement_notif_v1 *notif; 5712 5713 if (iwm_rx_packet_payload_len(pkt) < sizeof(*notif)) { 5714 device_printf(sc->sc_dev, 5715 "Invalid DTS_MEASUREMENT_NOTIFICATION\n"); 5716 break; 5717 } 5718 notif = (void *)pkt->data; 5719 IWM_DPRINTF(sc, IWM_DEBUG_TEMP, 5720 "IWM_DTS_MEASUREMENT_NOTIFICATION - %d\n", 5721 notif->temp); 5722 break; 5723 } 5724 5725 case IWM_PHY_CONFIGURATION_CMD: 5726 case IWM_TX_ANT_CONFIGURATION_CMD: 5727 case IWM_ADD_STA: 5728 case IWM_MAC_CONTEXT_CMD: 5729 case IWM_REPLY_SF_CFG_CMD: 5730 case IWM_POWER_TABLE_CMD: 5731 case IWM_LTR_CONFIG: 5732 case IWM_PHY_CONTEXT_CMD: 5733 case IWM_BINDING_CONTEXT_CMD: 5734 case IWM_TIME_EVENT_CMD: 5735 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_CFG_CMD): 5736 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_REQ_UMAC): 5737 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_ABORT_UMAC): 5738 case IWM_SCAN_OFFLOAD_REQUEST_CMD: 5739 case IWM_SCAN_OFFLOAD_ABORT_CMD: 5740 case IWM_REPLY_BEACON_FILTERING_CMD: 5741 case IWM_MAC_PM_POWER_TABLE: 5742 case IWM_TIME_QUOTA_CMD: 5743 case IWM_REMOVE_STA: 5744 case IWM_TXPATH_FLUSH: 5745 case IWM_LQ_CMD: 5746 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, 5747 IWM_FW_PAGING_BLOCK_CMD): 5748 case IWM_BT_CONFIG: 5749 case IWM_REPLY_THERMAL_MNG_BACKOFF: 5750 cresp = (void *)pkt->data; 5751 if (sc->sc_wantresp == (((qid & ~0x80) << 16) | idx)) { 5752 memcpy(sc->sc_cmd_resp, 5753 pkt, sizeof(*pkt)+sizeof(*cresp)); 5754 } 5755 break; 5756 5757 /* ignore */ 5758 case IWM_PHY_DB_CMD: 5759 break; 5760 5761 case IWM_INIT_COMPLETE_NOTIF: 5762 break; 5763 5764 case IWM_SCAN_OFFLOAD_COMPLETE: 5765 iwm_rx_lmac_scan_complete_notif(sc, pkt); 5766 if (sc->sc_flags & IWM_FLAG_SCAN_RUNNING) { 5767 sc->sc_flags &= ~IWM_FLAG_SCAN_RUNNING; 5768 ieee80211_runtask(ic, &sc->sc_es_task); 5769 } 5770 break; 5771 5772 case IWM_SCAN_ITERATION_COMPLETE: { 5773 break; 5774 } 5775 5776 case IWM_SCAN_COMPLETE_UMAC: 5777 iwm_rx_umac_scan_complete_notif(sc, pkt); 5778 if (sc->sc_flags & IWM_FLAG_SCAN_RUNNING) { 5779 sc->sc_flags &= ~IWM_FLAG_SCAN_RUNNING; 5780 ieee80211_runtask(ic, &sc->sc_es_task); 5781 } 5782 break; 5783 5784 case IWM_SCAN_ITERATION_COMPLETE_UMAC: { 5785 #ifdef IWM_DEBUG 5786 struct iwm_umac_scan_iter_complete_notif *notif; 5787 notif = (void *)pkt->data; 5788 5789 IWM_DPRINTF(sc, IWM_DEBUG_SCAN, "UMAC scan iteration " 5790 "complete, status=0x%x, %d channels scanned\n", 5791 notif->status, notif->scanned_channels); 5792 #endif 5793 break; 5794 } 5795 5796 case IWM_REPLY_ERROR: { 5797 struct iwm_error_resp *resp; 5798 resp = (void *)pkt->data; 5799 5800 device_printf(sc->sc_dev, 5801 "firmware error 0x%x, cmd 0x%x\n", 5802 le32toh(resp->error_type), 5803 resp->cmd_id); 5804 break; 5805 } 5806 5807 case IWM_TIME_EVENT_NOTIFICATION: 5808 iwm_rx_time_event_notif(sc, pkt); 5809 break; 5810 5811 /* 5812 * Firmware versions 21 and 22 generate some DEBUG_LOG_MSG 5813 * messages. Just ignore them for now. 5814 */ 5815 case IWM_DEBUG_LOG_MSG: 5816 break; 5817 5818 case IWM_MCAST_FILTER_CMD: 5819 break; 5820 5821 case IWM_SCD_QUEUE_CFG: { 5822 #ifdef IWM_DEBUG 5823 struct iwm_scd_txq_cfg_rsp *rsp; 5824 rsp = (void *)pkt->data; 5825 5826 IWM_DPRINTF(sc, IWM_DEBUG_CMD, 5827 "queue cfg token=0x%x sta_id=%d " 5828 "tid=%d scd_queue=%d\n", 5829 rsp->token, rsp->sta_id, rsp->tid, 5830 rsp->scd_queue); 5831 #endif 5832 break; 5833 } 5834 5835 default: 5836 device_printf(sc->sc_dev, 5837 "code %x, frame %d/%d %x unhandled\n", 5838 code, qid & ~0x80, idx, pkt->len_n_flags); 5839 break; 5840 } 5841 5842 /* 5843 * Why test bit 0x80? The Linux driver: 5844 * 5845 * There is one exception: uCode sets bit 15 when it 5846 * originates the response/notification, i.e. when the 5847 * response/notification is not a direct response to a 5848 * command sent by the driver. For example, uCode issues 5849 * IWM_REPLY_RX when it sends a received frame to the driver; 5850 * it is not a direct response to any driver command. 5851 * 5852 * Ok, so since when is 7 == 15? Well, the Linux driver 5853 * uses a slightly different format for pkt->hdr, and "qid" 5854 * is actually the upper byte of a two-byte field. 5855 */ 5856 if (!(qid & (1 << 7))) 5857 iwm_cmd_done(sc, pkt); 5858 5859 offset = nextoff; 5860 } 5861 if (stolen) 5862 m_freem(m); 5863 #undef HAVEROOM 5864 } 5865 5866 /* 5867 * Process an IWM_CSR_INT_BIT_FH_RX or IWM_CSR_INT_BIT_SW_RX interrupt. 5868 * Basic structure from if_iwn 5869 */ 5870 static void 5871 iwm_notif_intr(struct iwm_softc *sc) 5872 { 5873 int count; 5874 uint32_t wreg; 5875 uint16_t hw; 5876 5877 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 5878 BUS_DMASYNC_POSTREAD); 5879 5880 if (sc->cfg->mqrx_supported) { 5881 count = IWM_RX_MQ_RING_COUNT; 5882 wreg = IWM_RFH_Q0_FRBDCB_WIDX_TRG; 5883 } else { 5884 count = IWM_RX_LEGACY_RING_COUNT; 5885 wreg = IWM_FH_RSCSR_CHNL0_WPTR; 5886 } 5887 5888 hw = le16toh(sc->rxq.stat->closed_rb_num) & 0xfff; 5889 5890 /* 5891 * Process responses 5892 */ 5893 while (sc->rxq.cur != hw) { 5894 struct iwm_rx_ring *ring = &sc->rxq; 5895 struct iwm_rx_data *data = &ring->data[ring->cur]; 5896 5897 bus_dmamap_sync(ring->data_dmat, data->map, 5898 BUS_DMASYNC_POSTREAD); 5899 5900 IWM_DPRINTF(sc, IWM_DEBUG_INTR, 5901 "%s: hw = %d cur = %d\n", __func__, hw, ring->cur); 5902 iwm_handle_rxb(sc, data->m); 5903 5904 ring->cur = (ring->cur + 1) % count; 5905 } 5906 5907 /* 5908 * Tell the firmware that it can reuse the ring entries that 5909 * we have just processed. 5910 * Seems like the hardware gets upset unless we align 5911 * the write by 8?? 5912 */ 5913 hw = (hw == 0) ? count - 1 : hw - 1; 5914 IWM_WRITE(sc, wreg, rounddown2(hw, 8)); 5915 } 5916 5917 static void 5918 iwm_intr(void *arg) 5919 { 5920 struct iwm_softc *sc = arg; 5921 int handled = 0; 5922 int r1, r2; 5923 int isperiodic = 0; 5924 5925 IWM_LOCK(sc); 5926 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0); 5927 5928 if (sc->sc_flags & IWM_FLAG_USE_ICT) { 5929 uint32_t *ict = sc->ict_dma.vaddr; 5930 int tmp; 5931 5932 tmp = htole32(ict[sc->ict_cur]); 5933 if (!tmp) 5934 goto out_ena; 5935 5936 /* 5937 * ok, there was something. keep plowing until we have all. 5938 */ 5939 r1 = r2 = 0; 5940 while (tmp) { 5941 r1 |= tmp; 5942 ict[sc->ict_cur] = 0; 5943 sc->ict_cur = (sc->ict_cur+1) % IWM_ICT_COUNT; 5944 tmp = htole32(ict[sc->ict_cur]); 5945 } 5946 5947 /* this is where the fun begins. don't ask */ 5948 if (r1 == 0xffffffff) 5949 r1 = 0; 5950 5951 /* i am not expected to understand this */ 5952 if (r1 & 0xc0000) 5953 r1 |= 0x8000; 5954 r1 = (0xff & r1) | ((0xff00 & r1) << 16); 5955 } else { 5956 r1 = IWM_READ(sc, IWM_CSR_INT); 5957 /* "hardware gone" (where, fishing?) */ 5958 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 5959 goto out; 5960 r2 = IWM_READ(sc, IWM_CSR_FH_INT_STATUS); 5961 } 5962 if (r1 == 0 && r2 == 0) { 5963 goto out_ena; 5964 } 5965 5966 IWM_WRITE(sc, IWM_CSR_INT, r1 | ~sc->sc_intmask); 5967 5968 /* Safely ignore these bits for debug checks below */ 5969 r1 &= ~(IWM_CSR_INT_BIT_ALIVE | IWM_CSR_INT_BIT_SCD); 5970 5971 if (r1 & IWM_CSR_INT_BIT_SW_ERR) { 5972 int i; 5973 struct ieee80211com *ic = &sc->sc_ic; 5974 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5975 5976 #ifdef IWM_DEBUG 5977 iwm_nic_error(sc); 5978 #endif 5979 /* Dump driver status (TX and RX rings) while we're here. */ 5980 device_printf(sc->sc_dev, "driver status:\n"); 5981 for (i = 0; i < IWM_MAX_QUEUES; i++) { 5982 struct iwm_tx_ring *ring = &sc->txq[i]; 5983 device_printf(sc->sc_dev, 5984 " tx ring %2d: qid=%-2d cur=%-3d " 5985 "queued=%-3d\n", 5986 i, ring->qid, ring->cur, ring->queued); 5987 } 5988 device_printf(sc->sc_dev, 5989 " rx ring: cur=%d\n", sc->rxq.cur); 5990 device_printf(sc->sc_dev, 5991 " 802.11 state %d\n", (vap == NULL) ? -1 : vap->iv_state); 5992 5993 /* Reset our firmware state tracking. */ 5994 sc->sc_firmware_state = 0; 5995 /* Don't stop the device; just do a VAP restart */ 5996 IWM_UNLOCK(sc); 5997 5998 if (vap == NULL) { 5999 printf("%s: null vap\n", __func__); 6000 return; 6001 } 6002 6003 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 6004 "restarting\n", __func__, vap->iv_state); 6005 6006 ieee80211_restart_all(ic); 6007 return; 6008 } 6009 6010 if (r1 & IWM_CSR_INT_BIT_HW_ERR) { 6011 handled |= IWM_CSR_INT_BIT_HW_ERR; 6012 device_printf(sc->sc_dev, "hardware error, stopping device\n"); 6013 iwm_stop(sc); 6014 goto out; 6015 } 6016 6017 /* firmware chunk loaded */ 6018 if (r1 & IWM_CSR_INT_BIT_FH_TX) { 6019 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_TX_MASK); 6020 handled |= IWM_CSR_INT_BIT_FH_TX; 6021 sc->sc_fw_chunk_done = 1; 6022 wakeup(&sc->sc_fw); 6023 } 6024 6025 if (r1 & IWM_CSR_INT_BIT_RF_KILL) { 6026 handled |= IWM_CSR_INT_BIT_RF_KILL; 6027 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 6028 } 6029 6030 /* 6031 * The Linux driver uses periodic interrupts to avoid races. 6032 * We cargo-cult like it's going out of fashion. 6033 */ 6034 if (r1 & IWM_CSR_INT_BIT_RX_PERIODIC) { 6035 handled |= IWM_CSR_INT_BIT_RX_PERIODIC; 6036 IWM_WRITE(sc, IWM_CSR_INT, IWM_CSR_INT_BIT_RX_PERIODIC); 6037 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) == 0) 6038 IWM_WRITE_1(sc, 6039 IWM_CSR_INT_PERIODIC_REG, IWM_CSR_INT_PERIODIC_DIS); 6040 isperiodic = 1; 6041 } 6042 6043 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) || isperiodic) { 6044 handled |= (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX); 6045 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_RX_MASK); 6046 6047 iwm_notif_intr(sc); 6048 6049 /* enable periodic interrupt, see above */ 6050 if (r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX) && !isperiodic) 6051 IWM_WRITE_1(sc, IWM_CSR_INT_PERIODIC_REG, 6052 IWM_CSR_INT_PERIODIC_ENA); 6053 } 6054 6055 if (__predict_false(r1 & ~handled)) 6056 IWM_DPRINTF(sc, IWM_DEBUG_INTR, 6057 "%s: unhandled interrupts: %x\n", __func__, r1); 6058 out_ena: 6059 iwm_restore_interrupts(sc); 6060 out: 6061 IWM_UNLOCK(sc); 6062 return; 6063 } 6064 6065 static void 6066 iwm_intr_msix(void *arg) 6067 { 6068 struct iwm_softc *sc = arg; 6069 uint32_t inta_fh, inta_hw; 6070 int vector = 0; 6071 6072 IWM_LOCK(sc); 6073 6074 inta_fh = IWM_READ(sc, IWM_CSR_MSIX_FH_INT_CAUSES_AD); 6075 inta_hw = IWM_READ(sc, IWM_CSR_MSIX_HW_INT_CAUSES_AD); 6076 /* acknowledge all interrupts */ 6077 IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 6078 IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 6079 inta_fh &= sc->sc_fh_mask; 6080 inta_hw &= sc->sc_hw_mask; 6081 6082 if (inta_fh & IWM_MSIX_FH_INT_CAUSES_Q0 || 6083 inta_fh & IWM_MSIX_FH_INT_CAUSES_Q1) 6084 iwm_notif_intr(sc); 6085 6086 /* firmware chunk loaded */ 6087 if (inta_fh & IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 6088 sc->sc_fw_chunk_done = 1; 6089 wakeup(&sc->sc_fw); 6090 } 6091 6092 if ((inta_fh & IWM_MSIX_FH_INT_CAUSES_FH_ERR) || 6093 (inta_hw & IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR) || 6094 (inta_hw & IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2)) { 6095 struct ieee80211com *ic = &sc->sc_ic; 6096 struct ieee80211vap *vap; 6097 int i; 6098 6099 #ifdef IWM_DEBUG 6100 iwm_nic_error(sc); 6101 #endif 6102 /* Dump driver status (TX and RX rings) while we're here. */ 6103 device_printf(sc->sc_dev, "driver status:\n"); 6104 for (i = 0; i < IWM_MAX_QUEUES; i++) { 6105 struct iwm_tx_ring *ring = &sc->txq[i]; 6106 device_printf(sc->sc_dev, 6107 " tx ring %2d: qid=%-2d cur=%-3d " 6108 "queued=%-3d\n", 6109 i, ring->qid, ring->cur, ring->queued); 6110 } 6111 device_printf(sc->sc_dev, " rx ring: cur=%d\n", sc->rxq.cur); 6112 6113 /* Reset our firmware state tracking. */ 6114 sc->sc_firmware_state = 0; 6115 IWM_UNLOCK(sc); 6116 6117 vap = TAILQ_FIRST(&ic->ic_vaps); 6118 if (vap == NULL) { 6119 printf("%s: null vap\n", __func__); 6120 return; 6121 } 6122 6123 device_printf(sc->sc_dev, 6124 "%s: controller panicked, iv_state = %d; restarting\n", 6125 __func__, vap->iv_state); 6126 6127 ieee80211_restart_all(ic); 6128 return; 6129 } 6130 6131 if (inta_hw & IWM_MSIX_HW_INT_CAUSES_REG_RF_KILL) 6132 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 6133 6134 if (inta_hw & IWM_MSIX_HW_INT_CAUSES_REG_HW_ERR) { 6135 device_printf(sc->sc_dev, "hardware error, stopping device\n"); 6136 iwm_stop(sc); 6137 goto out; 6138 } 6139 6140 /* 6141 * Before sending the interrupt the HW disables it to prevent 6142 * a nested interrupt. This is done by writing 1 to the 6143 * corresponding bit in the mask register. After handling the 6144 * interrupt, it should be re-enabled by clearing this bit. 6145 * This register is defined as a write 1 clear (W1C) register, 6146 * meaning that it's being cleared by writing 1 to the bit. 6147 */ 6148 IWM_WRITE(sc, IWM_CSR_MSIX_AUTOMASK_ST_AD, 1 << vector); 6149 6150 out: 6151 IWM_UNLOCK(sc); 6152 } 6153 6154 /* 6155 * Autoconf glue-sniffing 6156 */ 6157 #define PCI_VENDOR_INTEL 0x8086 6158 #define PCI_PRODUCT_INTEL_WL_3160_1 0x08b3 6159 #define PCI_PRODUCT_INTEL_WL_3160_2 0x08b4 6160 #define PCI_PRODUCT_INTEL_WL_3165_1 0x3165 6161 #define PCI_PRODUCT_INTEL_WL_3165_2 0x3166 6162 #define PCI_PRODUCT_INTEL_WL_3168_1 0x24fb 6163 #define PCI_PRODUCT_INTEL_WL_7260_1 0x08b1 6164 #define PCI_PRODUCT_INTEL_WL_7260_2 0x08b2 6165 #define PCI_PRODUCT_INTEL_WL_7265_1 0x095a 6166 #define PCI_PRODUCT_INTEL_WL_7265_2 0x095b 6167 #define PCI_PRODUCT_INTEL_WL_8260_1 0x24f3 6168 #define PCI_PRODUCT_INTEL_WL_8260_2 0x24f4 6169 #define PCI_PRODUCT_INTEL_WL_8265_1 0x24fd 6170 #define PCI_PRODUCT_INTEL_WL_9560_1 0x9df0 6171 #define PCI_PRODUCT_INTEL_WL_9560_2 0xa370 6172 #define PCI_PRODUCT_INTEL_WL_9560_3 0x31dc 6173 #define PCI_PRODUCT_INTEL_WL_9260_1 0x2526 6174 6175 static const struct iwm_devices { 6176 uint16_t device; 6177 const struct iwm_cfg *cfg; 6178 } iwm_devices[] = { 6179 { PCI_PRODUCT_INTEL_WL_3160_1, &iwm3160_cfg }, 6180 { PCI_PRODUCT_INTEL_WL_3160_2, &iwm3160_cfg }, 6181 { PCI_PRODUCT_INTEL_WL_3165_1, &iwm3165_cfg }, 6182 { PCI_PRODUCT_INTEL_WL_3165_2, &iwm3165_cfg }, 6183 { PCI_PRODUCT_INTEL_WL_3168_1, &iwm3168_cfg }, 6184 { PCI_PRODUCT_INTEL_WL_7260_1, &iwm7260_cfg }, 6185 { PCI_PRODUCT_INTEL_WL_7260_2, &iwm7260_cfg }, 6186 { PCI_PRODUCT_INTEL_WL_7265_1, &iwm7265_cfg }, 6187 { PCI_PRODUCT_INTEL_WL_7265_2, &iwm7265_cfg }, 6188 { PCI_PRODUCT_INTEL_WL_8260_1, &iwm8260_cfg }, 6189 { PCI_PRODUCT_INTEL_WL_8260_2, &iwm8260_cfg }, 6190 { PCI_PRODUCT_INTEL_WL_8265_1, &iwm8265_cfg }, 6191 { PCI_PRODUCT_INTEL_WL_9560_1, &iwm9560_cfg }, 6192 { PCI_PRODUCT_INTEL_WL_9560_2, &iwm9560_cfg }, 6193 { PCI_PRODUCT_INTEL_WL_9560_3, &iwm9560_cfg }, 6194 { PCI_PRODUCT_INTEL_WL_9260_1, &iwm9260_cfg }, 6195 }; 6196 6197 static int 6198 iwm_probe(device_t dev) 6199 { 6200 int i; 6201 6202 for (i = 0; i < nitems(iwm_devices); i++) { 6203 if (pci_get_vendor(dev) == PCI_VENDOR_INTEL && 6204 pci_get_device(dev) == iwm_devices[i].device) { 6205 device_set_desc(dev, iwm_devices[i].cfg->name); 6206 return (BUS_PROBE_DEFAULT); 6207 } 6208 } 6209 6210 return (ENXIO); 6211 } 6212 6213 static int 6214 iwm_dev_check(device_t dev) 6215 { 6216 struct iwm_softc *sc; 6217 uint16_t devid; 6218 int i; 6219 6220 sc = device_get_softc(dev); 6221 6222 devid = pci_get_device(dev); 6223 for (i = 0; i < nitems(iwm_devices); i++) { 6224 if (iwm_devices[i].device == devid) { 6225 sc->cfg = iwm_devices[i].cfg; 6226 return (0); 6227 } 6228 } 6229 device_printf(dev, "unknown adapter type\n"); 6230 return ENXIO; 6231 } 6232 6233 /* PCI registers */ 6234 #define PCI_CFG_RETRY_TIMEOUT 0x041 6235 6236 static int 6237 iwm_pci_attach(device_t dev) 6238 { 6239 struct iwm_softc *sc; 6240 int count, error, rid; 6241 uint16_t reg; 6242 6243 sc = device_get_softc(dev); 6244 6245 /* We disable the RETRY_TIMEOUT register (0x41) to keep 6246 * PCI Tx retries from interfering with C3 CPU state */ 6247 pci_write_config(dev, PCI_CFG_RETRY_TIMEOUT, 0x00, 1); 6248 6249 /* Enable bus-mastering and hardware bug workaround. */ 6250 pci_enable_busmaster(dev); 6251 reg = pci_read_config(dev, PCIR_STATUS, sizeof(reg)); 6252 /* if !MSI */ 6253 if (reg & PCIM_STATUS_INTxSTATE) { 6254 reg &= ~PCIM_STATUS_INTxSTATE; 6255 } 6256 pci_write_config(dev, PCIR_STATUS, reg, sizeof(reg)); 6257 6258 rid = PCIR_BAR(0); 6259 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 6260 RF_ACTIVE); 6261 if (sc->sc_mem == NULL) { 6262 device_printf(sc->sc_dev, "can't map mem space\n"); 6263 return (ENXIO); 6264 } 6265 sc->sc_st = rman_get_bustag(sc->sc_mem); 6266 sc->sc_sh = rman_get_bushandle(sc->sc_mem); 6267 6268 /* Install interrupt handler. */ 6269 count = 1; 6270 rid = 0; 6271 if (pci_alloc_msix(dev, &count) == 0) { 6272 rid = 1; 6273 sc->sc_msix = 1; 6274 } else if (pci_alloc_msi(dev, &count) == 0) { 6275 rid = 1; 6276 } 6277 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 6278 (rid != 0 ? 0 : RF_SHAREABLE)); 6279 if (sc->sc_irq == NULL) { 6280 device_printf(dev, "can't map interrupt\n"); 6281 return (ENXIO); 6282 } 6283 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 6284 NULL, sc->sc_msix ? iwm_intr_msix : iwm_intr, sc, &sc->sc_ih); 6285 if (error != 0) { 6286 device_printf(dev, "can't establish interrupt"); 6287 return (error); 6288 } 6289 sc->sc_dmat = bus_get_dma_tag(sc->sc_dev); 6290 6291 return (0); 6292 } 6293 6294 static void 6295 iwm_pci_detach(device_t dev) 6296 { 6297 struct iwm_softc *sc = device_get_softc(dev); 6298 6299 if (sc->sc_irq != NULL) { 6300 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 6301 bus_release_resource(dev, SYS_RES_IRQ, 6302 rman_get_rid(sc->sc_irq), sc->sc_irq); 6303 pci_release_msi(dev); 6304 } 6305 if (sc->sc_mem != NULL) 6306 bus_release_resource(dev, SYS_RES_MEMORY, 6307 rman_get_rid(sc->sc_mem), sc->sc_mem); 6308 } 6309 6310 static int 6311 iwm_attach(device_t dev) 6312 { 6313 struct iwm_softc *sc = device_get_softc(dev); 6314 struct ieee80211com *ic = &sc->sc_ic; 6315 int error; 6316 int txq_i, i; 6317 6318 sc->sc_dev = dev; 6319 sc->sc_attached = 1; 6320 IWM_LOCK_INIT(sc); 6321 mbufq_init(&sc->sc_snd, ifqmaxlen); 6322 callout_init_mtx(&sc->sc_watchdog_to, &sc->sc_mtx, 0); 6323 callout_init_mtx(&sc->sc_led_blink_to, &sc->sc_mtx, 0); 6324 TASK_INIT(&sc->sc_es_task, 0, iwm_endscan_cb, sc); 6325 TASK_INIT(&sc->sc_rftoggle_task, 0, iwm_rftoggle_task, sc); 6326 6327 sc->sc_tq = taskqueue_create("iwm_taskq", M_WAITOK, 6328 taskqueue_thread_enqueue, &sc->sc_tq); 6329 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwm_taskq"); 6330 if (error != 0) { 6331 device_printf(dev, "can't start taskq thread, error %d\n", 6332 error); 6333 goto fail; 6334 } 6335 6336 error = iwm_dev_check(dev); 6337 if (error != 0) 6338 goto fail; 6339 6340 sc->sc_notif_wait = iwm_notification_wait_init(sc); 6341 if (sc->sc_notif_wait == NULL) { 6342 device_printf(dev, "failed to init notification wait struct\n"); 6343 goto fail; 6344 } 6345 6346 sc->sf_state = IWM_SF_UNINIT; 6347 6348 /* Init phy db */ 6349 sc->sc_phy_db = iwm_phy_db_init(sc); 6350 if (!sc->sc_phy_db) { 6351 device_printf(dev, "Cannot init phy_db\n"); 6352 goto fail; 6353 } 6354 6355 /* Set EBS as successful as long as not stated otherwise by the FW. */ 6356 sc->last_ebs_successful = TRUE; 6357 6358 /* PCI attach */ 6359 error = iwm_pci_attach(dev); 6360 if (error != 0) 6361 goto fail; 6362 6363 sc->sc_wantresp = -1; 6364 6365 sc->sc_hw_rev = IWM_READ(sc, IWM_CSR_HW_REV); 6366 /* 6367 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 6368 * changed, and now the revision step also includes bit 0-1 (no more 6369 * "dash" value). To keep hw_rev backwards compatible - we'll store it 6370 * in the old format. 6371 */ 6372 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) { 6373 int ret; 6374 uint32_t hw_step; 6375 6376 sc->sc_hw_rev = (sc->sc_hw_rev & 0xfff0) | 6377 (IWM_CSR_HW_REV_STEP(sc->sc_hw_rev << 2) << 2); 6378 6379 if (iwm_prepare_card_hw(sc) != 0) { 6380 device_printf(dev, "could not initialize hardware\n"); 6381 goto fail; 6382 } 6383 6384 /* 6385 * In order to recognize C step the driver should read the 6386 * chip version id located at the AUX bus MISC address. 6387 */ 6388 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 6389 IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 6390 DELAY(2); 6391 6392 ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 6393 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 6394 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 6395 25000); 6396 if (!ret) { 6397 device_printf(sc->sc_dev, 6398 "Failed to wake up the nic\n"); 6399 goto fail; 6400 } 6401 6402 if (iwm_nic_lock(sc)) { 6403 hw_step = iwm_read_prph(sc, IWM_WFPM_CTRL_REG); 6404 hw_step |= IWM_ENABLE_WFPM; 6405 iwm_write_prph(sc, IWM_WFPM_CTRL_REG, hw_step); 6406 hw_step = iwm_read_prph(sc, IWM_AUX_MISC_REG); 6407 hw_step = (hw_step >> IWM_HW_STEP_LOCATION_BITS) & 0xF; 6408 if (hw_step == 0x3) 6409 sc->sc_hw_rev = (sc->sc_hw_rev & 0xFFFFFFF3) | 6410 (IWM_SILICON_C_STEP << 2); 6411 iwm_nic_unlock(sc); 6412 } else { 6413 device_printf(sc->sc_dev, "Failed to lock the nic\n"); 6414 goto fail; 6415 } 6416 } 6417 6418 /* special-case 7265D, it has the same PCI IDs. */ 6419 if (sc->cfg == &iwm7265_cfg && 6420 (sc->sc_hw_rev & IWM_CSR_HW_REV_TYPE_MSK) == IWM_CSR_HW_REV_TYPE_7265D) { 6421 sc->cfg = &iwm7265d_cfg; 6422 } 6423 6424 /* Allocate DMA memory for firmware transfers. */ 6425 if ((error = iwm_alloc_fwmem(sc)) != 0) { 6426 device_printf(dev, "could not allocate memory for firmware\n"); 6427 goto fail; 6428 } 6429 6430 /* Allocate "Keep Warm" page. */ 6431 if ((error = iwm_alloc_kw(sc)) != 0) { 6432 device_printf(dev, "could not allocate keep warm page\n"); 6433 goto fail; 6434 } 6435 6436 /* We use ICT interrupts */ 6437 if ((error = iwm_alloc_ict(sc)) != 0) { 6438 device_printf(dev, "could not allocate ICT table\n"); 6439 goto fail; 6440 } 6441 6442 /* Allocate TX scheduler "rings". */ 6443 if ((error = iwm_alloc_sched(sc)) != 0) { 6444 device_printf(dev, "could not allocate TX scheduler rings\n"); 6445 goto fail; 6446 } 6447 6448 /* Allocate TX rings */ 6449 for (txq_i = 0; txq_i < nitems(sc->txq); txq_i++) { 6450 if ((error = iwm_alloc_tx_ring(sc, 6451 &sc->txq[txq_i], txq_i)) != 0) { 6452 device_printf(dev, 6453 "could not allocate TX ring %d\n", 6454 txq_i); 6455 goto fail; 6456 } 6457 } 6458 6459 /* Allocate RX ring. */ 6460 if ((error = iwm_alloc_rx_ring(sc, &sc->rxq)) != 0) { 6461 device_printf(dev, "could not allocate RX ring\n"); 6462 goto fail; 6463 } 6464 6465 /* Clear pending interrupts. */ 6466 IWM_WRITE(sc, IWM_CSR_INT, 0xffffffff); 6467 6468 ic->ic_softc = sc; 6469 ic->ic_name = device_get_nameunit(sc->sc_dev); 6470 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 6471 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 6472 6473 /* Set device capabilities. */ 6474 ic->ic_caps = 6475 IEEE80211_C_STA | 6476 IEEE80211_C_WPA | /* WPA/RSN */ 6477 IEEE80211_C_WME | 6478 IEEE80211_C_PMGT | 6479 IEEE80211_C_SHSLOT | /* short slot time supported */ 6480 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 6481 // IEEE80211_C_BGSCAN /* capable of bg scanning */ 6482 ; 6483 /* Advertise full-offload scanning */ 6484 ic->ic_flags_ext |= IEEE80211_FEXT_SCAN_OFFLOAD; 6485 ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD; 6486 for (i = 0; i < nitems(sc->sc_phyctxt); i++) { 6487 sc->sc_phyctxt[i].id = i; 6488 sc->sc_phyctxt[i].sco = IEEE80211_HTINFO_2NDCHAN_NONE; 6489 sc->sc_phyctxt[i].color = 0; 6490 sc->sc_phyctxt[i].ref = 0; 6491 sc->sc_phyctxt[i].channel = NULL; 6492 } 6493 6494 /* Default noise floor */ 6495 sc->sc_noise = -96; 6496 6497 /* Max RSSI */ 6498 sc->sc_max_rssi = IWM_MAX_DBM - IWM_MIN_DBM; 6499 6500 #ifdef IWM_DEBUG 6501 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 6502 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "debug", 6503 CTLFLAG_RW, &sc->sc_debug, 0, "control debugging"); 6504 #endif 6505 6506 error = iwm_read_firmware(sc); 6507 if (error) { 6508 goto fail; 6509 } else if (sc->sc_fw.fw_fp == NULL) { 6510 /* 6511 * XXX Add a solution for properly deferring firmware load 6512 * during bootup. 6513 */ 6514 goto fail; 6515 } else { 6516 sc->sc_preinit_hook.ich_func = iwm_preinit; 6517 sc->sc_preinit_hook.ich_arg = sc; 6518 if (config_intrhook_establish(&sc->sc_preinit_hook) != 0) { 6519 device_printf(dev, 6520 "config_intrhook_establish failed\n"); 6521 goto fail; 6522 } 6523 } 6524 6525 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6526 "<-%s\n", __func__); 6527 6528 device_printf(dev, "%s: TX ant=0x%x, RX ant=0x%x\n", 6529 __func__, 6530 iwm_get_valid_tx_ant(sc), 6531 iwm_get_valid_rx_ant(sc)); 6532 6533 return 0; 6534 6535 /* Free allocated memory if something failed during attachment. */ 6536 fail: 6537 iwm_detach_local(sc, 0); 6538 6539 return ENXIO; 6540 } 6541 6542 static int 6543 iwm_is_valid_ether_addr(uint8_t *addr) 6544 { 6545 char zero_addr[IEEE80211_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 6546 6547 if ((addr[0] & 1) || IEEE80211_ADDR_EQ(zero_addr, addr)) 6548 return (FALSE); 6549 6550 return (TRUE); 6551 } 6552 6553 static int 6554 iwm_wme_update(struct ieee80211com *ic) 6555 { 6556 #define IWM_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 6557 struct iwm_softc *sc = ic->ic_softc; 6558 struct chanAccParams chp; 6559 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6560 struct iwm_vap *ivp = IWM_VAP(vap); 6561 struct iwm_node *in; 6562 struct wmeParams tmp[WME_NUM_AC]; 6563 int aci, error; 6564 6565 if (vap == NULL) 6566 return (0); 6567 6568 ieee80211_wme_ic_getparams(ic, &chp); 6569 6570 IEEE80211_LOCK(ic); 6571 for (aci = 0; aci < WME_NUM_AC; aci++) 6572 tmp[aci] = chp.cap_wmeParams[aci]; 6573 IEEE80211_UNLOCK(ic); 6574 6575 IWM_LOCK(sc); 6576 for (aci = 0; aci < WME_NUM_AC; aci++) { 6577 const struct wmeParams *ac = &tmp[aci]; 6578 ivp->queue_params[aci].aifsn = ac->wmep_aifsn; 6579 ivp->queue_params[aci].cw_min = IWM_EXP2(ac->wmep_logcwmin); 6580 ivp->queue_params[aci].cw_max = IWM_EXP2(ac->wmep_logcwmax); 6581 ivp->queue_params[aci].edca_txop = 6582 IEEE80211_TXOP_TO_US(ac->wmep_txopLimit); 6583 } 6584 ivp->have_wme = TRUE; 6585 if (ivp->is_uploaded && vap->iv_bss != NULL) { 6586 in = IWM_NODE(vap->iv_bss); 6587 if (in->in_assoc) { 6588 if ((error = iwm_mac_ctxt_changed(sc, vap)) != 0) { 6589 device_printf(sc->sc_dev, 6590 "%s: failed to update MAC\n", __func__); 6591 } 6592 } 6593 } 6594 IWM_UNLOCK(sc); 6595 6596 return (0); 6597 #undef IWM_EXP2 6598 } 6599 6600 static void 6601 iwm_preinit(void *arg) 6602 { 6603 struct iwm_softc *sc = arg; 6604 device_t dev = sc->sc_dev; 6605 struct ieee80211com *ic = &sc->sc_ic; 6606 int error; 6607 6608 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6609 "->%s\n", __func__); 6610 6611 IWM_LOCK(sc); 6612 if ((error = iwm_start_hw(sc)) != 0) { 6613 device_printf(dev, "could not initialize hardware\n"); 6614 IWM_UNLOCK(sc); 6615 goto fail; 6616 } 6617 6618 error = iwm_run_init_ucode(sc, 1); 6619 iwm_stop_device(sc); 6620 if (error) { 6621 IWM_UNLOCK(sc); 6622 goto fail; 6623 } 6624 device_printf(dev, 6625 "hw rev 0x%x, fw ver %s, address %s\n", 6626 sc->sc_hw_rev & IWM_CSR_HW_REV_TYPE_MSK, 6627 sc->sc_fwver, ether_sprintf(sc->nvm_data->hw_addr)); 6628 6629 if (sc->nvm_data->sku_cap_11n_enable) 6630 iwm_setup_ht_rates(sc); 6631 6632 /* not all hardware can do 5GHz band */ 6633 if (!sc->nvm_data->sku_cap_band_52GHz_enable) 6634 memset(&ic->ic_sup_rates[IEEE80211_MODE_11A], 0, 6635 sizeof(ic->ic_sup_rates[IEEE80211_MODE_11A])); 6636 IWM_UNLOCK(sc); 6637 6638 iwm_init_channel_map(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 6639 ic->ic_channels); 6640 6641 /* 6642 * At this point we've committed - if we fail to do setup, 6643 * we now also have to tear down the net80211 state. 6644 */ 6645 ieee80211_ifattach(ic); 6646 ic->ic_vap_create = iwm_vap_create; 6647 ic->ic_vap_delete = iwm_vap_delete; 6648 ic->ic_raw_xmit = iwm_raw_xmit; 6649 ic->ic_node_alloc = iwm_node_alloc; 6650 ic->ic_scan_start = iwm_scan_start; 6651 ic->ic_scan_end = iwm_scan_end; 6652 ic->ic_update_mcast = iwm_update_mcast; 6653 ic->ic_getradiocaps = iwm_init_channel_map; 6654 ic->ic_set_channel = iwm_set_channel; 6655 ic->ic_scan_curchan = iwm_scan_curchan; 6656 ic->ic_scan_mindwell = iwm_scan_mindwell; 6657 ic->ic_wme.wme_update = iwm_wme_update; 6658 ic->ic_parent = iwm_parent; 6659 ic->ic_transmit = iwm_transmit; 6660 iwm_radiotap_attach(sc); 6661 if (bootverbose) 6662 ieee80211_announce(ic); 6663 6664 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6665 "<-%s\n", __func__); 6666 config_intrhook_disestablish(&sc->sc_preinit_hook); 6667 6668 return; 6669 fail: 6670 config_intrhook_disestablish(&sc->sc_preinit_hook); 6671 iwm_detach_local(sc, 0); 6672 } 6673 6674 /* 6675 * Attach the interface to 802.11 radiotap. 6676 */ 6677 static void 6678 iwm_radiotap_attach(struct iwm_softc *sc) 6679 { 6680 struct ieee80211com *ic = &sc->sc_ic; 6681 6682 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6683 "->%s begin\n", __func__); 6684 ieee80211_radiotap_attach(ic, 6685 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 6686 IWM_TX_RADIOTAP_PRESENT, 6687 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 6688 IWM_RX_RADIOTAP_PRESENT); 6689 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6690 "->%s end\n", __func__); 6691 } 6692 6693 static struct ieee80211vap * 6694 iwm_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 6695 enum ieee80211_opmode opmode, int flags, 6696 const uint8_t bssid[IEEE80211_ADDR_LEN], 6697 const uint8_t mac[IEEE80211_ADDR_LEN]) 6698 { 6699 struct iwm_vap *ivp; 6700 struct ieee80211vap *vap; 6701 6702 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 6703 return NULL; 6704 ivp = malloc(sizeof(struct iwm_vap), M_80211_VAP, M_WAITOK | M_ZERO); 6705 vap = &ivp->iv_vap; 6706 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 6707 vap->iv_bmissthreshold = 10; /* override default */ 6708 /* Override with driver methods. */ 6709 ivp->iv_newstate = vap->iv_newstate; 6710 vap->iv_newstate = iwm_newstate; 6711 6712 ivp->id = IWM_DEFAULT_MACID; 6713 ivp->color = IWM_DEFAULT_COLOR; 6714 6715 ivp->have_wme = FALSE; 6716 ivp->ps_disabled = FALSE; 6717 6718 ieee80211_ratectl_init(vap); 6719 /* Complete setup. */ 6720 ieee80211_vap_attach(vap, ieee80211_media_change, 6721 ieee80211_media_status, mac); 6722 ic->ic_opmode = opmode; 6723 6724 return vap; 6725 } 6726 6727 static void 6728 iwm_vap_delete(struct ieee80211vap *vap) 6729 { 6730 struct iwm_vap *ivp = IWM_VAP(vap); 6731 6732 ieee80211_ratectl_deinit(vap); 6733 ieee80211_vap_detach(vap); 6734 free(ivp, M_80211_VAP); 6735 } 6736 6737 static void 6738 iwm_xmit_queue_drain(struct iwm_softc *sc) 6739 { 6740 struct mbuf *m; 6741 struct ieee80211_node *ni; 6742 6743 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 6744 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 6745 ieee80211_free_node(ni); 6746 m_freem(m); 6747 } 6748 } 6749 6750 static void 6751 iwm_scan_start(struct ieee80211com *ic) 6752 { 6753 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6754 struct iwm_softc *sc = ic->ic_softc; 6755 int error; 6756 6757 IWM_LOCK(sc); 6758 if (sc->sc_flags & IWM_FLAG_SCAN_RUNNING) { 6759 /* This should not be possible */ 6760 device_printf(sc->sc_dev, 6761 "%s: Previous scan not completed yet\n", __func__); 6762 } 6763 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_UMAC_SCAN)) 6764 error = iwm_umac_scan(sc); 6765 else 6766 error = iwm_lmac_scan(sc); 6767 if (error != 0) { 6768 device_printf(sc->sc_dev, "could not initiate scan\n"); 6769 IWM_UNLOCK(sc); 6770 ieee80211_cancel_scan(vap); 6771 } else { 6772 sc->sc_flags |= IWM_FLAG_SCAN_RUNNING; 6773 iwm_led_blink_start(sc); 6774 IWM_UNLOCK(sc); 6775 } 6776 } 6777 6778 static void 6779 iwm_scan_end(struct ieee80211com *ic) 6780 { 6781 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6782 struct iwm_softc *sc = ic->ic_softc; 6783 6784 IWM_LOCK(sc); 6785 iwm_led_blink_stop(sc); 6786 if (vap->iv_state == IEEE80211_S_RUN) 6787 iwm_led_enable(sc); 6788 if (sc->sc_flags & IWM_FLAG_SCAN_RUNNING) { 6789 /* 6790 * Removing IWM_FLAG_SCAN_RUNNING now, is fine because 6791 * both iwm_scan_end and iwm_scan_start run in the ic->ic_tq 6792 * taskqueue. 6793 */ 6794 sc->sc_flags &= ~IWM_FLAG_SCAN_RUNNING; 6795 iwm_scan_stop_wait(sc); 6796 } 6797 IWM_UNLOCK(sc); 6798 6799 /* 6800 * Make sure we don't race, if sc_es_task is still enqueued here. 6801 * This is to make sure that it won't call ieee80211_scan_done 6802 * when we have already started the next scan. 6803 */ 6804 taskqueue_cancel(ic->ic_tq, &sc->sc_es_task, NULL); 6805 } 6806 6807 static void 6808 iwm_update_mcast(struct ieee80211com *ic) 6809 { 6810 } 6811 6812 static void 6813 iwm_set_channel(struct ieee80211com *ic) 6814 { 6815 } 6816 6817 static void 6818 iwm_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 6819 { 6820 } 6821 6822 static void 6823 iwm_scan_mindwell(struct ieee80211_scan_state *ss) 6824 { 6825 } 6826 6827 void 6828 iwm_init_task(void *arg1) 6829 { 6830 struct iwm_softc *sc = arg1; 6831 6832 IWM_LOCK(sc); 6833 while (sc->sc_flags & IWM_FLAG_BUSY) 6834 msleep(&sc->sc_flags, &sc->sc_mtx, 0, "iwmpwr", 0); 6835 sc->sc_flags |= IWM_FLAG_BUSY; 6836 iwm_stop(sc); 6837 if (sc->sc_ic.ic_nrunning > 0) 6838 iwm_init(sc); 6839 sc->sc_flags &= ~IWM_FLAG_BUSY; 6840 wakeup(&sc->sc_flags); 6841 IWM_UNLOCK(sc); 6842 } 6843 6844 static int 6845 iwm_resume(device_t dev) 6846 { 6847 struct iwm_softc *sc = device_get_softc(dev); 6848 int do_reinit = 0; 6849 6850 /* 6851 * We disable the RETRY_TIMEOUT register (0x41) to keep 6852 * PCI Tx retries from interfering with C3 CPU state. 6853 */ 6854 pci_write_config(dev, PCI_CFG_RETRY_TIMEOUT, 0x00, 1); 6855 6856 if (!sc->sc_attached) 6857 return 0; 6858 6859 iwm_init_task(device_get_softc(dev)); 6860 6861 IWM_LOCK(sc); 6862 if (sc->sc_flags & IWM_FLAG_SCANNING) { 6863 sc->sc_flags &= ~IWM_FLAG_SCANNING; 6864 do_reinit = 1; 6865 } 6866 IWM_UNLOCK(sc); 6867 6868 if (do_reinit) 6869 ieee80211_resume_all(&sc->sc_ic); 6870 6871 return 0; 6872 } 6873 6874 static int 6875 iwm_suspend(device_t dev) 6876 { 6877 int do_stop = 0; 6878 struct iwm_softc *sc = device_get_softc(dev); 6879 6880 do_stop = !! (sc->sc_ic.ic_nrunning > 0); 6881 6882 if (!sc->sc_attached) 6883 return (0); 6884 6885 ieee80211_suspend_all(&sc->sc_ic); 6886 6887 if (do_stop) { 6888 IWM_LOCK(sc); 6889 iwm_stop(sc); 6890 sc->sc_flags |= IWM_FLAG_SCANNING; 6891 IWM_UNLOCK(sc); 6892 } 6893 6894 return (0); 6895 } 6896 6897 static int 6898 iwm_detach_local(struct iwm_softc *sc, int do_net80211) 6899 { 6900 struct iwm_fw_info *fw = &sc->sc_fw; 6901 device_t dev = sc->sc_dev; 6902 int i; 6903 6904 IWM_LOCK_ASSERT_UNLOCKED(sc); 6905 6906 if (!sc->sc_attached) 6907 return 0; 6908 sc->sc_attached = 0; 6909 if (do_net80211) { 6910 ieee80211_draintask(&sc->sc_ic, &sc->sc_es_task); 6911 } 6912 iwm_stop_device(sc); 6913 taskqueue_drain_all(sc->sc_tq); 6914 taskqueue_free(sc->sc_tq); 6915 if (do_net80211) { 6916 IWM_LOCK(sc); 6917 iwm_xmit_queue_drain(sc); 6918 IWM_UNLOCK(sc); 6919 ieee80211_ifdetach(&sc->sc_ic); 6920 } 6921 callout_drain(&sc->sc_led_blink_to); 6922 callout_drain(&sc->sc_watchdog_to); 6923 6924 iwm_phy_db_free(sc->sc_phy_db); 6925 sc->sc_phy_db = NULL; 6926 6927 iwm_free_nvm_data(sc->nvm_data); 6928 6929 /* Free descriptor rings */ 6930 iwm_free_rx_ring(sc, &sc->rxq); 6931 for (i = 0; i < nitems(sc->txq); i++) 6932 iwm_free_tx_ring(sc, &sc->txq[i]); 6933 6934 /* Free firmware */ 6935 if (fw->fw_fp != NULL) 6936 iwm_fw_info_free(fw); 6937 6938 /* Free scheduler */ 6939 iwm_dma_contig_free(&sc->sched_dma); 6940 iwm_dma_contig_free(&sc->ict_dma); 6941 iwm_dma_contig_free(&sc->kw_dma); 6942 iwm_dma_contig_free(&sc->fw_dma); 6943 6944 iwm_free_fw_paging(sc); 6945 6946 /* Finished with the hardware - detach things */ 6947 iwm_pci_detach(dev); 6948 6949 if (sc->sc_notif_wait != NULL) { 6950 iwm_notification_wait_free(sc->sc_notif_wait); 6951 sc->sc_notif_wait = NULL; 6952 } 6953 6954 IWM_LOCK_DESTROY(sc); 6955 6956 return (0); 6957 } 6958 6959 static int 6960 iwm_detach(device_t dev) 6961 { 6962 struct iwm_softc *sc = device_get_softc(dev); 6963 6964 return (iwm_detach_local(sc, 1)); 6965 } 6966 6967 static device_method_t iwm_pci_methods[] = { 6968 /* Device interface */ 6969 DEVMETHOD(device_probe, iwm_probe), 6970 DEVMETHOD(device_attach, iwm_attach), 6971 DEVMETHOD(device_detach, iwm_detach), 6972 DEVMETHOD(device_suspend, iwm_suspend), 6973 DEVMETHOD(device_resume, iwm_resume), 6974 6975 DEVMETHOD_END 6976 }; 6977 6978 static driver_t iwm_pci_driver = { 6979 "iwm", 6980 iwm_pci_methods, 6981 sizeof (struct iwm_softc) 6982 }; 6983 6984 DRIVER_MODULE(iwm, pci, iwm_pci_driver, NULL, NULL); 6985 MODULE_PNP_INFO("U16:device;P:#;T:vendor=0x8086", pci, iwm_pci_driver, 6986 iwm_devices, nitems(iwm_devices)); 6987 MODULE_DEPEND(iwm, firmware, 1, 1, 1); 6988 MODULE_DEPEND(iwm, pci, 1, 1, 1); 6989 MODULE_DEPEND(iwm, wlan, 1, 1, 1); 6990