1 /* $OpenBSD: if_iwm.c,v 1.42 2015/05/30 02:49:23 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90 /*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105 #include <sys/cdefs.h> 106 __FBSDID("$FreeBSD$"); 107 108 #include "opt_wlan.h" 109 110 #include <sys/param.h> 111 #include <sys/bus.h> 112 #include <sys/conf.h> 113 #include <sys/endian.h> 114 #include <sys/firmware.h> 115 #include <sys/kernel.h> 116 #include <sys/malloc.h> 117 #include <sys/mbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/module.h> 120 #include <sys/proc.h> 121 #include <sys/rman.h> 122 #include <sys/socket.h> 123 #include <sys/sockio.h> 124 #include <sys/sysctl.h> 125 #include <sys/linker.h> 126 127 #include <machine/bus.h> 128 #include <machine/endian.h> 129 #include <machine/resource.h> 130 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/pcireg.h> 133 134 #include <net/bpf.h> 135 136 #include <net/if.h> 137 #include <net/if_var.h> 138 #include <net/if_arp.h> 139 #include <net/if_dl.h> 140 #include <net/if_media.h> 141 #include <net/if_types.h> 142 143 #include <netinet/in.h> 144 #include <netinet/in_systm.h> 145 #include <netinet/if_ether.h> 146 #include <netinet/ip.h> 147 148 #include <net80211/ieee80211_var.h> 149 #include <net80211/ieee80211_regdomain.h> 150 #include <net80211/ieee80211_ratectl.h> 151 #include <net80211/ieee80211_radiotap.h> 152 153 #include <dev/iwm/if_iwmreg.h> 154 #include <dev/iwm/if_iwmvar.h> 155 #include <dev/iwm/if_iwm_debug.h> 156 #include <dev/iwm/if_iwm_util.h> 157 #include <dev/iwm/if_iwm_binding.h> 158 #include <dev/iwm/if_iwm_phy_db.h> 159 #include <dev/iwm/if_iwm_mac_ctxt.h> 160 #include <dev/iwm/if_iwm_phy_ctxt.h> 161 #include <dev/iwm/if_iwm_time_event.h> 162 #include <dev/iwm/if_iwm_power.h> 163 #include <dev/iwm/if_iwm_scan.h> 164 165 #include <dev/iwm/if_iwm_pcie_trans.h> 166 #include <dev/iwm/if_iwm_led.h> 167 168 const uint8_t iwm_nvm_channels[] = { 169 /* 2.4 GHz */ 170 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 171 /* 5 GHz */ 172 36, 40, 44, 48, 52, 56, 60, 64, 173 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 174 149, 153, 157, 161, 165 175 }; 176 _Static_assert(nitems(iwm_nvm_channels) <= IWM_NUM_CHANNELS, 177 "IWM_NUM_CHANNELS is too small"); 178 179 const uint8_t iwm_nvm_channels_8000[] = { 180 /* 2.4 GHz */ 181 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 182 /* 5 GHz */ 183 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 184 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 185 149, 153, 157, 161, 165, 169, 173, 177, 181 186 }; 187 _Static_assert(nitems(iwm_nvm_channels_8000) <= IWM_NUM_CHANNELS_8000, 188 "IWM_NUM_CHANNELS_8000 is too small"); 189 190 #define IWM_NUM_2GHZ_CHANNELS 14 191 #define IWM_N_HW_ADDR_MASK 0xF 192 193 /* 194 * XXX For now, there's simply a fixed set of rate table entries 195 * that are populated. 196 */ 197 const struct iwm_rate { 198 uint8_t rate; 199 uint8_t plcp; 200 } iwm_rates[] = { 201 { 2, IWM_RATE_1M_PLCP }, 202 { 4, IWM_RATE_2M_PLCP }, 203 { 11, IWM_RATE_5M_PLCP }, 204 { 22, IWM_RATE_11M_PLCP }, 205 { 12, IWM_RATE_6M_PLCP }, 206 { 18, IWM_RATE_9M_PLCP }, 207 { 24, IWM_RATE_12M_PLCP }, 208 { 36, IWM_RATE_18M_PLCP }, 209 { 48, IWM_RATE_24M_PLCP }, 210 { 72, IWM_RATE_36M_PLCP }, 211 { 96, IWM_RATE_48M_PLCP }, 212 { 108, IWM_RATE_54M_PLCP }, 213 }; 214 #define IWM_RIDX_CCK 0 215 #define IWM_RIDX_OFDM 4 216 #define IWM_RIDX_MAX (nitems(iwm_rates)-1) 217 #define IWM_RIDX_IS_CCK(_i_) ((_i_) < IWM_RIDX_OFDM) 218 #define IWM_RIDX_IS_OFDM(_i_) ((_i_) >= IWM_RIDX_OFDM) 219 220 struct iwm_nvm_section { 221 uint16_t length; 222 uint8_t *data; 223 }; 224 225 static int iwm_store_cscheme(struct iwm_softc *, const uint8_t *, size_t); 226 static int iwm_firmware_store_section(struct iwm_softc *, 227 enum iwm_ucode_type, 228 const uint8_t *, size_t); 229 static int iwm_set_default_calib(struct iwm_softc *, const void *); 230 static void iwm_fw_info_free(struct iwm_fw_info *); 231 static int iwm_read_firmware(struct iwm_softc *, enum iwm_ucode_type); 232 static void iwm_dma_map_addr(void *, bus_dma_segment_t *, int, int); 233 static int iwm_dma_contig_alloc(bus_dma_tag_t, struct iwm_dma_info *, 234 bus_size_t, bus_size_t); 235 static void iwm_dma_contig_free(struct iwm_dma_info *); 236 static int iwm_alloc_fwmem(struct iwm_softc *); 237 static int iwm_alloc_sched(struct iwm_softc *); 238 static int iwm_alloc_kw(struct iwm_softc *); 239 static int iwm_alloc_ict(struct iwm_softc *); 240 static int iwm_alloc_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 241 static void iwm_disable_rx_dma(struct iwm_softc *); 242 static void iwm_reset_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 243 static void iwm_free_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 244 static int iwm_alloc_tx_ring(struct iwm_softc *, struct iwm_tx_ring *, 245 int); 246 static void iwm_reset_tx_ring(struct iwm_softc *, struct iwm_tx_ring *); 247 static void iwm_free_tx_ring(struct iwm_softc *, struct iwm_tx_ring *); 248 static void iwm_enable_interrupts(struct iwm_softc *); 249 static void iwm_restore_interrupts(struct iwm_softc *); 250 static void iwm_disable_interrupts(struct iwm_softc *); 251 static void iwm_ict_reset(struct iwm_softc *); 252 static int iwm_allow_mcast(struct ieee80211vap *, struct iwm_softc *); 253 static void iwm_stop_device(struct iwm_softc *); 254 static void iwm_mvm_nic_config(struct iwm_softc *); 255 static int iwm_nic_rx_init(struct iwm_softc *); 256 static int iwm_nic_tx_init(struct iwm_softc *); 257 static int iwm_nic_init(struct iwm_softc *); 258 static int iwm_enable_txq(struct iwm_softc *, int, int, int); 259 static int iwm_post_alive(struct iwm_softc *); 260 static int iwm_nvm_read_chunk(struct iwm_softc *, uint16_t, uint16_t, 261 uint16_t, uint8_t *, uint16_t *); 262 static int iwm_nvm_read_section(struct iwm_softc *, uint16_t, uint8_t *, 263 uint16_t *, size_t); 264 static uint32_t iwm_eeprom_channel_flags(uint16_t); 265 static void iwm_add_channel_band(struct iwm_softc *, 266 struct ieee80211_channel[], int, int *, int, size_t, 267 const uint8_t[]); 268 static void iwm_init_channel_map(struct ieee80211com *, int, int *, 269 struct ieee80211_channel[]); 270 static int iwm_parse_nvm_data(struct iwm_softc *, const uint16_t *, 271 const uint16_t *, const uint16_t *, 272 const uint16_t *, const uint16_t *, 273 const uint16_t *); 274 static void iwm_set_hw_address_8000(struct iwm_softc *, 275 struct iwm_nvm_data *, 276 const uint16_t *, const uint16_t *); 277 static int iwm_get_sku(const struct iwm_softc *, const uint16_t *, 278 const uint16_t *); 279 static int iwm_get_nvm_version(const struct iwm_softc *, const uint16_t *); 280 static int iwm_get_radio_cfg(const struct iwm_softc *, const uint16_t *, 281 const uint16_t *); 282 static int iwm_get_n_hw_addrs(const struct iwm_softc *, 283 const uint16_t *); 284 static void iwm_set_radio_cfg(const struct iwm_softc *, 285 struct iwm_nvm_data *, uint32_t); 286 static int iwm_parse_nvm_sections(struct iwm_softc *, 287 struct iwm_nvm_section *); 288 static int iwm_nvm_init(struct iwm_softc *); 289 static int iwm_firmware_load_sect(struct iwm_softc *, uint32_t, 290 const uint8_t *, uint32_t); 291 static int iwm_firmware_load_chunk(struct iwm_softc *, uint32_t, 292 const uint8_t *, uint32_t); 293 static int iwm_load_firmware_7000(struct iwm_softc *, enum iwm_ucode_type); 294 static int iwm_load_cpu_sections_8000(struct iwm_softc *, 295 struct iwm_fw_sects *, int , int *); 296 static int iwm_load_firmware_8000(struct iwm_softc *, enum iwm_ucode_type); 297 static int iwm_load_firmware(struct iwm_softc *, enum iwm_ucode_type); 298 static int iwm_start_fw(struct iwm_softc *, enum iwm_ucode_type); 299 static int iwm_send_tx_ant_cfg(struct iwm_softc *, uint8_t); 300 static int iwm_send_phy_cfg_cmd(struct iwm_softc *); 301 static int iwm_mvm_load_ucode_wait_alive(struct iwm_softc *, 302 enum iwm_ucode_type); 303 static int iwm_run_init_mvm_ucode(struct iwm_softc *, int); 304 static int iwm_rx_addbuf(struct iwm_softc *, int, int); 305 static int iwm_mvm_calc_rssi(struct iwm_softc *, struct iwm_rx_phy_info *); 306 static int iwm_mvm_get_signal_strength(struct iwm_softc *, 307 struct iwm_rx_phy_info *); 308 static void iwm_mvm_rx_rx_phy_cmd(struct iwm_softc *, 309 struct iwm_rx_packet *, 310 struct iwm_rx_data *); 311 static int iwm_get_noise(struct iwm_softc *sc, 312 const struct iwm_mvm_statistics_rx_non_phy *); 313 static void iwm_mvm_rx_rx_mpdu(struct iwm_softc *, struct iwm_rx_packet *, 314 struct iwm_rx_data *); 315 static int iwm_mvm_rx_tx_cmd_single(struct iwm_softc *, 316 struct iwm_rx_packet *, 317 struct iwm_node *); 318 static void iwm_mvm_rx_tx_cmd(struct iwm_softc *, struct iwm_rx_packet *, 319 struct iwm_rx_data *); 320 static void iwm_cmd_done(struct iwm_softc *, struct iwm_rx_packet *); 321 #if 0 322 static void iwm_update_sched(struct iwm_softc *, int, int, uint8_t, 323 uint16_t); 324 #endif 325 static const struct iwm_rate * 326 iwm_tx_fill_cmd(struct iwm_softc *, struct iwm_node *, 327 struct mbuf *, struct iwm_tx_cmd *); 328 static int iwm_tx(struct iwm_softc *, struct mbuf *, 329 struct ieee80211_node *, int); 330 static int iwm_raw_xmit(struct ieee80211_node *, struct mbuf *, 331 const struct ieee80211_bpf_params *); 332 static int iwm_mvm_flush_tx_path(struct iwm_softc *sc, 333 uint32_t tfd_msk, uint32_t flags); 334 static int iwm_mvm_send_add_sta_cmd_status(struct iwm_softc *, 335 struct iwm_mvm_add_sta_cmd_v7 *, 336 int *); 337 static int iwm_mvm_sta_send_to_fw(struct iwm_softc *, struct iwm_node *, 338 int); 339 static int iwm_mvm_add_sta(struct iwm_softc *, struct iwm_node *); 340 static int iwm_mvm_update_sta(struct iwm_softc *, struct iwm_node *); 341 static int iwm_mvm_add_int_sta_common(struct iwm_softc *, 342 struct iwm_int_sta *, 343 const uint8_t *, uint16_t, uint16_t); 344 static int iwm_mvm_add_aux_sta(struct iwm_softc *); 345 static int iwm_mvm_update_quotas(struct iwm_softc *, struct iwm_node *); 346 static int iwm_auth(struct ieee80211vap *, struct iwm_softc *); 347 static int iwm_assoc(struct ieee80211vap *, struct iwm_softc *); 348 static int iwm_release(struct iwm_softc *, struct iwm_node *); 349 static struct ieee80211_node * 350 iwm_node_alloc(struct ieee80211vap *, 351 const uint8_t[IEEE80211_ADDR_LEN]); 352 static void iwm_setrates(struct iwm_softc *, struct iwm_node *); 353 static int iwm_media_change(struct ifnet *); 354 static int iwm_newstate(struct ieee80211vap *, enum ieee80211_state, int); 355 static void iwm_endscan_cb(void *, int); 356 static void iwm_mvm_fill_sf_command(struct iwm_softc *, 357 struct iwm_sf_cfg_cmd *, 358 struct ieee80211_node *); 359 static int iwm_mvm_sf_config(struct iwm_softc *, enum iwm_sf_state); 360 static int iwm_send_bt_init_conf(struct iwm_softc *); 361 static int iwm_send_update_mcc_cmd(struct iwm_softc *, const char *); 362 static void iwm_mvm_tt_tx_backoff(struct iwm_softc *, uint32_t); 363 static int iwm_init_hw(struct iwm_softc *); 364 static void iwm_init(struct iwm_softc *); 365 static void iwm_start(struct iwm_softc *); 366 static void iwm_stop(struct iwm_softc *); 367 static void iwm_watchdog(void *); 368 static void iwm_parent(struct ieee80211com *); 369 #ifdef IWM_DEBUG 370 static const char * 371 iwm_desc_lookup(uint32_t); 372 static void iwm_nic_error(struct iwm_softc *); 373 static void iwm_nic_umac_error(struct iwm_softc *); 374 #endif 375 static void iwm_notif_intr(struct iwm_softc *); 376 static void iwm_intr(void *); 377 static int iwm_attach(device_t); 378 static int iwm_is_valid_ether_addr(uint8_t *); 379 static void iwm_preinit(void *); 380 static int iwm_detach_local(struct iwm_softc *sc, int); 381 static void iwm_init_task(void *); 382 static void iwm_radiotap_attach(struct iwm_softc *); 383 static struct ieee80211vap * 384 iwm_vap_create(struct ieee80211com *, 385 const char [IFNAMSIZ], int, 386 enum ieee80211_opmode, int, 387 const uint8_t [IEEE80211_ADDR_LEN], 388 const uint8_t [IEEE80211_ADDR_LEN]); 389 static void iwm_vap_delete(struct ieee80211vap *); 390 static void iwm_scan_start(struct ieee80211com *); 391 static void iwm_scan_end(struct ieee80211com *); 392 static void iwm_update_mcast(struct ieee80211com *); 393 static void iwm_set_channel(struct ieee80211com *); 394 static void iwm_scan_curchan(struct ieee80211_scan_state *, unsigned long); 395 static void iwm_scan_mindwell(struct ieee80211_scan_state *); 396 static int iwm_detach(device_t); 397 398 /* 399 * Firmware parser. 400 */ 401 402 static int 403 iwm_store_cscheme(struct iwm_softc *sc, const uint8_t *data, size_t dlen) 404 { 405 const struct iwm_fw_cscheme_list *l = (const void *)data; 406 407 if (dlen < sizeof(*l) || 408 dlen < sizeof(l->size) + l->size * sizeof(*l->cs)) 409 return EINVAL; 410 411 /* we don't actually store anything for now, always use s/w crypto */ 412 413 return 0; 414 } 415 416 static int 417 iwm_firmware_store_section(struct iwm_softc *sc, 418 enum iwm_ucode_type type, const uint8_t *data, size_t dlen) 419 { 420 struct iwm_fw_sects *fws; 421 struct iwm_fw_onesect *fwone; 422 423 if (type >= IWM_UCODE_TYPE_MAX) 424 return EINVAL; 425 if (dlen < sizeof(uint32_t)) 426 return EINVAL; 427 428 fws = &sc->sc_fw.fw_sects[type]; 429 if (fws->fw_count >= IWM_UCODE_SECT_MAX) 430 return EINVAL; 431 432 fwone = &fws->fw_sect[fws->fw_count]; 433 434 /* first 32bit are device load offset */ 435 memcpy(&fwone->fws_devoff, data, sizeof(uint32_t)); 436 437 /* rest is data */ 438 fwone->fws_data = data + sizeof(uint32_t); 439 fwone->fws_len = dlen - sizeof(uint32_t); 440 441 fws->fw_count++; 442 443 return 0; 444 } 445 446 #define IWM_DEFAULT_SCAN_CHANNELS 40 447 448 /* iwlwifi: iwl-drv.c */ 449 struct iwm_tlv_calib_data { 450 uint32_t ucode_type; 451 struct iwm_tlv_calib_ctrl calib; 452 } __packed; 453 454 static int 455 iwm_set_default_calib(struct iwm_softc *sc, const void *data) 456 { 457 const struct iwm_tlv_calib_data *def_calib = data; 458 uint32_t ucode_type = le32toh(def_calib->ucode_type); 459 460 if (ucode_type >= IWM_UCODE_TYPE_MAX) { 461 device_printf(sc->sc_dev, 462 "Wrong ucode_type %u for default " 463 "calibration.\n", ucode_type); 464 return EINVAL; 465 } 466 467 sc->sc_default_calib[ucode_type].flow_trigger = 468 def_calib->calib.flow_trigger; 469 sc->sc_default_calib[ucode_type].event_trigger = 470 def_calib->calib.event_trigger; 471 472 return 0; 473 } 474 475 static void 476 iwm_fw_info_free(struct iwm_fw_info *fw) 477 { 478 firmware_put(fw->fw_fp, FIRMWARE_UNLOAD); 479 fw->fw_fp = NULL; 480 /* don't touch fw->fw_status */ 481 memset(fw->fw_sects, 0, sizeof(fw->fw_sects)); 482 } 483 484 static int 485 iwm_read_firmware(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 486 { 487 struct iwm_fw_info *fw = &sc->sc_fw; 488 const struct iwm_tlv_ucode_header *uhdr; 489 struct iwm_ucode_tlv tlv; 490 enum iwm_ucode_tlv_type tlv_type; 491 const struct firmware *fwp; 492 const uint8_t *data; 493 int error = 0; 494 size_t len; 495 496 if (fw->fw_status == IWM_FW_STATUS_DONE && 497 ucode_type != IWM_UCODE_TYPE_INIT) 498 return 0; 499 500 while (fw->fw_status == IWM_FW_STATUS_INPROGRESS) 501 msleep(&sc->sc_fw, &sc->sc_mtx, 0, "iwmfwp", 0); 502 fw->fw_status = IWM_FW_STATUS_INPROGRESS; 503 504 if (fw->fw_fp != NULL) 505 iwm_fw_info_free(fw); 506 507 /* 508 * Load firmware into driver memory. 509 * fw_fp will be set. 510 */ 511 IWM_UNLOCK(sc); 512 fwp = firmware_get(sc->sc_fwname); 513 IWM_LOCK(sc); 514 if (fwp == NULL) { 515 device_printf(sc->sc_dev, 516 "could not read firmware %s (error %d)\n", 517 sc->sc_fwname, error); 518 goto out; 519 } 520 fw->fw_fp = fwp; 521 522 /* (Re-)Initialize default values. */ 523 sc->sc_capaflags = 0; 524 sc->sc_capa_n_scan_channels = IWM_DEFAULT_SCAN_CHANNELS; 525 memset(sc->sc_enabled_capa, 0, sizeof(sc->sc_enabled_capa)); 526 memset(sc->sc_fw_mcc, 0, sizeof(sc->sc_fw_mcc)); 527 528 /* 529 * Parse firmware contents 530 */ 531 532 uhdr = (const void *)fw->fw_fp->data; 533 if (*(const uint32_t *)fw->fw_fp->data != 0 534 || le32toh(uhdr->magic) != IWM_TLV_UCODE_MAGIC) { 535 device_printf(sc->sc_dev, "invalid firmware %s\n", 536 sc->sc_fwname); 537 error = EINVAL; 538 goto out; 539 } 540 541 snprintf(sc->sc_fwver, sizeof(sc->sc_fwver), "%d.%d (API ver %d)", 542 IWM_UCODE_MAJOR(le32toh(uhdr->ver)), 543 IWM_UCODE_MINOR(le32toh(uhdr->ver)), 544 IWM_UCODE_API(le32toh(uhdr->ver))); 545 data = uhdr->data; 546 len = fw->fw_fp->datasize - sizeof(*uhdr); 547 548 while (len >= sizeof(tlv)) { 549 size_t tlv_len; 550 const void *tlv_data; 551 552 memcpy(&tlv, data, sizeof(tlv)); 553 tlv_len = le32toh(tlv.length); 554 tlv_type = le32toh(tlv.type); 555 556 len -= sizeof(tlv); 557 data += sizeof(tlv); 558 tlv_data = data; 559 560 if (len < tlv_len) { 561 device_printf(sc->sc_dev, 562 "firmware too short: %zu bytes\n", 563 len); 564 error = EINVAL; 565 goto parse_out; 566 } 567 568 switch ((int)tlv_type) { 569 case IWM_UCODE_TLV_PROBE_MAX_LEN: 570 if (tlv_len < sizeof(uint32_t)) { 571 device_printf(sc->sc_dev, 572 "%s: PROBE_MAX_LEN (%d) < sizeof(uint32_t)\n", 573 __func__, 574 (int) tlv_len); 575 error = EINVAL; 576 goto parse_out; 577 } 578 sc->sc_capa_max_probe_len 579 = le32toh(*(const uint32_t *)tlv_data); 580 /* limit it to something sensible */ 581 if (sc->sc_capa_max_probe_len > 582 IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE) { 583 IWM_DPRINTF(sc, IWM_DEBUG_FIRMWARE_TLV, 584 "%s: IWM_UCODE_TLV_PROBE_MAX_LEN " 585 "ridiculous\n", __func__); 586 error = EINVAL; 587 goto parse_out; 588 } 589 break; 590 case IWM_UCODE_TLV_PAN: 591 if (tlv_len) { 592 device_printf(sc->sc_dev, 593 "%s: IWM_UCODE_TLV_PAN: tlv_len (%d) > 0\n", 594 __func__, 595 (int) tlv_len); 596 error = EINVAL; 597 goto parse_out; 598 } 599 sc->sc_capaflags |= IWM_UCODE_TLV_FLAGS_PAN; 600 break; 601 case IWM_UCODE_TLV_FLAGS: 602 if (tlv_len < sizeof(uint32_t)) { 603 device_printf(sc->sc_dev, 604 "%s: IWM_UCODE_TLV_FLAGS: tlv_len (%d) < sizeof(uint32_t)\n", 605 __func__, 606 (int) tlv_len); 607 error = EINVAL; 608 goto parse_out; 609 } 610 /* 611 * Apparently there can be many flags, but Linux driver 612 * parses only the first one, and so do we. 613 * 614 * XXX: why does this override IWM_UCODE_TLV_PAN? 615 * Intentional or a bug? Observations from 616 * current firmware file: 617 * 1) TLV_PAN is parsed first 618 * 2) TLV_FLAGS contains TLV_FLAGS_PAN 619 * ==> this resets TLV_PAN to itself... hnnnk 620 */ 621 sc->sc_capaflags = le32toh(*(const uint32_t *)tlv_data); 622 break; 623 case IWM_UCODE_TLV_CSCHEME: 624 if ((error = iwm_store_cscheme(sc, 625 tlv_data, tlv_len)) != 0) { 626 device_printf(sc->sc_dev, 627 "%s: iwm_store_cscheme(): returned %d\n", 628 __func__, 629 error); 630 goto parse_out; 631 } 632 break; 633 case IWM_UCODE_TLV_NUM_OF_CPU: { 634 uint32_t num_cpu; 635 if (tlv_len != sizeof(uint32_t)) { 636 device_printf(sc->sc_dev, 637 "%s: IWM_UCODE_TLV_NUM_OF_CPU: tlv_len (%d) < sizeof(uint32_t)\n", 638 __func__, 639 (int) tlv_len); 640 error = EINVAL; 641 goto parse_out; 642 } 643 num_cpu = le32toh(*(const uint32_t *)tlv_data); 644 if (num_cpu < 1 || num_cpu > 2) { 645 device_printf(sc->sc_dev, 646 "%s: Driver supports only 1 or 2 CPUs\n", 647 __func__); 648 error = EINVAL; 649 goto parse_out; 650 } 651 break; 652 } 653 case IWM_UCODE_TLV_SEC_RT: 654 if ((error = iwm_firmware_store_section(sc, 655 IWM_UCODE_TYPE_REGULAR, tlv_data, tlv_len)) != 0) { 656 device_printf(sc->sc_dev, 657 "%s: IWM_UCODE_TYPE_REGULAR: iwm_firmware_store_section() failed; %d\n", 658 __func__, 659 error); 660 goto parse_out; 661 } 662 break; 663 case IWM_UCODE_TLV_SEC_INIT: 664 if ((error = iwm_firmware_store_section(sc, 665 IWM_UCODE_TYPE_INIT, tlv_data, tlv_len)) != 0) { 666 device_printf(sc->sc_dev, 667 "%s: IWM_UCODE_TYPE_INIT: iwm_firmware_store_section() failed; %d\n", 668 __func__, 669 error); 670 goto parse_out; 671 } 672 break; 673 case IWM_UCODE_TLV_SEC_WOWLAN: 674 if ((error = iwm_firmware_store_section(sc, 675 IWM_UCODE_TYPE_WOW, tlv_data, tlv_len)) != 0) { 676 device_printf(sc->sc_dev, 677 "%s: IWM_UCODE_TYPE_WOW: iwm_firmware_store_section() failed; %d\n", 678 __func__, 679 error); 680 goto parse_out; 681 } 682 break; 683 case IWM_UCODE_TLV_DEF_CALIB: 684 if (tlv_len != sizeof(struct iwm_tlv_calib_data)) { 685 device_printf(sc->sc_dev, 686 "%s: IWM_UCODE_TLV_DEV_CALIB: tlv_len (%d) < sizeof(iwm_tlv_calib_data) (%d)\n", 687 __func__, 688 (int) tlv_len, 689 (int) sizeof(struct iwm_tlv_calib_data)); 690 error = EINVAL; 691 goto parse_out; 692 } 693 if ((error = iwm_set_default_calib(sc, tlv_data)) != 0) { 694 device_printf(sc->sc_dev, 695 "%s: iwm_set_default_calib() failed: %d\n", 696 __func__, 697 error); 698 goto parse_out; 699 } 700 break; 701 case IWM_UCODE_TLV_PHY_SKU: 702 if (tlv_len != sizeof(uint32_t)) { 703 error = EINVAL; 704 device_printf(sc->sc_dev, 705 "%s: IWM_UCODE_TLV_PHY_SKU: tlv_len (%d) < sizeof(uint32_t)\n", 706 __func__, 707 (int) tlv_len); 708 goto parse_out; 709 } 710 sc->sc_fw_phy_config = 711 le32toh(*(const uint32_t *)tlv_data); 712 break; 713 714 case IWM_UCODE_TLV_API_CHANGES_SET: { 715 const struct iwm_ucode_api *api; 716 if (tlv_len != sizeof(*api)) { 717 error = EINVAL; 718 goto parse_out; 719 } 720 api = (const struct iwm_ucode_api *)tlv_data; 721 /* Flags may exceed 32 bits in future firmware. */ 722 if (le32toh(api->api_index) > 0) { 723 device_printf(sc->sc_dev, 724 "unsupported API index %d\n", 725 le32toh(api->api_index)); 726 goto parse_out; 727 } 728 sc->sc_ucode_api = le32toh(api->api_flags); 729 break; 730 } 731 732 case IWM_UCODE_TLV_ENABLED_CAPABILITIES: { 733 const struct iwm_ucode_capa *capa; 734 int idx, i; 735 if (tlv_len != sizeof(*capa)) { 736 error = EINVAL; 737 goto parse_out; 738 } 739 capa = (const struct iwm_ucode_capa *)tlv_data; 740 idx = le32toh(capa->api_index); 741 if (idx >= howmany(IWM_NUM_UCODE_TLV_CAPA, 32)) { 742 device_printf(sc->sc_dev, 743 "unsupported API index %d\n", idx); 744 goto parse_out; 745 } 746 for (i = 0; i < 32; i++) { 747 if ((le32toh(capa->api_capa) & (1U << i)) == 0) 748 continue; 749 setbit(sc->sc_enabled_capa, i + (32 * idx)); 750 } 751 break; 752 } 753 754 case 48: /* undocumented TLV */ 755 case IWM_UCODE_TLV_SDIO_ADMA_ADDR: 756 case IWM_UCODE_TLV_FW_GSCAN_CAPA: 757 /* ignore, not used by current driver */ 758 break; 759 760 case IWM_UCODE_TLV_SEC_RT_USNIFFER: 761 if ((error = iwm_firmware_store_section(sc, 762 IWM_UCODE_TYPE_REGULAR_USNIFFER, tlv_data, 763 tlv_len)) != 0) 764 goto parse_out; 765 break; 766 767 case IWM_UCODE_TLV_N_SCAN_CHANNELS: 768 if (tlv_len != sizeof(uint32_t)) { 769 error = EINVAL; 770 goto parse_out; 771 } 772 sc->sc_capa_n_scan_channels = 773 le32toh(*(const uint32_t *)tlv_data); 774 break; 775 776 case IWM_UCODE_TLV_FW_VERSION: 777 if (tlv_len != sizeof(uint32_t) * 3) { 778 error = EINVAL; 779 goto parse_out; 780 } 781 snprintf(sc->sc_fwver, sizeof(sc->sc_fwver), 782 "%d.%d.%d", 783 le32toh(((const uint32_t *)tlv_data)[0]), 784 le32toh(((const uint32_t *)tlv_data)[1]), 785 le32toh(((const uint32_t *)tlv_data)[2])); 786 break; 787 788 default: 789 device_printf(sc->sc_dev, 790 "%s: unknown firmware section %d, abort\n", 791 __func__, tlv_type); 792 error = EINVAL; 793 goto parse_out; 794 } 795 796 len -= roundup(tlv_len, 4); 797 data += roundup(tlv_len, 4); 798 } 799 800 KASSERT(error == 0, ("unhandled error")); 801 802 parse_out: 803 if (error) { 804 device_printf(sc->sc_dev, "firmware parse error %d, " 805 "section type %d\n", error, tlv_type); 806 } 807 808 if (!(sc->sc_capaflags & IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT)) { 809 device_printf(sc->sc_dev, 810 "device uses unsupported power ops\n"); 811 error = ENOTSUP; 812 } 813 814 out: 815 if (error) { 816 fw->fw_status = IWM_FW_STATUS_NONE; 817 if (fw->fw_fp != NULL) 818 iwm_fw_info_free(fw); 819 } else 820 fw->fw_status = IWM_FW_STATUS_DONE; 821 wakeup(&sc->sc_fw); 822 823 return error; 824 } 825 826 /* 827 * DMA resource routines 828 */ 829 830 static void 831 iwm_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 832 { 833 if (error != 0) 834 return; 835 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 836 *(bus_addr_t *)arg = segs[0].ds_addr; 837 } 838 839 static int 840 iwm_dma_contig_alloc(bus_dma_tag_t tag, struct iwm_dma_info *dma, 841 bus_size_t size, bus_size_t alignment) 842 { 843 int error; 844 845 dma->tag = NULL; 846 dma->map = NULL; 847 dma->size = size; 848 dma->vaddr = NULL; 849 850 error = bus_dma_tag_create(tag, alignment, 851 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 852 1, size, 0, NULL, NULL, &dma->tag); 853 if (error != 0) 854 goto fail; 855 856 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 857 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 858 if (error != 0) 859 goto fail; 860 861 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 862 iwm_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 863 if (error != 0) { 864 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 865 dma->vaddr = NULL; 866 goto fail; 867 } 868 869 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 870 871 return 0; 872 873 fail: 874 iwm_dma_contig_free(dma); 875 876 return error; 877 } 878 879 static void 880 iwm_dma_contig_free(struct iwm_dma_info *dma) 881 { 882 if (dma->vaddr != NULL) { 883 bus_dmamap_sync(dma->tag, dma->map, 884 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 885 bus_dmamap_unload(dma->tag, dma->map); 886 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 887 dma->vaddr = NULL; 888 } 889 if (dma->tag != NULL) { 890 bus_dma_tag_destroy(dma->tag); 891 dma->tag = NULL; 892 } 893 } 894 895 /* fwmem is used to load firmware onto the card */ 896 static int 897 iwm_alloc_fwmem(struct iwm_softc *sc) 898 { 899 /* Must be aligned on a 16-byte boundary. */ 900 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, 901 sc->sc_fwdmasegsz, 16); 902 } 903 904 /* tx scheduler rings. not used? */ 905 static int 906 iwm_alloc_sched(struct iwm_softc *sc) 907 { 908 /* TX scheduler rings must be aligned on a 1KB boundary. */ 909 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 910 nitems(sc->txq) * sizeof(struct iwm_agn_scd_bc_tbl), 1024); 911 } 912 913 /* keep-warm page is used internally by the card. see iwl-fh.h for more info */ 914 static int 915 iwm_alloc_kw(struct iwm_softc *sc) 916 { 917 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, 4096, 4096); 918 } 919 920 /* interrupt cause table */ 921 static int 922 iwm_alloc_ict(struct iwm_softc *sc) 923 { 924 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 925 IWM_ICT_SIZE, 1<<IWM_ICT_PADDR_SHIFT); 926 } 927 928 static int 929 iwm_alloc_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 930 { 931 bus_size_t size; 932 int i, error; 933 934 ring->cur = 0; 935 936 /* Allocate RX descriptors (256-byte aligned). */ 937 size = IWM_RX_RING_COUNT * sizeof(uint32_t); 938 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, size, 256); 939 if (error != 0) { 940 device_printf(sc->sc_dev, 941 "could not allocate RX ring DMA memory\n"); 942 goto fail; 943 } 944 ring->desc = ring->desc_dma.vaddr; 945 946 /* Allocate RX status area (16-byte aligned). */ 947 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 948 sizeof(*ring->stat), 16); 949 if (error != 0) { 950 device_printf(sc->sc_dev, 951 "could not allocate RX status DMA memory\n"); 952 goto fail; 953 } 954 ring->stat = ring->stat_dma.vaddr; 955 956 /* Create RX buffer DMA tag. */ 957 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 958 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 959 IWM_RBUF_SIZE, 1, IWM_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat); 960 if (error != 0) { 961 device_printf(sc->sc_dev, 962 "%s: could not create RX buf DMA tag, error %d\n", 963 __func__, error); 964 goto fail; 965 } 966 967 /* Allocate spare bus_dmamap_t for iwm_rx_addbuf() */ 968 error = bus_dmamap_create(ring->data_dmat, 0, &ring->spare_map); 969 if (error != 0) { 970 device_printf(sc->sc_dev, 971 "%s: could not create RX buf DMA map, error %d\n", 972 __func__, error); 973 goto fail; 974 } 975 /* 976 * Allocate and map RX buffers. 977 */ 978 for (i = 0; i < IWM_RX_RING_COUNT; i++) { 979 struct iwm_rx_data *data = &ring->data[i]; 980 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 981 if (error != 0) { 982 device_printf(sc->sc_dev, 983 "%s: could not create RX buf DMA map, error %d\n", 984 __func__, error); 985 goto fail; 986 } 987 data->m = NULL; 988 989 if ((error = iwm_rx_addbuf(sc, IWM_RBUF_SIZE, i)) != 0) { 990 goto fail; 991 } 992 } 993 return 0; 994 995 fail: iwm_free_rx_ring(sc, ring); 996 return error; 997 } 998 999 static void 1000 iwm_disable_rx_dma(struct iwm_softc *sc) 1001 { 1002 /* XXX conditional nic locks are stupid */ 1003 /* XXX print out if we can't lock the NIC? */ 1004 if (iwm_nic_lock(sc)) { 1005 /* XXX handle if RX stop doesn't finish? */ 1006 (void) iwm_pcie_rx_stop(sc); 1007 iwm_nic_unlock(sc); 1008 } 1009 } 1010 1011 static void 1012 iwm_reset_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 1013 { 1014 /* Reset the ring state */ 1015 ring->cur = 0; 1016 1017 /* 1018 * The hw rx ring index in shared memory must also be cleared, 1019 * otherwise the discrepancy can cause reprocessing chaos. 1020 */ 1021 memset(sc->rxq.stat, 0, sizeof(*sc->rxq.stat)); 1022 } 1023 1024 static void 1025 iwm_free_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 1026 { 1027 int i; 1028 1029 iwm_dma_contig_free(&ring->desc_dma); 1030 iwm_dma_contig_free(&ring->stat_dma); 1031 1032 for (i = 0; i < IWM_RX_RING_COUNT; i++) { 1033 struct iwm_rx_data *data = &ring->data[i]; 1034 1035 if (data->m != NULL) { 1036 bus_dmamap_sync(ring->data_dmat, data->map, 1037 BUS_DMASYNC_POSTREAD); 1038 bus_dmamap_unload(ring->data_dmat, data->map); 1039 m_freem(data->m); 1040 data->m = NULL; 1041 } 1042 if (data->map != NULL) { 1043 bus_dmamap_destroy(ring->data_dmat, data->map); 1044 data->map = NULL; 1045 } 1046 } 1047 if (ring->spare_map != NULL) { 1048 bus_dmamap_destroy(ring->data_dmat, ring->spare_map); 1049 ring->spare_map = NULL; 1050 } 1051 if (ring->data_dmat != NULL) { 1052 bus_dma_tag_destroy(ring->data_dmat); 1053 ring->data_dmat = NULL; 1054 } 1055 } 1056 1057 static int 1058 iwm_alloc_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring, int qid) 1059 { 1060 bus_addr_t paddr; 1061 bus_size_t size; 1062 size_t maxsize; 1063 int nsegments; 1064 int i, error; 1065 1066 ring->qid = qid; 1067 ring->queued = 0; 1068 ring->cur = 0; 1069 1070 /* Allocate TX descriptors (256-byte aligned). */ 1071 size = IWM_TX_RING_COUNT * sizeof (struct iwm_tfd); 1072 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, size, 256); 1073 if (error != 0) { 1074 device_printf(sc->sc_dev, 1075 "could not allocate TX ring DMA memory\n"); 1076 goto fail; 1077 } 1078 ring->desc = ring->desc_dma.vaddr; 1079 1080 /* 1081 * We only use rings 0 through 9 (4 EDCA + cmd) so there is no need 1082 * to allocate commands space for other rings. 1083 */ 1084 if (qid > IWM_MVM_CMD_QUEUE) 1085 return 0; 1086 1087 size = IWM_TX_RING_COUNT * sizeof(struct iwm_device_cmd); 1088 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, size, 4); 1089 if (error != 0) { 1090 device_printf(sc->sc_dev, 1091 "could not allocate TX cmd DMA memory\n"); 1092 goto fail; 1093 } 1094 ring->cmd = ring->cmd_dma.vaddr; 1095 1096 /* FW commands may require more mapped space than packets. */ 1097 if (qid == IWM_MVM_CMD_QUEUE) { 1098 maxsize = IWM_RBUF_SIZE; 1099 nsegments = 1; 1100 } else { 1101 maxsize = MCLBYTES; 1102 nsegments = IWM_MAX_SCATTER - 2; 1103 } 1104 1105 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1106 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1107 nsegments, maxsize, 0, NULL, NULL, &ring->data_dmat); 1108 if (error != 0) { 1109 device_printf(sc->sc_dev, "could not create TX buf DMA tag\n"); 1110 goto fail; 1111 } 1112 1113 paddr = ring->cmd_dma.paddr; 1114 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1115 struct iwm_tx_data *data = &ring->data[i]; 1116 1117 data->cmd_paddr = paddr; 1118 data->scratch_paddr = paddr + sizeof(struct iwm_cmd_header) 1119 + offsetof(struct iwm_tx_cmd, scratch); 1120 paddr += sizeof(struct iwm_device_cmd); 1121 1122 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1123 if (error != 0) { 1124 device_printf(sc->sc_dev, 1125 "could not create TX buf DMA map\n"); 1126 goto fail; 1127 } 1128 } 1129 KASSERT(paddr == ring->cmd_dma.paddr + size, 1130 ("invalid physical address")); 1131 return 0; 1132 1133 fail: iwm_free_tx_ring(sc, ring); 1134 return error; 1135 } 1136 1137 static void 1138 iwm_reset_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring) 1139 { 1140 int i; 1141 1142 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1143 struct iwm_tx_data *data = &ring->data[i]; 1144 1145 if (data->m != NULL) { 1146 bus_dmamap_sync(ring->data_dmat, data->map, 1147 BUS_DMASYNC_POSTWRITE); 1148 bus_dmamap_unload(ring->data_dmat, data->map); 1149 m_freem(data->m); 1150 data->m = NULL; 1151 } 1152 } 1153 /* Clear TX descriptors. */ 1154 memset(ring->desc, 0, ring->desc_dma.size); 1155 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1156 BUS_DMASYNC_PREWRITE); 1157 sc->qfullmsk &= ~(1 << ring->qid); 1158 ring->queued = 0; 1159 ring->cur = 0; 1160 } 1161 1162 static void 1163 iwm_free_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring) 1164 { 1165 int i; 1166 1167 iwm_dma_contig_free(&ring->desc_dma); 1168 iwm_dma_contig_free(&ring->cmd_dma); 1169 1170 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1171 struct iwm_tx_data *data = &ring->data[i]; 1172 1173 if (data->m != NULL) { 1174 bus_dmamap_sync(ring->data_dmat, data->map, 1175 BUS_DMASYNC_POSTWRITE); 1176 bus_dmamap_unload(ring->data_dmat, data->map); 1177 m_freem(data->m); 1178 data->m = NULL; 1179 } 1180 if (data->map != NULL) { 1181 bus_dmamap_destroy(ring->data_dmat, data->map); 1182 data->map = NULL; 1183 } 1184 } 1185 if (ring->data_dmat != NULL) { 1186 bus_dma_tag_destroy(ring->data_dmat); 1187 ring->data_dmat = NULL; 1188 } 1189 } 1190 1191 /* 1192 * High-level hardware frobbing routines 1193 */ 1194 1195 static void 1196 iwm_enable_interrupts(struct iwm_softc *sc) 1197 { 1198 sc->sc_intmask = IWM_CSR_INI_SET_MASK; 1199 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 1200 } 1201 1202 static void 1203 iwm_restore_interrupts(struct iwm_softc *sc) 1204 { 1205 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 1206 } 1207 1208 static void 1209 iwm_disable_interrupts(struct iwm_softc *sc) 1210 { 1211 /* disable interrupts */ 1212 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0); 1213 1214 /* acknowledge all interrupts */ 1215 IWM_WRITE(sc, IWM_CSR_INT, ~0); 1216 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, ~0); 1217 } 1218 1219 static void 1220 iwm_ict_reset(struct iwm_softc *sc) 1221 { 1222 iwm_disable_interrupts(sc); 1223 1224 /* Reset ICT table. */ 1225 memset(sc->ict_dma.vaddr, 0, IWM_ICT_SIZE); 1226 sc->ict_cur = 0; 1227 1228 /* Set physical address of ICT table (4KB aligned). */ 1229 IWM_WRITE(sc, IWM_CSR_DRAM_INT_TBL_REG, 1230 IWM_CSR_DRAM_INT_TBL_ENABLE 1231 | IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER 1232 | IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK 1233 | sc->ict_dma.paddr >> IWM_ICT_PADDR_SHIFT); 1234 1235 /* Switch to ICT interrupt mode in driver. */ 1236 sc->sc_flags |= IWM_FLAG_USE_ICT; 1237 1238 /* Re-enable interrupts. */ 1239 IWM_WRITE(sc, IWM_CSR_INT, ~0); 1240 iwm_enable_interrupts(sc); 1241 } 1242 1243 /* iwlwifi pcie/trans.c */ 1244 1245 /* 1246 * Since this .. hard-resets things, it's time to actually 1247 * mark the first vap (if any) as having no mac context. 1248 * It's annoying, but since the driver is potentially being 1249 * stop/start'ed whilst active (thanks openbsd port!) we 1250 * have to correctly track this. 1251 */ 1252 static void 1253 iwm_stop_device(struct iwm_softc *sc) 1254 { 1255 struct ieee80211com *ic = &sc->sc_ic; 1256 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1257 int chnl, qid; 1258 uint32_t mask = 0; 1259 1260 /* tell the device to stop sending interrupts */ 1261 iwm_disable_interrupts(sc); 1262 1263 /* 1264 * FreeBSD-local: mark the first vap as not-uploaded, 1265 * so the next transition through auth/assoc 1266 * will correctly populate the MAC context. 1267 */ 1268 if (vap) { 1269 struct iwm_vap *iv = IWM_VAP(vap); 1270 iv->is_uploaded = 0; 1271 } 1272 1273 /* device going down, Stop using ICT table */ 1274 sc->sc_flags &= ~IWM_FLAG_USE_ICT; 1275 1276 /* stop tx and rx. tx and rx bits, as usual, are from if_iwn */ 1277 1278 iwm_write_prph(sc, IWM_SCD_TXFACT, 0); 1279 1280 if (iwm_nic_lock(sc)) { 1281 /* Stop each Tx DMA channel */ 1282 for (chnl = 0; chnl < IWM_FH_TCSR_CHNL_NUM; chnl++) { 1283 IWM_WRITE(sc, 1284 IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl), 0); 1285 mask |= IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(chnl); 1286 } 1287 1288 /* Wait for DMA channels to be idle */ 1289 if (!iwm_poll_bit(sc, IWM_FH_TSSR_TX_STATUS_REG, mask, mask, 1290 5000)) { 1291 device_printf(sc->sc_dev, 1292 "Failing on timeout while stopping DMA channel: [0x%08x]\n", 1293 IWM_READ(sc, IWM_FH_TSSR_TX_STATUS_REG)); 1294 } 1295 iwm_nic_unlock(sc); 1296 } 1297 iwm_disable_rx_dma(sc); 1298 1299 /* Stop RX ring. */ 1300 iwm_reset_rx_ring(sc, &sc->rxq); 1301 1302 /* Reset all TX rings. */ 1303 for (qid = 0; qid < nitems(sc->txq); qid++) 1304 iwm_reset_tx_ring(sc, &sc->txq[qid]); 1305 1306 /* 1307 * Power-down device's busmaster DMA clocks 1308 */ 1309 iwm_write_prph(sc, IWM_APMG_CLK_DIS_REG, IWM_APMG_CLK_VAL_DMA_CLK_RQT); 1310 DELAY(5); 1311 1312 /* Make sure (redundant) we've released our request to stay awake */ 1313 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 1314 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1315 1316 /* Stop the device, and put it in low power state */ 1317 iwm_apm_stop(sc); 1318 1319 /* Upon stop, the APM issues an interrupt if HW RF kill is set. 1320 * Clean again the interrupt here 1321 */ 1322 iwm_disable_interrupts(sc); 1323 /* stop and reset the on-board processor */ 1324 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET); 1325 1326 /* 1327 * Even if we stop the HW, we still want the RF kill 1328 * interrupt 1329 */ 1330 iwm_enable_rfkill_int(sc); 1331 iwm_check_rfkill(sc); 1332 } 1333 1334 /* iwlwifi: mvm/ops.c */ 1335 static void 1336 iwm_mvm_nic_config(struct iwm_softc *sc) 1337 { 1338 uint8_t radio_cfg_type, radio_cfg_step, radio_cfg_dash; 1339 uint32_t reg_val = 0; 1340 1341 radio_cfg_type = (sc->sc_fw_phy_config & IWM_FW_PHY_CFG_RADIO_TYPE) >> 1342 IWM_FW_PHY_CFG_RADIO_TYPE_POS; 1343 radio_cfg_step = (sc->sc_fw_phy_config & IWM_FW_PHY_CFG_RADIO_STEP) >> 1344 IWM_FW_PHY_CFG_RADIO_STEP_POS; 1345 radio_cfg_dash = (sc->sc_fw_phy_config & IWM_FW_PHY_CFG_RADIO_DASH) >> 1346 IWM_FW_PHY_CFG_RADIO_DASH_POS; 1347 1348 /* SKU control */ 1349 reg_val |= IWM_CSR_HW_REV_STEP(sc->sc_hw_rev) << 1350 IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP; 1351 reg_val |= IWM_CSR_HW_REV_DASH(sc->sc_hw_rev) << 1352 IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH; 1353 1354 /* radio configuration */ 1355 reg_val |= radio_cfg_type << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE; 1356 reg_val |= radio_cfg_step << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP; 1357 reg_val |= radio_cfg_dash << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH; 1358 1359 IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, reg_val); 1360 1361 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1362 "Radio type=0x%x-0x%x-0x%x\n", radio_cfg_type, 1363 radio_cfg_step, radio_cfg_dash); 1364 1365 /* 1366 * W/A : NIC is stuck in a reset state after Early PCIe power off 1367 * (PCIe power is lost before PERST# is asserted), causing ME FW 1368 * to lose ownership and not being able to obtain it back. 1369 */ 1370 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) { 1371 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 1372 IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 1373 ~IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 1374 } 1375 } 1376 1377 static int 1378 iwm_nic_rx_init(struct iwm_softc *sc) 1379 { 1380 if (!iwm_nic_lock(sc)) 1381 return EBUSY; 1382 1383 /* 1384 * Initialize RX ring. This is from the iwn driver. 1385 */ 1386 memset(sc->rxq.stat, 0, sizeof(*sc->rxq.stat)); 1387 1388 /* stop DMA */ 1389 iwm_disable_rx_dma(sc); 1390 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 1391 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 1392 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RDPTR, 0); 1393 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 1394 1395 /* Set physical address of RX ring (256-byte aligned). */ 1396 IWM_WRITE(sc, 1397 IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG, sc->rxq.desc_dma.paddr >> 8); 1398 1399 /* Set physical address of RX status (16-byte aligned). */ 1400 IWM_WRITE(sc, 1401 IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG, sc->rxq.stat_dma.paddr >> 4); 1402 1403 /* Enable RX. */ 1404 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 1405 IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 1406 IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | /* HW bug */ 1407 IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 1408 IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | 1409 (IWM_RX_RB_TIMEOUT << IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 1410 IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K | 1411 IWM_RX_QUEUE_SIZE_LOG << IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS); 1412 1413 IWM_WRITE_1(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_TIMEOUT_DEF); 1414 1415 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 1416 if (sc->host_interrupt_operation_mode) 1417 IWM_SETBITS(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_OPER_MODE); 1418 1419 /* 1420 * Thus sayeth el jefe (iwlwifi) via a comment: 1421 * 1422 * This value should initially be 0 (before preparing any 1423 * RBs), should be 8 after preparing the first 8 RBs (for example) 1424 */ 1425 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, 8); 1426 1427 iwm_nic_unlock(sc); 1428 1429 return 0; 1430 } 1431 1432 static int 1433 iwm_nic_tx_init(struct iwm_softc *sc) 1434 { 1435 int qid; 1436 1437 if (!iwm_nic_lock(sc)) 1438 return EBUSY; 1439 1440 /* Deactivate TX scheduler. */ 1441 iwm_write_prph(sc, IWM_SCD_TXFACT, 0); 1442 1443 /* Set physical address of "keep warm" page (16-byte aligned). */ 1444 IWM_WRITE(sc, IWM_FH_KW_MEM_ADDR_REG, sc->kw_dma.paddr >> 4); 1445 1446 /* Initialize TX rings. */ 1447 for (qid = 0; qid < nitems(sc->txq); qid++) { 1448 struct iwm_tx_ring *txq = &sc->txq[qid]; 1449 1450 /* Set physical address of TX ring (256-byte aligned). */ 1451 IWM_WRITE(sc, IWM_FH_MEM_CBBC_QUEUE(qid), 1452 txq->desc_dma.paddr >> 8); 1453 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 1454 "%s: loading ring %d descriptors (%p) at %lx\n", 1455 __func__, 1456 qid, txq->desc, 1457 (unsigned long) (txq->desc_dma.paddr >> 8)); 1458 } 1459 1460 iwm_write_prph(sc, IWM_SCD_GP_CTRL, IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1461 1462 iwm_nic_unlock(sc); 1463 1464 return 0; 1465 } 1466 1467 static int 1468 iwm_nic_init(struct iwm_softc *sc) 1469 { 1470 int error; 1471 1472 iwm_apm_init(sc); 1473 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) 1474 iwm_set_pwr(sc); 1475 1476 iwm_mvm_nic_config(sc); 1477 1478 if ((error = iwm_nic_rx_init(sc)) != 0) 1479 return error; 1480 1481 /* 1482 * Ditto for TX, from iwn 1483 */ 1484 if ((error = iwm_nic_tx_init(sc)) != 0) 1485 return error; 1486 1487 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1488 "%s: shadow registers enabled\n", __func__); 1489 IWM_SETBITS(sc, IWM_CSR_MAC_SHADOW_REG_CTRL, 0x800fffff); 1490 1491 return 0; 1492 } 1493 1494 const uint8_t iwm_mvm_ac_to_tx_fifo[] = { 1495 IWM_MVM_TX_FIFO_VO, 1496 IWM_MVM_TX_FIFO_VI, 1497 IWM_MVM_TX_FIFO_BE, 1498 IWM_MVM_TX_FIFO_BK, 1499 }; 1500 1501 static int 1502 iwm_enable_txq(struct iwm_softc *sc, int sta_id, int qid, int fifo) 1503 { 1504 if (!iwm_nic_lock(sc)) { 1505 device_printf(sc->sc_dev, 1506 "%s: cannot enable txq %d\n", 1507 __func__, 1508 qid); 1509 return EBUSY; 1510 } 1511 1512 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | 0); 1513 1514 if (qid == IWM_MVM_CMD_QUEUE) { 1515 /* unactivate before configuration */ 1516 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1517 (0 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) 1518 | (1 << IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 1519 1520 iwm_clear_bits_prph(sc, IWM_SCD_AGGR_SEL, (1 << qid)); 1521 1522 iwm_write_prph(sc, IWM_SCD_QUEUE_RDPTR(qid), 0); 1523 1524 iwm_write_mem32(sc, sc->sched_base + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid), 0); 1525 /* Set scheduler window size and frame limit. */ 1526 iwm_write_mem32(sc, 1527 sc->sched_base + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid) + 1528 sizeof(uint32_t), 1529 ((IWM_FRAME_LIMIT << IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1530 IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1531 ((IWM_FRAME_LIMIT << IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1532 IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1533 1534 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1535 (1 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1536 (fifo << IWM_SCD_QUEUE_STTS_REG_POS_TXF) | 1537 (1 << IWM_SCD_QUEUE_STTS_REG_POS_WSL) | 1538 IWM_SCD_QUEUE_STTS_REG_MSK); 1539 } else { 1540 struct iwm_scd_txq_cfg_cmd cmd; 1541 int error; 1542 1543 iwm_nic_unlock(sc); 1544 1545 memset(&cmd, 0, sizeof(cmd)); 1546 cmd.scd_queue = qid; 1547 cmd.enable = 1; 1548 cmd.sta_id = sta_id; 1549 cmd.tx_fifo = fifo; 1550 cmd.aggregate = 0; 1551 cmd.window = IWM_FRAME_LIMIT; 1552 1553 error = iwm_mvm_send_cmd_pdu(sc, IWM_SCD_QUEUE_CFG, IWM_CMD_SYNC, 1554 sizeof(cmd), &cmd); 1555 if (error) { 1556 device_printf(sc->sc_dev, 1557 "cannot enable txq %d\n", qid); 1558 return error; 1559 } 1560 1561 if (!iwm_nic_lock(sc)) 1562 return EBUSY; 1563 } 1564 1565 iwm_write_prph(sc, IWM_SCD_EN_CTRL, 1566 iwm_read_prph(sc, IWM_SCD_EN_CTRL) | qid); 1567 1568 iwm_nic_unlock(sc); 1569 1570 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, "%s: enabled txq %d FIFO %d\n", 1571 __func__, qid, fifo); 1572 1573 return 0; 1574 } 1575 1576 static int 1577 iwm_post_alive(struct iwm_softc *sc) 1578 { 1579 int nwords; 1580 int error, chnl; 1581 uint32_t base; 1582 1583 if (!iwm_nic_lock(sc)) 1584 return EBUSY; 1585 1586 base = iwm_read_prph(sc, IWM_SCD_SRAM_BASE_ADDR); 1587 if (sc->sched_base != base) { 1588 device_printf(sc->sc_dev, 1589 "%s: sched addr mismatch: alive: 0x%x prph: 0x%x\n", 1590 __func__, sc->sched_base, base); 1591 } 1592 1593 iwm_ict_reset(sc); 1594 1595 /* Clear TX scheduler state in SRAM. */ 1596 nwords = (IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND - 1597 IWM_SCD_CONTEXT_MEM_LOWER_BOUND) 1598 / sizeof(uint32_t); 1599 error = iwm_write_mem(sc, 1600 sc->sched_base + IWM_SCD_CONTEXT_MEM_LOWER_BOUND, 1601 NULL, nwords); 1602 if (error) 1603 goto out; 1604 1605 /* Set physical address of TX scheduler rings (1KB aligned). */ 1606 iwm_write_prph(sc, IWM_SCD_DRAM_BASE_ADDR, sc->sched_dma.paddr >> 10); 1607 1608 iwm_write_prph(sc, IWM_SCD_CHAINEXT_EN, 0); 1609 1610 iwm_nic_unlock(sc); 1611 1612 /* enable command channel */ 1613 error = iwm_enable_txq(sc, 0 /* unused */, IWM_MVM_CMD_QUEUE, 7); 1614 if (error) 1615 return error; 1616 1617 if (!iwm_nic_lock(sc)) 1618 return EBUSY; 1619 1620 iwm_write_prph(sc, IWM_SCD_TXFACT, 0xff); 1621 1622 /* Enable DMA channels. */ 1623 for (chnl = 0; chnl < IWM_FH_TCSR_CHNL_NUM; chnl++) { 1624 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl), 1625 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1626 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 1627 } 1628 1629 IWM_SETBITS(sc, IWM_FH_TX_CHICKEN_BITS_REG, 1630 IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 1631 1632 /* Enable L1-Active */ 1633 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) { 1634 iwm_clear_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 1635 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 1636 } 1637 1638 out: 1639 iwm_nic_unlock(sc); 1640 return error; 1641 } 1642 1643 /* 1644 * NVM read access and content parsing. We do not support 1645 * external NVM or writing NVM. 1646 * iwlwifi/mvm/nvm.c 1647 */ 1648 1649 /* list of NVM sections we are allowed/need to read */ 1650 const int nvm_to_read[] = { 1651 IWM_NVM_SECTION_TYPE_HW, 1652 IWM_NVM_SECTION_TYPE_SW, 1653 IWM_NVM_SECTION_TYPE_REGULATORY, 1654 IWM_NVM_SECTION_TYPE_CALIBRATION, 1655 IWM_NVM_SECTION_TYPE_PRODUCTION, 1656 IWM_NVM_SECTION_TYPE_HW_8000, 1657 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE, 1658 IWM_NVM_SECTION_TYPE_PHY_SKU, 1659 }; 1660 1661 /* Default NVM size to read */ 1662 #define IWM_NVM_DEFAULT_CHUNK_SIZE (2*1024) 1663 #define IWM_MAX_NVM_SECTION_SIZE 8192 1664 1665 #define IWM_NVM_WRITE_OPCODE 1 1666 #define IWM_NVM_READ_OPCODE 0 1667 1668 /* load nvm chunk response */ 1669 #define IWM_READ_NVM_CHUNK_SUCCEED 0 1670 #define IWM_READ_NVM_CHUNK_INVALID_ADDRESS 1 1671 1672 static int 1673 iwm_nvm_read_chunk(struct iwm_softc *sc, uint16_t section, 1674 uint16_t offset, uint16_t length, uint8_t *data, uint16_t *len) 1675 { 1676 offset = 0; 1677 struct iwm_nvm_access_cmd nvm_access_cmd = { 1678 .offset = htole16(offset), 1679 .length = htole16(length), 1680 .type = htole16(section), 1681 .op_code = IWM_NVM_READ_OPCODE, 1682 }; 1683 struct iwm_nvm_access_resp *nvm_resp; 1684 struct iwm_rx_packet *pkt; 1685 struct iwm_host_cmd cmd = { 1686 .id = IWM_NVM_ACCESS_CMD, 1687 .flags = IWM_CMD_SYNC | IWM_CMD_WANT_SKB | 1688 IWM_CMD_SEND_IN_RFKILL, 1689 .data = { &nvm_access_cmd, }, 1690 }; 1691 int ret, offset_read; 1692 size_t bytes_read; 1693 uint8_t *resp_data; 1694 1695 cmd.len[0] = sizeof(struct iwm_nvm_access_cmd); 1696 1697 ret = iwm_send_cmd(sc, &cmd); 1698 if (ret) { 1699 device_printf(sc->sc_dev, 1700 "Could not send NVM_ACCESS command (error=%d)\n", ret); 1701 return ret; 1702 } 1703 1704 pkt = cmd.resp_pkt; 1705 if (pkt->hdr.flags & IWM_CMD_FAILED_MSK) { 1706 device_printf(sc->sc_dev, 1707 "Bad return from IWM_NVM_ACCES_COMMAND (0x%08X)\n", 1708 pkt->hdr.flags); 1709 ret = EIO; 1710 goto exit; 1711 } 1712 1713 /* Extract NVM response */ 1714 nvm_resp = (void *)pkt->data; 1715 1716 ret = le16toh(nvm_resp->status); 1717 bytes_read = le16toh(nvm_resp->length); 1718 offset_read = le16toh(nvm_resp->offset); 1719 resp_data = nvm_resp->data; 1720 if (ret) { 1721 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1722 "NVM access command failed with status %d\n", ret); 1723 ret = EINVAL; 1724 goto exit; 1725 } 1726 1727 if (offset_read != offset) { 1728 device_printf(sc->sc_dev, 1729 "NVM ACCESS response with invalid offset %d\n", 1730 offset_read); 1731 ret = EINVAL; 1732 goto exit; 1733 } 1734 1735 if (bytes_read > length) { 1736 device_printf(sc->sc_dev, 1737 "NVM ACCESS response with too much data " 1738 "(%d bytes requested, %zd bytes received)\n", 1739 length, bytes_read); 1740 ret = EINVAL; 1741 goto exit; 1742 } 1743 1744 memcpy(data + offset, resp_data, bytes_read); 1745 *len = bytes_read; 1746 1747 exit: 1748 iwm_free_resp(sc, &cmd); 1749 return ret; 1750 } 1751 1752 /* 1753 * Reads an NVM section completely. 1754 * NICs prior to 7000 family don't have a real NVM, but just read 1755 * section 0 which is the EEPROM. Because the EEPROM reading is unlimited 1756 * by uCode, we need to manually check in this case that we don't 1757 * overflow and try to read more than the EEPROM size. 1758 * For 7000 family NICs, we supply the maximal size we can read, and 1759 * the uCode fills the response with as much data as we can, 1760 * without overflowing, so no check is needed. 1761 */ 1762 static int 1763 iwm_nvm_read_section(struct iwm_softc *sc, 1764 uint16_t section, uint8_t *data, uint16_t *len, size_t max_len) 1765 { 1766 uint16_t chunklen, seglen; 1767 int error = 0; 1768 1769 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1770 "reading NVM section %d\n", section); 1771 1772 chunklen = seglen = IWM_NVM_DEFAULT_CHUNK_SIZE; 1773 *len = 0; 1774 1775 /* Read NVM chunks until exhausted (reading less than requested) */ 1776 while (seglen == chunklen && *len < max_len) { 1777 error = iwm_nvm_read_chunk(sc, 1778 section, *len, chunklen, data, &seglen); 1779 if (error) { 1780 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1781 "Cannot read from NVM section " 1782 "%d at offset %d\n", section, *len); 1783 return error; 1784 } 1785 *len += seglen; 1786 } 1787 1788 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1789 "NVM section %d read completed (%d bytes, error=%d)\n", 1790 section, *len, error); 1791 return error; 1792 } 1793 1794 /* 1795 * BEGIN IWM_NVM_PARSE 1796 */ 1797 1798 /* iwlwifi/iwl-nvm-parse.c */ 1799 1800 /* NVM offsets (in words) definitions */ 1801 enum iwm_nvm_offsets { 1802 /* NVM HW-Section offset (in words) definitions */ 1803 IWM_HW_ADDR = 0x15, 1804 1805 /* NVM SW-Section offset (in words) definitions */ 1806 IWM_NVM_SW_SECTION = 0x1C0, 1807 IWM_NVM_VERSION = 0, 1808 IWM_RADIO_CFG = 1, 1809 IWM_SKU = 2, 1810 IWM_N_HW_ADDRS = 3, 1811 IWM_NVM_CHANNELS = 0x1E0 - IWM_NVM_SW_SECTION, 1812 1813 /* NVM calibration section offset (in words) definitions */ 1814 IWM_NVM_CALIB_SECTION = 0x2B8, 1815 IWM_XTAL_CALIB = 0x316 - IWM_NVM_CALIB_SECTION 1816 }; 1817 1818 enum iwm_8000_nvm_offsets { 1819 /* NVM HW-Section offset (in words) definitions */ 1820 IWM_HW_ADDR0_WFPM_8000 = 0x12, 1821 IWM_HW_ADDR1_WFPM_8000 = 0x16, 1822 IWM_HW_ADDR0_PCIE_8000 = 0x8A, 1823 IWM_HW_ADDR1_PCIE_8000 = 0x8E, 1824 IWM_MAC_ADDRESS_OVERRIDE_8000 = 1, 1825 1826 /* NVM SW-Section offset (in words) definitions */ 1827 IWM_NVM_SW_SECTION_8000 = 0x1C0, 1828 IWM_NVM_VERSION_8000 = 0, 1829 IWM_RADIO_CFG_8000 = 0, 1830 IWM_SKU_8000 = 2, 1831 IWM_N_HW_ADDRS_8000 = 3, 1832 1833 /* NVM REGULATORY -Section offset (in words) definitions */ 1834 IWM_NVM_CHANNELS_8000 = 0, 1835 IWM_NVM_LAR_OFFSET_8000_OLD = 0x4C7, 1836 IWM_NVM_LAR_OFFSET_8000 = 0x507, 1837 IWM_NVM_LAR_ENABLED_8000 = 0x7, 1838 1839 /* NVM calibration section offset (in words) definitions */ 1840 IWM_NVM_CALIB_SECTION_8000 = 0x2B8, 1841 IWM_XTAL_CALIB_8000 = 0x316 - IWM_NVM_CALIB_SECTION_8000 1842 }; 1843 1844 /* SKU Capabilities (actual values from NVM definition) */ 1845 enum nvm_sku_bits { 1846 IWM_NVM_SKU_CAP_BAND_24GHZ = (1 << 0), 1847 IWM_NVM_SKU_CAP_BAND_52GHZ = (1 << 1), 1848 IWM_NVM_SKU_CAP_11N_ENABLE = (1 << 2), 1849 IWM_NVM_SKU_CAP_11AC_ENABLE = (1 << 3), 1850 }; 1851 1852 /* radio config bits (actual values from NVM definition) */ 1853 #define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */ 1854 #define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 1855 #define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 1856 #define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 1857 #define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 1858 #define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 1859 1860 #define IWM_NVM_RF_CFG_FLAVOR_MSK_8000(x) (x & 0xF) 1861 #define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF) 1862 #define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF) 1863 #define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF) 1864 #define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF) 1865 #define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF) 1866 1867 #define DEFAULT_MAX_TX_POWER 16 1868 1869 /** 1870 * enum iwm_nvm_channel_flags - channel flags in NVM 1871 * @IWM_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 1872 * @IWM_NVM_CHANNEL_IBSS: usable as an IBSS channel 1873 * @IWM_NVM_CHANNEL_ACTIVE: active scanning allowed 1874 * @IWM_NVM_CHANNEL_RADAR: radar detection required 1875 * XXX cannot find this (DFS) flag in iwl-nvm-parse.c 1876 * @IWM_NVM_CHANNEL_DFS: dynamic freq selection candidate 1877 * @IWM_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 1878 * @IWM_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 1879 * @IWM_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 1880 * @IWM_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 1881 */ 1882 enum iwm_nvm_channel_flags { 1883 IWM_NVM_CHANNEL_VALID = (1 << 0), 1884 IWM_NVM_CHANNEL_IBSS = (1 << 1), 1885 IWM_NVM_CHANNEL_ACTIVE = (1 << 3), 1886 IWM_NVM_CHANNEL_RADAR = (1 << 4), 1887 IWM_NVM_CHANNEL_DFS = (1 << 7), 1888 IWM_NVM_CHANNEL_WIDE = (1 << 8), 1889 IWM_NVM_CHANNEL_40MHZ = (1 << 9), 1890 IWM_NVM_CHANNEL_80MHZ = (1 << 10), 1891 IWM_NVM_CHANNEL_160MHZ = (1 << 11), 1892 }; 1893 1894 /* 1895 * Translate EEPROM flags to net80211. 1896 */ 1897 static uint32_t 1898 iwm_eeprom_channel_flags(uint16_t ch_flags) 1899 { 1900 uint32_t nflags; 1901 1902 nflags = 0; 1903 if ((ch_flags & IWM_NVM_CHANNEL_ACTIVE) == 0) 1904 nflags |= IEEE80211_CHAN_PASSIVE; 1905 if ((ch_flags & IWM_NVM_CHANNEL_IBSS) == 0) 1906 nflags |= IEEE80211_CHAN_NOADHOC; 1907 if (ch_flags & IWM_NVM_CHANNEL_RADAR) { 1908 nflags |= IEEE80211_CHAN_DFS; 1909 /* Just in case. */ 1910 nflags |= IEEE80211_CHAN_NOADHOC; 1911 } 1912 1913 return (nflags); 1914 } 1915 1916 static void 1917 iwm_add_channel_band(struct iwm_softc *sc, struct ieee80211_channel chans[], 1918 int maxchans, int *nchans, int ch_idx, size_t ch_num, 1919 const uint8_t bands[]) 1920 { 1921 const uint16_t * const nvm_ch_flags = sc->sc_nvm.nvm_ch_flags; 1922 uint32_t nflags; 1923 uint16_t ch_flags; 1924 uint8_t ieee; 1925 int error; 1926 1927 for (; ch_idx < ch_num; ch_idx++) { 1928 ch_flags = le16_to_cpup(nvm_ch_flags + ch_idx); 1929 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) 1930 ieee = iwm_nvm_channels[ch_idx]; 1931 else 1932 ieee = iwm_nvm_channels_8000[ch_idx]; 1933 1934 if (!(ch_flags & IWM_NVM_CHANNEL_VALID)) { 1935 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM, 1936 "Ch. %d Flags %x [%sGHz] - No traffic\n", 1937 ieee, ch_flags, 1938 (ch_idx >= IWM_NUM_2GHZ_CHANNELS) ? 1939 "5.2" : "2.4"); 1940 continue; 1941 } 1942 1943 nflags = iwm_eeprom_channel_flags(ch_flags); 1944 error = ieee80211_add_channel(chans, maxchans, nchans, 1945 ieee, 0, 0, nflags, bands); 1946 if (error != 0) 1947 break; 1948 1949 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM, 1950 "Ch. %d Flags %x [%sGHz] - Added\n", 1951 ieee, ch_flags, 1952 (ch_idx >= IWM_NUM_2GHZ_CHANNELS) ? 1953 "5.2" : "2.4"); 1954 } 1955 } 1956 1957 static void 1958 iwm_init_channel_map(struct ieee80211com *ic, int maxchans, int *nchans, 1959 struct ieee80211_channel chans[]) 1960 { 1961 struct iwm_softc *sc = ic->ic_softc; 1962 struct iwm_nvm_data *data = &sc->sc_nvm; 1963 uint8_t bands[IEEE80211_MODE_BYTES]; 1964 size_t ch_num; 1965 1966 memset(bands, 0, sizeof(bands)); 1967 /* 1-13: 11b/g channels. */ 1968 setbit(bands, IEEE80211_MODE_11B); 1969 setbit(bands, IEEE80211_MODE_11G); 1970 iwm_add_channel_band(sc, chans, maxchans, nchans, 0, 1971 IWM_NUM_2GHZ_CHANNELS - 1, bands); 1972 1973 /* 14: 11b channel only. */ 1974 clrbit(bands, IEEE80211_MODE_11G); 1975 iwm_add_channel_band(sc, chans, maxchans, nchans, 1976 IWM_NUM_2GHZ_CHANNELS - 1, IWM_NUM_2GHZ_CHANNELS, bands); 1977 1978 if (data->sku_cap_band_52GHz_enable) { 1979 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) 1980 ch_num = nitems(iwm_nvm_channels); 1981 else 1982 ch_num = nitems(iwm_nvm_channels_8000); 1983 memset(bands, 0, sizeof(bands)); 1984 setbit(bands, IEEE80211_MODE_11A); 1985 iwm_add_channel_band(sc, chans, maxchans, nchans, 1986 IWM_NUM_2GHZ_CHANNELS, ch_num, bands); 1987 } 1988 } 1989 1990 static void 1991 iwm_set_hw_address_8000(struct iwm_softc *sc, struct iwm_nvm_data *data, 1992 const uint16_t *mac_override, const uint16_t *nvm_hw) 1993 { 1994 const uint8_t *hw_addr; 1995 1996 if (mac_override) { 1997 static const uint8_t reserved_mac[] = { 1998 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 1999 }; 2000 2001 hw_addr = (const uint8_t *)(mac_override + 2002 IWM_MAC_ADDRESS_OVERRIDE_8000); 2003 2004 /* 2005 * Store the MAC address from MAO section. 2006 * No byte swapping is required in MAO section 2007 */ 2008 IEEE80211_ADDR_COPY(data->hw_addr, hw_addr); 2009 2010 /* 2011 * Force the use of the OTP MAC address in case of reserved MAC 2012 * address in the NVM, or if address is given but invalid. 2013 */ 2014 if (!IEEE80211_ADDR_EQ(reserved_mac, hw_addr) && 2015 !IEEE80211_ADDR_EQ(ieee80211broadcastaddr, data->hw_addr) && 2016 iwm_is_valid_ether_addr(data->hw_addr) && 2017 !IEEE80211_IS_MULTICAST(data->hw_addr)) 2018 return; 2019 2020 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2021 "%s: mac address from nvm override section invalid\n", 2022 __func__); 2023 } 2024 2025 if (nvm_hw) { 2026 /* read the mac address from WFMP registers */ 2027 uint32_t mac_addr0 = 2028 htole32(iwm_read_prph(sc, IWM_WFMP_MAC_ADDR_0)); 2029 uint32_t mac_addr1 = 2030 htole32(iwm_read_prph(sc, IWM_WFMP_MAC_ADDR_1)); 2031 2032 hw_addr = (const uint8_t *)&mac_addr0; 2033 data->hw_addr[0] = hw_addr[3]; 2034 data->hw_addr[1] = hw_addr[2]; 2035 data->hw_addr[2] = hw_addr[1]; 2036 data->hw_addr[3] = hw_addr[0]; 2037 2038 hw_addr = (const uint8_t *)&mac_addr1; 2039 data->hw_addr[4] = hw_addr[1]; 2040 data->hw_addr[5] = hw_addr[0]; 2041 2042 return; 2043 } 2044 2045 device_printf(sc->sc_dev, "%s: mac address not found\n", __func__); 2046 memset(data->hw_addr, 0, sizeof(data->hw_addr)); 2047 } 2048 2049 static int 2050 iwm_get_sku(const struct iwm_softc *sc, const uint16_t *nvm_sw, 2051 const uint16_t *phy_sku) 2052 { 2053 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) 2054 return le16_to_cpup(nvm_sw + IWM_SKU); 2055 2056 return le32_to_cpup((const uint32_t *)(phy_sku + IWM_SKU_8000)); 2057 } 2058 2059 static int 2060 iwm_get_nvm_version(const struct iwm_softc *sc, const uint16_t *nvm_sw) 2061 { 2062 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) 2063 return le16_to_cpup(nvm_sw + IWM_NVM_VERSION); 2064 else 2065 return le32_to_cpup((const uint32_t *)(nvm_sw + 2066 IWM_NVM_VERSION_8000)); 2067 } 2068 2069 static int 2070 iwm_get_radio_cfg(const struct iwm_softc *sc, const uint16_t *nvm_sw, 2071 const uint16_t *phy_sku) 2072 { 2073 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) 2074 return le16_to_cpup(nvm_sw + IWM_RADIO_CFG); 2075 2076 return le32_to_cpup((const uint32_t *)(phy_sku + IWM_RADIO_CFG_8000)); 2077 } 2078 2079 static int 2080 iwm_get_n_hw_addrs(const struct iwm_softc *sc, const uint16_t *nvm_sw) 2081 { 2082 int n_hw_addr; 2083 2084 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) 2085 return le16_to_cpup(nvm_sw + IWM_N_HW_ADDRS); 2086 2087 n_hw_addr = le32_to_cpup((const uint32_t *)(nvm_sw + IWM_N_HW_ADDRS_8000)); 2088 2089 return n_hw_addr & IWM_N_HW_ADDR_MASK; 2090 } 2091 2092 static void 2093 iwm_set_radio_cfg(const struct iwm_softc *sc, struct iwm_nvm_data *data, 2094 uint32_t radio_cfg) 2095 { 2096 if (sc->sc_device_family != IWM_DEVICE_FAMILY_8000) { 2097 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK(radio_cfg); 2098 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK(radio_cfg); 2099 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK(radio_cfg); 2100 data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK(radio_cfg); 2101 return; 2102 } 2103 2104 /* set the radio configuration for family 8000 */ 2105 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK_8000(radio_cfg); 2106 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK_8000(radio_cfg); 2107 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK_8000(radio_cfg); 2108 data->radio_cfg_pnum = IWM_NVM_RF_CFG_FLAVOR_MSK_8000(radio_cfg); 2109 data->valid_tx_ant = IWM_NVM_RF_CFG_TX_ANT_MSK_8000(radio_cfg); 2110 data->valid_rx_ant = IWM_NVM_RF_CFG_RX_ANT_MSK_8000(radio_cfg); 2111 } 2112 2113 static int 2114 iwm_parse_nvm_data(struct iwm_softc *sc, 2115 const uint16_t *nvm_hw, const uint16_t *nvm_sw, 2116 const uint16_t *nvm_calib, const uint16_t *mac_override, 2117 const uint16_t *phy_sku, const uint16_t *regulatory) 2118 { 2119 struct iwm_nvm_data *data = &sc->sc_nvm; 2120 uint8_t hw_addr[IEEE80211_ADDR_LEN]; 2121 uint32_t sku, radio_cfg; 2122 2123 data->nvm_version = iwm_get_nvm_version(sc, nvm_sw); 2124 2125 radio_cfg = iwm_get_radio_cfg(sc, nvm_sw, phy_sku); 2126 iwm_set_radio_cfg(sc, data, radio_cfg); 2127 2128 sku = iwm_get_sku(sc, nvm_sw, phy_sku); 2129 data->sku_cap_band_24GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_24GHZ; 2130 data->sku_cap_band_52GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_52GHZ; 2131 data->sku_cap_11n_enable = 0; 2132 2133 data->n_hw_addrs = iwm_get_n_hw_addrs(sc, nvm_sw); 2134 2135 /* The byte order is little endian 16 bit, meaning 214365 */ 2136 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) { 2137 IEEE80211_ADDR_COPY(hw_addr, nvm_hw + IWM_HW_ADDR); 2138 data->hw_addr[0] = hw_addr[1]; 2139 data->hw_addr[1] = hw_addr[0]; 2140 data->hw_addr[2] = hw_addr[3]; 2141 data->hw_addr[3] = hw_addr[2]; 2142 data->hw_addr[4] = hw_addr[5]; 2143 data->hw_addr[5] = hw_addr[4]; 2144 } else { 2145 iwm_set_hw_address_8000(sc, data, mac_override, nvm_hw); 2146 } 2147 2148 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) { 2149 memcpy(data->nvm_ch_flags, &nvm_sw[IWM_NVM_CHANNELS], 2150 IWM_NUM_CHANNELS * sizeof(uint16_t)); 2151 } else { 2152 memcpy(data->nvm_ch_flags, ®ulatory[IWM_NVM_CHANNELS_8000], 2153 IWM_NUM_CHANNELS_8000 * sizeof(uint16_t)); 2154 } 2155 2156 return 0; 2157 } 2158 2159 /* 2160 * END NVM PARSE 2161 */ 2162 2163 static int 2164 iwm_parse_nvm_sections(struct iwm_softc *sc, struct iwm_nvm_section *sections) 2165 { 2166 const uint16_t *hw, *sw, *calib, *regulatory, *mac_override, *phy_sku; 2167 2168 /* Checking for required sections */ 2169 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) { 2170 if (!sections[IWM_NVM_SECTION_TYPE_SW].data || 2171 !sections[IWM_NVM_SECTION_TYPE_HW].data) { 2172 device_printf(sc->sc_dev, 2173 "Can't parse empty OTP/NVM sections\n"); 2174 return ENOENT; 2175 } 2176 2177 hw = (const uint16_t *) sections[IWM_NVM_SECTION_TYPE_HW].data; 2178 } else if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) { 2179 /* SW and REGULATORY sections are mandatory */ 2180 if (!sections[IWM_NVM_SECTION_TYPE_SW].data || 2181 !sections[IWM_NVM_SECTION_TYPE_REGULATORY].data) { 2182 device_printf(sc->sc_dev, 2183 "Can't parse empty OTP/NVM sections\n"); 2184 return ENOENT; 2185 } 2186 /* MAC_OVERRIDE or at least HW section must exist */ 2187 if (!sections[IWM_NVM_SECTION_TYPE_HW_8000].data && 2188 !sections[IWM_NVM_SECTION_TYPE_MAC_OVERRIDE].data) { 2189 device_printf(sc->sc_dev, 2190 "Can't parse mac_address, empty sections\n"); 2191 return ENOENT; 2192 } 2193 2194 /* PHY_SKU section is mandatory in B0 */ 2195 if (!sections[IWM_NVM_SECTION_TYPE_PHY_SKU].data) { 2196 device_printf(sc->sc_dev, 2197 "Can't parse phy_sku in B0, empty sections\n"); 2198 return ENOENT; 2199 } 2200 2201 hw = (const uint16_t *) 2202 sections[IWM_NVM_SECTION_TYPE_HW_8000].data; 2203 } else { 2204 panic("unknown device family %d\n", sc->sc_device_family); 2205 } 2206 2207 sw = (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_SW].data; 2208 calib = (const uint16_t *) 2209 sections[IWM_NVM_SECTION_TYPE_CALIBRATION].data; 2210 regulatory = (const uint16_t *) 2211 sections[IWM_NVM_SECTION_TYPE_REGULATORY].data; 2212 mac_override = (const uint16_t *) 2213 sections[IWM_NVM_SECTION_TYPE_MAC_OVERRIDE].data; 2214 phy_sku = (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_PHY_SKU].data; 2215 2216 return iwm_parse_nvm_data(sc, hw, sw, calib, mac_override, 2217 phy_sku, regulatory); 2218 } 2219 2220 static int 2221 iwm_nvm_init(struct iwm_softc *sc) 2222 { 2223 struct iwm_nvm_section nvm_sections[IWM_NVM_NUM_OF_SECTIONS]; 2224 int i, section, error; 2225 uint16_t len; 2226 uint8_t *buf; 2227 const size_t bufsz = IWM_MAX_NVM_SECTION_SIZE; 2228 2229 memset(nvm_sections, 0 , sizeof(nvm_sections)); 2230 2231 buf = malloc(bufsz, M_DEVBUF, M_NOWAIT); 2232 if (buf == NULL) 2233 return ENOMEM; 2234 2235 for (i = 0; i < nitems(nvm_to_read); i++) { 2236 section = nvm_to_read[i]; 2237 KASSERT(section <= nitems(nvm_sections), 2238 ("too many sections")); 2239 2240 error = iwm_nvm_read_section(sc, section, buf, &len, bufsz); 2241 if (error) { 2242 error = 0; 2243 continue; 2244 } 2245 nvm_sections[section].data = malloc(len, M_DEVBUF, M_NOWAIT); 2246 if (nvm_sections[section].data == NULL) { 2247 error = ENOMEM; 2248 break; 2249 } 2250 memcpy(nvm_sections[section].data, buf, len); 2251 nvm_sections[section].length = len; 2252 } 2253 free(buf, M_DEVBUF); 2254 if (error == 0) 2255 error = iwm_parse_nvm_sections(sc, nvm_sections); 2256 2257 for (i = 0; i < IWM_NVM_NUM_OF_SECTIONS; i++) { 2258 if (nvm_sections[i].data != NULL) 2259 free(nvm_sections[i].data, M_DEVBUF); 2260 } 2261 2262 return error; 2263 } 2264 2265 /* 2266 * Firmware loading gunk. This is kind of a weird hybrid between the 2267 * iwn driver and the Linux iwlwifi driver. 2268 */ 2269 2270 static int 2271 iwm_firmware_load_sect(struct iwm_softc *sc, uint32_t dst_addr, 2272 const uint8_t *section, uint32_t byte_cnt) 2273 { 2274 int error = EINVAL; 2275 uint32_t chunk_sz, offset; 2276 2277 chunk_sz = MIN(IWM_FH_MEM_TB_MAX_LENGTH, byte_cnt); 2278 2279 for (offset = 0; offset < byte_cnt; offset += chunk_sz) { 2280 uint32_t addr, len; 2281 const uint8_t *data; 2282 2283 addr = dst_addr + offset; 2284 len = MIN(chunk_sz, byte_cnt - offset); 2285 data = section + offset; 2286 2287 error = iwm_firmware_load_chunk(sc, addr, data, len); 2288 if (error) 2289 break; 2290 } 2291 2292 return error; 2293 } 2294 2295 static int 2296 iwm_firmware_load_chunk(struct iwm_softc *sc, uint32_t dst_addr, 2297 const uint8_t *chunk, uint32_t byte_cnt) 2298 { 2299 struct iwm_dma_info *dma = &sc->fw_dma; 2300 int error; 2301 2302 /* Copy firmware chunk into pre-allocated DMA-safe memory. */ 2303 memcpy(dma->vaddr, chunk, byte_cnt); 2304 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 2305 2306 if (dst_addr >= IWM_FW_MEM_EXTENDED_START && 2307 dst_addr <= IWM_FW_MEM_EXTENDED_END) { 2308 iwm_set_bits_prph(sc, IWM_LMPM_CHICK, 2309 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE); 2310 } 2311 2312 sc->sc_fw_chunk_done = 0; 2313 2314 if (!iwm_nic_lock(sc)) 2315 return EBUSY; 2316 2317 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL), 2318 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 2319 IWM_WRITE(sc, IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(IWM_FH_SRVC_CHNL), 2320 dst_addr); 2321 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL0_REG(IWM_FH_SRVC_CHNL), 2322 dma->paddr & IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 2323 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL1_REG(IWM_FH_SRVC_CHNL), 2324 (iwm_get_dma_hi_addr(dma->paddr) 2325 << IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 2326 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(IWM_FH_SRVC_CHNL), 2327 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 2328 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 2329 IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 2330 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL), 2331 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 2332 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 2333 IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 2334 2335 iwm_nic_unlock(sc); 2336 2337 /* wait 1s for this segment to load */ 2338 while (!sc->sc_fw_chunk_done) 2339 if ((error = msleep(&sc->sc_fw, &sc->sc_mtx, 0, "iwmfw", hz)) != 0) 2340 break; 2341 2342 if (!sc->sc_fw_chunk_done) { 2343 device_printf(sc->sc_dev, 2344 "fw chunk addr 0x%x len %d failed to load\n", 2345 dst_addr, byte_cnt); 2346 } 2347 2348 if (dst_addr >= IWM_FW_MEM_EXTENDED_START && 2349 dst_addr <= IWM_FW_MEM_EXTENDED_END && iwm_nic_lock(sc)) { 2350 iwm_clear_bits_prph(sc, IWM_LMPM_CHICK, 2351 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE); 2352 iwm_nic_unlock(sc); 2353 } 2354 2355 return error; 2356 } 2357 2358 int 2359 iwm_load_cpu_sections_8000(struct iwm_softc *sc, struct iwm_fw_sects *fws, 2360 int cpu, int *first_ucode_section) 2361 { 2362 int shift_param; 2363 int i, error = 0, sec_num = 0x1; 2364 uint32_t val, last_read_idx = 0; 2365 const void *data; 2366 uint32_t dlen; 2367 uint32_t offset; 2368 2369 if (cpu == 1) { 2370 shift_param = 0; 2371 *first_ucode_section = 0; 2372 } else { 2373 shift_param = 16; 2374 (*first_ucode_section)++; 2375 } 2376 2377 for (i = *first_ucode_section; i < IWM_UCODE_SECT_MAX; i++) { 2378 last_read_idx = i; 2379 data = fws->fw_sect[i].fws_data; 2380 dlen = fws->fw_sect[i].fws_len; 2381 offset = fws->fw_sect[i].fws_devoff; 2382 2383 /* 2384 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 2385 * CPU1 to CPU2. 2386 * PAGING_SEPARATOR_SECTION delimiter - separate between 2387 * CPU2 non paged to CPU2 paging sec. 2388 */ 2389 if (!data || offset == IWM_CPU1_CPU2_SEPARATOR_SECTION || 2390 offset == IWM_PAGING_SEPARATOR_SECTION) 2391 break; 2392 2393 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2394 "LOAD FIRMWARE chunk %d offset 0x%x len %d for cpu %d\n", 2395 i, offset, dlen, cpu); 2396 2397 if (dlen > sc->sc_fwdmasegsz) { 2398 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2399 "chunk %d too large (%d bytes)\n", i, dlen); 2400 error = EFBIG; 2401 } else { 2402 error = iwm_firmware_load_sect(sc, offset, data, dlen); 2403 } 2404 if (error) { 2405 device_printf(sc->sc_dev, 2406 "could not load firmware chunk %d (error %d)\n", 2407 i, error); 2408 return error; 2409 } 2410 2411 /* Notify the ucode of the loaded section number and status */ 2412 if (iwm_nic_lock(sc)) { 2413 val = IWM_READ(sc, IWM_FH_UCODE_LOAD_STATUS); 2414 val = val | (sec_num << shift_param); 2415 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, val); 2416 sec_num = (sec_num << 1) | 0x1; 2417 iwm_nic_unlock(sc); 2418 2419 /* 2420 * The firmware won't load correctly without this delay. 2421 */ 2422 DELAY(8000); 2423 } 2424 } 2425 2426 *first_ucode_section = last_read_idx; 2427 2428 if (iwm_nic_lock(sc)) { 2429 if (cpu == 1) 2430 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFF); 2431 else 2432 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); 2433 iwm_nic_unlock(sc); 2434 } 2435 2436 return 0; 2437 } 2438 2439 int 2440 iwm_load_firmware_8000(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 2441 { 2442 struct iwm_fw_sects *fws; 2443 int error = 0; 2444 int first_ucode_section; 2445 2446 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "loading ucode type %d\n", 2447 ucode_type); 2448 2449 fws = &sc->sc_fw.fw_sects[ucode_type]; 2450 2451 /* configure the ucode to be ready to get the secured image */ 2452 /* release CPU reset */ 2453 iwm_write_prph(sc, IWM_RELEASE_CPU_RESET, IWM_RELEASE_CPU_RESET_BIT); 2454 2455 /* load to FW the binary Secured sections of CPU1 */ 2456 error = iwm_load_cpu_sections_8000(sc, fws, 1, &first_ucode_section); 2457 if (error) 2458 return error; 2459 2460 /* load to FW the binary sections of CPU2 */ 2461 return iwm_load_cpu_sections_8000(sc, fws, 2, &first_ucode_section); 2462 } 2463 2464 static int 2465 iwm_load_firmware_7000(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 2466 { 2467 struct iwm_fw_sects *fws; 2468 int error, i; 2469 const void *data; 2470 uint32_t dlen; 2471 uint32_t offset; 2472 2473 sc->sc_uc.uc_intr = 0; 2474 2475 fws = &sc->sc_fw.fw_sects[ucode_type]; 2476 for (i = 0; i < fws->fw_count; i++) { 2477 data = fws->fw_sect[i].fws_data; 2478 dlen = fws->fw_sect[i].fws_len; 2479 offset = fws->fw_sect[i].fws_devoff; 2480 IWM_DPRINTF(sc, IWM_DEBUG_FIRMWARE_TLV, 2481 "LOAD FIRMWARE type %d offset %u len %d\n", 2482 ucode_type, offset, dlen); 2483 if (dlen > sc->sc_fwdmasegsz) { 2484 IWM_DPRINTF(sc, IWM_DEBUG_FIRMWARE_TLV, 2485 "chunk %d too large (%d bytes)\n", i, dlen); 2486 error = EFBIG; 2487 } else { 2488 error = iwm_firmware_load_sect(sc, offset, data, dlen); 2489 } 2490 if (error) { 2491 device_printf(sc->sc_dev, 2492 "could not load firmware chunk %u of %u " 2493 "(error=%d)\n", i, fws->fw_count, error); 2494 return error; 2495 } 2496 } 2497 2498 IWM_WRITE(sc, IWM_CSR_RESET, 0); 2499 2500 return 0; 2501 } 2502 2503 static int 2504 iwm_load_firmware(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 2505 { 2506 int error, w; 2507 2508 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) 2509 error = iwm_load_firmware_8000(sc, ucode_type); 2510 else 2511 error = iwm_load_firmware_7000(sc, ucode_type); 2512 if (error) 2513 return error; 2514 2515 /* wait for the firmware to load */ 2516 for (w = 0; !sc->sc_uc.uc_intr && w < 10; w++) { 2517 error = msleep(&sc->sc_uc, &sc->sc_mtx, 0, "iwmuc", hz/10); 2518 } 2519 if (error || !sc->sc_uc.uc_ok) { 2520 device_printf(sc->sc_dev, "could not load firmware\n"); 2521 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) { 2522 device_printf(sc->sc_dev, "cpu1 status: 0x%x\n", 2523 iwm_read_prph(sc, IWM_SB_CPU_1_STATUS)); 2524 device_printf(sc->sc_dev, "cpu2 status: 0x%x\n", 2525 iwm_read_prph(sc, IWM_SB_CPU_2_STATUS)); 2526 } 2527 } 2528 2529 /* 2530 * Give the firmware some time to initialize. 2531 * Accessing it too early causes errors. 2532 */ 2533 msleep(&w, &sc->sc_mtx, 0, "iwmfwinit", hz); 2534 2535 return error; 2536 } 2537 2538 /* iwlwifi: pcie/trans.c */ 2539 static int 2540 iwm_start_fw(struct iwm_softc *sc, enum iwm_ucode_type ucode_type) 2541 { 2542 int error; 2543 2544 IWM_WRITE(sc, IWM_CSR_INT, ~0); 2545 2546 if ((error = iwm_nic_init(sc)) != 0) { 2547 device_printf(sc->sc_dev, "unable to init nic\n"); 2548 return error; 2549 } 2550 2551 /* make sure rfkill handshake bits are cleared */ 2552 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL); 2553 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, 2554 IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 2555 2556 /* clear (again), then enable host interrupts */ 2557 IWM_WRITE(sc, IWM_CSR_INT, ~0); 2558 iwm_enable_interrupts(sc); 2559 2560 /* really make sure rfkill handshake bits are cleared */ 2561 /* maybe we should write a few times more? just to make sure */ 2562 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL); 2563 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL); 2564 2565 /* Load the given image to the HW */ 2566 return iwm_load_firmware(sc, ucode_type); 2567 } 2568 2569 static int 2570 iwm_send_tx_ant_cfg(struct iwm_softc *sc, uint8_t valid_tx_ant) 2571 { 2572 struct iwm_tx_ant_cfg_cmd tx_ant_cmd = { 2573 .valid = htole32(valid_tx_ant), 2574 }; 2575 2576 return iwm_mvm_send_cmd_pdu(sc, IWM_TX_ANT_CONFIGURATION_CMD, 2577 IWM_CMD_SYNC, sizeof(tx_ant_cmd), &tx_ant_cmd); 2578 } 2579 2580 /* iwlwifi: mvm/fw.c */ 2581 static int 2582 iwm_send_phy_cfg_cmd(struct iwm_softc *sc) 2583 { 2584 struct iwm_phy_cfg_cmd phy_cfg_cmd; 2585 enum iwm_ucode_type ucode_type = sc->sc_uc_current; 2586 2587 /* Set parameters */ 2588 phy_cfg_cmd.phy_cfg = htole32(sc->sc_fw_phy_config); 2589 phy_cfg_cmd.calib_control.event_trigger = 2590 sc->sc_default_calib[ucode_type].event_trigger; 2591 phy_cfg_cmd.calib_control.flow_trigger = 2592 sc->sc_default_calib[ucode_type].flow_trigger; 2593 2594 IWM_DPRINTF(sc, IWM_DEBUG_CMD | IWM_DEBUG_RESET, 2595 "Sending Phy CFG command: 0x%x\n", phy_cfg_cmd.phy_cfg); 2596 return iwm_mvm_send_cmd_pdu(sc, IWM_PHY_CONFIGURATION_CMD, IWM_CMD_SYNC, 2597 sizeof(phy_cfg_cmd), &phy_cfg_cmd); 2598 } 2599 2600 static int 2601 iwm_mvm_load_ucode_wait_alive(struct iwm_softc *sc, 2602 enum iwm_ucode_type ucode_type) 2603 { 2604 enum iwm_ucode_type old_type = sc->sc_uc_current; 2605 int error; 2606 2607 if ((error = iwm_read_firmware(sc, ucode_type)) != 0) { 2608 device_printf(sc->sc_dev, "iwm_read_firmware: failed %d\n", 2609 error); 2610 return error; 2611 } 2612 2613 sc->sc_uc_current = ucode_type; 2614 error = iwm_start_fw(sc, ucode_type); 2615 if (error) { 2616 device_printf(sc->sc_dev, "iwm_start_fw: failed %d\n", error); 2617 sc->sc_uc_current = old_type; 2618 return error; 2619 } 2620 2621 error = iwm_post_alive(sc); 2622 if (error) { 2623 device_printf(sc->sc_dev, "iwm_fw_alive: failed %d\n", error); 2624 } 2625 return error; 2626 } 2627 2628 /* 2629 * mvm misc bits 2630 */ 2631 2632 /* 2633 * follows iwlwifi/fw.c 2634 */ 2635 static int 2636 iwm_run_init_mvm_ucode(struct iwm_softc *sc, int justnvm) 2637 { 2638 int error; 2639 2640 /* do not operate with rfkill switch turned on */ 2641 if ((sc->sc_flags & IWM_FLAG_RFKILL) && !justnvm) { 2642 device_printf(sc->sc_dev, 2643 "radio is disabled by hardware switch\n"); 2644 return EPERM; 2645 } 2646 2647 sc->sc_init_complete = 0; 2648 if ((error = iwm_mvm_load_ucode_wait_alive(sc, 2649 IWM_UCODE_TYPE_INIT)) != 0) { 2650 device_printf(sc->sc_dev, "failed to load init firmware\n"); 2651 return error; 2652 } 2653 2654 if (justnvm) { 2655 if ((error = iwm_nvm_init(sc)) != 0) { 2656 device_printf(sc->sc_dev, "failed to read nvm\n"); 2657 return error; 2658 } 2659 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, sc->sc_nvm.hw_addr); 2660 2661 return 0; 2662 } 2663 2664 if ((error = iwm_send_bt_init_conf(sc)) != 0) { 2665 device_printf(sc->sc_dev, 2666 "failed to send bt coex configuration: %d\n", error); 2667 return error; 2668 } 2669 2670 /* Init Smart FIFO. */ 2671 error = iwm_mvm_sf_config(sc, IWM_SF_INIT_OFF); 2672 if (error != 0) 2673 return error; 2674 2675 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2676 "%s: phy_txant=0x%08x, nvm_valid_tx_ant=0x%02x, valid=0x%02x\n", 2677 __func__, 2678 ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_TX_CHAIN) 2679 >> IWM_FW_PHY_CFG_TX_CHAIN_POS), 2680 sc->sc_nvm.valid_tx_ant, 2681 iwm_fw_valid_tx_ant(sc)); 2682 2683 2684 /* Send TX valid antennas before triggering calibrations */ 2685 if ((error = iwm_send_tx_ant_cfg(sc, iwm_fw_valid_tx_ant(sc))) != 0) { 2686 device_printf(sc->sc_dev, 2687 "failed to send antennas before calibration: %d\n", error); 2688 return error; 2689 } 2690 2691 /* 2692 * Send phy configurations command to init uCode 2693 * to start the 16.0 uCode init image internal calibrations. 2694 */ 2695 if ((error = iwm_send_phy_cfg_cmd(sc)) != 0 ) { 2696 device_printf(sc->sc_dev, 2697 "%s: failed to run internal calibration: %d\n", 2698 __func__, error); 2699 return error; 2700 } 2701 2702 /* 2703 * Nothing to do but wait for the init complete notification 2704 * from the firmware 2705 */ 2706 while (!sc->sc_init_complete) { 2707 error = msleep(&sc->sc_init_complete, &sc->sc_mtx, 2708 0, "iwminit", 2*hz); 2709 if (error) { 2710 device_printf(sc->sc_dev, "init complete failed: %d\n", 2711 sc->sc_init_complete); 2712 break; 2713 } 2714 } 2715 2716 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "init %scomplete\n", 2717 sc->sc_init_complete ? "" : "not "); 2718 2719 return error; 2720 } 2721 2722 /* 2723 * receive side 2724 */ 2725 2726 /* (re)stock rx ring, called at init-time and at runtime */ 2727 static int 2728 iwm_rx_addbuf(struct iwm_softc *sc, int size, int idx) 2729 { 2730 struct iwm_rx_ring *ring = &sc->rxq; 2731 struct iwm_rx_data *data = &ring->data[idx]; 2732 struct mbuf *m; 2733 bus_dmamap_t dmamap = NULL; 2734 bus_dma_segment_t seg; 2735 int nsegs, error; 2736 2737 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWM_RBUF_SIZE); 2738 if (m == NULL) 2739 return ENOBUFS; 2740 2741 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2742 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, ring->spare_map, m, 2743 &seg, &nsegs, BUS_DMA_NOWAIT); 2744 if (error != 0) { 2745 device_printf(sc->sc_dev, 2746 "%s: can't map mbuf, error %d\n", __func__, error); 2747 goto fail; 2748 } 2749 2750 if (data->m != NULL) 2751 bus_dmamap_unload(ring->data_dmat, data->map); 2752 2753 /* Swap ring->spare_map with data->map */ 2754 dmamap = data->map; 2755 data->map = ring->spare_map; 2756 ring->spare_map = dmamap; 2757 2758 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREREAD); 2759 data->m = m; 2760 2761 /* Update RX descriptor. */ 2762 KASSERT((seg.ds_addr & 255) == 0, ("seg.ds_addr not aligned")); 2763 ring->desc[idx] = htole32(seg.ds_addr >> 8); 2764 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2765 BUS_DMASYNC_PREWRITE); 2766 2767 return 0; 2768 fail: 2769 m_freem(m); 2770 return error; 2771 } 2772 2773 /* iwlwifi: mvm/rx.c */ 2774 #define IWM_RSSI_OFFSET 50 2775 static int 2776 iwm_mvm_calc_rssi(struct iwm_softc *sc, struct iwm_rx_phy_info *phy_info) 2777 { 2778 int rssi_a, rssi_b, rssi_a_dbm, rssi_b_dbm, max_rssi_dbm; 2779 uint32_t agc_a, agc_b; 2780 uint32_t val; 2781 2782 val = le32toh(phy_info->non_cfg_phy[IWM_RX_INFO_AGC_IDX]); 2783 agc_a = (val & IWM_OFDM_AGC_A_MSK) >> IWM_OFDM_AGC_A_POS; 2784 agc_b = (val & IWM_OFDM_AGC_B_MSK) >> IWM_OFDM_AGC_B_POS; 2785 2786 val = le32toh(phy_info->non_cfg_phy[IWM_RX_INFO_RSSI_AB_IDX]); 2787 rssi_a = (val & IWM_OFDM_RSSI_INBAND_A_MSK) >> IWM_OFDM_RSSI_A_POS; 2788 rssi_b = (val & IWM_OFDM_RSSI_INBAND_B_MSK) >> IWM_OFDM_RSSI_B_POS; 2789 2790 /* 2791 * dBm = rssi dB - agc dB - constant. 2792 * Higher AGC (higher radio gain) means lower signal. 2793 */ 2794 rssi_a_dbm = rssi_a - IWM_RSSI_OFFSET - agc_a; 2795 rssi_b_dbm = rssi_b - IWM_RSSI_OFFSET - agc_b; 2796 max_rssi_dbm = MAX(rssi_a_dbm, rssi_b_dbm); 2797 2798 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 2799 "Rssi In A %d B %d Max %d AGCA %d AGCB %d\n", 2800 rssi_a_dbm, rssi_b_dbm, max_rssi_dbm, agc_a, agc_b); 2801 2802 return max_rssi_dbm; 2803 } 2804 2805 /* iwlwifi: mvm/rx.c */ 2806 /* 2807 * iwm_mvm_get_signal_strength - use new rx PHY INFO API 2808 * values are reported by the fw as positive values - need to negate 2809 * to obtain their dBM. Account for missing antennas by replacing 0 2810 * values by -256dBm: practically 0 power and a non-feasible 8 bit value. 2811 */ 2812 static int 2813 iwm_mvm_get_signal_strength(struct iwm_softc *sc, struct iwm_rx_phy_info *phy_info) 2814 { 2815 int energy_a, energy_b, energy_c, max_energy; 2816 uint32_t val; 2817 2818 val = le32toh(phy_info->non_cfg_phy[IWM_RX_INFO_ENERGY_ANT_ABC_IDX]); 2819 energy_a = (val & IWM_RX_INFO_ENERGY_ANT_A_MSK) >> 2820 IWM_RX_INFO_ENERGY_ANT_A_POS; 2821 energy_a = energy_a ? -energy_a : -256; 2822 energy_b = (val & IWM_RX_INFO_ENERGY_ANT_B_MSK) >> 2823 IWM_RX_INFO_ENERGY_ANT_B_POS; 2824 energy_b = energy_b ? -energy_b : -256; 2825 energy_c = (val & IWM_RX_INFO_ENERGY_ANT_C_MSK) >> 2826 IWM_RX_INFO_ENERGY_ANT_C_POS; 2827 energy_c = energy_c ? -energy_c : -256; 2828 max_energy = MAX(energy_a, energy_b); 2829 max_energy = MAX(max_energy, energy_c); 2830 2831 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 2832 "energy In A %d B %d C %d , and max %d\n", 2833 energy_a, energy_b, energy_c, max_energy); 2834 2835 return max_energy; 2836 } 2837 2838 static void 2839 iwm_mvm_rx_rx_phy_cmd(struct iwm_softc *sc, 2840 struct iwm_rx_packet *pkt, struct iwm_rx_data *data) 2841 { 2842 struct iwm_rx_phy_info *phy_info = (void *)pkt->data; 2843 2844 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "received PHY stats\n"); 2845 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2846 2847 memcpy(&sc->sc_last_phy_info, phy_info, sizeof(sc->sc_last_phy_info)); 2848 } 2849 2850 /* 2851 * Retrieve the average noise (in dBm) among receivers. 2852 */ 2853 static int 2854 iwm_get_noise(struct iwm_softc *sc, 2855 const struct iwm_mvm_statistics_rx_non_phy *stats) 2856 { 2857 int i, total, nbant, noise; 2858 2859 total = nbant = noise = 0; 2860 for (i = 0; i < 3; i++) { 2861 noise = le32toh(stats->beacon_silence_rssi[i]) & 0xff; 2862 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "%s: i=%d, noise=%d\n", 2863 __func__, 2864 i, 2865 noise); 2866 2867 if (noise) { 2868 total += noise; 2869 nbant++; 2870 } 2871 } 2872 2873 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "%s: nbant=%d, total=%d\n", 2874 __func__, nbant, total); 2875 #if 0 2876 /* There should be at least one antenna but check anyway. */ 2877 return (nbant == 0) ? -127 : (total / nbant) - 107; 2878 #else 2879 /* For now, just hard-code it to -96 to be safe */ 2880 return (-96); 2881 #endif 2882 } 2883 2884 /* 2885 * iwm_mvm_rx_rx_mpdu - IWM_REPLY_RX_MPDU_CMD handler 2886 * 2887 * Handles the actual data of the Rx packet from the fw 2888 */ 2889 static void 2890 iwm_mvm_rx_rx_mpdu(struct iwm_softc *sc, 2891 struct iwm_rx_packet *pkt, struct iwm_rx_data *data) 2892 { 2893 struct ieee80211com *ic = &sc->sc_ic; 2894 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2895 struct ieee80211_frame *wh; 2896 struct ieee80211_node *ni; 2897 struct ieee80211_rx_stats rxs; 2898 struct mbuf *m; 2899 struct iwm_rx_phy_info *phy_info; 2900 struct iwm_rx_mpdu_res_start *rx_res; 2901 uint32_t len; 2902 uint32_t rx_pkt_status; 2903 int rssi; 2904 2905 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2906 2907 phy_info = &sc->sc_last_phy_info; 2908 rx_res = (struct iwm_rx_mpdu_res_start *)pkt->data; 2909 wh = (struct ieee80211_frame *)(pkt->data + sizeof(*rx_res)); 2910 len = le16toh(rx_res->byte_count); 2911 rx_pkt_status = le32toh(*(uint32_t *)(pkt->data + sizeof(*rx_res) + len)); 2912 2913 m = data->m; 2914 m->m_data = pkt->data + sizeof(*rx_res); 2915 m->m_pkthdr.len = m->m_len = len; 2916 2917 if (__predict_false(phy_info->cfg_phy_cnt > 20)) { 2918 device_printf(sc->sc_dev, 2919 "dsp size out of range [0,20]: %d\n", 2920 phy_info->cfg_phy_cnt); 2921 goto fail; 2922 } 2923 2924 if (!(rx_pkt_status & IWM_RX_MPDU_RES_STATUS_CRC_OK) || 2925 !(rx_pkt_status & IWM_RX_MPDU_RES_STATUS_OVERRUN_OK)) { 2926 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 2927 "Bad CRC or FIFO: 0x%08X.\n", rx_pkt_status); 2928 goto fail; 2929 } 2930 2931 if (sc->sc_capaflags & IWM_UCODE_TLV_FLAGS_RX_ENERGY_API) { 2932 rssi = iwm_mvm_get_signal_strength(sc, phy_info); 2933 } else { 2934 rssi = iwm_mvm_calc_rssi(sc, phy_info); 2935 } 2936 2937 /* Note: RSSI is absolute (ie a -ve value) */ 2938 if (rssi < IWM_MIN_DBM) 2939 rssi = IWM_MIN_DBM; 2940 else if (rssi > IWM_MAX_DBM) 2941 rssi = IWM_MAX_DBM; 2942 2943 /* Map it to relative value */ 2944 rssi = rssi - sc->sc_noise; 2945 2946 /* replenish ring for the buffer we're going to feed to the sharks */ 2947 if (iwm_rx_addbuf(sc, IWM_RBUF_SIZE, sc->rxq.cur) != 0) { 2948 device_printf(sc->sc_dev, "%s: unable to add more buffers\n", 2949 __func__); 2950 goto fail; 2951 } 2952 2953 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 2954 "%s: rssi=%d, noise=%d\n", __func__, rssi, sc->sc_noise); 2955 2956 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2957 2958 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 2959 "%s: phy_info: channel=%d, flags=0x%08x\n", 2960 __func__, 2961 le16toh(phy_info->channel), 2962 le16toh(phy_info->phy_flags)); 2963 2964 /* 2965 * Populate an RX state struct with the provided information. 2966 */ 2967 bzero(&rxs, sizeof(rxs)); 2968 rxs.r_flags |= IEEE80211_R_IEEE | IEEE80211_R_FREQ; 2969 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI; 2970 rxs.c_ieee = le16toh(phy_info->channel); 2971 if (le16toh(phy_info->phy_flags & IWM_RX_RES_PHY_FLAGS_BAND_24)) { 2972 rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, IEEE80211_CHAN_2GHZ); 2973 } else { 2974 rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, IEEE80211_CHAN_5GHZ); 2975 } 2976 2977 /* rssi is in 1/2db units */ 2978 rxs.c_rssi = rssi * 2; 2979 rxs.c_nf = sc->sc_noise; 2980 2981 if (ieee80211_radiotap_active_vap(vap)) { 2982 struct iwm_rx_radiotap_header *tap = &sc->sc_rxtap; 2983 2984 tap->wr_flags = 0; 2985 if (phy_info->phy_flags & htole16(IWM_PHY_INFO_FLAG_SHPREAMBLE)) 2986 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2987 tap->wr_chan_freq = htole16(rxs.c_freq); 2988 /* XXX only if ic->ic_curchan->ic_ieee == rxs.c_ieee */ 2989 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2990 tap->wr_dbm_antsignal = (int8_t)rssi; 2991 tap->wr_dbm_antnoise = (int8_t)sc->sc_noise; 2992 tap->wr_tsft = phy_info->system_timestamp; 2993 switch (phy_info->rate) { 2994 /* CCK rates. */ 2995 case 10: tap->wr_rate = 2; break; 2996 case 20: tap->wr_rate = 4; break; 2997 case 55: tap->wr_rate = 11; break; 2998 case 110: tap->wr_rate = 22; break; 2999 /* OFDM rates. */ 3000 case 0xd: tap->wr_rate = 12; break; 3001 case 0xf: tap->wr_rate = 18; break; 3002 case 0x5: tap->wr_rate = 24; break; 3003 case 0x7: tap->wr_rate = 36; break; 3004 case 0x9: tap->wr_rate = 48; break; 3005 case 0xb: tap->wr_rate = 72; break; 3006 case 0x1: tap->wr_rate = 96; break; 3007 case 0x3: tap->wr_rate = 108; break; 3008 /* Unknown rate: should not happen. */ 3009 default: tap->wr_rate = 0; 3010 } 3011 } 3012 3013 IWM_UNLOCK(sc); 3014 if (ni != NULL) { 3015 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "input m %p\n", m); 3016 ieee80211_input_mimo(ni, m, &rxs); 3017 ieee80211_free_node(ni); 3018 } else { 3019 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "inputall m %p\n", m); 3020 ieee80211_input_mimo_all(ic, m, &rxs); 3021 } 3022 IWM_LOCK(sc); 3023 3024 return; 3025 3026 fail: counter_u64_add(ic->ic_ierrors, 1); 3027 } 3028 3029 static int 3030 iwm_mvm_rx_tx_cmd_single(struct iwm_softc *sc, struct iwm_rx_packet *pkt, 3031 struct iwm_node *in) 3032 { 3033 struct iwm_mvm_tx_resp *tx_resp = (void *)pkt->data; 3034 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3035 struct ieee80211_node *ni = &in->in_ni; 3036 int status = le16toh(tx_resp->status.status) & IWM_TX_STATUS_MSK; 3037 3038 KASSERT(tx_resp->frame_count == 1, ("too many frames")); 3039 3040 /* Update rate control statistics. */ 3041 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, "%s: status=0x%04x, seq=%d, fc=%d, btc=%d, frts=%d, ff=%d, irate=%08x, wmt=%d\n", 3042 __func__, 3043 (int) le16toh(tx_resp->status.status), 3044 (int) le16toh(tx_resp->status.sequence), 3045 tx_resp->frame_count, 3046 tx_resp->bt_kill_count, 3047 tx_resp->failure_rts, 3048 tx_resp->failure_frame, 3049 le32toh(tx_resp->initial_rate), 3050 (int) le16toh(tx_resp->wireless_media_time)); 3051 3052 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3053 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3054 txs->short_retries = tx_resp->failure_rts; 3055 txs->long_retries = tx_resp->failure_frame; 3056 if (status != IWM_TX_STATUS_SUCCESS && 3057 status != IWM_TX_STATUS_DIRECT_DONE) { 3058 switch (status) { 3059 case IWM_TX_STATUS_FAIL_SHORT_LIMIT: 3060 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT; 3061 break; 3062 case IWM_TX_STATUS_FAIL_LONG_LIMIT: 3063 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG; 3064 break; 3065 case IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 3066 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED; 3067 break; 3068 default: 3069 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3070 break; 3071 } 3072 } else { 3073 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3074 } 3075 ieee80211_ratectl_tx_complete(ni, txs); 3076 3077 return (txs->status != IEEE80211_RATECTL_TX_SUCCESS); 3078 } 3079 3080 static void 3081 iwm_mvm_rx_tx_cmd(struct iwm_softc *sc, 3082 struct iwm_rx_packet *pkt, struct iwm_rx_data *data) 3083 { 3084 struct iwm_cmd_header *cmd_hdr = &pkt->hdr; 3085 int idx = cmd_hdr->idx; 3086 int qid = cmd_hdr->qid; 3087 struct iwm_tx_ring *ring = &sc->txq[qid]; 3088 struct iwm_tx_data *txd = &ring->data[idx]; 3089 struct iwm_node *in = txd->in; 3090 struct mbuf *m = txd->m; 3091 int status; 3092 3093 KASSERT(txd->done == 0, ("txd not done")); 3094 KASSERT(txd->in != NULL, ("txd without node")); 3095 KASSERT(txd->m != NULL, ("txd without mbuf")); 3096 3097 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3098 3099 sc->sc_tx_timer = 0; 3100 3101 status = iwm_mvm_rx_tx_cmd_single(sc, pkt, in); 3102 3103 /* Unmap and free mbuf. */ 3104 bus_dmamap_sync(ring->data_dmat, txd->map, BUS_DMASYNC_POSTWRITE); 3105 bus_dmamap_unload(ring->data_dmat, txd->map); 3106 3107 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 3108 "free txd %p, in %p\n", txd, txd->in); 3109 txd->done = 1; 3110 txd->m = NULL; 3111 txd->in = NULL; 3112 3113 ieee80211_tx_complete(&in->in_ni, m, status); 3114 3115 if (--ring->queued < IWM_TX_RING_LOMARK) { 3116 sc->qfullmsk &= ~(1 << ring->qid); 3117 if (sc->qfullmsk == 0) { 3118 /* 3119 * Well, we're in interrupt context, but then again 3120 * I guess net80211 does all sorts of stunts in 3121 * interrupt context, so maybe this is no biggie. 3122 */ 3123 iwm_start(sc); 3124 } 3125 } 3126 } 3127 3128 /* 3129 * transmit side 3130 */ 3131 3132 /* 3133 * Process a "command done" firmware notification. This is where we wakeup 3134 * processes waiting for a synchronous command completion. 3135 * from if_iwn 3136 */ 3137 static void 3138 iwm_cmd_done(struct iwm_softc *sc, struct iwm_rx_packet *pkt) 3139 { 3140 struct iwm_tx_ring *ring = &sc->txq[IWM_MVM_CMD_QUEUE]; 3141 struct iwm_tx_data *data; 3142 3143 if (pkt->hdr.qid != IWM_MVM_CMD_QUEUE) { 3144 return; /* Not a command ack. */ 3145 } 3146 3147 /* XXX wide commands? */ 3148 IWM_DPRINTF(sc, IWM_DEBUG_CMD, 3149 "cmd notification type 0x%x qid %d idx %d\n", 3150 pkt->hdr.code, pkt->hdr.qid, pkt->hdr.idx); 3151 3152 data = &ring->data[pkt->hdr.idx]; 3153 3154 /* If the command was mapped in an mbuf, free it. */ 3155 if (data->m != NULL) { 3156 bus_dmamap_sync(ring->data_dmat, data->map, 3157 BUS_DMASYNC_POSTWRITE); 3158 bus_dmamap_unload(ring->data_dmat, data->map); 3159 m_freem(data->m); 3160 data->m = NULL; 3161 } 3162 wakeup(&ring->desc[pkt->hdr.idx]); 3163 } 3164 3165 #if 0 3166 /* 3167 * necessary only for block ack mode 3168 */ 3169 void 3170 iwm_update_sched(struct iwm_softc *sc, int qid, int idx, uint8_t sta_id, 3171 uint16_t len) 3172 { 3173 struct iwm_agn_scd_bc_tbl *scd_bc_tbl; 3174 uint16_t w_val; 3175 3176 scd_bc_tbl = sc->sched_dma.vaddr; 3177 3178 len += 8; /* magic numbers came naturally from paris */ 3179 if (sc->sc_capaflags & IWM_UCODE_TLV_FLAGS_DW_BC_TABLE) 3180 len = roundup(len, 4) / 4; 3181 3182 w_val = htole16(sta_id << 12 | len); 3183 3184 /* Update TX scheduler. */ 3185 scd_bc_tbl[qid].tfd_offset[idx] = w_val; 3186 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3187 BUS_DMASYNC_PREWRITE); 3188 3189 /* I really wonder what this is ?!? */ 3190 if (idx < IWM_TFD_QUEUE_SIZE_BC_DUP) { 3191 scd_bc_tbl[qid].tfd_offset[IWM_TFD_QUEUE_SIZE_MAX + idx] = w_val; 3192 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3193 BUS_DMASYNC_PREWRITE); 3194 } 3195 } 3196 #endif 3197 3198 /* 3199 * Take an 802.11 (non-n) rate, find the relevant rate 3200 * table entry. return the index into in_ridx[]. 3201 * 3202 * The caller then uses that index back into in_ridx 3203 * to figure out the rate index programmed /into/ 3204 * the firmware for this given node. 3205 */ 3206 static int 3207 iwm_tx_rateidx_lookup(struct iwm_softc *sc, struct iwm_node *in, 3208 uint8_t rate) 3209 { 3210 int i; 3211 uint8_t r; 3212 3213 for (i = 0; i < nitems(in->in_ridx); i++) { 3214 r = iwm_rates[in->in_ridx[i]].rate; 3215 if (rate == r) 3216 return (i); 3217 } 3218 3219 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE, 3220 "%s: couldn't find an entry for rate=%d\n", 3221 __func__, 3222 rate); 3223 3224 /* XXX Return the first */ 3225 /* XXX TODO: have it return the /lowest/ */ 3226 return (0); 3227 } 3228 3229 static int 3230 iwm_tx_rateidx_global_lookup(struct iwm_softc *sc, uint8_t rate) 3231 { 3232 int i; 3233 3234 for (i = 0; i < nitems(iwm_rates); i++) { 3235 if (iwm_rates[i].rate == rate) 3236 return (i); 3237 } 3238 /* XXX error? */ 3239 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE, 3240 "%s: couldn't find an entry for rate=%d\n", 3241 __func__, 3242 rate); 3243 return (0); 3244 } 3245 3246 /* 3247 * Fill in the rate related information for a transmit command. 3248 */ 3249 static const struct iwm_rate * 3250 iwm_tx_fill_cmd(struct iwm_softc *sc, struct iwm_node *in, 3251 struct mbuf *m, struct iwm_tx_cmd *tx) 3252 { 3253 struct ieee80211_node *ni = &in->in_ni; 3254 struct ieee80211_frame *wh; 3255 const struct ieee80211_txparam *tp = ni->ni_txparms; 3256 const struct iwm_rate *rinfo; 3257 int type; 3258 int ridx, rate_flags; 3259 3260 wh = mtod(m, struct ieee80211_frame *); 3261 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3262 3263 tx->rts_retry_limit = IWM_RTS_DFAULT_RETRY_LIMIT; 3264 tx->data_retry_limit = IWM_DEFAULT_TX_RETRY; 3265 3266 if (type == IEEE80211_FC0_TYPE_MGT) { 3267 ridx = iwm_tx_rateidx_global_lookup(sc, tp->mgmtrate); 3268 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3269 "%s: MGT (%d)\n", __func__, tp->mgmtrate); 3270 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3271 ridx = iwm_tx_rateidx_global_lookup(sc, tp->mcastrate); 3272 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3273 "%s: MCAST (%d)\n", __func__, tp->mcastrate); 3274 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 3275 ridx = iwm_tx_rateidx_global_lookup(sc, tp->ucastrate); 3276 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3277 "%s: FIXED_RATE (%d)\n", __func__, tp->ucastrate); 3278 } else if (m->m_flags & M_EAPOL) { 3279 ridx = iwm_tx_rateidx_global_lookup(sc, tp->mgmtrate); 3280 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3281 "%s: EAPOL\n", __func__); 3282 } else if (type == IEEE80211_FC0_TYPE_DATA) { 3283 int i; 3284 3285 /* for data frames, use RS table */ 3286 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: DATA\n", __func__); 3287 /* XXX pass pktlen */ 3288 (void) ieee80211_ratectl_rate(ni, NULL, 0); 3289 i = iwm_tx_rateidx_lookup(sc, in, ni->ni_txrate); 3290 ridx = in->in_ridx[i]; 3291 3292 /* This is the index into the programmed table */ 3293 tx->initial_rate_index = i; 3294 tx->tx_flags |= htole32(IWM_TX_CMD_FLG_STA_RATE); 3295 3296 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE, 3297 "%s: start with i=%d, txrate %d\n", 3298 __func__, i, iwm_rates[ridx].rate); 3299 } else { 3300 ridx = iwm_tx_rateidx_global_lookup(sc, tp->mgmtrate); 3301 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: DEFAULT (%d)\n", 3302 __func__, tp->mgmtrate); 3303 } 3304 3305 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE, 3306 "%s: frame type=%d txrate %d\n", 3307 __func__, type, iwm_rates[ridx].rate); 3308 3309 rinfo = &iwm_rates[ridx]; 3310 3311 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: ridx=%d; rate=%d, CCK=%d\n", 3312 __func__, ridx, 3313 rinfo->rate, 3314 !! (IWM_RIDX_IS_CCK(ridx)) 3315 ); 3316 3317 /* XXX TODO: hard-coded TX antenna? */ 3318 rate_flags = 1 << IWM_RATE_MCS_ANT_POS; 3319 if (IWM_RIDX_IS_CCK(ridx)) 3320 rate_flags |= IWM_RATE_MCS_CCK_MSK; 3321 tx->rate_n_flags = htole32(rate_flags | rinfo->plcp); 3322 3323 return rinfo; 3324 } 3325 3326 #define TB0_SIZE 16 3327 static int 3328 iwm_tx(struct iwm_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 3329 { 3330 struct ieee80211com *ic = &sc->sc_ic; 3331 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3332 struct iwm_node *in = IWM_NODE(ni); 3333 struct iwm_tx_ring *ring; 3334 struct iwm_tx_data *data; 3335 struct iwm_tfd *desc; 3336 struct iwm_device_cmd *cmd; 3337 struct iwm_tx_cmd *tx; 3338 struct ieee80211_frame *wh; 3339 struct ieee80211_key *k = NULL; 3340 struct mbuf *m1; 3341 const struct iwm_rate *rinfo; 3342 uint32_t flags; 3343 u_int hdrlen; 3344 bus_dma_segment_t *seg, segs[IWM_MAX_SCATTER]; 3345 int nsegs; 3346 uint8_t tid, type; 3347 int i, totlen, error, pad; 3348 3349 wh = mtod(m, struct ieee80211_frame *); 3350 hdrlen = ieee80211_anyhdrsize(wh); 3351 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3352 tid = 0; 3353 ring = &sc->txq[ac]; 3354 desc = &ring->desc[ring->cur]; 3355 memset(desc, 0, sizeof(*desc)); 3356 data = &ring->data[ring->cur]; 3357 3358 /* Fill out iwm_tx_cmd to send to the firmware */ 3359 cmd = &ring->cmd[ring->cur]; 3360 cmd->hdr.code = IWM_TX_CMD; 3361 cmd->hdr.flags = 0; 3362 cmd->hdr.qid = ring->qid; 3363 cmd->hdr.idx = ring->cur; 3364 3365 tx = (void *)cmd->data; 3366 memset(tx, 0, sizeof(*tx)); 3367 3368 rinfo = iwm_tx_fill_cmd(sc, in, m, tx); 3369 3370 /* Encrypt the frame if need be. */ 3371 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3372 /* Retrieve key for TX && do software encryption. */ 3373 k = ieee80211_crypto_encap(ni, m); 3374 if (k == NULL) { 3375 m_freem(m); 3376 return (ENOBUFS); 3377 } 3378 /* 802.11 header may have moved. */ 3379 wh = mtod(m, struct ieee80211_frame *); 3380 } 3381 3382 if (ieee80211_radiotap_active_vap(vap)) { 3383 struct iwm_tx_radiotap_header *tap = &sc->sc_txtap; 3384 3385 tap->wt_flags = 0; 3386 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 3387 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 3388 tap->wt_rate = rinfo->rate; 3389 if (k != NULL) 3390 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3391 ieee80211_radiotap_tx(vap, m); 3392 } 3393 3394 3395 totlen = m->m_pkthdr.len; 3396 3397 flags = 0; 3398 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3399 flags |= IWM_TX_CMD_FLG_ACK; 3400 } 3401 3402 if (type == IEEE80211_FC0_TYPE_DATA 3403 && (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 3404 && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3405 flags |= IWM_TX_CMD_FLG_PROT_REQUIRE; 3406 } 3407 3408 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3409 type != IEEE80211_FC0_TYPE_DATA) 3410 tx->sta_id = sc->sc_aux_sta.sta_id; 3411 else 3412 tx->sta_id = IWM_STATION_ID; 3413 3414 if (type == IEEE80211_FC0_TYPE_MGT) { 3415 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3416 3417 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3418 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) { 3419 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_ASSOC); 3420 } else if (subtype == IEEE80211_FC0_SUBTYPE_ACTION) { 3421 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_NONE); 3422 } else { 3423 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_MGMT); 3424 } 3425 } else { 3426 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_NONE); 3427 } 3428 3429 if (hdrlen & 3) { 3430 /* First segment length must be a multiple of 4. */ 3431 flags |= IWM_TX_CMD_FLG_MH_PAD; 3432 pad = 4 - (hdrlen & 3); 3433 } else 3434 pad = 0; 3435 3436 tx->driver_txop = 0; 3437 tx->next_frame_len = 0; 3438 3439 tx->len = htole16(totlen); 3440 tx->tid_tspec = tid; 3441 tx->life_time = htole32(IWM_TX_CMD_LIFE_TIME_INFINITE); 3442 3443 /* Set physical address of "scratch area". */ 3444 tx->dram_lsb_ptr = htole32(data->scratch_paddr); 3445 tx->dram_msb_ptr = iwm_get_dma_hi_addr(data->scratch_paddr); 3446 3447 /* Copy 802.11 header in TX command. */ 3448 memcpy(((uint8_t *)tx) + sizeof(*tx), wh, hdrlen); 3449 3450 flags |= IWM_TX_CMD_FLG_BT_DIS | IWM_TX_CMD_FLG_SEQ_CTL; 3451 3452 tx->sec_ctl = 0; 3453 tx->tx_flags |= htole32(flags); 3454 3455 /* Trim 802.11 header. */ 3456 m_adj(m, hdrlen); 3457 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3458 segs, &nsegs, BUS_DMA_NOWAIT); 3459 if (error != 0) { 3460 if (error != EFBIG) { 3461 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 3462 error); 3463 m_freem(m); 3464 return error; 3465 } 3466 /* Too many DMA segments, linearize mbuf. */ 3467 m1 = m_collapse(m, M_NOWAIT, IWM_MAX_SCATTER - 2); 3468 if (m1 == NULL) { 3469 device_printf(sc->sc_dev, 3470 "%s: could not defrag mbuf\n", __func__); 3471 m_freem(m); 3472 return (ENOBUFS); 3473 } 3474 m = m1; 3475 3476 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 3477 segs, &nsegs, BUS_DMA_NOWAIT); 3478 if (error != 0) { 3479 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 3480 error); 3481 m_freem(m); 3482 return error; 3483 } 3484 } 3485 data->m = m; 3486 data->in = in; 3487 data->done = 0; 3488 3489 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 3490 "sending txd %p, in %p\n", data, data->in); 3491 KASSERT(data->in != NULL, ("node is NULL")); 3492 3493 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 3494 "sending data: qid=%d idx=%d len=%d nsegs=%d txflags=0x%08x rate_n_flags=0x%08x rateidx=%u\n", 3495 ring->qid, ring->cur, totlen, nsegs, 3496 le32toh(tx->tx_flags), 3497 le32toh(tx->rate_n_flags), 3498 tx->initial_rate_index 3499 ); 3500 3501 /* Fill TX descriptor. */ 3502 desc->num_tbs = 2 + nsegs; 3503 3504 desc->tbs[0].lo = htole32(data->cmd_paddr); 3505 desc->tbs[0].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr)) | 3506 (TB0_SIZE << 4); 3507 desc->tbs[1].lo = htole32(data->cmd_paddr + TB0_SIZE); 3508 desc->tbs[1].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr)) | 3509 ((sizeof(struct iwm_cmd_header) + sizeof(*tx) 3510 + hdrlen + pad - TB0_SIZE) << 4); 3511 3512 /* Other DMA segments are for data payload. */ 3513 for (i = 0; i < nsegs; i++) { 3514 seg = &segs[i]; 3515 desc->tbs[i+2].lo = htole32(seg->ds_addr); 3516 desc->tbs[i+2].hi_n_len = \ 3517 htole16(iwm_get_dma_hi_addr(seg->ds_addr)) 3518 | ((seg->ds_len) << 4); 3519 } 3520 3521 bus_dmamap_sync(ring->data_dmat, data->map, 3522 BUS_DMASYNC_PREWRITE); 3523 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 3524 BUS_DMASYNC_PREWRITE); 3525 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3526 BUS_DMASYNC_PREWRITE); 3527 3528 #if 0 3529 iwm_update_sched(sc, ring->qid, ring->cur, tx->sta_id, le16toh(tx->len)); 3530 #endif 3531 3532 /* Kick TX ring. */ 3533 ring->cur = (ring->cur + 1) % IWM_TX_RING_COUNT; 3534 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3535 3536 /* Mark TX ring as full if we reach a certain threshold. */ 3537 if (++ring->queued > IWM_TX_RING_HIMARK) { 3538 sc->qfullmsk |= 1 << ring->qid; 3539 } 3540 3541 return 0; 3542 } 3543 3544 static int 3545 iwm_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3546 const struct ieee80211_bpf_params *params) 3547 { 3548 struct ieee80211com *ic = ni->ni_ic; 3549 struct iwm_softc *sc = ic->ic_softc; 3550 int error = 0; 3551 3552 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 3553 "->%s begin\n", __func__); 3554 3555 if ((sc->sc_flags & IWM_FLAG_HW_INITED) == 0) { 3556 m_freem(m); 3557 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 3558 "<-%s not RUNNING\n", __func__); 3559 return (ENETDOWN); 3560 } 3561 3562 IWM_LOCK(sc); 3563 /* XXX fix this */ 3564 if (params == NULL) { 3565 error = iwm_tx(sc, m, ni, 0); 3566 } else { 3567 error = iwm_tx(sc, m, ni, 0); 3568 } 3569 sc->sc_tx_timer = 5; 3570 IWM_UNLOCK(sc); 3571 3572 return (error); 3573 } 3574 3575 /* 3576 * mvm/tx.c 3577 */ 3578 3579 /* 3580 * Note that there are transports that buffer frames before they reach 3581 * the firmware. This means that after flush_tx_path is called, the 3582 * queue might not be empty. The race-free way to handle this is to: 3583 * 1) set the station as draining 3584 * 2) flush the Tx path 3585 * 3) wait for the transport queues to be empty 3586 */ 3587 int 3588 iwm_mvm_flush_tx_path(struct iwm_softc *sc, uint32_t tfd_msk, uint32_t flags) 3589 { 3590 int ret; 3591 struct iwm_tx_path_flush_cmd flush_cmd = { 3592 .queues_ctl = htole32(tfd_msk), 3593 .flush_ctl = htole16(IWM_DUMP_TX_FIFO_FLUSH), 3594 }; 3595 3596 ret = iwm_mvm_send_cmd_pdu(sc, IWM_TXPATH_FLUSH, flags, 3597 sizeof(flush_cmd), &flush_cmd); 3598 if (ret) 3599 device_printf(sc->sc_dev, 3600 "Flushing tx queue failed: %d\n", ret); 3601 return ret; 3602 } 3603 3604 /* 3605 * BEGIN mvm/sta.c 3606 */ 3607 3608 static int 3609 iwm_mvm_send_add_sta_cmd_status(struct iwm_softc *sc, 3610 struct iwm_mvm_add_sta_cmd_v7 *cmd, int *status) 3611 { 3612 return iwm_mvm_send_cmd_pdu_status(sc, IWM_ADD_STA, sizeof(*cmd), 3613 cmd, status); 3614 } 3615 3616 /* send station add/update command to firmware */ 3617 static int 3618 iwm_mvm_sta_send_to_fw(struct iwm_softc *sc, struct iwm_node *in, int update) 3619 { 3620 struct iwm_mvm_add_sta_cmd_v7 add_sta_cmd; 3621 int ret; 3622 uint32_t status; 3623 3624 memset(&add_sta_cmd, 0, sizeof(add_sta_cmd)); 3625 3626 add_sta_cmd.sta_id = IWM_STATION_ID; 3627 add_sta_cmd.mac_id_n_color 3628 = htole32(IWM_FW_CMD_ID_AND_COLOR(IWM_DEFAULT_MACID, 3629 IWM_DEFAULT_COLOR)); 3630 if (!update) { 3631 int ac; 3632 for (ac = 0; ac < WME_NUM_AC; ac++) { 3633 add_sta_cmd.tfd_queue_msk |= 3634 htole32(1 << iwm_mvm_ac_to_tx_fifo[ac]); 3635 } 3636 IEEE80211_ADDR_COPY(&add_sta_cmd.addr, in->in_ni.ni_bssid); 3637 } 3638 add_sta_cmd.add_modify = update ? 1 : 0; 3639 add_sta_cmd.station_flags_msk 3640 |= htole32(IWM_STA_FLG_FAT_EN_MSK | IWM_STA_FLG_MIMO_EN_MSK); 3641 add_sta_cmd.tid_disable_tx = htole16(0xffff); 3642 if (update) 3643 add_sta_cmd.modify_mask |= (IWM_STA_MODIFY_TID_DISABLE_TX); 3644 3645 status = IWM_ADD_STA_SUCCESS; 3646 ret = iwm_mvm_send_add_sta_cmd_status(sc, &add_sta_cmd, &status); 3647 if (ret) 3648 return ret; 3649 3650 switch (status) { 3651 case IWM_ADD_STA_SUCCESS: 3652 break; 3653 default: 3654 ret = EIO; 3655 device_printf(sc->sc_dev, "IWM_ADD_STA failed\n"); 3656 break; 3657 } 3658 3659 return ret; 3660 } 3661 3662 static int 3663 iwm_mvm_add_sta(struct iwm_softc *sc, struct iwm_node *in) 3664 { 3665 return iwm_mvm_sta_send_to_fw(sc, in, 0); 3666 } 3667 3668 static int 3669 iwm_mvm_update_sta(struct iwm_softc *sc, struct iwm_node *in) 3670 { 3671 return iwm_mvm_sta_send_to_fw(sc, in, 1); 3672 } 3673 3674 static int 3675 iwm_mvm_add_int_sta_common(struct iwm_softc *sc, struct iwm_int_sta *sta, 3676 const uint8_t *addr, uint16_t mac_id, uint16_t color) 3677 { 3678 struct iwm_mvm_add_sta_cmd_v7 cmd; 3679 int ret; 3680 uint32_t status; 3681 3682 memset(&cmd, 0, sizeof(cmd)); 3683 cmd.sta_id = sta->sta_id; 3684 cmd.mac_id_n_color = htole32(IWM_FW_CMD_ID_AND_COLOR(mac_id, color)); 3685 3686 cmd.tfd_queue_msk = htole32(sta->tfd_queue_msk); 3687 cmd.tid_disable_tx = htole16(0xffff); 3688 3689 if (addr) 3690 IEEE80211_ADDR_COPY(cmd.addr, addr); 3691 3692 ret = iwm_mvm_send_add_sta_cmd_status(sc, &cmd, &status); 3693 if (ret) 3694 return ret; 3695 3696 switch (status) { 3697 case IWM_ADD_STA_SUCCESS: 3698 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 3699 "%s: Internal station added.\n", __func__); 3700 return 0; 3701 default: 3702 device_printf(sc->sc_dev, 3703 "%s: Add internal station failed, status=0x%x\n", 3704 __func__, status); 3705 ret = EIO; 3706 break; 3707 } 3708 return ret; 3709 } 3710 3711 static int 3712 iwm_mvm_add_aux_sta(struct iwm_softc *sc) 3713 { 3714 int ret; 3715 3716 sc->sc_aux_sta.sta_id = IWM_AUX_STA_ID; 3717 sc->sc_aux_sta.tfd_queue_msk = (1 << IWM_MVM_AUX_QUEUE); 3718 3719 ret = iwm_enable_txq(sc, 0, IWM_MVM_AUX_QUEUE, IWM_MVM_TX_FIFO_MCAST); 3720 if (ret) 3721 return ret; 3722 3723 ret = iwm_mvm_add_int_sta_common(sc, 3724 &sc->sc_aux_sta, NULL, IWM_MAC_INDEX_AUX, 0); 3725 3726 if (ret) 3727 memset(&sc->sc_aux_sta, 0, sizeof(sc->sc_aux_sta)); 3728 return ret; 3729 } 3730 3731 /* 3732 * END mvm/sta.c 3733 */ 3734 3735 /* 3736 * BEGIN mvm/quota.c 3737 */ 3738 3739 static int 3740 iwm_mvm_update_quotas(struct iwm_softc *sc, struct iwm_node *in) 3741 { 3742 struct iwm_time_quota_cmd cmd; 3743 int i, idx, ret, num_active_macs, quota, quota_rem; 3744 int colors[IWM_MAX_BINDINGS] = { -1, -1, -1, -1, }; 3745 int n_ifs[IWM_MAX_BINDINGS] = {0, }; 3746 uint16_t id; 3747 3748 memset(&cmd, 0, sizeof(cmd)); 3749 3750 /* currently, PHY ID == binding ID */ 3751 if (in) { 3752 id = in->in_phyctxt->id; 3753 KASSERT(id < IWM_MAX_BINDINGS, ("invalid id")); 3754 colors[id] = in->in_phyctxt->color; 3755 3756 if (1) 3757 n_ifs[id] = 1; 3758 } 3759 3760 /* 3761 * The FW's scheduling session consists of 3762 * IWM_MVM_MAX_QUOTA fragments. Divide these fragments 3763 * equally between all the bindings that require quota 3764 */ 3765 num_active_macs = 0; 3766 for (i = 0; i < IWM_MAX_BINDINGS; i++) { 3767 cmd.quotas[i].id_and_color = htole32(IWM_FW_CTXT_INVALID); 3768 num_active_macs += n_ifs[i]; 3769 } 3770 3771 quota = 0; 3772 quota_rem = 0; 3773 if (num_active_macs) { 3774 quota = IWM_MVM_MAX_QUOTA / num_active_macs; 3775 quota_rem = IWM_MVM_MAX_QUOTA % num_active_macs; 3776 } 3777 3778 for (idx = 0, i = 0; i < IWM_MAX_BINDINGS; i++) { 3779 if (colors[i] < 0) 3780 continue; 3781 3782 cmd.quotas[idx].id_and_color = 3783 htole32(IWM_FW_CMD_ID_AND_COLOR(i, colors[i])); 3784 3785 if (n_ifs[i] <= 0) { 3786 cmd.quotas[idx].quota = htole32(0); 3787 cmd.quotas[idx].max_duration = htole32(0); 3788 } else { 3789 cmd.quotas[idx].quota = htole32(quota * n_ifs[i]); 3790 cmd.quotas[idx].max_duration = htole32(0); 3791 } 3792 idx++; 3793 } 3794 3795 /* Give the remainder of the session to the first binding */ 3796 cmd.quotas[0].quota = htole32(le32toh(cmd.quotas[0].quota) + quota_rem); 3797 3798 ret = iwm_mvm_send_cmd_pdu(sc, IWM_TIME_QUOTA_CMD, IWM_CMD_SYNC, 3799 sizeof(cmd), &cmd); 3800 if (ret) 3801 device_printf(sc->sc_dev, 3802 "%s: Failed to send quota: %d\n", __func__, ret); 3803 return ret; 3804 } 3805 3806 /* 3807 * END mvm/quota.c 3808 */ 3809 3810 /* 3811 * ieee80211 routines 3812 */ 3813 3814 /* 3815 * Change to AUTH state in 80211 state machine. Roughly matches what 3816 * Linux does in bss_info_changed(). 3817 */ 3818 static int 3819 iwm_auth(struct ieee80211vap *vap, struct iwm_softc *sc) 3820 { 3821 struct ieee80211_node *ni; 3822 struct iwm_node *in; 3823 struct iwm_vap *iv = IWM_VAP(vap); 3824 uint32_t duration; 3825 int error; 3826 3827 /* 3828 * XXX i have a feeling that the vap node is being 3829 * freed from underneath us. Grr. 3830 */ 3831 ni = ieee80211_ref_node(vap->iv_bss); 3832 in = IWM_NODE(ni); 3833 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_STATE, 3834 "%s: called; vap=%p, bss ni=%p\n", 3835 __func__, 3836 vap, 3837 ni); 3838 3839 in->in_assoc = 0; 3840 3841 error = iwm_mvm_sf_config(sc, IWM_SF_FULL_ON); 3842 if (error != 0) 3843 return error; 3844 3845 error = iwm_allow_mcast(vap, sc); 3846 if (error) { 3847 device_printf(sc->sc_dev, 3848 "%s: failed to set multicast\n", __func__); 3849 goto out; 3850 } 3851 3852 /* 3853 * This is where it deviates from what Linux does. 3854 * 3855 * Linux iwlwifi doesn't reset the nic each time, nor does it 3856 * call ctxt_add() here. Instead, it adds it during vap creation, 3857 * and always does a mac_ctx_changed(). 3858 * 3859 * The openbsd port doesn't attempt to do that - it reset things 3860 * at odd states and does the add here. 3861 * 3862 * So, until the state handling is fixed (ie, we never reset 3863 * the NIC except for a firmware failure, which should drag 3864 * the NIC back to IDLE, re-setup and re-add all the mac/phy 3865 * contexts that are required), let's do a dirty hack here. 3866 */ 3867 if (iv->is_uploaded) { 3868 if ((error = iwm_mvm_mac_ctxt_changed(sc, vap)) != 0) { 3869 device_printf(sc->sc_dev, 3870 "%s: failed to update MAC\n", __func__); 3871 goto out; 3872 } 3873 if ((error = iwm_mvm_phy_ctxt_changed(sc, &sc->sc_phyctxt[0], 3874 in->in_ni.ni_chan, 1, 1)) != 0) { 3875 device_printf(sc->sc_dev, 3876 "%s: failed update phy ctxt\n", __func__); 3877 goto out; 3878 } 3879 in->in_phyctxt = &sc->sc_phyctxt[0]; 3880 3881 if ((error = iwm_mvm_binding_update(sc, in)) != 0) { 3882 device_printf(sc->sc_dev, 3883 "%s: binding update cmd\n", __func__); 3884 goto out; 3885 } 3886 if ((error = iwm_mvm_update_sta(sc, in)) != 0) { 3887 device_printf(sc->sc_dev, 3888 "%s: failed to update sta\n", __func__); 3889 goto out; 3890 } 3891 } else { 3892 if ((error = iwm_mvm_mac_ctxt_add(sc, vap)) != 0) { 3893 device_printf(sc->sc_dev, 3894 "%s: failed to add MAC\n", __func__); 3895 goto out; 3896 } 3897 if ((error = iwm_mvm_phy_ctxt_changed(sc, &sc->sc_phyctxt[0], 3898 in->in_ni.ni_chan, 1, 1)) != 0) { 3899 device_printf(sc->sc_dev, 3900 "%s: failed add phy ctxt!\n", __func__); 3901 error = ETIMEDOUT; 3902 goto out; 3903 } 3904 in->in_phyctxt = &sc->sc_phyctxt[0]; 3905 3906 if ((error = iwm_mvm_binding_add_vif(sc, in)) != 0) { 3907 device_printf(sc->sc_dev, 3908 "%s: binding add cmd\n", __func__); 3909 goto out; 3910 } 3911 if ((error = iwm_mvm_add_sta(sc, in)) != 0) { 3912 device_printf(sc->sc_dev, 3913 "%s: failed to add sta\n", __func__); 3914 goto out; 3915 } 3916 } 3917 3918 /* 3919 * Prevent the FW from wandering off channel during association 3920 * by "protecting" the session with a time event. 3921 */ 3922 /* XXX duration is in units of TU, not MS */ 3923 duration = IWM_MVM_TE_SESSION_PROTECTION_MAX_TIME_MS; 3924 iwm_mvm_protect_session(sc, in, duration, 500 /* XXX magic number */); 3925 DELAY(100); 3926 3927 error = 0; 3928 out: 3929 ieee80211_free_node(ni); 3930 return (error); 3931 } 3932 3933 static int 3934 iwm_assoc(struct ieee80211vap *vap, struct iwm_softc *sc) 3935 { 3936 struct iwm_node *in = IWM_NODE(vap->iv_bss); 3937 int error; 3938 3939 if ((error = iwm_mvm_update_sta(sc, in)) != 0) { 3940 device_printf(sc->sc_dev, 3941 "%s: failed to update STA\n", __func__); 3942 return error; 3943 } 3944 3945 in->in_assoc = 1; 3946 if ((error = iwm_mvm_mac_ctxt_changed(sc, vap)) != 0) { 3947 device_printf(sc->sc_dev, 3948 "%s: failed to update MAC\n", __func__); 3949 return error; 3950 } 3951 3952 return 0; 3953 } 3954 3955 static int 3956 iwm_release(struct iwm_softc *sc, struct iwm_node *in) 3957 { 3958 uint32_t tfd_msk; 3959 3960 /* 3961 * Ok, so *technically* the proper set of calls for going 3962 * from RUN back to SCAN is: 3963 * 3964 * iwm_mvm_power_mac_disable(sc, in); 3965 * iwm_mvm_mac_ctxt_changed(sc, in); 3966 * iwm_mvm_rm_sta(sc, in); 3967 * iwm_mvm_update_quotas(sc, NULL); 3968 * iwm_mvm_mac_ctxt_changed(sc, in); 3969 * iwm_mvm_binding_remove_vif(sc, in); 3970 * iwm_mvm_mac_ctxt_remove(sc, in); 3971 * 3972 * However, that freezes the device not matter which permutations 3973 * and modifications are attempted. Obviously, this driver is missing 3974 * something since it works in the Linux driver, but figuring out what 3975 * is missing is a little more complicated. Now, since we're going 3976 * back to nothing anyway, we'll just do a complete device reset. 3977 * Up your's, device! 3978 */ 3979 /* 3980 * Just using 0xf for the queues mask is fine as long as we only 3981 * get here from RUN state. 3982 */ 3983 tfd_msk = 0xf; 3984 mbufq_drain(&sc->sc_snd); 3985 iwm_mvm_flush_tx_path(sc, tfd_msk, IWM_CMD_SYNC); 3986 /* 3987 * We seem to get away with just synchronously sending the 3988 * IWM_TXPATH_FLUSH command. 3989 */ 3990 // iwm_trans_wait_tx_queue_empty(sc, tfd_msk); 3991 iwm_stop_device(sc); 3992 iwm_init_hw(sc); 3993 if (in) 3994 in->in_assoc = 0; 3995 return 0; 3996 3997 #if 0 3998 int error; 3999 4000 iwm_mvm_power_mac_disable(sc, in); 4001 4002 if ((error = iwm_mvm_mac_ctxt_changed(sc, in)) != 0) { 4003 device_printf(sc->sc_dev, "mac ctxt change fail 1 %d\n", error); 4004 return error; 4005 } 4006 4007 if ((error = iwm_mvm_rm_sta(sc, in)) != 0) { 4008 device_printf(sc->sc_dev, "sta remove fail %d\n", error); 4009 return error; 4010 } 4011 error = iwm_mvm_rm_sta(sc, in); 4012 in->in_assoc = 0; 4013 iwm_mvm_update_quotas(sc, NULL); 4014 if ((error = iwm_mvm_mac_ctxt_changed(sc, in)) != 0) { 4015 device_printf(sc->sc_dev, "mac ctxt change fail 2 %d\n", error); 4016 return error; 4017 } 4018 iwm_mvm_binding_remove_vif(sc, in); 4019 4020 iwm_mvm_mac_ctxt_remove(sc, in); 4021 4022 return error; 4023 #endif 4024 } 4025 4026 static struct ieee80211_node * 4027 iwm_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 4028 { 4029 return malloc(sizeof (struct iwm_node), M_80211_NODE, 4030 M_NOWAIT | M_ZERO); 4031 } 4032 4033 static void 4034 iwm_setrates(struct iwm_softc *sc, struct iwm_node *in) 4035 { 4036 struct ieee80211_node *ni = &in->in_ni; 4037 struct iwm_lq_cmd *lq = &in->in_lq; 4038 int nrates = ni->ni_rates.rs_nrates; 4039 int i, ridx, tab = 0; 4040 // int txant = 0; 4041 4042 if (nrates > nitems(lq->rs_table)) { 4043 device_printf(sc->sc_dev, 4044 "%s: node supports %d rates, driver handles " 4045 "only %zu\n", __func__, nrates, nitems(lq->rs_table)); 4046 return; 4047 } 4048 if (nrates == 0) { 4049 device_printf(sc->sc_dev, 4050 "%s: node supports 0 rates, odd!\n", __func__); 4051 return; 4052 } 4053 4054 /* 4055 * XXX .. and most of iwm_node is not initialised explicitly; 4056 * it's all just 0x0 passed to the firmware. 4057 */ 4058 4059 /* first figure out which rates we should support */ 4060 /* XXX TODO: this isn't 11n aware /at all/ */ 4061 memset(&in->in_ridx, -1, sizeof(in->in_ridx)); 4062 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 4063 "%s: nrates=%d\n", __func__, nrates); 4064 4065 /* 4066 * Loop over nrates and populate in_ridx from the highest 4067 * rate to the lowest rate. Remember, in_ridx[] has 4068 * IEEE80211_RATE_MAXSIZE entries! 4069 */ 4070 for (i = 0; i < min(nrates, IEEE80211_RATE_MAXSIZE); i++) { 4071 int rate = ni->ni_rates.rs_rates[(nrates - 1) - i] & IEEE80211_RATE_VAL; 4072 4073 /* Map 802.11 rate to HW rate index. */ 4074 for (ridx = 0; ridx <= IWM_RIDX_MAX; ridx++) 4075 if (iwm_rates[ridx].rate == rate) 4076 break; 4077 if (ridx > IWM_RIDX_MAX) { 4078 device_printf(sc->sc_dev, 4079 "%s: WARNING: device rate for %d not found!\n", 4080 __func__, rate); 4081 } else { 4082 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 4083 "%s: rate: i: %d, rate=%d, ridx=%d\n", 4084 __func__, 4085 i, 4086 rate, 4087 ridx); 4088 in->in_ridx[i] = ridx; 4089 } 4090 } 4091 4092 /* then construct a lq_cmd based on those */ 4093 memset(lq, 0, sizeof(*lq)); 4094 lq->sta_id = IWM_STATION_ID; 4095 4096 /* For HT, always enable RTS/CTS to avoid excessive retries. */ 4097 if (ni->ni_flags & IEEE80211_NODE_HT) 4098 lq->flags |= IWM_LQ_FLAG_USE_RTS_MSK; 4099 4100 /* 4101 * are these used? (we don't do SISO or MIMO) 4102 * need to set them to non-zero, though, or we get an error. 4103 */ 4104 lq->single_stream_ant_msk = 1; 4105 lq->dual_stream_ant_msk = 1; 4106 4107 /* 4108 * Build the actual rate selection table. 4109 * The lowest bits are the rates. Additionally, 4110 * CCK needs bit 9 to be set. The rest of the bits 4111 * we add to the table select the tx antenna 4112 * Note that we add the rates in the highest rate first 4113 * (opposite of ni_rates). 4114 */ 4115 /* 4116 * XXX TODO: this should be looping over the min of nrates 4117 * and LQ_MAX_RETRY_NUM. Sigh. 4118 */ 4119 for (i = 0; i < nrates; i++) { 4120 int nextant; 4121 4122 #if 0 4123 if (txant == 0) 4124 txant = iwm_fw_valid_tx_ant(sc); 4125 nextant = 1<<(ffs(txant)-1); 4126 txant &= ~nextant; 4127 #else 4128 nextant = iwm_fw_valid_tx_ant(sc); 4129 #endif 4130 /* 4131 * Map the rate id into a rate index into 4132 * our hardware table containing the 4133 * configuration to use for this rate. 4134 */ 4135 ridx = in->in_ridx[i]; 4136 tab = iwm_rates[ridx].plcp; 4137 tab |= nextant << IWM_RATE_MCS_ANT_POS; 4138 if (IWM_RIDX_IS_CCK(ridx)) 4139 tab |= IWM_RATE_MCS_CCK_MSK; 4140 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 4141 "station rate i=%d, rate=%d, hw=%x\n", 4142 i, iwm_rates[ridx].rate, tab); 4143 lq->rs_table[i] = htole32(tab); 4144 } 4145 /* then fill the rest with the lowest possible rate */ 4146 for (i = nrates; i < nitems(lq->rs_table); i++) { 4147 KASSERT(tab != 0, ("invalid tab")); 4148 lq->rs_table[i] = htole32(tab); 4149 } 4150 } 4151 4152 static int 4153 iwm_media_change(struct ifnet *ifp) 4154 { 4155 struct ieee80211vap *vap = ifp->if_softc; 4156 struct ieee80211com *ic = vap->iv_ic; 4157 struct iwm_softc *sc = ic->ic_softc; 4158 int error; 4159 4160 error = ieee80211_media_change(ifp); 4161 if (error != ENETRESET) 4162 return error; 4163 4164 IWM_LOCK(sc); 4165 if (ic->ic_nrunning > 0) { 4166 iwm_stop(sc); 4167 iwm_init(sc); 4168 } 4169 IWM_UNLOCK(sc); 4170 return error; 4171 } 4172 4173 4174 static int 4175 iwm_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4176 { 4177 struct iwm_vap *ivp = IWM_VAP(vap); 4178 struct ieee80211com *ic = vap->iv_ic; 4179 struct iwm_softc *sc = ic->ic_softc; 4180 struct iwm_node *in; 4181 int error; 4182 4183 IWM_DPRINTF(sc, IWM_DEBUG_STATE, 4184 "switching state %s -> %s\n", 4185 ieee80211_state_name[vap->iv_state], 4186 ieee80211_state_name[nstate]); 4187 IEEE80211_UNLOCK(ic); 4188 IWM_LOCK(sc); 4189 4190 if (vap->iv_state == IEEE80211_S_SCAN && nstate != vap->iv_state) 4191 iwm_led_blink_stop(sc); 4192 4193 /* disable beacon filtering if we're hopping out of RUN */ 4194 if (vap->iv_state == IEEE80211_S_RUN && nstate != vap->iv_state) { 4195 iwm_mvm_disable_beacon_filter(sc); 4196 4197 if (((in = IWM_NODE(vap->iv_bss)) != NULL)) 4198 in->in_assoc = 0; 4199 4200 if (nstate == IEEE80211_S_INIT) { 4201 IWM_UNLOCK(sc); 4202 IEEE80211_LOCK(ic); 4203 error = ivp->iv_newstate(vap, nstate, arg); 4204 IEEE80211_UNLOCK(ic); 4205 IWM_LOCK(sc); 4206 iwm_release(sc, NULL); 4207 IWM_UNLOCK(sc); 4208 IEEE80211_LOCK(ic); 4209 return error; 4210 } 4211 4212 /* 4213 * It's impossible to directly go RUN->SCAN. If we iwm_release() 4214 * above then the card will be completely reinitialized, 4215 * so the driver must do everything necessary to bring the card 4216 * from INIT to SCAN. 4217 * 4218 * Additionally, upon receiving deauth frame from AP, 4219 * OpenBSD 802.11 stack puts the driver in IEEE80211_S_AUTH 4220 * state. This will also fail with this driver, so bring the FSM 4221 * from IEEE80211_S_RUN to IEEE80211_S_SCAN in this case as well. 4222 * 4223 * XXX TODO: fix this for FreeBSD! 4224 */ 4225 if (nstate == IEEE80211_S_SCAN || 4226 nstate == IEEE80211_S_AUTH || 4227 nstate == IEEE80211_S_ASSOC) { 4228 IWM_DPRINTF(sc, IWM_DEBUG_STATE, 4229 "Force transition to INIT; MGT=%d\n", arg); 4230 IWM_UNLOCK(sc); 4231 IEEE80211_LOCK(ic); 4232 /* Always pass arg as -1 since we can't Tx right now. */ 4233 /* 4234 * XXX arg is just ignored anyway when transitioning 4235 * to IEEE80211_S_INIT. 4236 */ 4237 vap->iv_newstate(vap, IEEE80211_S_INIT, -1); 4238 IWM_DPRINTF(sc, IWM_DEBUG_STATE, 4239 "Going INIT->SCAN\n"); 4240 nstate = IEEE80211_S_SCAN; 4241 IEEE80211_UNLOCK(ic); 4242 IWM_LOCK(sc); 4243 } 4244 } 4245 4246 switch (nstate) { 4247 case IEEE80211_S_INIT: 4248 break; 4249 4250 case IEEE80211_S_AUTH: 4251 if ((error = iwm_auth(vap, sc)) != 0) { 4252 device_printf(sc->sc_dev, 4253 "%s: could not move to auth state: %d\n", 4254 __func__, error); 4255 break; 4256 } 4257 break; 4258 4259 case IEEE80211_S_ASSOC: 4260 if ((error = iwm_assoc(vap, sc)) != 0) { 4261 device_printf(sc->sc_dev, 4262 "%s: failed to associate: %d\n", __func__, 4263 error); 4264 break; 4265 } 4266 break; 4267 4268 case IEEE80211_S_RUN: 4269 { 4270 struct iwm_host_cmd cmd = { 4271 .id = IWM_LQ_CMD, 4272 .len = { sizeof(in->in_lq), }, 4273 .flags = IWM_CMD_SYNC, 4274 }; 4275 4276 /* Update the association state, now we have it all */ 4277 /* (eg associd comes in at this point */ 4278 error = iwm_assoc(vap, sc); 4279 if (error != 0) { 4280 device_printf(sc->sc_dev, 4281 "%s: failed to update association state: %d\n", 4282 __func__, 4283 error); 4284 break; 4285 } 4286 4287 in = IWM_NODE(vap->iv_bss); 4288 iwm_mvm_power_mac_update_mode(sc, in); 4289 iwm_mvm_enable_beacon_filter(sc, in); 4290 iwm_mvm_update_quotas(sc, in); 4291 iwm_setrates(sc, in); 4292 4293 cmd.data[0] = &in->in_lq; 4294 if ((error = iwm_send_cmd(sc, &cmd)) != 0) { 4295 device_printf(sc->sc_dev, 4296 "%s: IWM_LQ_CMD failed\n", __func__); 4297 } 4298 4299 iwm_mvm_led_enable(sc); 4300 break; 4301 } 4302 4303 default: 4304 break; 4305 } 4306 IWM_UNLOCK(sc); 4307 IEEE80211_LOCK(ic); 4308 4309 return (ivp->iv_newstate(vap, nstate, arg)); 4310 } 4311 4312 void 4313 iwm_endscan_cb(void *arg, int pending) 4314 { 4315 struct iwm_softc *sc = arg; 4316 struct ieee80211com *ic = &sc->sc_ic; 4317 4318 IWM_DPRINTF(sc, IWM_DEBUG_SCAN | IWM_DEBUG_TRACE, 4319 "%s: scan ended\n", 4320 __func__); 4321 4322 ieee80211_scan_done(TAILQ_FIRST(&ic->ic_vaps)); 4323 } 4324 4325 /* 4326 * Aging and idle timeouts for the different possible scenarios 4327 * in default configuration 4328 */ 4329 static const uint32_t 4330 iwm_sf_full_timeout_def[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES] = { 4331 { 4332 htole32(IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF), 4333 htole32(IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF) 4334 }, 4335 { 4336 htole32(IWM_SF_AGG_UNICAST_AGING_TIMER_DEF), 4337 htole32(IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF) 4338 }, 4339 { 4340 htole32(IWM_SF_MCAST_AGING_TIMER_DEF), 4341 htole32(IWM_SF_MCAST_IDLE_TIMER_DEF) 4342 }, 4343 { 4344 htole32(IWM_SF_BA_AGING_TIMER_DEF), 4345 htole32(IWM_SF_BA_IDLE_TIMER_DEF) 4346 }, 4347 { 4348 htole32(IWM_SF_TX_RE_AGING_TIMER_DEF), 4349 htole32(IWM_SF_TX_RE_IDLE_TIMER_DEF) 4350 }, 4351 }; 4352 4353 /* 4354 * Aging and idle timeouts for the different possible scenarios 4355 * in single BSS MAC configuration. 4356 */ 4357 static const uint32_t 4358 iwm_sf_full_timeout[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES] = { 4359 { 4360 htole32(IWM_SF_SINGLE_UNICAST_AGING_TIMER), 4361 htole32(IWM_SF_SINGLE_UNICAST_IDLE_TIMER) 4362 }, 4363 { 4364 htole32(IWM_SF_AGG_UNICAST_AGING_TIMER), 4365 htole32(IWM_SF_AGG_UNICAST_IDLE_TIMER) 4366 }, 4367 { 4368 htole32(IWM_SF_MCAST_AGING_TIMER), 4369 htole32(IWM_SF_MCAST_IDLE_TIMER) 4370 }, 4371 { 4372 htole32(IWM_SF_BA_AGING_TIMER), 4373 htole32(IWM_SF_BA_IDLE_TIMER) 4374 }, 4375 { 4376 htole32(IWM_SF_TX_RE_AGING_TIMER), 4377 htole32(IWM_SF_TX_RE_IDLE_TIMER) 4378 }, 4379 }; 4380 4381 static void 4382 iwm_mvm_fill_sf_command(struct iwm_softc *sc, struct iwm_sf_cfg_cmd *sf_cmd, 4383 struct ieee80211_node *ni) 4384 { 4385 int i, j, watermark; 4386 4387 sf_cmd->watermark[IWM_SF_LONG_DELAY_ON] = htole32(IWM_SF_W_MARK_SCAN); 4388 4389 /* 4390 * If we are in association flow - check antenna configuration 4391 * capabilities of the AP station, and choose the watermark accordingly. 4392 */ 4393 if (ni) { 4394 if (ni->ni_flags & IEEE80211_NODE_HT) { 4395 #ifdef notyet 4396 if (ni->ni_rxmcs[2] != 0) 4397 watermark = IWM_SF_W_MARK_MIMO3; 4398 else if (ni->ni_rxmcs[1] != 0) 4399 watermark = IWM_SF_W_MARK_MIMO2; 4400 else 4401 #endif 4402 watermark = IWM_SF_W_MARK_SISO; 4403 } else { 4404 watermark = IWM_SF_W_MARK_LEGACY; 4405 } 4406 /* default watermark value for unassociated mode. */ 4407 } else { 4408 watermark = IWM_SF_W_MARK_MIMO2; 4409 } 4410 sf_cmd->watermark[IWM_SF_FULL_ON] = htole32(watermark); 4411 4412 for (i = 0; i < IWM_SF_NUM_SCENARIO; i++) { 4413 for (j = 0; j < IWM_SF_NUM_TIMEOUT_TYPES; j++) { 4414 sf_cmd->long_delay_timeouts[i][j] = 4415 htole32(IWM_SF_LONG_DELAY_AGING_TIMER); 4416 } 4417 } 4418 4419 if (ni) { 4420 memcpy(sf_cmd->full_on_timeouts, iwm_sf_full_timeout, 4421 sizeof(iwm_sf_full_timeout)); 4422 } else { 4423 memcpy(sf_cmd->full_on_timeouts, iwm_sf_full_timeout_def, 4424 sizeof(iwm_sf_full_timeout_def)); 4425 } 4426 } 4427 4428 static int 4429 iwm_mvm_sf_config(struct iwm_softc *sc, enum iwm_sf_state new_state) 4430 { 4431 struct ieee80211com *ic = &sc->sc_ic; 4432 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4433 struct iwm_sf_cfg_cmd sf_cmd = { 4434 .state = htole32(IWM_SF_FULL_ON), 4435 }; 4436 int ret = 0; 4437 4438 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) 4439 sf_cmd.state |= htole32(IWM_SF_CFG_DUMMY_NOTIF_OFF); 4440 4441 switch (new_state) { 4442 case IWM_SF_UNINIT: 4443 case IWM_SF_INIT_OFF: 4444 iwm_mvm_fill_sf_command(sc, &sf_cmd, NULL); 4445 break; 4446 case IWM_SF_FULL_ON: 4447 iwm_mvm_fill_sf_command(sc, &sf_cmd, vap->iv_bss); 4448 break; 4449 default: 4450 IWM_DPRINTF(sc, IWM_DEBUG_PWRSAVE, 4451 "Invalid state: %d. not sending Smart Fifo cmd\n", 4452 new_state); 4453 return EINVAL; 4454 } 4455 4456 ret = iwm_mvm_send_cmd_pdu(sc, IWM_REPLY_SF_CFG_CMD, IWM_CMD_ASYNC, 4457 sizeof(sf_cmd), &sf_cmd); 4458 return ret; 4459 } 4460 4461 static int 4462 iwm_send_bt_init_conf(struct iwm_softc *sc) 4463 { 4464 struct iwm_bt_coex_cmd bt_cmd; 4465 4466 bt_cmd.mode = htole32(IWM_BT_COEX_WIFI); 4467 bt_cmd.enabled_modules = htole32(IWM_BT_COEX_HIGH_BAND_RET); 4468 4469 return iwm_mvm_send_cmd_pdu(sc, IWM_BT_CONFIG, 0, sizeof(bt_cmd), 4470 &bt_cmd); 4471 } 4472 4473 static int 4474 iwm_send_update_mcc_cmd(struct iwm_softc *sc, const char *alpha2) 4475 { 4476 struct iwm_mcc_update_cmd mcc_cmd; 4477 struct iwm_host_cmd hcmd = { 4478 .id = IWM_MCC_UPDATE_CMD, 4479 .flags = (IWM_CMD_SYNC | IWM_CMD_WANT_SKB), 4480 .data = { &mcc_cmd }, 4481 }; 4482 int ret; 4483 #ifdef IWM_DEBUG 4484 struct iwm_rx_packet *pkt; 4485 struct iwm_mcc_update_resp_v1 *mcc_resp_v1 = NULL; 4486 struct iwm_mcc_update_resp *mcc_resp; 4487 int n_channels; 4488 uint16_t mcc; 4489 #endif 4490 int resp_v2 = isset(sc->sc_enabled_capa, 4491 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2); 4492 4493 memset(&mcc_cmd, 0, sizeof(mcc_cmd)); 4494 mcc_cmd.mcc = htole16(alpha2[0] << 8 | alpha2[1]); 4495 if ((sc->sc_ucode_api & IWM_UCODE_TLV_API_WIFI_MCC_UPDATE) || 4496 isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC)) 4497 mcc_cmd.source_id = IWM_MCC_SOURCE_GET_CURRENT; 4498 else 4499 mcc_cmd.source_id = IWM_MCC_SOURCE_OLD_FW; 4500 4501 if (resp_v2) 4502 hcmd.len[0] = sizeof(struct iwm_mcc_update_cmd); 4503 else 4504 hcmd.len[0] = sizeof(struct iwm_mcc_update_cmd_v1); 4505 4506 IWM_DPRINTF(sc, IWM_DEBUG_NODE, 4507 "send MCC update to FW with '%c%c' src = %d\n", 4508 alpha2[0], alpha2[1], mcc_cmd.source_id); 4509 4510 ret = iwm_send_cmd(sc, &hcmd); 4511 if (ret) 4512 return ret; 4513 4514 #ifdef IWM_DEBUG 4515 pkt = hcmd.resp_pkt; 4516 4517 /* Extract MCC response */ 4518 if (resp_v2) { 4519 mcc_resp = (void *)pkt->data; 4520 mcc = mcc_resp->mcc; 4521 n_channels = le32toh(mcc_resp->n_channels); 4522 } else { 4523 mcc_resp_v1 = (void *)pkt->data; 4524 mcc = mcc_resp_v1->mcc; 4525 n_channels = le32toh(mcc_resp_v1->n_channels); 4526 } 4527 4528 /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ 4529 if (mcc == 0) 4530 mcc = 0x3030; /* "00" - world */ 4531 4532 IWM_DPRINTF(sc, IWM_DEBUG_NODE, 4533 "regulatory domain '%c%c' (%d channels available)\n", 4534 mcc >> 8, mcc & 0xff, n_channels); 4535 #endif 4536 iwm_free_resp(sc, &hcmd); 4537 4538 return 0; 4539 } 4540 4541 static void 4542 iwm_mvm_tt_tx_backoff(struct iwm_softc *sc, uint32_t backoff) 4543 { 4544 struct iwm_host_cmd cmd = { 4545 .id = IWM_REPLY_THERMAL_MNG_BACKOFF, 4546 .len = { sizeof(uint32_t), }, 4547 .data = { &backoff, }, 4548 }; 4549 4550 if (iwm_send_cmd(sc, &cmd) != 0) { 4551 device_printf(sc->sc_dev, 4552 "failed to change thermal tx backoff\n"); 4553 } 4554 } 4555 4556 static int 4557 iwm_init_hw(struct iwm_softc *sc) 4558 { 4559 struct ieee80211com *ic = &sc->sc_ic; 4560 int error, i, ac; 4561 4562 if ((error = iwm_start_hw(sc)) != 0) { 4563 printf("iwm_start_hw: failed %d\n", error); 4564 return error; 4565 } 4566 4567 if ((error = iwm_run_init_mvm_ucode(sc, 0)) != 0) { 4568 printf("iwm_run_init_mvm_ucode: failed %d\n", error); 4569 return error; 4570 } 4571 4572 /* 4573 * should stop and start HW since that INIT 4574 * image just loaded 4575 */ 4576 iwm_stop_device(sc); 4577 if ((error = iwm_start_hw(sc)) != 0) { 4578 device_printf(sc->sc_dev, "could not initialize hardware\n"); 4579 return error; 4580 } 4581 4582 /* omstart, this time with the regular firmware */ 4583 error = iwm_mvm_load_ucode_wait_alive(sc, IWM_UCODE_TYPE_REGULAR); 4584 if (error) { 4585 device_printf(sc->sc_dev, "could not load firmware\n"); 4586 goto error; 4587 } 4588 4589 if ((error = iwm_send_bt_init_conf(sc)) != 0) { 4590 device_printf(sc->sc_dev, "bt init conf failed\n"); 4591 goto error; 4592 } 4593 4594 if ((error = iwm_send_tx_ant_cfg(sc, iwm_fw_valid_tx_ant(sc))) != 0) { 4595 device_printf(sc->sc_dev, "antenna config failed\n"); 4596 goto error; 4597 } 4598 4599 /* Send phy db control command and then phy db calibration*/ 4600 if ((error = iwm_send_phy_db_data(sc)) != 0) { 4601 device_printf(sc->sc_dev, "phy_db_data failed\n"); 4602 goto error; 4603 } 4604 4605 if ((error = iwm_send_phy_cfg_cmd(sc)) != 0) { 4606 device_printf(sc->sc_dev, "phy_cfg_cmd failed\n"); 4607 goto error; 4608 } 4609 4610 /* Add auxiliary station for scanning */ 4611 if ((error = iwm_mvm_add_aux_sta(sc)) != 0) { 4612 device_printf(sc->sc_dev, "add_aux_sta failed\n"); 4613 goto error; 4614 } 4615 4616 for (i = 0; i < IWM_NUM_PHY_CTX; i++) { 4617 /* 4618 * The channel used here isn't relevant as it's 4619 * going to be overwritten in the other flows. 4620 * For now use the first channel we have. 4621 */ 4622 if ((error = iwm_mvm_phy_ctxt_add(sc, 4623 &sc->sc_phyctxt[i], &ic->ic_channels[1], 1, 1)) != 0) 4624 goto error; 4625 } 4626 4627 /* Initialize tx backoffs to the minimum. */ 4628 if (sc->sc_device_family == IWM_DEVICE_FAMILY_7000) 4629 iwm_mvm_tt_tx_backoff(sc, 0); 4630 4631 error = iwm_mvm_power_update_device(sc); 4632 if (error) 4633 goto error; 4634 4635 if (isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_LAR_SUPPORT)) { 4636 if ((error = iwm_send_update_mcc_cmd(sc, "ZZ")) != 0) 4637 goto error; 4638 } 4639 4640 if (isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_UMAC_SCAN)) { 4641 if ((error = iwm_mvm_config_umac_scan(sc)) != 0) 4642 goto error; 4643 } 4644 4645 /* Enable Tx queues. */ 4646 for (ac = 0; ac < WME_NUM_AC; ac++) { 4647 error = iwm_enable_txq(sc, IWM_STATION_ID, ac, 4648 iwm_mvm_ac_to_tx_fifo[ac]); 4649 if (error) 4650 goto error; 4651 } 4652 4653 if ((error = iwm_mvm_disable_beacon_filter(sc)) != 0) { 4654 device_printf(sc->sc_dev, "failed to disable beacon filter\n"); 4655 goto error; 4656 } 4657 4658 return 0; 4659 4660 error: 4661 iwm_stop_device(sc); 4662 return error; 4663 } 4664 4665 /* Allow multicast from our BSSID. */ 4666 static int 4667 iwm_allow_mcast(struct ieee80211vap *vap, struct iwm_softc *sc) 4668 { 4669 struct ieee80211_node *ni = vap->iv_bss; 4670 struct iwm_mcast_filter_cmd *cmd; 4671 size_t size; 4672 int error; 4673 4674 size = roundup(sizeof(*cmd), 4); 4675 cmd = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 4676 if (cmd == NULL) 4677 return ENOMEM; 4678 cmd->filter_own = 1; 4679 cmd->port_id = 0; 4680 cmd->count = 0; 4681 cmd->pass_all = 1; 4682 IEEE80211_ADDR_COPY(cmd->bssid, ni->ni_bssid); 4683 4684 error = iwm_mvm_send_cmd_pdu(sc, IWM_MCAST_FILTER_CMD, 4685 IWM_CMD_SYNC, size, cmd); 4686 free(cmd, M_DEVBUF); 4687 4688 return (error); 4689 } 4690 4691 /* 4692 * ifnet interfaces 4693 */ 4694 4695 static void 4696 iwm_init(struct iwm_softc *sc) 4697 { 4698 int error; 4699 4700 if (sc->sc_flags & IWM_FLAG_HW_INITED) { 4701 return; 4702 } 4703 sc->sc_generation++; 4704 sc->sc_flags &= ~IWM_FLAG_STOPPED; 4705 4706 if ((error = iwm_init_hw(sc)) != 0) { 4707 printf("iwm_init_hw failed %d\n", error); 4708 iwm_stop(sc); 4709 return; 4710 } 4711 4712 /* 4713 * Ok, firmware loaded and we are jogging 4714 */ 4715 sc->sc_flags |= IWM_FLAG_HW_INITED; 4716 callout_reset(&sc->sc_watchdog_to, hz, iwm_watchdog, sc); 4717 } 4718 4719 static int 4720 iwm_transmit(struct ieee80211com *ic, struct mbuf *m) 4721 { 4722 struct iwm_softc *sc; 4723 int error; 4724 4725 sc = ic->ic_softc; 4726 4727 IWM_LOCK(sc); 4728 if ((sc->sc_flags & IWM_FLAG_HW_INITED) == 0) { 4729 IWM_UNLOCK(sc); 4730 return (ENXIO); 4731 } 4732 error = mbufq_enqueue(&sc->sc_snd, m); 4733 if (error) { 4734 IWM_UNLOCK(sc); 4735 return (error); 4736 } 4737 iwm_start(sc); 4738 IWM_UNLOCK(sc); 4739 return (0); 4740 } 4741 4742 /* 4743 * Dequeue packets from sendq and call send. 4744 */ 4745 static void 4746 iwm_start(struct iwm_softc *sc) 4747 { 4748 struct ieee80211_node *ni; 4749 struct mbuf *m; 4750 int ac = 0; 4751 4752 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TRACE, "->%s\n", __func__); 4753 while (sc->qfullmsk == 0 && 4754 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 4755 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4756 if (iwm_tx(sc, m, ni, ac) != 0) { 4757 if_inc_counter(ni->ni_vap->iv_ifp, 4758 IFCOUNTER_OERRORS, 1); 4759 ieee80211_free_node(ni); 4760 continue; 4761 } 4762 sc->sc_tx_timer = 15; 4763 } 4764 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TRACE, "<-%s\n", __func__); 4765 } 4766 4767 static void 4768 iwm_stop(struct iwm_softc *sc) 4769 { 4770 4771 sc->sc_flags &= ~IWM_FLAG_HW_INITED; 4772 sc->sc_flags |= IWM_FLAG_STOPPED; 4773 sc->sc_generation++; 4774 iwm_led_blink_stop(sc); 4775 sc->sc_tx_timer = 0; 4776 iwm_stop_device(sc); 4777 } 4778 4779 static void 4780 iwm_watchdog(void *arg) 4781 { 4782 struct iwm_softc *sc = arg; 4783 struct ieee80211com *ic = &sc->sc_ic; 4784 4785 if (sc->sc_tx_timer > 0) { 4786 if (--sc->sc_tx_timer == 0) { 4787 device_printf(sc->sc_dev, "device timeout\n"); 4788 #ifdef IWM_DEBUG 4789 iwm_nic_error(sc); 4790 #endif 4791 ieee80211_restart_all(ic); 4792 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 4793 return; 4794 } 4795 } 4796 callout_reset(&sc->sc_watchdog_to, hz, iwm_watchdog, sc); 4797 } 4798 4799 static void 4800 iwm_parent(struct ieee80211com *ic) 4801 { 4802 struct iwm_softc *sc = ic->ic_softc; 4803 int startall = 0; 4804 4805 IWM_LOCK(sc); 4806 if (ic->ic_nrunning > 0) { 4807 if (!(sc->sc_flags & IWM_FLAG_HW_INITED)) { 4808 iwm_init(sc); 4809 startall = 1; 4810 } 4811 } else if (sc->sc_flags & IWM_FLAG_HW_INITED) 4812 iwm_stop(sc); 4813 IWM_UNLOCK(sc); 4814 if (startall) 4815 ieee80211_start_all(ic); 4816 } 4817 4818 /* 4819 * The interrupt side of things 4820 */ 4821 4822 /* 4823 * error dumping routines are from iwlwifi/mvm/utils.c 4824 */ 4825 4826 /* 4827 * Note: This structure is read from the device with IO accesses, 4828 * and the reading already does the endian conversion. As it is 4829 * read with uint32_t-sized accesses, any members with a different size 4830 * need to be ordered correctly though! 4831 */ 4832 struct iwm_error_event_table { 4833 uint32_t valid; /* (nonzero) valid, (0) log is empty */ 4834 uint32_t error_id; /* type of error */ 4835 uint32_t trm_hw_status0; /* TRM HW status */ 4836 uint32_t trm_hw_status1; /* TRM HW status */ 4837 uint32_t blink2; /* branch link */ 4838 uint32_t ilink1; /* interrupt link */ 4839 uint32_t ilink2; /* interrupt link */ 4840 uint32_t data1; /* error-specific data */ 4841 uint32_t data2; /* error-specific data */ 4842 uint32_t data3; /* error-specific data */ 4843 uint32_t bcon_time; /* beacon timer */ 4844 uint32_t tsf_low; /* network timestamp function timer */ 4845 uint32_t tsf_hi; /* network timestamp function timer */ 4846 uint32_t gp1; /* GP1 timer register */ 4847 uint32_t gp2; /* GP2 timer register */ 4848 uint32_t fw_rev_type; /* firmware revision type */ 4849 uint32_t major; /* uCode version major */ 4850 uint32_t minor; /* uCode version minor */ 4851 uint32_t hw_ver; /* HW Silicon version */ 4852 uint32_t brd_ver; /* HW board version */ 4853 uint32_t log_pc; /* log program counter */ 4854 uint32_t frame_ptr; /* frame pointer */ 4855 uint32_t stack_ptr; /* stack pointer */ 4856 uint32_t hcmd; /* last host command header */ 4857 uint32_t isr0; /* isr status register LMPM_NIC_ISR0: 4858 * rxtx_flag */ 4859 uint32_t isr1; /* isr status register LMPM_NIC_ISR1: 4860 * host_flag */ 4861 uint32_t isr2; /* isr status register LMPM_NIC_ISR2: 4862 * enc_flag */ 4863 uint32_t isr3; /* isr status register LMPM_NIC_ISR3: 4864 * time_flag */ 4865 uint32_t isr4; /* isr status register LMPM_NIC_ISR4: 4866 * wico interrupt */ 4867 uint32_t last_cmd_id; /* last HCMD id handled by the firmware */ 4868 uint32_t wait_event; /* wait event() caller address */ 4869 uint32_t l2p_control; /* L2pControlField */ 4870 uint32_t l2p_duration; /* L2pDurationField */ 4871 uint32_t l2p_mhvalid; /* L2pMhValidBits */ 4872 uint32_t l2p_addr_match; /* L2pAddrMatchStat */ 4873 uint32_t lmpm_pmg_sel; /* indicate which clocks are turned on 4874 * (LMPM_PMG_SEL) */ 4875 uint32_t u_timestamp; /* indicate when the date and time of the 4876 * compilation */ 4877 uint32_t flow_handler; /* FH read/write pointers, RX credit */ 4878 } __packed /* LOG_ERROR_TABLE_API_S_VER_3 */; 4879 4880 /* 4881 * UMAC error struct - relevant starting from family 8000 chip. 4882 * Note: This structure is read from the device with IO accesses, 4883 * and the reading already does the endian conversion. As it is 4884 * read with u32-sized accesses, any members with a different size 4885 * need to be ordered correctly though! 4886 */ 4887 struct iwm_umac_error_event_table { 4888 uint32_t valid; /* (nonzero) valid, (0) log is empty */ 4889 uint32_t error_id; /* type of error */ 4890 uint32_t blink1; /* branch link */ 4891 uint32_t blink2; /* branch link */ 4892 uint32_t ilink1; /* interrupt link */ 4893 uint32_t ilink2; /* interrupt link */ 4894 uint32_t data1; /* error-specific data */ 4895 uint32_t data2; /* error-specific data */ 4896 uint32_t data3; /* error-specific data */ 4897 uint32_t umac_major; 4898 uint32_t umac_minor; 4899 uint32_t frame_pointer; /* core register 27*/ 4900 uint32_t stack_pointer; /* core register 28 */ 4901 uint32_t cmd_header; /* latest host cmd sent to UMAC */ 4902 uint32_t nic_isr_pref; /* ISR status register */ 4903 } __packed; 4904 4905 #define ERROR_START_OFFSET (1 * sizeof(uint32_t)) 4906 #define ERROR_ELEM_SIZE (7 * sizeof(uint32_t)) 4907 4908 #ifdef IWM_DEBUG 4909 struct { 4910 const char *name; 4911 uint8_t num; 4912 } advanced_lookup[] = { 4913 { "NMI_INTERRUPT_WDG", 0x34 }, 4914 { "SYSASSERT", 0x35 }, 4915 { "UCODE_VERSION_MISMATCH", 0x37 }, 4916 { "BAD_COMMAND", 0x38 }, 4917 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, 4918 { "FATAL_ERROR", 0x3D }, 4919 { "NMI_TRM_HW_ERR", 0x46 }, 4920 { "NMI_INTERRUPT_TRM", 0x4C }, 4921 { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, 4922 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, 4923 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, 4924 { "NMI_INTERRUPT_HOST", 0x66 }, 4925 { "NMI_INTERRUPT_ACTION_PT", 0x7C }, 4926 { "NMI_INTERRUPT_UNKNOWN", 0x84 }, 4927 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, 4928 { "ADVANCED_SYSASSERT", 0 }, 4929 }; 4930 4931 static const char * 4932 iwm_desc_lookup(uint32_t num) 4933 { 4934 int i; 4935 4936 for (i = 0; i < nitems(advanced_lookup) - 1; i++) 4937 if (advanced_lookup[i].num == num) 4938 return advanced_lookup[i].name; 4939 4940 /* No entry matches 'num', so it is the last: ADVANCED_SYSASSERT */ 4941 return advanced_lookup[i].name; 4942 } 4943 4944 static void 4945 iwm_nic_umac_error(struct iwm_softc *sc) 4946 { 4947 struct iwm_umac_error_event_table table; 4948 uint32_t base; 4949 4950 base = sc->sc_uc.uc_umac_error_event_table; 4951 4952 if (base < 0x800000) { 4953 device_printf(sc->sc_dev, "Invalid error log pointer 0x%08x\n", 4954 base); 4955 return; 4956 } 4957 4958 if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) { 4959 device_printf(sc->sc_dev, "reading errlog failed\n"); 4960 return; 4961 } 4962 4963 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 4964 device_printf(sc->sc_dev, "Start UMAC Error Log Dump:\n"); 4965 device_printf(sc->sc_dev, "Status: 0x%x, count: %d\n", 4966 sc->sc_flags, table.valid); 4967 } 4968 4969 device_printf(sc->sc_dev, "0x%08X | %s\n", table.error_id, 4970 iwm_desc_lookup(table.error_id)); 4971 device_printf(sc->sc_dev, "0x%08X | umac branchlink1\n", table.blink1); 4972 device_printf(sc->sc_dev, "0x%08X | umac branchlink2\n", table.blink2); 4973 device_printf(sc->sc_dev, "0x%08X | umac interruptlink1\n", 4974 table.ilink1); 4975 device_printf(sc->sc_dev, "0x%08X | umac interruptlink2\n", 4976 table.ilink2); 4977 device_printf(sc->sc_dev, "0x%08X | umac data1\n", table.data1); 4978 device_printf(sc->sc_dev, "0x%08X | umac data2\n", table.data2); 4979 device_printf(sc->sc_dev, "0x%08X | umac data3\n", table.data3); 4980 device_printf(sc->sc_dev, "0x%08X | umac major\n", table.umac_major); 4981 device_printf(sc->sc_dev, "0x%08X | umac minor\n", table.umac_minor); 4982 device_printf(sc->sc_dev, "0x%08X | frame pointer\n", 4983 table.frame_pointer); 4984 device_printf(sc->sc_dev, "0x%08X | stack pointer\n", 4985 table.stack_pointer); 4986 device_printf(sc->sc_dev, "0x%08X | last host cmd\n", table.cmd_header); 4987 device_printf(sc->sc_dev, "0x%08X | isr status reg\n", 4988 table.nic_isr_pref); 4989 } 4990 4991 /* 4992 * Support for dumping the error log seemed like a good idea ... 4993 * but it's mostly hex junk and the only sensible thing is the 4994 * hw/ucode revision (which we know anyway). Since it's here, 4995 * I'll just leave it in, just in case e.g. the Intel guys want to 4996 * help us decipher some "ADVANCED_SYSASSERT" later. 4997 */ 4998 static void 4999 iwm_nic_error(struct iwm_softc *sc) 5000 { 5001 struct iwm_error_event_table table; 5002 uint32_t base; 5003 5004 device_printf(sc->sc_dev, "dumping device error log\n"); 5005 base = sc->sc_uc.uc_error_event_table; 5006 if (base < 0x800000) { 5007 device_printf(sc->sc_dev, 5008 "Invalid error log pointer 0x%08x\n", base); 5009 return; 5010 } 5011 5012 if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) { 5013 device_printf(sc->sc_dev, "reading errlog failed\n"); 5014 return; 5015 } 5016 5017 if (!table.valid) { 5018 device_printf(sc->sc_dev, "errlog not found, skipping\n"); 5019 return; 5020 } 5021 5022 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 5023 device_printf(sc->sc_dev, "Start Error Log Dump:\n"); 5024 device_printf(sc->sc_dev, "Status: 0x%x, count: %d\n", 5025 sc->sc_flags, table.valid); 5026 } 5027 5028 device_printf(sc->sc_dev, "0x%08X | %-28s\n", table.error_id, 5029 iwm_desc_lookup(table.error_id)); 5030 device_printf(sc->sc_dev, "%08X | trm_hw_status0\n", 5031 table.trm_hw_status0); 5032 device_printf(sc->sc_dev, "%08X | trm_hw_status1\n", 5033 table.trm_hw_status1); 5034 device_printf(sc->sc_dev, "%08X | branchlink2\n", table.blink2); 5035 device_printf(sc->sc_dev, "%08X | interruptlink1\n", table.ilink1); 5036 device_printf(sc->sc_dev, "%08X | interruptlink2\n", table.ilink2); 5037 device_printf(sc->sc_dev, "%08X | data1\n", table.data1); 5038 device_printf(sc->sc_dev, "%08X | data2\n", table.data2); 5039 device_printf(sc->sc_dev, "%08X | data3\n", table.data3); 5040 device_printf(sc->sc_dev, "%08X | beacon time\n", table.bcon_time); 5041 device_printf(sc->sc_dev, "%08X | tsf low\n", table.tsf_low); 5042 device_printf(sc->sc_dev, "%08X | tsf hi\n", table.tsf_hi); 5043 device_printf(sc->sc_dev, "%08X | time gp1\n", table.gp1); 5044 device_printf(sc->sc_dev, "%08X | time gp2\n", table.gp2); 5045 device_printf(sc->sc_dev, "%08X | uCode revision type\n", 5046 table.fw_rev_type); 5047 device_printf(sc->sc_dev, "%08X | uCode version major\n", table.major); 5048 device_printf(sc->sc_dev, "%08X | uCode version minor\n", table.minor); 5049 device_printf(sc->sc_dev, "%08X | hw version\n", table.hw_ver); 5050 device_printf(sc->sc_dev, "%08X | board version\n", table.brd_ver); 5051 device_printf(sc->sc_dev, "%08X | hcmd\n", table.hcmd); 5052 device_printf(sc->sc_dev, "%08X | isr0\n", table.isr0); 5053 device_printf(sc->sc_dev, "%08X | isr1\n", table.isr1); 5054 device_printf(sc->sc_dev, "%08X | isr2\n", table.isr2); 5055 device_printf(sc->sc_dev, "%08X | isr3\n", table.isr3); 5056 device_printf(sc->sc_dev, "%08X | isr4\n", table.isr4); 5057 device_printf(sc->sc_dev, "%08X | last cmd Id\n", table.last_cmd_id); 5058 device_printf(sc->sc_dev, "%08X | wait_event\n", table.wait_event); 5059 device_printf(sc->sc_dev, "%08X | l2p_control\n", table.l2p_control); 5060 device_printf(sc->sc_dev, "%08X | l2p_duration\n", table.l2p_duration); 5061 device_printf(sc->sc_dev, "%08X | l2p_mhvalid\n", table.l2p_mhvalid); 5062 device_printf(sc->sc_dev, "%08X | l2p_addr_match\n", table.l2p_addr_match); 5063 device_printf(sc->sc_dev, "%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel); 5064 device_printf(sc->sc_dev, "%08X | timestamp\n", table.u_timestamp); 5065 device_printf(sc->sc_dev, "%08X | flow_handler\n", table.flow_handler); 5066 5067 if (sc->sc_uc.uc_umac_error_event_table) 5068 iwm_nic_umac_error(sc); 5069 } 5070 #endif 5071 5072 #define SYNC_RESP_STRUCT(_var_, _pkt_) \ 5073 do { \ 5074 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);\ 5075 _var_ = (void *)((_pkt_)+1); \ 5076 } while (/*CONSTCOND*/0) 5077 5078 #define SYNC_RESP_PTR(_ptr_, _len_, _pkt_) \ 5079 do { \ 5080 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);\ 5081 _ptr_ = (void *)((_pkt_)+1); \ 5082 } while (/*CONSTCOND*/0) 5083 5084 #define ADVANCE_RXQ(sc) (sc->rxq.cur = (sc->rxq.cur + 1) % IWM_RX_RING_COUNT); 5085 5086 /* 5087 * Process an IWM_CSR_INT_BIT_FH_RX or IWM_CSR_INT_BIT_SW_RX interrupt. 5088 * Basic structure from if_iwn 5089 */ 5090 static void 5091 iwm_notif_intr(struct iwm_softc *sc) 5092 { 5093 struct ieee80211com *ic = &sc->sc_ic; 5094 uint16_t hw; 5095 5096 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 5097 BUS_DMASYNC_POSTREAD); 5098 5099 hw = le16toh(sc->rxq.stat->closed_rb_num) & 0xfff; 5100 5101 /* 5102 * Process responses 5103 */ 5104 while (sc->rxq.cur != hw) { 5105 struct iwm_rx_ring *ring = &sc->rxq; 5106 struct iwm_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 5107 struct iwm_rx_packet *pkt; 5108 struct iwm_cmd_response *cresp; 5109 int qid, idx, code; 5110 5111 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 5112 BUS_DMASYNC_POSTREAD); 5113 pkt = mtod(data->m, struct iwm_rx_packet *); 5114 5115 qid = pkt->hdr.qid & ~0x80; 5116 idx = pkt->hdr.idx; 5117 5118 code = IWM_WIDE_ID(pkt->hdr.flags, pkt->hdr.code); 5119 IWM_DPRINTF(sc, IWM_DEBUG_INTR, 5120 "rx packet qid=%d idx=%d type=%x %d %d\n", 5121 pkt->hdr.qid & ~0x80, pkt->hdr.idx, code, sc->rxq.cur, hw); 5122 5123 /* 5124 * randomly get these from the firmware, no idea why. 5125 * they at least seem harmless, so just ignore them for now 5126 */ 5127 if (__predict_false((pkt->hdr.code == 0 && qid == 0 && idx == 0) 5128 || pkt->len_n_flags == htole32(0x55550000))) { 5129 ADVANCE_RXQ(sc); 5130 continue; 5131 } 5132 5133 switch (code) { 5134 case IWM_REPLY_RX_PHY_CMD: 5135 iwm_mvm_rx_rx_phy_cmd(sc, pkt, data); 5136 break; 5137 5138 case IWM_REPLY_RX_MPDU_CMD: 5139 iwm_mvm_rx_rx_mpdu(sc, pkt, data); 5140 break; 5141 5142 case IWM_TX_CMD: 5143 iwm_mvm_rx_tx_cmd(sc, pkt, data); 5144 break; 5145 5146 case IWM_MISSED_BEACONS_NOTIFICATION: { 5147 struct iwm_missed_beacons_notif *resp; 5148 int missed; 5149 5150 /* XXX look at mac_id to determine interface ID */ 5151 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5152 5153 SYNC_RESP_STRUCT(resp, pkt); 5154 missed = le32toh(resp->consec_missed_beacons); 5155 5156 IWM_DPRINTF(sc, IWM_DEBUG_BEACON | IWM_DEBUG_STATE, 5157 "%s: MISSED_BEACON: mac_id=%d, " 5158 "consec_since_last_rx=%d, consec=%d, num_expect=%d " 5159 "num_rx=%d\n", 5160 __func__, 5161 le32toh(resp->mac_id), 5162 le32toh(resp->consec_missed_beacons_since_last_rx), 5163 le32toh(resp->consec_missed_beacons), 5164 le32toh(resp->num_expected_beacons), 5165 le32toh(resp->num_recvd_beacons)); 5166 5167 /* Be paranoid */ 5168 if (vap == NULL) 5169 break; 5170 5171 /* XXX no net80211 locking? */ 5172 if (vap->iv_state == IEEE80211_S_RUN && 5173 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 5174 if (missed > vap->iv_bmissthreshold) { 5175 /* XXX bad locking; turn into task */ 5176 IWM_UNLOCK(sc); 5177 ieee80211_beacon_miss(ic); 5178 IWM_LOCK(sc); 5179 } 5180 } 5181 5182 break; } 5183 5184 case IWM_MFUART_LOAD_NOTIFICATION: 5185 break; 5186 5187 case IWM_MVM_ALIVE: { 5188 struct iwm_mvm_alive_resp_v1 *resp1; 5189 struct iwm_mvm_alive_resp_v2 *resp2; 5190 struct iwm_mvm_alive_resp_v3 *resp3; 5191 5192 if (iwm_rx_packet_payload_len(pkt) == sizeof(*resp1)) { 5193 SYNC_RESP_STRUCT(resp1, pkt); 5194 sc->sc_uc.uc_error_event_table 5195 = le32toh(resp1->error_event_table_ptr); 5196 sc->sc_uc.uc_log_event_table 5197 = le32toh(resp1->log_event_table_ptr); 5198 sc->sched_base = le32toh(resp1->scd_base_ptr); 5199 if (resp1->status == IWM_ALIVE_STATUS_OK) 5200 sc->sc_uc.uc_ok = 1; 5201 else 5202 sc->sc_uc.uc_ok = 0; 5203 } 5204 5205 if (iwm_rx_packet_payload_len(pkt) == sizeof(*resp2)) { 5206 SYNC_RESP_STRUCT(resp2, pkt); 5207 sc->sc_uc.uc_error_event_table 5208 = le32toh(resp2->error_event_table_ptr); 5209 sc->sc_uc.uc_log_event_table 5210 = le32toh(resp2->log_event_table_ptr); 5211 sc->sched_base = le32toh(resp2->scd_base_ptr); 5212 sc->sc_uc.uc_umac_error_event_table 5213 = le32toh(resp2->error_info_addr); 5214 if (resp2->status == IWM_ALIVE_STATUS_OK) 5215 sc->sc_uc.uc_ok = 1; 5216 else 5217 sc->sc_uc.uc_ok = 0; 5218 } 5219 5220 if (iwm_rx_packet_payload_len(pkt) == sizeof(*resp3)) { 5221 SYNC_RESP_STRUCT(resp3, pkt); 5222 sc->sc_uc.uc_error_event_table 5223 = le32toh(resp3->error_event_table_ptr); 5224 sc->sc_uc.uc_log_event_table 5225 = le32toh(resp3->log_event_table_ptr); 5226 sc->sched_base = le32toh(resp3->scd_base_ptr); 5227 sc->sc_uc.uc_umac_error_event_table 5228 = le32toh(resp3->error_info_addr); 5229 if (resp3->status == IWM_ALIVE_STATUS_OK) 5230 sc->sc_uc.uc_ok = 1; 5231 else 5232 sc->sc_uc.uc_ok = 0; 5233 } 5234 5235 sc->sc_uc.uc_intr = 1; 5236 wakeup(&sc->sc_uc); 5237 break; } 5238 5239 case IWM_CALIB_RES_NOTIF_PHY_DB: { 5240 struct iwm_calib_res_notif_phy_db *phy_db_notif; 5241 SYNC_RESP_STRUCT(phy_db_notif, pkt); 5242 5243 iwm_phy_db_set_section(sc, phy_db_notif); 5244 5245 break; } 5246 5247 case IWM_STATISTICS_NOTIFICATION: { 5248 struct iwm_notif_statistics *stats; 5249 SYNC_RESP_STRUCT(stats, pkt); 5250 memcpy(&sc->sc_stats, stats, sizeof(sc->sc_stats)); 5251 sc->sc_noise = iwm_get_noise(sc, &stats->rx.general); 5252 break; } 5253 5254 case IWM_NVM_ACCESS_CMD: 5255 case IWM_MCC_UPDATE_CMD: 5256 if (sc->sc_wantresp == ((qid << 16) | idx)) { 5257 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 5258 BUS_DMASYNC_POSTREAD); 5259 memcpy(sc->sc_cmd_resp, 5260 pkt, sizeof(sc->sc_cmd_resp)); 5261 } 5262 break; 5263 5264 case IWM_MCC_CHUB_UPDATE_CMD: { 5265 struct iwm_mcc_chub_notif *notif; 5266 SYNC_RESP_STRUCT(notif, pkt); 5267 5268 sc->sc_fw_mcc[0] = (notif->mcc & 0xff00) >> 8; 5269 sc->sc_fw_mcc[1] = notif->mcc & 0xff; 5270 sc->sc_fw_mcc[2] = '\0'; 5271 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 5272 "fw source %d sent CC '%s'\n", 5273 notif->source_id, sc->sc_fw_mcc); 5274 break; } 5275 5276 case IWM_DTS_MEASUREMENT_NOTIFICATION: 5277 break; 5278 5279 case IWM_PHY_CONFIGURATION_CMD: 5280 case IWM_TX_ANT_CONFIGURATION_CMD: 5281 case IWM_ADD_STA: 5282 case IWM_MAC_CONTEXT_CMD: 5283 case IWM_REPLY_SF_CFG_CMD: 5284 case IWM_POWER_TABLE_CMD: 5285 case IWM_PHY_CONTEXT_CMD: 5286 case IWM_BINDING_CONTEXT_CMD: 5287 case IWM_TIME_EVENT_CMD: 5288 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_CFG_CMD): 5289 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_REQ_UMAC): 5290 case IWM_SCAN_OFFLOAD_REQUEST_CMD: 5291 case IWM_REPLY_BEACON_FILTERING_CMD: 5292 case IWM_MAC_PM_POWER_TABLE: 5293 case IWM_TIME_QUOTA_CMD: 5294 case IWM_REMOVE_STA: 5295 case IWM_TXPATH_FLUSH: 5296 case IWM_LQ_CMD: 5297 case IWM_BT_CONFIG: 5298 case IWM_REPLY_THERMAL_MNG_BACKOFF: 5299 SYNC_RESP_STRUCT(cresp, pkt); 5300 if (sc->sc_wantresp == ((qid << 16) | idx)) { 5301 memcpy(sc->sc_cmd_resp, 5302 pkt, sizeof(*pkt)+sizeof(*cresp)); 5303 } 5304 break; 5305 5306 /* ignore */ 5307 case 0x6c: /* IWM_PHY_DB_CMD, no idea why it's not in fw-api.h */ 5308 break; 5309 5310 case IWM_INIT_COMPLETE_NOTIF: 5311 sc->sc_init_complete = 1; 5312 wakeup(&sc->sc_init_complete); 5313 break; 5314 5315 case IWM_SCAN_OFFLOAD_COMPLETE: { 5316 struct iwm_periodic_scan_complete *notif; 5317 SYNC_RESP_STRUCT(notif, pkt); 5318 break; 5319 } 5320 5321 case IWM_SCAN_ITERATION_COMPLETE: { 5322 struct iwm_lmac_scan_complete_notif *notif; 5323 SYNC_RESP_STRUCT(notif, pkt); 5324 ieee80211_runtask(&sc->sc_ic, &sc->sc_es_task); 5325 break; 5326 } 5327 5328 case IWM_SCAN_COMPLETE_UMAC: { 5329 struct iwm_umac_scan_complete *notif; 5330 SYNC_RESP_STRUCT(notif, pkt); 5331 5332 IWM_DPRINTF(sc, IWM_DEBUG_SCAN, 5333 "UMAC scan complete, status=0x%x\n", 5334 notif->status); 5335 #if 0 /* XXX This would be a duplicate scan end call */ 5336 taskqueue_enqueue(sc->sc_tq, &sc->sc_es_task); 5337 #endif 5338 break; 5339 } 5340 5341 case IWM_SCAN_ITERATION_COMPLETE_UMAC: { 5342 struct iwm_umac_scan_iter_complete_notif *notif; 5343 SYNC_RESP_STRUCT(notif, pkt); 5344 5345 IWM_DPRINTF(sc, IWM_DEBUG_SCAN, "UMAC scan iteration " 5346 "complete, status=0x%x, %d channels scanned\n", 5347 notif->status, notif->scanned_channels); 5348 ieee80211_runtask(&sc->sc_ic, &sc->sc_es_task); 5349 break; 5350 } 5351 5352 case IWM_REPLY_ERROR: { 5353 struct iwm_error_resp *resp; 5354 SYNC_RESP_STRUCT(resp, pkt); 5355 5356 device_printf(sc->sc_dev, 5357 "firmware error 0x%x, cmd 0x%x\n", 5358 le32toh(resp->error_type), 5359 resp->cmd_id); 5360 break; 5361 } 5362 5363 case IWM_TIME_EVENT_NOTIFICATION: { 5364 struct iwm_time_event_notif *notif; 5365 SYNC_RESP_STRUCT(notif, pkt); 5366 5367 IWM_DPRINTF(sc, IWM_DEBUG_INTR, 5368 "TE notif status = 0x%x action = 0x%x\n", 5369 notif->status, notif->action); 5370 break; 5371 } 5372 5373 case IWM_MCAST_FILTER_CMD: 5374 break; 5375 5376 case IWM_SCD_QUEUE_CFG: { 5377 struct iwm_scd_txq_cfg_rsp *rsp; 5378 SYNC_RESP_STRUCT(rsp, pkt); 5379 5380 IWM_DPRINTF(sc, IWM_DEBUG_CMD, 5381 "queue cfg token=0x%x sta_id=%d " 5382 "tid=%d scd_queue=%d\n", 5383 rsp->token, rsp->sta_id, rsp->tid, 5384 rsp->scd_queue); 5385 break; 5386 } 5387 5388 default: 5389 device_printf(sc->sc_dev, 5390 "frame %d/%d %x UNHANDLED (this should " 5391 "not happen)\n", qid, idx, 5392 pkt->len_n_flags); 5393 break; 5394 } 5395 5396 /* 5397 * Why test bit 0x80? The Linux driver: 5398 * 5399 * There is one exception: uCode sets bit 15 when it 5400 * originates the response/notification, i.e. when the 5401 * response/notification is not a direct response to a 5402 * command sent by the driver. For example, uCode issues 5403 * IWM_REPLY_RX when it sends a received frame to the driver; 5404 * it is not a direct response to any driver command. 5405 * 5406 * Ok, so since when is 7 == 15? Well, the Linux driver 5407 * uses a slightly different format for pkt->hdr, and "qid" 5408 * is actually the upper byte of a two-byte field. 5409 */ 5410 if (!(pkt->hdr.qid & (1 << 7))) { 5411 iwm_cmd_done(sc, pkt); 5412 } 5413 5414 ADVANCE_RXQ(sc); 5415 } 5416 5417 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 5418 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 5419 5420 /* 5421 * Tell the firmware what we have processed. 5422 * Seems like the hardware gets upset unless we align 5423 * the write by 8?? 5424 */ 5425 hw = (hw == 0) ? IWM_RX_RING_COUNT - 1 : hw - 1; 5426 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, hw & ~7); 5427 } 5428 5429 static void 5430 iwm_intr(void *arg) 5431 { 5432 struct iwm_softc *sc = arg; 5433 int handled = 0; 5434 int r1, r2, rv = 0; 5435 int isperiodic = 0; 5436 5437 IWM_LOCK(sc); 5438 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0); 5439 5440 if (sc->sc_flags & IWM_FLAG_USE_ICT) { 5441 uint32_t *ict = sc->ict_dma.vaddr; 5442 int tmp; 5443 5444 tmp = htole32(ict[sc->ict_cur]); 5445 if (!tmp) 5446 goto out_ena; 5447 5448 /* 5449 * ok, there was something. keep plowing until we have all. 5450 */ 5451 r1 = r2 = 0; 5452 while (tmp) { 5453 r1 |= tmp; 5454 ict[sc->ict_cur] = 0; 5455 sc->ict_cur = (sc->ict_cur+1) % IWM_ICT_COUNT; 5456 tmp = htole32(ict[sc->ict_cur]); 5457 } 5458 5459 /* this is where the fun begins. don't ask */ 5460 if (r1 == 0xffffffff) 5461 r1 = 0; 5462 5463 /* i am not expected to understand this */ 5464 if (r1 & 0xc0000) 5465 r1 |= 0x8000; 5466 r1 = (0xff & r1) | ((0xff00 & r1) << 16); 5467 } else { 5468 r1 = IWM_READ(sc, IWM_CSR_INT); 5469 /* "hardware gone" (where, fishing?) */ 5470 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 5471 goto out; 5472 r2 = IWM_READ(sc, IWM_CSR_FH_INT_STATUS); 5473 } 5474 if (r1 == 0 && r2 == 0) { 5475 goto out_ena; 5476 } 5477 5478 IWM_WRITE(sc, IWM_CSR_INT, r1 | ~sc->sc_intmask); 5479 5480 /* ignored */ 5481 handled |= (r1 & (IWM_CSR_INT_BIT_ALIVE /*| IWM_CSR_INT_BIT_SCD*/)); 5482 5483 if (r1 & IWM_CSR_INT_BIT_SW_ERR) { 5484 int i; 5485 struct ieee80211com *ic = &sc->sc_ic; 5486 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5487 5488 #ifdef IWM_DEBUG 5489 iwm_nic_error(sc); 5490 #endif 5491 /* Dump driver status (TX and RX rings) while we're here. */ 5492 device_printf(sc->sc_dev, "driver status:\n"); 5493 for (i = 0; i < IWM_MVM_MAX_QUEUES; i++) { 5494 struct iwm_tx_ring *ring = &sc->txq[i]; 5495 device_printf(sc->sc_dev, 5496 " tx ring %2d: qid=%-2d cur=%-3d " 5497 "queued=%-3d\n", 5498 i, ring->qid, ring->cur, ring->queued); 5499 } 5500 device_printf(sc->sc_dev, 5501 " rx ring: cur=%d\n", sc->rxq.cur); 5502 device_printf(sc->sc_dev, 5503 " 802.11 state %d\n", (vap == NULL) ? -1 : vap->iv_state); 5504 5505 /* Don't stop the device; just do a VAP restart */ 5506 IWM_UNLOCK(sc); 5507 5508 if (vap == NULL) { 5509 printf("%s: null vap\n", __func__); 5510 return; 5511 } 5512 5513 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 5514 "restarting\n", __func__, vap->iv_state); 5515 5516 /* XXX TODO: turn this into a callout/taskqueue */ 5517 ieee80211_restart_all(ic); 5518 return; 5519 } 5520 5521 if (r1 & IWM_CSR_INT_BIT_HW_ERR) { 5522 handled |= IWM_CSR_INT_BIT_HW_ERR; 5523 device_printf(sc->sc_dev, "hardware error, stopping device\n"); 5524 iwm_stop(sc); 5525 rv = 1; 5526 goto out; 5527 } 5528 5529 /* firmware chunk loaded */ 5530 if (r1 & IWM_CSR_INT_BIT_FH_TX) { 5531 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_TX_MASK); 5532 handled |= IWM_CSR_INT_BIT_FH_TX; 5533 sc->sc_fw_chunk_done = 1; 5534 wakeup(&sc->sc_fw); 5535 } 5536 5537 if (r1 & IWM_CSR_INT_BIT_RF_KILL) { 5538 handled |= IWM_CSR_INT_BIT_RF_KILL; 5539 if (iwm_check_rfkill(sc)) { 5540 device_printf(sc->sc_dev, 5541 "%s: rfkill switch, disabling interface\n", 5542 __func__); 5543 iwm_stop(sc); 5544 } 5545 } 5546 5547 /* 5548 * The Linux driver uses periodic interrupts to avoid races. 5549 * We cargo-cult like it's going out of fashion. 5550 */ 5551 if (r1 & IWM_CSR_INT_BIT_RX_PERIODIC) { 5552 handled |= IWM_CSR_INT_BIT_RX_PERIODIC; 5553 IWM_WRITE(sc, IWM_CSR_INT, IWM_CSR_INT_BIT_RX_PERIODIC); 5554 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) == 0) 5555 IWM_WRITE_1(sc, 5556 IWM_CSR_INT_PERIODIC_REG, IWM_CSR_INT_PERIODIC_DIS); 5557 isperiodic = 1; 5558 } 5559 5560 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) || isperiodic) { 5561 handled |= (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX); 5562 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_RX_MASK); 5563 5564 iwm_notif_intr(sc); 5565 5566 /* enable periodic interrupt, see above */ 5567 if (r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX) && !isperiodic) 5568 IWM_WRITE_1(sc, IWM_CSR_INT_PERIODIC_REG, 5569 IWM_CSR_INT_PERIODIC_ENA); 5570 } 5571 5572 if (__predict_false(r1 & ~handled)) 5573 IWM_DPRINTF(sc, IWM_DEBUG_INTR, 5574 "%s: unhandled interrupts: %x\n", __func__, r1); 5575 rv = 1; 5576 5577 out_ena: 5578 iwm_restore_interrupts(sc); 5579 out: 5580 IWM_UNLOCK(sc); 5581 return; 5582 } 5583 5584 /* 5585 * Autoconf glue-sniffing 5586 */ 5587 #define PCI_VENDOR_INTEL 0x8086 5588 #define PCI_PRODUCT_INTEL_WL_3160_1 0x08b3 5589 #define PCI_PRODUCT_INTEL_WL_3160_2 0x08b4 5590 #define PCI_PRODUCT_INTEL_WL_3165_1 0x3165 5591 #define PCI_PRODUCT_INTEL_WL_3165_2 0x3166 5592 #define PCI_PRODUCT_INTEL_WL_7260_1 0x08b1 5593 #define PCI_PRODUCT_INTEL_WL_7260_2 0x08b2 5594 #define PCI_PRODUCT_INTEL_WL_7265_1 0x095a 5595 #define PCI_PRODUCT_INTEL_WL_7265_2 0x095b 5596 #define PCI_PRODUCT_INTEL_WL_8260_1 0x24f3 5597 #define PCI_PRODUCT_INTEL_WL_8260_2 0x24f4 5598 5599 static const struct iwm_devices { 5600 uint16_t device; 5601 const char *name; 5602 } iwm_devices[] = { 5603 { PCI_PRODUCT_INTEL_WL_3160_1, "Intel Dual Band Wireless AC 3160" }, 5604 { PCI_PRODUCT_INTEL_WL_3160_2, "Intel Dual Band Wireless AC 3160" }, 5605 { PCI_PRODUCT_INTEL_WL_3165_1, "Intel Dual Band Wireless AC 3165" }, 5606 { PCI_PRODUCT_INTEL_WL_3165_2, "Intel Dual Band Wireless AC 3165" }, 5607 { PCI_PRODUCT_INTEL_WL_7260_1, "Intel Dual Band Wireless AC 7260" }, 5608 { PCI_PRODUCT_INTEL_WL_7260_2, "Intel Dual Band Wireless AC 7260" }, 5609 { PCI_PRODUCT_INTEL_WL_7265_1, "Intel Dual Band Wireless AC 7265" }, 5610 { PCI_PRODUCT_INTEL_WL_7265_2, "Intel Dual Band Wireless AC 7265" }, 5611 { PCI_PRODUCT_INTEL_WL_8260_1, "Intel Dual Band Wireless AC 8260" }, 5612 { PCI_PRODUCT_INTEL_WL_8260_2, "Intel Dual Band Wireless AC 8260" }, 5613 }; 5614 5615 static int 5616 iwm_probe(device_t dev) 5617 { 5618 int i; 5619 5620 for (i = 0; i < nitems(iwm_devices); i++) { 5621 if (pci_get_vendor(dev) == PCI_VENDOR_INTEL && 5622 pci_get_device(dev) == iwm_devices[i].device) { 5623 device_set_desc(dev, iwm_devices[i].name); 5624 return (BUS_PROBE_DEFAULT); 5625 } 5626 } 5627 5628 return (ENXIO); 5629 } 5630 5631 static int 5632 iwm_dev_check(device_t dev) 5633 { 5634 struct iwm_softc *sc; 5635 5636 sc = device_get_softc(dev); 5637 5638 sc->sc_hw_rev = IWM_READ(sc, IWM_CSR_HW_REV); 5639 switch (pci_get_device(dev)) { 5640 case PCI_PRODUCT_INTEL_WL_3160_1: 5641 case PCI_PRODUCT_INTEL_WL_3160_2: 5642 sc->sc_fwname = "iwm3160fw"; 5643 sc->host_interrupt_operation_mode = 1; 5644 sc->sc_device_family = IWM_DEVICE_FAMILY_7000; 5645 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ; 5646 return (0); 5647 case PCI_PRODUCT_INTEL_WL_3165_1: 5648 case PCI_PRODUCT_INTEL_WL_3165_2: 5649 sc->sc_fwname = "iwm7265fw"; 5650 sc->host_interrupt_operation_mode = 0; 5651 sc->sc_device_family = IWM_DEVICE_FAMILY_7000; 5652 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ; 5653 return (0); 5654 case PCI_PRODUCT_INTEL_WL_7260_1: 5655 case PCI_PRODUCT_INTEL_WL_7260_2: 5656 sc->sc_fwname = "iwm7260fw"; 5657 sc->host_interrupt_operation_mode = 1; 5658 sc->sc_device_family = IWM_DEVICE_FAMILY_7000; 5659 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ; 5660 return (0); 5661 case PCI_PRODUCT_INTEL_WL_7265_1: 5662 case PCI_PRODUCT_INTEL_WL_7265_2: 5663 sc->sc_fwname = "iwm7265fw"; 5664 sc->host_interrupt_operation_mode = 0; 5665 sc->sc_device_family = IWM_DEVICE_FAMILY_7000; 5666 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ; 5667 return (0); 5668 case PCI_PRODUCT_INTEL_WL_8260_1: 5669 case PCI_PRODUCT_INTEL_WL_8260_2: 5670 sc->sc_fwname = "iwm8000Cfw"; 5671 sc->host_interrupt_operation_mode = 0; 5672 sc->sc_device_family = IWM_DEVICE_FAMILY_8000; 5673 sc->sc_fwdmasegsz = IWM_FWDMASEGSZ_8000; 5674 return (0); 5675 default: 5676 device_printf(dev, "unknown adapter type\n"); 5677 return ENXIO; 5678 } 5679 } 5680 5681 static int 5682 iwm_pci_attach(device_t dev) 5683 { 5684 struct iwm_softc *sc; 5685 int count, error, rid; 5686 uint16_t reg; 5687 5688 sc = device_get_softc(dev); 5689 5690 /* Clear device-specific "PCI retry timeout" register (41h). */ 5691 reg = pci_read_config(dev, 0x40, sizeof(reg)); 5692 pci_write_config(dev, 0x40, reg & ~0xff00, sizeof(reg)); 5693 5694 /* Enable bus-mastering and hardware bug workaround. */ 5695 pci_enable_busmaster(dev); 5696 reg = pci_read_config(dev, PCIR_STATUS, sizeof(reg)); 5697 /* if !MSI */ 5698 if (reg & PCIM_STATUS_INTxSTATE) { 5699 reg &= ~PCIM_STATUS_INTxSTATE; 5700 } 5701 pci_write_config(dev, PCIR_STATUS, reg, sizeof(reg)); 5702 5703 rid = PCIR_BAR(0); 5704 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 5705 RF_ACTIVE); 5706 if (sc->sc_mem == NULL) { 5707 device_printf(sc->sc_dev, "can't map mem space\n"); 5708 return (ENXIO); 5709 } 5710 sc->sc_st = rman_get_bustag(sc->sc_mem); 5711 sc->sc_sh = rman_get_bushandle(sc->sc_mem); 5712 5713 /* Install interrupt handler. */ 5714 count = 1; 5715 rid = 0; 5716 if (pci_alloc_msi(dev, &count) == 0) 5717 rid = 1; 5718 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 5719 (rid != 0 ? 0 : RF_SHAREABLE)); 5720 if (sc->sc_irq == NULL) { 5721 device_printf(dev, "can't map interrupt\n"); 5722 return (ENXIO); 5723 } 5724 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 5725 NULL, iwm_intr, sc, &sc->sc_ih); 5726 if (sc->sc_ih == NULL) { 5727 device_printf(dev, "can't establish interrupt"); 5728 return (ENXIO); 5729 } 5730 sc->sc_dmat = bus_get_dma_tag(sc->sc_dev); 5731 5732 return (0); 5733 } 5734 5735 static void 5736 iwm_pci_detach(device_t dev) 5737 { 5738 struct iwm_softc *sc = device_get_softc(dev); 5739 5740 if (sc->sc_irq != NULL) { 5741 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 5742 bus_release_resource(dev, SYS_RES_IRQ, 5743 rman_get_rid(sc->sc_irq), sc->sc_irq); 5744 pci_release_msi(dev); 5745 } 5746 if (sc->sc_mem != NULL) 5747 bus_release_resource(dev, SYS_RES_MEMORY, 5748 rman_get_rid(sc->sc_mem), sc->sc_mem); 5749 } 5750 5751 5752 5753 static int 5754 iwm_attach(device_t dev) 5755 { 5756 struct iwm_softc *sc = device_get_softc(dev); 5757 struct ieee80211com *ic = &sc->sc_ic; 5758 int error; 5759 int txq_i, i; 5760 5761 sc->sc_dev = dev; 5762 IWM_LOCK_INIT(sc); 5763 mbufq_init(&sc->sc_snd, ifqmaxlen); 5764 callout_init_mtx(&sc->sc_watchdog_to, &sc->sc_mtx, 0); 5765 callout_init_mtx(&sc->sc_led_blink_to, &sc->sc_mtx, 0); 5766 TASK_INIT(&sc->sc_es_task, 0, iwm_endscan_cb, sc); 5767 5768 /* PCI attach */ 5769 error = iwm_pci_attach(dev); 5770 if (error != 0) 5771 goto fail; 5772 5773 sc->sc_wantresp = -1; 5774 5775 /* Check device type */ 5776 error = iwm_dev_check(dev); 5777 if (error != 0) 5778 goto fail; 5779 5780 /* 5781 * We now start fiddling with the hardware 5782 */ 5783 /* 5784 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 5785 * changed, and now the revision step also includes bit 0-1 (no more 5786 * "dash" value). To keep hw_rev backwards compatible - we'll store it 5787 * in the old format. 5788 */ 5789 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) 5790 sc->sc_hw_rev = (sc->sc_hw_rev & 0xfff0) | 5791 (IWM_CSR_HW_REV_STEP(sc->sc_hw_rev << 2) << 2); 5792 5793 if (iwm_prepare_card_hw(sc) != 0) { 5794 device_printf(dev, "could not initialize hardware\n"); 5795 goto fail; 5796 } 5797 5798 if (sc->sc_device_family == IWM_DEVICE_FAMILY_8000) { 5799 int ret; 5800 uint32_t hw_step; 5801 5802 /* 5803 * In order to recognize C step the driver should read the 5804 * chip version id located at the AUX bus MISC address. 5805 */ 5806 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 5807 IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 5808 DELAY(2); 5809 5810 ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 5811 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 5812 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 5813 25000); 5814 if (!ret) { 5815 device_printf(sc->sc_dev, 5816 "Failed to wake up the nic\n"); 5817 goto fail; 5818 } 5819 5820 if (iwm_nic_lock(sc)) { 5821 hw_step = iwm_read_prph(sc, IWM_WFPM_CTRL_REG); 5822 hw_step |= IWM_ENABLE_WFPM; 5823 iwm_write_prph(sc, IWM_WFPM_CTRL_REG, hw_step); 5824 hw_step = iwm_read_prph(sc, IWM_AUX_MISC_REG); 5825 hw_step = (hw_step >> IWM_HW_STEP_LOCATION_BITS) & 0xF; 5826 if (hw_step == 0x3) 5827 sc->sc_hw_rev = (sc->sc_hw_rev & 0xFFFFFFF3) | 5828 (IWM_SILICON_C_STEP << 2); 5829 iwm_nic_unlock(sc); 5830 } else { 5831 device_printf(sc->sc_dev, "Failed to lock the nic\n"); 5832 goto fail; 5833 } 5834 } 5835 5836 /* Allocate DMA memory for firmware transfers. */ 5837 if ((error = iwm_alloc_fwmem(sc)) != 0) { 5838 device_printf(dev, "could not allocate memory for firmware\n"); 5839 goto fail; 5840 } 5841 5842 /* Allocate "Keep Warm" page. */ 5843 if ((error = iwm_alloc_kw(sc)) != 0) { 5844 device_printf(dev, "could not allocate keep warm page\n"); 5845 goto fail; 5846 } 5847 5848 /* We use ICT interrupts */ 5849 if ((error = iwm_alloc_ict(sc)) != 0) { 5850 device_printf(dev, "could not allocate ICT table\n"); 5851 goto fail; 5852 } 5853 5854 /* Allocate TX scheduler "rings". */ 5855 if ((error = iwm_alloc_sched(sc)) != 0) { 5856 device_printf(dev, "could not allocate TX scheduler rings\n"); 5857 goto fail; 5858 } 5859 5860 /* Allocate TX rings */ 5861 for (txq_i = 0; txq_i < nitems(sc->txq); txq_i++) { 5862 if ((error = iwm_alloc_tx_ring(sc, 5863 &sc->txq[txq_i], txq_i)) != 0) { 5864 device_printf(dev, 5865 "could not allocate TX ring %d\n", 5866 txq_i); 5867 goto fail; 5868 } 5869 } 5870 5871 /* Allocate RX ring. */ 5872 if ((error = iwm_alloc_rx_ring(sc, &sc->rxq)) != 0) { 5873 device_printf(dev, "could not allocate RX ring\n"); 5874 goto fail; 5875 } 5876 5877 /* Clear pending interrupts. */ 5878 IWM_WRITE(sc, IWM_CSR_INT, 0xffffffff); 5879 5880 ic->ic_softc = sc; 5881 ic->ic_name = device_get_nameunit(sc->sc_dev); 5882 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 5883 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 5884 5885 /* Set device capabilities. */ 5886 ic->ic_caps = 5887 IEEE80211_C_STA | 5888 IEEE80211_C_WPA | /* WPA/RSN */ 5889 IEEE80211_C_WME | 5890 IEEE80211_C_SHSLOT | /* short slot time supported */ 5891 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 5892 // IEEE80211_C_BGSCAN /* capable of bg scanning */ 5893 ; 5894 for (i = 0; i < nitems(sc->sc_phyctxt); i++) { 5895 sc->sc_phyctxt[i].id = i; 5896 sc->sc_phyctxt[i].color = 0; 5897 sc->sc_phyctxt[i].ref = 0; 5898 sc->sc_phyctxt[i].channel = NULL; 5899 } 5900 5901 /* Default noise floor */ 5902 sc->sc_noise = -96; 5903 5904 /* Max RSSI */ 5905 sc->sc_max_rssi = IWM_MAX_DBM - IWM_MIN_DBM; 5906 5907 sc->sc_preinit_hook.ich_func = iwm_preinit; 5908 sc->sc_preinit_hook.ich_arg = sc; 5909 if (config_intrhook_establish(&sc->sc_preinit_hook) != 0) { 5910 device_printf(dev, "config_intrhook_establish failed\n"); 5911 goto fail; 5912 } 5913 5914 #ifdef IWM_DEBUG 5915 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 5916 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "debug", 5917 CTLFLAG_RW, &sc->sc_debug, 0, "control debugging"); 5918 #endif 5919 5920 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 5921 "<-%s\n", __func__); 5922 5923 return 0; 5924 5925 /* Free allocated memory if something failed during attachment. */ 5926 fail: 5927 iwm_detach_local(sc, 0); 5928 5929 return ENXIO; 5930 } 5931 5932 static int 5933 iwm_is_valid_ether_addr(uint8_t *addr) 5934 { 5935 char zero_addr[IEEE80211_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 5936 5937 if ((addr[0] & 1) || IEEE80211_ADDR_EQ(zero_addr, addr)) 5938 return (FALSE); 5939 5940 return (TRUE); 5941 } 5942 5943 static int 5944 iwm_update_edca(struct ieee80211com *ic) 5945 { 5946 struct iwm_softc *sc = ic->ic_softc; 5947 5948 device_printf(sc->sc_dev, "%s: called\n", __func__); 5949 return (0); 5950 } 5951 5952 static void 5953 iwm_preinit(void *arg) 5954 { 5955 struct iwm_softc *sc = arg; 5956 device_t dev = sc->sc_dev; 5957 struct ieee80211com *ic = &sc->sc_ic; 5958 int error; 5959 5960 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 5961 "->%s\n", __func__); 5962 5963 IWM_LOCK(sc); 5964 if ((error = iwm_start_hw(sc)) != 0) { 5965 device_printf(dev, "could not initialize hardware\n"); 5966 IWM_UNLOCK(sc); 5967 goto fail; 5968 } 5969 5970 error = iwm_run_init_mvm_ucode(sc, 1); 5971 iwm_stop_device(sc); 5972 if (error) { 5973 IWM_UNLOCK(sc); 5974 goto fail; 5975 } 5976 device_printf(dev, 5977 "hw rev 0x%x, fw ver %s, address %s\n", 5978 sc->sc_hw_rev & IWM_CSR_HW_REV_TYPE_MSK, 5979 sc->sc_fwver, ether_sprintf(sc->sc_nvm.hw_addr)); 5980 5981 /* not all hardware can do 5GHz band */ 5982 if (!sc->sc_nvm.sku_cap_band_52GHz_enable) 5983 memset(&ic->ic_sup_rates[IEEE80211_MODE_11A], 0, 5984 sizeof(ic->ic_sup_rates[IEEE80211_MODE_11A])); 5985 IWM_UNLOCK(sc); 5986 5987 iwm_init_channel_map(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 5988 ic->ic_channels); 5989 5990 /* 5991 * At this point we've committed - if we fail to do setup, 5992 * we now also have to tear down the net80211 state. 5993 */ 5994 ieee80211_ifattach(ic); 5995 ic->ic_vap_create = iwm_vap_create; 5996 ic->ic_vap_delete = iwm_vap_delete; 5997 ic->ic_raw_xmit = iwm_raw_xmit; 5998 ic->ic_node_alloc = iwm_node_alloc; 5999 ic->ic_scan_start = iwm_scan_start; 6000 ic->ic_scan_end = iwm_scan_end; 6001 ic->ic_update_mcast = iwm_update_mcast; 6002 ic->ic_getradiocaps = iwm_init_channel_map; 6003 ic->ic_set_channel = iwm_set_channel; 6004 ic->ic_scan_curchan = iwm_scan_curchan; 6005 ic->ic_scan_mindwell = iwm_scan_mindwell; 6006 ic->ic_wme.wme_update = iwm_update_edca; 6007 ic->ic_parent = iwm_parent; 6008 ic->ic_transmit = iwm_transmit; 6009 iwm_radiotap_attach(sc); 6010 if (bootverbose) 6011 ieee80211_announce(ic); 6012 6013 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6014 "<-%s\n", __func__); 6015 config_intrhook_disestablish(&sc->sc_preinit_hook); 6016 6017 return; 6018 fail: 6019 config_intrhook_disestablish(&sc->sc_preinit_hook); 6020 iwm_detach_local(sc, 0); 6021 } 6022 6023 /* 6024 * Attach the interface to 802.11 radiotap. 6025 */ 6026 static void 6027 iwm_radiotap_attach(struct iwm_softc *sc) 6028 { 6029 struct ieee80211com *ic = &sc->sc_ic; 6030 6031 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6032 "->%s begin\n", __func__); 6033 ieee80211_radiotap_attach(ic, 6034 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 6035 IWM_TX_RADIOTAP_PRESENT, 6036 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 6037 IWM_RX_RADIOTAP_PRESENT); 6038 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6039 "->%s end\n", __func__); 6040 } 6041 6042 static struct ieee80211vap * 6043 iwm_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 6044 enum ieee80211_opmode opmode, int flags, 6045 const uint8_t bssid[IEEE80211_ADDR_LEN], 6046 const uint8_t mac[IEEE80211_ADDR_LEN]) 6047 { 6048 struct iwm_vap *ivp; 6049 struct ieee80211vap *vap; 6050 6051 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 6052 return NULL; 6053 ivp = malloc(sizeof(struct iwm_vap), M_80211_VAP, M_WAITOK | M_ZERO); 6054 vap = &ivp->iv_vap; 6055 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 6056 vap->iv_bmissthreshold = 10; /* override default */ 6057 /* Override with driver methods. */ 6058 ivp->iv_newstate = vap->iv_newstate; 6059 vap->iv_newstate = iwm_newstate; 6060 6061 ieee80211_ratectl_init(vap); 6062 /* Complete setup. */ 6063 ieee80211_vap_attach(vap, iwm_media_change, ieee80211_media_status, 6064 mac); 6065 ic->ic_opmode = opmode; 6066 6067 return vap; 6068 } 6069 6070 static void 6071 iwm_vap_delete(struct ieee80211vap *vap) 6072 { 6073 struct iwm_vap *ivp = IWM_VAP(vap); 6074 6075 ieee80211_ratectl_deinit(vap); 6076 ieee80211_vap_detach(vap); 6077 free(ivp, M_80211_VAP); 6078 } 6079 6080 static void 6081 iwm_scan_start(struct ieee80211com *ic) 6082 { 6083 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6084 struct iwm_softc *sc = ic->ic_softc; 6085 int error; 6086 6087 IWM_LOCK(sc); 6088 if (isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_UMAC_SCAN)) 6089 error = iwm_mvm_umac_scan(sc); 6090 else 6091 error = iwm_mvm_lmac_scan(sc); 6092 if (error != 0) { 6093 device_printf(sc->sc_dev, "could not initiate 2 GHz scan\n"); 6094 IWM_UNLOCK(sc); 6095 ieee80211_cancel_scan(vap); 6096 } else { 6097 iwm_led_blink_start(sc); 6098 IWM_UNLOCK(sc); 6099 } 6100 } 6101 6102 static void 6103 iwm_scan_end(struct ieee80211com *ic) 6104 { 6105 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6106 struct iwm_softc *sc = ic->ic_softc; 6107 6108 IWM_LOCK(sc); 6109 iwm_led_blink_stop(sc); 6110 if (vap->iv_state == IEEE80211_S_RUN) 6111 iwm_mvm_led_enable(sc); 6112 IWM_UNLOCK(sc); 6113 } 6114 6115 static void 6116 iwm_update_mcast(struct ieee80211com *ic) 6117 { 6118 } 6119 6120 static void 6121 iwm_set_channel(struct ieee80211com *ic) 6122 { 6123 } 6124 6125 static void 6126 iwm_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 6127 { 6128 } 6129 6130 static void 6131 iwm_scan_mindwell(struct ieee80211_scan_state *ss) 6132 { 6133 return; 6134 } 6135 6136 void 6137 iwm_init_task(void *arg1) 6138 { 6139 struct iwm_softc *sc = arg1; 6140 6141 IWM_LOCK(sc); 6142 while (sc->sc_flags & IWM_FLAG_BUSY) 6143 msleep(&sc->sc_flags, &sc->sc_mtx, 0, "iwmpwr", 0); 6144 sc->sc_flags |= IWM_FLAG_BUSY; 6145 iwm_stop(sc); 6146 if (sc->sc_ic.ic_nrunning > 0) 6147 iwm_init(sc); 6148 sc->sc_flags &= ~IWM_FLAG_BUSY; 6149 wakeup(&sc->sc_flags); 6150 IWM_UNLOCK(sc); 6151 } 6152 6153 static int 6154 iwm_resume(device_t dev) 6155 { 6156 struct iwm_softc *sc = device_get_softc(dev); 6157 int do_reinit = 0; 6158 uint16_t reg; 6159 6160 /* Clear device-specific "PCI retry timeout" register (41h). */ 6161 reg = pci_read_config(dev, 0x40, sizeof(reg)); 6162 pci_write_config(dev, 0x40, reg & ~0xff00, sizeof(reg)); 6163 iwm_init_task(device_get_softc(dev)); 6164 6165 IWM_LOCK(sc); 6166 if (sc->sc_flags & IWM_FLAG_SCANNING) { 6167 sc->sc_flags &= ~IWM_FLAG_SCANNING; 6168 do_reinit = 1; 6169 } 6170 IWM_UNLOCK(sc); 6171 6172 if (do_reinit) 6173 ieee80211_resume_all(&sc->sc_ic); 6174 6175 return 0; 6176 } 6177 6178 static int 6179 iwm_suspend(device_t dev) 6180 { 6181 int do_stop = 0; 6182 struct iwm_softc *sc = device_get_softc(dev); 6183 6184 do_stop = !! (sc->sc_ic.ic_nrunning > 0); 6185 6186 ieee80211_suspend_all(&sc->sc_ic); 6187 6188 if (do_stop) { 6189 IWM_LOCK(sc); 6190 iwm_stop(sc); 6191 sc->sc_flags |= IWM_FLAG_SCANNING; 6192 IWM_UNLOCK(sc); 6193 } 6194 6195 return (0); 6196 } 6197 6198 static int 6199 iwm_detach_local(struct iwm_softc *sc, int do_net80211) 6200 { 6201 struct iwm_fw_info *fw = &sc->sc_fw; 6202 device_t dev = sc->sc_dev; 6203 int i; 6204 6205 ieee80211_draintask(&sc->sc_ic, &sc->sc_es_task); 6206 6207 callout_drain(&sc->sc_led_blink_to); 6208 callout_drain(&sc->sc_watchdog_to); 6209 iwm_stop_device(sc); 6210 if (do_net80211) { 6211 ieee80211_ifdetach(&sc->sc_ic); 6212 } 6213 6214 iwm_phy_db_free(sc); 6215 6216 /* Free descriptor rings */ 6217 iwm_free_rx_ring(sc, &sc->rxq); 6218 for (i = 0; i < nitems(sc->txq); i++) 6219 iwm_free_tx_ring(sc, &sc->txq[i]); 6220 6221 /* Free firmware */ 6222 if (fw->fw_fp != NULL) 6223 iwm_fw_info_free(fw); 6224 6225 /* Free scheduler */ 6226 iwm_dma_contig_free(&sc->sched_dma); 6227 iwm_dma_contig_free(&sc->ict_dma); 6228 iwm_dma_contig_free(&sc->kw_dma); 6229 iwm_dma_contig_free(&sc->fw_dma); 6230 6231 /* Finished with the hardware - detach things */ 6232 iwm_pci_detach(dev); 6233 6234 mbufq_drain(&sc->sc_snd); 6235 IWM_LOCK_DESTROY(sc); 6236 6237 return (0); 6238 } 6239 6240 static int 6241 iwm_detach(device_t dev) 6242 { 6243 struct iwm_softc *sc = device_get_softc(dev); 6244 6245 return (iwm_detach_local(sc, 1)); 6246 } 6247 6248 static device_method_t iwm_pci_methods[] = { 6249 /* Device interface */ 6250 DEVMETHOD(device_probe, iwm_probe), 6251 DEVMETHOD(device_attach, iwm_attach), 6252 DEVMETHOD(device_detach, iwm_detach), 6253 DEVMETHOD(device_suspend, iwm_suspend), 6254 DEVMETHOD(device_resume, iwm_resume), 6255 6256 DEVMETHOD_END 6257 }; 6258 6259 static driver_t iwm_pci_driver = { 6260 "iwm", 6261 iwm_pci_methods, 6262 sizeof (struct iwm_softc) 6263 }; 6264 6265 static devclass_t iwm_devclass; 6266 6267 DRIVER_MODULE(iwm, pci, iwm_pci_driver, iwm_devclass, NULL, NULL); 6268 MODULE_DEPEND(iwm, firmware, 1, 1, 1); 6269 MODULE_DEPEND(iwm, pci, 1, 1, 1); 6270 MODULE_DEPEND(iwm, wlan, 1, 1, 1); 6271