1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define IWI_CMD_RING_COUNT 16 31 #define IWI_TX_RING_COUNT 64 32 #define IWI_RX_RING_COUNT 32 33 34 #define IWI_TX_DESC_SIZE (sizeof (struct iwi_tx_desc)) 35 #define IWI_CMD_DESC_SIZE (sizeof (struct iwi_cmd_desc)) 36 37 #define IWI_CSR_INTR 0x0008 38 #define IWI_CSR_INTR_MASK 0x000c 39 #define IWI_CSR_INDIRECT_ADDR 0x0010 40 #define IWI_CSR_INDIRECT_DATA 0x0014 41 #define IWI_CSR_AUTOINC_ADDR 0x0018 42 #define IWI_CSR_AUTOINC_DATA 0x001c 43 #define IWI_CSR_RST 0x0020 44 #define IWI_CSR_CTL 0x0024 45 #define IWI_CSR_IO 0x0030 46 #define IWI_CSR_CMD_BASE 0x0200 47 #define IWI_CSR_CMD_SIZE 0x0204 48 #define IWI_CSR_TX1_BASE 0x0208 49 #define IWI_CSR_TX1_SIZE 0x020c 50 #define IWI_CSR_TX2_BASE 0x0210 51 #define IWI_CSR_TX2_SIZE 0x0214 52 #define IWI_CSR_TX3_BASE 0x0218 53 #define IWI_CSR_TX3_SIZE 0x021c 54 #define IWI_CSR_TX4_BASE 0x0220 55 #define IWI_CSR_TX4_SIZE 0x0224 56 #define IWI_CSR_CMD_RIDX 0x0280 57 #define IWI_CSR_TX1_RIDX 0x0284 58 #define IWI_CSR_TX2_RIDX 0x0288 59 #define IWI_CSR_TX3_RIDX 0x028c 60 #define IWI_CSR_TX4_RIDX 0x0290 61 #define IWI_CSR_RX_RIDX 0x02a0 62 #define IWI_CSR_RX_BASE 0x0500 63 #define IWI_CSR_TABLE0_SIZE 0x0700 64 #define IWI_CSR_TABLE0_BASE 0x0704 65 #define IWI_CSR_NODE_BASE 0x0c0c 66 #define IWI_CSR_CMD_WIDX 0x0f80 67 #define IWI_CSR_TX1_WIDX 0x0f84 68 #define IWI_CSR_TX2_WIDX 0x0f88 69 #define IWI_CSR_TX3_WIDX 0x0f8c 70 #define IWI_CSR_TX4_WIDX 0x0f90 71 #define IWI_CSR_RX_WIDX 0x0fa0 72 #define IWI_CSR_READ_INT 0x0ff4 73 74 /* aliases */ 75 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE 76 77 /* flags for IWI_CSR_INTR */ 78 #define IWI_INTR_RX_DONE 0x00000002 79 #define IWI_INTR_CMD_DONE 0x00000800 80 #define IWI_INTR_TX1_DONE 0x00001000 81 #define IWI_INTR_TX2_DONE 0x00002000 82 #define IWI_INTR_TX3_DONE 0x00004000 83 #define IWI_INTR_TX4_DONE 0x00008000 84 #define IWI_INTR_FW_INITED 0x01000000 85 #define IWI_INTR_RADIO_OFF 0x04000000 86 #define IWI_INTR_FATAL_ERROR 0x40000000 87 #define IWI_INTR_PARITY_ERROR 0x80000000 88 89 #define IWI_INTR_MASK \ 90 (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE | IWI_INTR_TX1_DONE | \ 91 IWI_INTR_TX2_DONE | IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE | \ 92 IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \ 93 IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR) 94 95 /* flags for IWI_CSR_RST */ 96 #define IWI_RST_PRINCETON_RESET 0x00000001 97 #define IWI_RST_SOFT_RESET 0x00000080 98 #define IWI_RST_MASTER_DISABLED 0x00000100 99 #define IWI_RST_STOP_MASTER 0x00000200 100 101 /* flags for IWI_CSR_CTL */ 102 #define IWI_CTL_CLOCK_READY 0x00000001 103 #define IWI_CTL_ALLOW_STANDBY 0x00000002 104 #define IWI_CTL_INIT 0x00000004 105 106 /* flags for IWI_CSR_IO */ 107 #define IWI_IO_RADIO_ENABLED 0x00010000 108 109 /* flags for IWI_CSR_READ_INT */ 110 #define IWI_READ_INT_INIT_HOST 0x20000000 111 112 /* constants for command blocks */ 113 #define IWI_CB_DEFAULT_CTL 0x8cea0000 114 #define IWI_CB_MAXDATALEN 8191 115 116 /* supported rates */ 117 #define IWI_RATE_DS1 10 118 #define IWI_RATE_DS2 20 119 #define IWI_RATE_DS5 55 120 #define IWI_RATE_DS11 110 121 #define IWI_RATE_OFDM6 13 122 #define IWI_RATE_OFDM9 15 123 #define IWI_RATE_OFDM12 5 124 #define IWI_RATE_OFDM18 7 125 #define IWI_RATE_OFDM24 9 126 #define IWI_RATE_OFDM36 11 127 #define IWI_RATE_OFDM48 1 128 #define IWI_RATE_OFDM54 3 129 130 struct iwi_hdr { 131 uint8_t type; 132 #define IWI_HDR_TYPE_DATA 0 133 #define IWI_HDR_TYPE_COMMAND 1 134 #define IWI_HDR_TYPE_NOTIF 3 135 #define IWI_HDR_TYPE_FRAME 9 136 137 uint8_t seq; 138 uint8_t flags; 139 #define IWI_HDR_FLAG_IRQ 0x04 140 141 uint8_t reserved; 142 } __packed; 143 144 struct iwi_notif { 145 uint32_t reserved[2]; 146 uint8_t type; 147 #define IWI_NOTIF_TYPE_ASSOCIATION 10 148 #define IWI_NOTIF_TYPE_AUTHENTICATION 11 149 #define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 150 #define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 151 #define IWI_NOTIF_TYPE_BEACON 17 152 #define IWI_NOTIF_TYPE_CALIBRATION 20 153 #define IWI_NOTIF_TYPE_NOISE 25 154 155 uint8_t flags; 156 uint16_t len; 157 } __packed; 158 159 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ 160 struct iwi_notif_authentication { 161 uint8_t state; 162 #define IWI_DEAUTHENTICATED 0 163 #define IWI_AUTHENTICATED 9 164 } __packed; 165 166 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ 167 struct iwi_notif_association { 168 uint8_t state; 169 #define IWI_DEASSOCIATED 0 170 #define IWI_ASSOCIATED 12 171 172 struct ieee80211_frame frame; 173 uint16_t capinfo; 174 uint16_t status; 175 uint16_t associd; 176 } __packed; 177 178 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ 179 struct iwi_notif_scan_channel { 180 uint8_t nchan; 181 uint8_t reserved[47]; 182 } __packed; 183 184 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ 185 struct iwi_notif_scan_complete { 186 uint8_t type; 187 uint8_t nchan; 188 uint8_t status; 189 uint8_t reserved; 190 } __packed; 191 192 /* received frame header */ 193 struct iwi_frame { 194 uint32_t reserved1[2]; 195 uint8_t chan; 196 uint8_t status; 197 uint8_t rate; 198 uint8_t rssi; 199 uint8_t agc; 200 uint8_t rssi_dbm; 201 uint16_t signal; 202 uint16_t noise; 203 uint8_t antenna; 204 uint8_t control; 205 uint8_t reserved2[2]; 206 uint16_t len; 207 } __packed; 208 209 /* header for transmission */ 210 struct iwi_tx_desc { 211 struct iwi_hdr hdr; 212 uint32_t reserved1; 213 uint8_t station; 214 uint8_t reserved2[3]; 215 uint8_t cmd; 216 #define IWI_DATA_CMD_TX 0x0b 217 218 uint8_t seq; 219 uint16_t len; 220 uint8_t priority; 221 uint8_t flags; 222 #define IWI_DATA_FLAG_SHPREAMBLE 0x04 223 #define IWI_DATA_FLAG_NO_WEP 0x20 224 #define IWI_DATA_FLAG_NEED_ACK 0x80 225 226 uint8_t xflags; 227 #define IWI_DATA_XFLAG_QOS 0x10 228 229 uint8_t wep_txkey; 230 uint8_t wepkey[IEEE80211_KEYBUF_SIZE]; 231 uint8_t rate; 232 uint8_t antenna; 233 uint8_t reserved3[10]; 234 struct ieee80211_qosframe_addr4 wh; 235 uint32_t iv; 236 uint32_t eiv; 237 uint32_t nseg; 238 #define IWI_MAX_NSEG 6 239 240 uint32_t seg_addr[IWI_MAX_NSEG]; 241 uint16_t seg_len[IWI_MAX_NSEG]; 242 } __packed; 243 244 /* command */ 245 struct iwi_cmd_desc { 246 struct iwi_hdr hdr; 247 uint8_t type; 248 #define IWI_CMD_ENABLE 2 249 #define IWI_CMD_SET_CONFIG 6 250 #define IWI_CMD_SET_ESSID 8 251 #define IWI_CMD_SET_MAC_ADDRESS 11 252 #define IWI_CMD_SET_RTS_THRESHOLD 15 253 #define IWI_CMD_SET_FRAG_THRESHOLD 16 254 #define IWI_CMD_SET_POWER_MODE 17 255 #define IWI_CMD_SET_WEP_KEY 18 256 #define IWI_CMD_SCAN 20 257 #define IWI_CMD_ASSOCIATE 21 258 #define IWI_CMD_SET_RATES 22 259 #define IWI_CMD_ABORT_SCAN 23 260 #define IWI_CMD_SET_WME_PARAMS 25 261 #define IWI_CMD_SET_OPTIE 31 262 #define IWI_CMD_DISABLE 33 263 #define IWI_CMD_SET_IV 34 264 #define IWI_CMD_SET_TX_POWER 35 265 #define IWI_CMD_SET_SENSITIVITY 42 266 #define IWI_CMD_SET_WMEIE 84 267 268 uint8_t len; 269 uint16_t reserved; 270 uint8_t data[120]; 271 } __packed; 272 273 /* node information (IBSS) */ 274 struct iwi_node { 275 uint8_t bssid[IEEE80211_ADDR_LEN]; 276 uint8_t reserved[2]; 277 } __packed; 278 279 /* constants for 'mode' fields */ 280 #define IWI_MODE_11A 0 281 #define IWI_MODE_11B 1 282 #define IWI_MODE_11G 2 283 284 /* possible values for command IWI_CMD_SET_POWER_MODE */ 285 #define IWI_POWER_MODE_CAM 0 286 287 /* structure for command IWI_CMD_SET_RATES */ 288 struct iwi_rateset { 289 uint8_t mode; 290 uint8_t nrates; 291 uint8_t type; 292 #define IWI_RATESET_TYPE_NEGOCIATED 0 293 #define IWI_RATESET_TYPE_SUPPORTED 1 294 295 uint8_t reserved; 296 uint8_t rates[12]; 297 } __packed; 298 299 /* structure for command IWI_CMD_SET_TX_POWER */ 300 struct iwi_txpower { 301 uint8_t nchan; 302 uint8_t mode; 303 struct { 304 uint8_t chan; 305 uint8_t power; 306 #define IWI_TXPOWER_MAX 20 307 #define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) 308 } __packed chan[37]; 309 } __packed; 310 311 /* structure for command IWI_CMD_ASSOCIATE */ 312 struct iwi_associate { 313 uint8_t chan; 314 uint8_t auth; 315 #define IWI_AUTH_OPEN 0 316 #define IWI_AUTH_SHARED 1 317 #define IWI_AUTH_NONE 3 318 319 uint8_t type; 320 uint8_t reserved1; 321 uint16_t policy; 322 #define IWI_POLICY_WME 1 323 #define IWI_POLICY_WPA 2 324 325 uint8_t plen; 326 uint8_t mode; 327 uint8_t bssid[IEEE80211_ADDR_LEN]; 328 uint8_t tstamp[8]; 329 uint16_t capinfo; 330 uint16_t lintval; 331 uint16_t intval; 332 uint8_t dst[IEEE80211_ADDR_LEN]; 333 uint32_t reserved3; 334 uint16_t reserved4; 335 } __packed; 336 337 /* structure for command IWI_CMD_SCAN */ 338 struct iwi_scan { 339 uint8_t type; 340 #define IWI_SCAN_TYPE_PASSIVE 1 341 #define IWI_SCAN_TYPE_DIRECTED 2 342 #define IWI_SCAN_TYPE_BROADCAST 3 343 #define IWI_SCAN_TYPE_BDIRECTED 4 344 345 uint16_t dwelltime; 346 uint8_t channels[54]; 347 #define IWI_CHAN_5GHZ (0 << 6) 348 #define IWI_CHAN_2GHZ (1 << 6) 349 350 uint8_t reserved[3]; 351 } __packed; 352 353 /* structure for command IWI_CMD_SET_CONFIG */ 354 struct iwi_configuration { 355 uint8_t bluetooth_coexistence; 356 uint8_t reserved1; 357 uint8_t answer_pbreq; 358 uint8_t allow_invalid_frames; 359 uint8_t multicast_enabled; 360 uint8_t drop_unicast_unencrypted; 361 uint8_t disable_unicast_decryption; 362 uint8_t drop_multicast_unencrypted; 363 uint8_t disable_multicast_decryption; 364 uint8_t antenna; 365 uint8_t reserved2; 366 uint8_t use_protection; 367 uint8_t protection_ctsonly; 368 uint8_t enable_multicast_filtering; 369 uint8_t bluetooth_threshold; 370 uint8_t reserved4; 371 uint8_t allow_beacon_and_probe_resp; 372 uint8_t allow_mgt; 373 uint8_t noise_reported; 374 uint8_t reserved5; 375 } __packed; 376 377 /* structure for command IWI_CMD_SET_WEP_KEY */ 378 struct iwi_wep_key { 379 uint8_t cmd; 380 #define IWI_WEP_KEY_CMD_SETKEY 0x08 381 382 uint8_t seq; 383 uint8_t idx; 384 uint8_t len; 385 uint8_t key[IEEE80211_KEYBUF_SIZE]; 386 } __packed; 387 388 /* structure for command IWI_CMD_SET_WME_PARAMS */ 389 struct iwi_wme_params { 390 uint16_t cwmin[WME_NUM_AC]; 391 uint16_t cwmax[WME_NUM_AC]; 392 uint8_t aifsn[WME_NUM_AC]; 393 uint8_t acm[WME_NUM_AC]; 394 uint16_t burst[WME_NUM_AC]; 395 } __packed; 396 397 #define IWI_MEM_EEPROM_CTL 0x00300040 398 399 #define IWI_EEPROM_MAC 0x21 400 401 #define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 402 403 #define IWI_EEPROM_C (1 << 0) /* Serial Clock */ 404 #define IWI_EEPROM_S (1 << 1) /* Chip Select */ 405 #define IWI_EEPROM_D (1 << 2) /* Serial data input */ 406 #define IWI_EEPROM_Q (1 << 4) /* Serial data output */ 407 408 #define IWI_EEPROM_SHIFT_D 2 409 #define IWI_EEPROM_SHIFT_Q 4 410 411 /* 412 * control and status registers access macros 413 */ 414 #define CSR_READ_1(sc, reg) \ 415 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 416 417 #define CSR_READ_2(sc, reg) \ 418 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 419 420 #define CSR_READ_4(sc, reg) \ 421 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 422 423 #define CSR_READ_REGION_4(sc, offset, datap, count) \ 424 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 425 (datap), (count)) 426 427 #define CSR_WRITE_1(sc, reg, val) \ 428 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 429 430 #define CSR_WRITE_2(sc, reg, val) \ 431 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 432 433 #define CSR_WRITE_4(sc, reg, val) \ 434 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 435 436 #define CSR_WRITE_REGION_1(sc, offset, datap, count) \ 437 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 438 (datap), (count)) 439 440 /* 441 * indirect memory space access macros 442 */ 443 #define MEM_WRITE_1(sc, addr, val) do { \ 444 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 445 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 446 } while (/* CONSTCOND */0) 447 448 #define MEM_WRITE_2(sc, addr, val) do { \ 449 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 450 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 451 } while (/* CONSTCOND */0) 452 453 #define MEM_WRITE_4(sc, addr, val) do { \ 454 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 455 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 456 } while (/* CONSTCOND */0) 457 458 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 459 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 460 CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ 461 } while (/* CONSTCOND */0) 462 463 /* 464 * EEPROM access macro 465 */ 466 #define IWI_EEPROM_CTL(sc, val) do { \ 467 MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ 468 DELAY(IWI_EEPROM_DELAY); \ 469 } while (/* CONSTCOND */0) 470