1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 1997-2007 by Matthew Jacob 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 /* 29 * Machine Independent (well, as best as possible) register 30 * definitions for Qlogic ISP SCSI adapters. 31 */ 32 #ifndef _ISPREG_H 33 #define _ISPREG_H 34 35 /* 36 * Hardware definitions for the Qlogic ISP registers. 37 */ 38 39 /* 40 * This defines types of access to various registers. 41 * 42 * R: Read Only 43 * W: Write Only 44 * RW: Read/Write 45 * 46 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 47 * if RISC processor in ISP is paused. 48 */ 49 50 /* 51 * Offsets for various register blocks. 52 * 53 * Sad but true, different architectures have different offsets. 54 * 55 * Don't be alarmed if none of this makes sense. The original register 56 * layout set some defines in a certain pattern. Everything else has been 57 * grafted on since. For example, the ISP1080 manual will state that DMA 58 * registers start at 0x80 from the base of the register address space. 59 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 60 * to start at offset 0x60 because the DMA registers are all defined to 61 * be DMA_BLOCK+0x20 and so on. Clear? 62 */ 63 64 #define BIU_REGS_OFF 0x00 65 66 #define PCI_MBOX_REGS_OFF 0x70 67 #define PCI_MBOX_REGS2100_OFF 0x10 68 #define PCI_MBOX_REGS2300_OFF 0x40 69 #define PCI_MBOX_REGS2400_OFF 0x80 70 #define SBUS_MBOX_REGS_OFF 0x80 71 72 #define PCI_SXP_REGS_OFF 0x80 73 #define SBUS_SXP_REGS_OFF 0x200 74 75 #define PCI_RISC_REGS_OFF 0x80 76 #define SBUS_RISC_REGS_OFF 0x400 77 78 /* Bless me! Chip designers have putzed it again! */ 79 #define ISP1080_DMA_REGS_OFF 0x60 80 #define DMA_REGS_OFF 0x00 /* same as BIU block */ 81 82 #define SBUS_REGSIZE 0x450 83 #define PCI_REGSIZE 0x100 84 85 /* 86 * NB: The *_BLOCK definitions have no specific hardware meaning. 87 * They serve simply to note to the MD layer which block of 88 * registers offsets are being accessed. 89 */ 90 #define _NREG_BLKS 5 91 #define _BLK_REG_SHFT 13 92 #define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 93 #define BIU_BLOCK (0 << _BLK_REG_SHFT) 94 #define MBOX_BLOCK (1 << _BLK_REG_SHFT) 95 #define SXP_BLOCK (2 << _BLK_REG_SHFT) 96 #define RISC_BLOCK (3 << _BLK_REG_SHFT) 97 #define DMA_BLOCK (4 << _BLK_REG_SHFT) 98 99 /* 100 * Bus Interface Block Register Offsets 101 */ 102 103 #define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 104 #define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 105 #define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 106 #define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 107 #define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 108 #define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 109 #define BIU2100_CSR (BIU_BLOCK+0x6) 110 #define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 111 #define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 112 #define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 113 #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 114 /* 115 * These are specific to the 2300. 116 */ 117 #define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */ 118 #define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */ 119 #define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */ 120 #define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */ 121 122 #define BIU_R2HSTSLO (BIU_BLOCK+0x18) 123 #define BIU_R2HSTSHI (BIU_BLOCK+0x1A) 124 125 #define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */ 126 #define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */ 127 #define BIU_R2HST_ISTAT_MASK 0x3f /* intr information && status */ 128 #define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 129 #define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 130 #define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 131 #define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 132 #define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */ 133 #define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 134 #define ISPR2HST_RQST_UPDATE 0x14 /* Resquest Queue Update */ 135 #define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */ 136 #define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ 137 #define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ 138 139 /* fifo command stuff- mostly for SPI */ 140 #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 141 #define RDMA2100_CONTROL DFIFO_COMMAND 142 #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 143 144 /* 145 * Putzed DMA register layouts. 146 */ 147 #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 148 #define CDMA2100_CONTROL CDMA_CONF 149 #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 150 #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 151 #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 152 #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 153 #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 154 #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 155 #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 156 #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 157 158 #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 159 #define TDMA2100_CONTROL DDMA_CONF 160 #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 161 #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 162 #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 163 #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 164 #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 165 #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 166 #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 167 /* these are for the 1040A cards */ 168 #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 169 #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 170 171 172 /* 173 * Bus Interface Block Register Definitions 174 */ 175 /* BUS CONFIGURATION REGISTER #0 */ 176 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 177 /* BUS CONFIGURATION REGISTER #1 */ 178 179 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 180 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 181 182 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 183 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 184 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 185 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 186 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 187 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 188 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 189 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 190 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 191 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 192 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 193 194 #define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 195 #define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 196 #define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 197 198 /* ISP2100 Bus Control/Status Register */ 199 200 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 201 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 202 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 203 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 204 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 205 #define BIU2100_NVRAM_OFFSET (1 << 14) 206 #define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */ 207 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 208 #define BIU2100_SOFT_RESET 0x01 209 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 210 211 212 /* BUS CONTROL REGISTER */ 213 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 214 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 215 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 216 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 217 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 218 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 219 220 #define BIU_IMASK (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS) 221 222 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 223 #define BIU2100_ICR_ENA_FPM_INT 0x0020 224 #define BIU2100_ICR_ENA_FB_INT 0x0010 225 #define BIU2100_ICR_ENA_RISC_INT 0x0008 226 #define BIU2100_ICR_ENA_CDMA_INT 0x0004 227 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 228 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 229 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 230 231 #define BIU2100_IMASK (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS) 232 233 /* BUS STATUS REGISTER */ 234 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 235 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 236 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 237 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 238 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 239 240 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 241 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 242 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 243 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 244 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 245 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 246 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 247 248 #define INT_PENDING(isp, isr) \ 249 IS_FC(isp)? \ 250 (IS_24XX(isp)? (isr & BIU2400_ISR_RISC_INT) : (isr & BIU2100_ISR_RISC_INT)) :\ 251 (isr & BIU_ISR_RISC_INT) 252 253 #define INT_PENDING_MASK(isp) \ 254 (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \ 255 (BIU_ISR_RISC_INT)) 256 257 /* BUS SEMAPHORE REGISTER */ 258 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 259 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 260 261 /* NVRAM SEMAPHORE REGISTER */ 262 #define BIU_NVRAM_CLOCK 0x0001 263 #define BIU_NVRAM_SELECT 0x0002 264 #define BIU_NVRAM_DATAOUT 0x0004 265 #define BIU_NVRAM_DATAIN 0x0008 266 #define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */ 267 #define ISP_NVRAM_READ 6 268 269 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 270 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 271 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 272 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 273 #define DMA_DMA_DIRECTION 0x0001 /* 274 * Set DMA direction: 275 * 0 - DMA FIFO to host 276 * 1 - Host to DMA FIFO 277 */ 278 279 /* COMMAND && DATA DMA CONTROL REGISTER */ 280 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 281 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 282 * Clear FIFO and DMA Channel, 283 * reset DMA registers 284 */ 285 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 286 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 287 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 288 289 /* 290 * Variants of same for 2100 291 */ 292 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004 293 #define DMA_CNTRL2100_RESET_INT 0x0002 294 295 296 297 /* DMA STATUS REGISTER */ 298 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 299 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 300 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 301 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 302 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 303 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 304 305 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 306 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 307 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 308 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 309 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 310 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 311 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 312 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 313 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 314 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 315 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 316 317 /* DMA Status Register, pipeline status bits */ 318 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 319 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 320 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 321 * Pipeline stage 1 Loaded, 322 * stage 2 empty 323 */ 324 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 325 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 326 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 327 * Pipeline stage 1 Loaded, 328 * stage 2 empty 329 */ 330 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 331 332 /* DMA Status Register, channel status bits */ 333 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 334 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 335 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 336 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 337 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 338 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 339 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 340 341 342 /* DMA FIFO STATUS REGISTER */ 343 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 344 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 345 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 346 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 347 348 /* 349 * 2400 Interface Offsets and Register Definitions 350 * 351 * The 2400 looks quite different in terms of registers from other QLogic cards. 352 * It is getting to be a genuine pain and challenge to keep the same model 353 * for all. 354 */ 355 #define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) 356 #define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) 357 #define BIU2400_CSR (BIU_BLOCK+0x08) 358 #define BIU2400_ICR (BIU_BLOCK+0x0C) 359 #define BIU2400_ISR (BIU_BLOCK+0x10) 360 361 #define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */ 362 #define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */ 363 #define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */ 364 #define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */ 365 #define BIU2400_PRI_RQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */ 366 #define BIU2400_PRI_RSPINP (BIU_BLOCK+0x30) /* Priority Request Q Out */ 367 368 #define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */ 369 #define BIU2400_ATIO_REQINP (BIU_BLOCK+0x40) /* ATIO Queue Out */ 370 371 #define BIU2400_R2HSTSLO (BIU_BLOCK+0x44) 372 #define BIU2400_R2HSTSHI (BIU_BLOCK+0x46) 373 374 #define BIU2400_HCCR (BIU_BLOCK+0x48) 375 #define BIU2400_GPIOD (BIU_BLOCK+0x4C) 376 #define BIU2400_GPIOE (BIU_BLOCK+0x50) 377 #define BIU2400_HSEMA (BIU_BLOCK+0x58) 378 379 /* BIU2400_FLASH_ADDR definitions */ 380 #define BIU2400_FLASH_DFLAG (1 << 30) 381 382 /* BIU2400_CSR definitions */ 383 #define BIU2400_NVERR (1 << 18) 384 #define BIU2400_DMA_ACTIVE (1 << 17) /* RO */ 385 #define BIU2400_DMA_STOP (1 << 16) 386 #define BIU2400_FUNCTION (1 << 15) /* RO */ 387 #define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */ 388 #define BIU2400_CSR_64BIT (1 << 2) /* RO */ 389 #define BIU2400_FLASH_ENABLE (1 << 1) 390 #define BIU2400_SOFT_RESET (1 << 0) 391 392 /* BIU2400_ICR definitions */ 393 #define BIU2400_ICR_ENA_RISC_INT 0x8 394 #define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT) 395 396 /* BIU2400_ISR definitions */ 397 #define BIU2400_ISR_RISC_INT 0x8 398 399 #define BIU2400_R2HST_INTR BIU_R2HST_INTR 400 #define BIU2400_R2HST_PAUSED BIU_R2HST_PAUSED 401 #define BIU2400_R2HST_ISTAT_MASK 0x1f 402 /* interrupt status meanings */ 403 #define ISP2400R2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 404 #define ISP2400R2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 405 #define ISP2400R2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 406 #define ISP2400R2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 407 #define ISP2400R2HST_ASYNC_EVENT 0x12 /* Async Event */ 408 #define ISP2400R2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 409 #define ISP2400R2HST_ATIO_RSPQ_UPDATE 0x1C /* ATIO Response Queue Update */ 410 #define ISP2400R2HST_ATIO_RQST_UPDATE 0x1D /* ATIO Request Queue Update */ 411 412 /* BIU2400_HCCR definitions */ 413 414 #define HCCR_2400_CMD_NOP 0x00000000 415 #define HCCR_2400_CMD_RESET 0x10000000 416 #define HCCR_2400_CMD_CLEAR_RESET 0x20000000 417 #define HCCR_2400_CMD_PAUSE 0x30000000 418 #define HCCR_2400_CMD_RELEASE 0x40000000 419 #define HCCR_2400_CMD_SET_HOST_INT 0x50000000 420 #define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000 421 #define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000 422 423 #define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ 424 #define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ 425 #define HCCR_2400_RISC_RESET (1 << 5) /* RO */ 426 427 428 /* 429 * Mailbox Block Register Offsets 430 */ 431 432 #define INMAILBOX0 (MBOX_BLOCK+0x0) 433 #define INMAILBOX1 (MBOX_BLOCK+0x2) 434 #define INMAILBOX2 (MBOX_BLOCK+0x4) 435 #define INMAILBOX3 (MBOX_BLOCK+0x6) 436 #define INMAILBOX4 (MBOX_BLOCK+0x8) 437 #define INMAILBOX5 (MBOX_BLOCK+0xA) 438 #define INMAILBOX6 (MBOX_BLOCK+0xC) 439 #define INMAILBOX7 (MBOX_BLOCK+0xE) 440 441 #define OUTMAILBOX0 (MBOX_BLOCK+0x0) 442 #define OUTMAILBOX1 (MBOX_BLOCK+0x2) 443 #define OUTMAILBOX2 (MBOX_BLOCK+0x4) 444 #define OUTMAILBOX3 (MBOX_BLOCK+0x6) 445 #define OUTMAILBOX4 (MBOX_BLOCK+0x8) 446 #define OUTMAILBOX5 (MBOX_BLOCK+0xA) 447 #define OUTMAILBOX6 (MBOX_BLOCK+0xC) 448 #define OUTMAILBOX7 (MBOX_BLOCK+0xE) 449 450 /* 451 * Strictly speaking, it's 452 * SCSI && 2100 : 8 MBOX registers 453 * 2200: 24 MBOX registers 454 * 2300/2400: 32 MBOX registers 455 */ 456 #define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 457 #define NMBOX(isp) \ 458 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 459 ((isp)->isp_type & ISP_HA_FC))? 12 : 6) 460 #define NMBOX_BMASK(isp) \ 461 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 462 ((isp)->isp_type & ISP_HA_FC))? 0xfff : 0x3f) 463 464 #define MAX_MAILBOX(isp) ((IS_FC(isp))? 12 : 8) 465 #define MAILBOX_STORAGE 12 466 /* if timeout == 0, then default timeout is picked */ 467 #define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */ 468 typedef struct { 469 uint16_t param[MAILBOX_STORAGE]; 470 uint16_t ibits; 471 uint16_t obits; 472 uint32_t : 28, 473 logval : 4; 474 uint32_t timeout; 475 } mbreg_t; 476 477 /* 478 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). 479 * NB: The RISC processor must be paused and the appropriate register 480 * bank selected via BIU2100_CSR bits. 481 */ 482 483 #define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) 484 #define FPM_SOFT_RESET 0x0100 485 486 #define FBM_CMD (BIU_BLOCK + 0xB8) 487 #define FBMCMD_FIFO_RESET_ALL 0xA000 488 489 490 /* 491 * SXP Block Register Offsets 492 */ 493 #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 494 #define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 495 #define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 496 #define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 497 #define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 498 #define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 499 #define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 500 #define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 501 #define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 502 #define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 503 #define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 504 #define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 505 #define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 506 #define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 507 #define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 508 #define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 509 #define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 510 #define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 511 #define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 512 #define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 513 #define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 514 #define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 515 #define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 516 #define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 517 #define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 518 #define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 519 #define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 520 #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 521 #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 522 #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 523 #define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 524 #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 525 #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 526 #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 527 #define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 528 #define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 529 #define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 530 #define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 531 #define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 532 533 /* for 1080/1280/1240 only */ 534 #define SXP_BANK1_SELECT 0x100 535 536 537 /* SXP CONF1 REGISTER */ 538 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 539 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 540 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 541 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 542 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 543 544 /* SXP CONF2 REGISTER */ 545 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 546 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 547 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 548 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 549 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 550 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 551 552 /* SXP INTERRUPT REGISTER */ 553 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 554 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 555 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 556 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 557 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 558 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 559 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 560 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 561 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 562 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 563 564 565 /* SXP GROSS ERROR REGISTER */ 566 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 567 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 568 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 569 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 570 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 571 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 572 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 573 574 /* SXP EXCEPTION REGISTER */ 575 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 576 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 577 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 578 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 579 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 580 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 581 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 582 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 583 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 584 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 585 586 /* SXP OVERRIDE REGISTER */ 587 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 588 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 589 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 590 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 591 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 592 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 593 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 594 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 595 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 596 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 597 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 598 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 599 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 600 601 /* SXP COMMANDS */ 602 #define SXP_RESET_BUS_CMD 0x300b 603 604 /* SXP SCSI ID REGISTER */ 605 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 606 #define SXP_SELECT_ID 0x000F /* Select id */ 607 608 /* SXP DEV CONFIG1 REGISTER */ 609 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 610 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 611 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 612 613 614 /* SXP DEV CONFIG2 REGISTER */ 615 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 616 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 617 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 618 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 619 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 620 621 622 /* SXP PHASE POINTER REGISTER */ 623 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 624 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 625 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 626 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 627 628 629 /* SXP FIFO STATUS REGISTER */ 630 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 631 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 632 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 633 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 634 635 636 /* SXP CONTROL PINS REGISTER */ 637 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 638 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 639 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 640 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 641 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 642 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 643 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 644 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 645 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 646 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 647 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 648 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 649 650 /* 651 * Set the hold time for the SCSI Bus Reset to be 250 ms 652 */ 653 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 654 655 /* SXP DIFF PINS REGISTER */ 656 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 657 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 658 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 659 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 660 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 661 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 662 663 /* Ultra2 only */ 664 #define SXP_PINS_LVD_MODE 0x1000 665 #define SXP_PINS_HVD_MODE 0x0800 666 #define SXP_PINS_SE_MODE 0x0400 667 668 /* The above have to be put together with the DIFFM pin to make sense */ 669 #define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 670 #define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 671 #define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 672 #define ISP1080_MODE_MASK \ 673 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 674 675 /* 676 * RISC and Host Command and Control Block Register Offsets 677 */ 678 679 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 680 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 681 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 682 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 683 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 684 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 685 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 686 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 687 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 688 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 689 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 690 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 691 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 692 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 693 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 694 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 695 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 696 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 697 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 698 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 699 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 700 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 701 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 702 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 703 #define RISC_MTR2100 RISC_BLOCK+0x30 704 705 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 706 #define DUAL_BANK 8 707 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 708 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 709 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 710 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 711 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 712 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 713 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 714 715 716 /* PROCESSOR STATUS REGISTER */ 717 #define RISC_PSR_FORCE_TRUE 0x8000 718 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 719 #define RISC_PSR_RISC_INT 0x2000 720 #define RISC_PSR_TIMER_ROLLOVER 0x1000 721 #define RISC_PSR_ALU_OVERFLOW 0x0800 722 #define RISC_PSR_ALU_MSB 0x0400 723 #define RISC_PSR_ALU_CARRY 0x0200 724 #define RISC_PSR_ALU_ZERO 0x0100 725 726 #define RISC_PSR_PCI_ULTRA 0x0080 727 #define RISC_PSR_SBUS_ULTRA 0x0020 728 729 #define RISC_PSR_DMA_INT 0x0010 730 #define RISC_PSR_SXP_INT 0x0008 731 #define RISC_PSR_HOST_INT 0x0004 732 #define RISC_PSR_INT_PENDING 0x0002 733 #define RISC_PSR_FORCE_FALSE 0x0001 734 735 736 /* Host Command and Control */ 737 #define HCCR_CMD_NOP 0x0000 /* NOP */ 738 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 739 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 740 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 741 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 742 #define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* 743 * Disable RISC pause on FPM 744 * parity error. 745 */ 746 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 747 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 748 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 749 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 750 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 751 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 752 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 753 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 754 755 756 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 757 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 758 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 759 #define ISP2100_HCCR_PARITY 0x0001 760 761 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 762 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 763 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 764 765 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 766 #define HCCR_RESET 0x0040 /* R : reset in progress */ 767 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 768 769 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 770 771 /* 772 * Defines for Interrupts 773 */ 774 #define ISP_INTS_ENABLED(isp) \ 775 ((IS_SCSI(isp))? \ 776 (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \ 777 (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \ 778 (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK))) 779 780 #define ISP_ENABLE_INTS(isp) \ 781 (IS_SCSI(isp) ? \ 782 ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \ 783 (IS_24XX(isp) ? \ 784 (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \ 785 (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK)))) 786 787 #define ISP_DISABLE_INTS(isp) \ 788 IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0) 789 790 /* 791 * NVRAM Definitions (PCI cards only) 792 */ 793 794 #define ISPBSMX(c, byte, shift, mask) \ 795 (((c)[(byte)] >> (shift)) & (mask)) 796 /* 797 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 798 * 799 * Some portion of the front of this is for general host adapter properties 800 * This is followed by an array of per-target parameters, and is tailed off 801 * with a checksum xor byte at offset 127. For non-byte entities data is 802 * stored in Little Endian order. 803 */ 804 805 #define ISP_NVRAM_SIZE 128 806 807 #define ISP_NVRAM_VERSION(c) (c)[4] 808 #define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 809 #define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 810 #define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 811 #define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 812 #define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 813 #define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 814 #define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 815 #define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 816 #define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 817 #define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 818 #define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 819 #define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 820 #define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 821 #define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 822 #define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 823 #define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 824 #define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 825 #define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 826 #define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 827 #define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 828 #define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 829 #define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 830 #define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 831 #define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 832 #define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 833 #define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 834 #define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 835 #define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 836 #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 837 838 #define ISP_NVRAM_TARGOFF 28 839 #define ISP_NVRAM_TARGSIZE 6 840 #define _IxT(tgt, tidx) \ 841 (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx)) 842 #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 843 #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 844 #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 845 #define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 846 #define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 847 #define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 848 #define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 849 #define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 850 #define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 851 #define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 852 #define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 853 #define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 854 #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 855 856 /* 857 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 858 * 859 * Some portion of the front of this is for general host adapter properties 860 * This is followed by an array of per-target parameters, and is tailed off 861 * with a checksum xor byte at offset 256. For non-byte entities data is 862 * stored in Little Endian order. 863 */ 864 865 #define ISP1080_NVRAM_SIZE 256 866 867 #define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 868 869 /* Offset 5 */ 870 /* 871 uint8_t bios_configuration_mode :2; 872 uint8_t bios_disable :1; 873 uint8_t selectable_scsi_boot_enable :1; 874 uint8_t cd_rom_boot_enable :1; 875 uint8_t disable_loading_risc_code :1; 876 uint8_t enable_64bit_addressing :1; 877 uint8_t unused_7 :1; 878 */ 879 880 /* Offsets 6, 7 */ 881 /* 882 uint8_t boot_lun_number :5; 883 uint8_t scsi_bus_number :1; 884 uint8_t unused_6 :1; 885 uint8_t unused_7 :1; 886 uint8_t boot_target_number :4; 887 uint8_t unused_12 :1; 888 uint8_t unused_13 :1; 889 uint8_t unused_14 :1; 890 uint8_t unused_15 :1; 891 */ 892 893 #define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 894 895 #define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 896 #define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 897 898 #define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 899 #define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 900 #define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 901 902 #define ISP1080_ISP_PARAMETER(c) \ 903 (((c)[18]) | ((c)[19] << 8)) 904 905 #define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 906 #define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 907 908 #define ISP1080_BUS1_OFF 112 909 910 #define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 911 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 912 #define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 913 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 914 #define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 915 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 916 #define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 917 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 918 919 #define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 920 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 921 #define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 922 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 923 #define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 924 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 925 #define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 926 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 927 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 928 #define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 929 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 930 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 931 932 #define ISP1080_NVRAM_TARGOFF(b) \ 933 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 934 #define ISP1080_NVRAM_TARGSIZE 6 935 #define _IxT8(tgt, tidx, b) \ 936 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 937 938 #define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 939 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 940 #define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 941 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 942 #define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 943 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 944 #define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 945 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 946 #define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 947 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 948 #define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 949 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 950 #define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 951 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 952 #define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 953 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 954 #define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 955 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 956 #define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 957 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 958 #define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 959 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 960 #define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 961 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 962 #define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 963 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 964 965 #define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 966 #define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 967 #define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 968 #define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 969 #define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 970 #define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 971 #define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 972 #define ISP12160_FAST_POST ISP1080_FAST_POST 973 #define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 974 975 #define ISP12160_NVRAM_INITIATOR_ID \ 976 ISP1080_NVRAM_INITIATOR_ID 977 #define ISP12160_NVRAM_BUS_RESET_DELAY \ 978 ISP1080_NVRAM_BUS_RESET_DELAY 979 #define ISP12160_NVRAM_BUS_RETRY_COUNT \ 980 ISP1080_NVRAM_BUS_RETRY_COUNT 981 #define ISP12160_NVRAM_BUS_RETRY_DELAY \ 982 ISP1080_NVRAM_BUS_RETRY_DELAY 983 #define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 984 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 985 #define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 986 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 987 #define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 988 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 989 #define ISP12160_NVRAM_SELECTION_TIMEOUT \ 990 ISP1080_NVRAM_SELECTION_TIMEOUT 991 #define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 992 ISP1080_NVRAM_MAX_QUEUE_DEPTH 993 994 995 #define ISP12160_BUS0_OFF 24 996 #define ISP12160_BUS1_OFF 136 997 998 #define ISP12160_NVRAM_TARGOFF(b) \ 999 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 1000 1001 #define ISP12160_NVRAM_TARGSIZE 6 1002 #define _IxT16(tgt, tidx, b) \ 1003 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 1004 1005 #define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 1006 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 1007 #define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 1008 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 1009 #define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 1010 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 1011 #define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 1012 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 1013 #define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 1014 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 1015 #define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 1016 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 1017 #define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 1018 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 1019 #define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 1020 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 1021 1022 #define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 1023 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 1024 #define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 1025 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 1026 1027 #define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 1028 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 1029 #define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 1030 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 1031 1032 #define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 1033 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 1034 #define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 1035 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 1036 #define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 1037 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 1038 1039 /* 1040 * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes. 1041 * 1042 * Some portion of the front of this is for general RISC engine parameters, 1043 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 1044 * 1045 * This is followed by some general host adapter parameters, and ends with 1046 * a checksum xor byte at offset 255. For non-byte entities data is stored 1047 * in Little Endian order. 1048 */ 1049 #define ISP2100_NVRAM_SIZE 256 1050 /* ISP_NVRAM_VERSION is in same overall place */ 1051 #define ISP2100_NVRAM_RISCVER(c) (c)[6] 1052 #define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8)) 1053 #define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 1054 #define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 1055 #define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1056 #define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 1057 #define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 1058 1059 #define ISP2100_NVRAM_PORT_NAME(c) (\ 1060 (((uint64_t)(c)[18]) << 56) | \ 1061 (((uint64_t)(c)[19]) << 48) | \ 1062 (((uint64_t)(c)[20]) << 40) | \ 1063 (((uint64_t)(c)[21]) << 32) | \ 1064 (((uint64_t)(c)[22]) << 24) | \ 1065 (((uint64_t)(c)[23]) << 16) | \ 1066 (((uint64_t)(c)[24]) << 8) | \ 1067 (((uint64_t)(c)[25]) << 0)) 1068 1069 #define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8)) 1070 #define ISP2100_NVRAM_TOV(c) ((c)[29]) 1071 1072 #define ISP2100_NVRAM_NODE_NAME(c) (\ 1073 (((uint64_t)(c)[30]) << 56) | \ 1074 (((uint64_t)(c)[31]) << 48) | \ 1075 (((uint64_t)(c)[32]) << 40) | \ 1076 (((uint64_t)(c)[33]) << 32) | \ 1077 (((uint64_t)(c)[34]) << 24) | \ 1078 (((uint64_t)(c)[35]) << 16) | \ 1079 (((uint64_t)(c)[36]) << 8) | \ 1080 (((uint64_t)(c)[37]) << 0)) 1081 1082 #define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8)) 1083 1084 #define ISP2100_RACC_TIMER(c) (c)[40] 1085 #define ISP2100_IDELAY_TIMER(c) (c)[41] 1086 1087 #define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8)) 1088 1089 #define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8)) 1090 1091 #define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8)) 1092 #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 1093 #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 1094 #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 1095 #define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 1096 #define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 1097 #define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 1098 1099 #define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 1100 (((uint64_t)(c)[72]) << 56) | \ 1101 (((uint64_t)(c)[73]) << 48) | \ 1102 (((uint64_t)(c)[74]) << 40) | \ 1103 (((uint64_t)(c)[75]) << 32) | \ 1104 (((uint64_t)(c)[76]) << 24) | \ 1105 (((uint64_t)(c)[77]) << 16) | \ 1106 (((uint64_t)(c)[78]) << 8) | \ 1107 (((uint64_t)(c)[79]) << 0)) 1108 1109 #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 1110 #define ISP2100_RESET_DELAY(c) (c)[81] 1111 1112 #define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8)) 1113 1114 /* 1115 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum. 1116 */ 1117 #define ISP2400_NVRAM_PORT0_ADDR 0x80 1118 #define ISP2400_NVRAM_PORT1_ADDR 0x180 1119 #define ISP2400_NVRAM_SIZE 512 1120 1121 #define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8)) 1122 #define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8)) 1123 #define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1124 #define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8)) 1125 #define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8)) 1126 1127 #define ISP2400_NVRAM_PORT_NAME(c) (\ 1128 (((uint64_t)(c)[20]) << 56) | \ 1129 (((uint64_t)(c)[21]) << 48) | \ 1130 (((uint64_t)(c)[22]) << 40) | \ 1131 (((uint64_t)(c)[23]) << 32) | \ 1132 (((uint64_t)(c)[24]) << 24) | \ 1133 (((uint64_t)(c)[25]) << 16) | \ 1134 (((uint64_t)(c)[26]) << 8) | \ 1135 (((uint64_t)(c)[27]) << 0)) 1136 1137 #define ISP2400_NVRAM_NODE_NAME(c) (\ 1138 (((uint64_t)(c)[28]) << 56) | \ 1139 (((uint64_t)(c)[29]) << 48) | \ 1140 (((uint64_t)(c)[30]) << 40) | \ 1141 (((uint64_t)(c)[31]) << 32) | \ 1142 (((uint64_t)(c)[32]) << 24) | \ 1143 (((uint64_t)(c)[33]) << 16) | \ 1144 (((uint64_t)(c)[34]) << 8) | \ 1145 (((uint64_t)(c)[35]) << 0)) 1146 1147 #define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8)) 1148 #define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8)) 1149 #define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8)) 1150 #define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8)) 1151 1152 #define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \ 1153 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24)) 1154 #define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \ 1155 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24)) 1156 #define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \ 1157 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24)) 1158 1159 /* 1160 * Firmware Crash Dump 1161 * 1162 * QLogic needs specific information format when they look at firmware crashes. 1163 * 1164 * This is incredibly kernel memory consumptive (to say the least), so this 1165 * code is only compiled in when needed. 1166 */ 1167 1168 #define QLA2200_RISC_IMAGE_DUMP_SIZE \ 1169 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1170 (352 * sizeof (uint16_t)) + /* RISC registers */ \ 1171 (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */ 1172 #define QLA2300_RISC_IMAGE_DUMP_SIZE \ 1173 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1174 (464 * sizeof (uint16_t)) + /* RISC registers */ \ 1175 (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \ 1176 (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \ 1177 (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */ 1178 /* the larger of the two */ 1179 #define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE 1180 #endif /* _ISPREG_H */ 1181