1 /* $FreeBSD$ */ 2 /* 3 * Machine Independent (well, as best as possible) register 4 * definitions for Qlogic ISP SCSI adapters. 5 * 6 * Copyright (c) 1997, 1998, 1999 by Matthew Jacob 7 * NASA/Ames Research Center 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice immediately at the beginning of the file, without modification, 15 * this list of conditions, and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 #ifndef _ISPREG_H 35 #define _ISPREG_H 36 37 /* 38 * Hardware definitions for the Qlogic ISP registers. 39 */ 40 41 /* 42 * This defines types of access to various registers. 43 * 44 * R: Read Only 45 * W: Write Only 46 * RW: Read/Write 47 * 48 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 49 * if RISC processor in ISP is paused. 50 */ 51 52 /* 53 * Offsets for various register blocks. 54 * 55 * Sad but true, different architectures have different offsets. 56 * 57 * Don't be alarmed if none of this makes sense. The original register 58 * layout set some defines in a certain pattern. Everything else has been 59 * grafted on since. For example, the ISP1080 manual will state that DMA 60 * registers start at 0x80 from the base of the register address space. 61 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 62 * to start at offset 0x60 because the DMA registers are all defined to 63 * be DMA_BLOCK+0x20 and so on. Clear? 64 */ 65 66 #define BIU_REGS_OFF 0x00 67 68 #define PCI_MBOX_REGS_OFF 0x70 69 #define PCI_MBOX_REGS2100_OFF 0x10 70 #define SBUS_MBOX_REGS_OFF 0x80 71 72 #define PCI_SXP_REGS_OFF 0x80 73 #define SBUS_SXP_REGS_OFF 0x200 74 75 #define PCI_RISC_REGS_OFF 0x80 76 #define SBUS_RISC_REGS_OFF 0x400 77 78 /* Bless me! Chip designers have putzed it again! */ 79 #define ISP1080_DMA_REGS_OFF 0x60 80 #define DMA_REGS_OFF 0x00 /* same as BIU block */ 81 82 #define SBUS_REGSIZE 0x450 83 #define PCI_REGSIZE 0x100 84 85 /* 86 * NB: The *_BLOCK definitions have no specific hardware meaning. 87 * They serve simply to note to the MD layer which block of 88 * registers offsets are being accessed. 89 */ 90 #define _NREG_BLKS 5 91 #define _BLK_REG_SHFT 13 92 #define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 93 #define BIU_BLOCK (0 << _BLK_REG_SHFT) 94 #define MBOX_BLOCK (1 << _BLK_REG_SHFT) 95 #define SXP_BLOCK (2 << _BLK_REG_SHFT) 96 #define RISC_BLOCK (3 << _BLK_REG_SHFT) 97 #define DMA_BLOCK (4 << _BLK_REG_SHFT) 98 99 /* 100 * Bus Interface Block Register Offsets 101 */ 102 103 #define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 104 #define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 105 #define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 106 #define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 107 #define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 108 #define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 109 #define BIU2100_CSR (BIU_BLOCK+0x6) 110 #define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 111 #define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 112 #define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 113 #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 114 #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 115 #define RDMA2100_CONTROL DFIFO_COMMAND 116 #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 117 118 /* 119 * Putzed DMA register layouts. 120 */ 121 #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 122 #define CDMA2100_CONTROL CDMA_CONF 123 #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 124 #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 125 #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 126 #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 127 #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 128 #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 129 #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 130 #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 131 132 #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 133 #define TDMA2100_CONTROL DDMA_CONF 134 #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 135 #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 136 #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 137 #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 138 #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 139 #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 140 #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 141 /* these are for the 1040A cards */ 142 #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 143 #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 144 145 146 /* 147 * Bus Interface Block Register Definitions 148 */ 149 /* BUS CONFIGURATION REGISTER #0 */ 150 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 151 /* BUS CONFIGURATION REGISTER #1 */ 152 153 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 154 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 155 156 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 157 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 158 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 159 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 160 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 161 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 162 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 163 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 164 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 165 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 166 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 167 168 #define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 169 #define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 170 #define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 171 172 /* ISP2100 Bus Control/Status Register */ 173 174 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 175 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 176 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 177 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 178 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 179 #define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 180 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 181 #define BIU2100_SOFT_RESET 0x01 182 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 183 184 185 /* BUS CONTROL REGISTER */ 186 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 187 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 188 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 189 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 190 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 191 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 192 193 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 194 #define BIU2100_ICR_ENA_FPM_INT 0x0020 195 #define BIU2100_ICR_ENA_FB_INT 0x0010 196 #define BIU2100_ICR_ENA_RISC_INT 0x0008 197 #define BIU2100_ICR_ENA_CDMA_INT 0x0004 198 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 199 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 200 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 201 202 #define ENABLE_INTS(isp) (IS_SCSI(isp))? \ 203 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 204 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 205 206 #define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ 207 (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ 208 (ISP_READ(isp, BIU_ICR) & \ 209 (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) 210 211 #define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 212 213 /* BUS STATUS REGISTER */ 214 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 215 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 216 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 217 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 218 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 219 220 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 221 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 222 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 223 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 224 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 225 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 226 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 227 228 #define INT_PENDING(isp, isr) (IS_FC(isp)? \ 229 ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) 230 231 #define INT_PENDING_MASK(isp) \ 232 (IS_FC(isp)? BIU2100_ISR_RISC_INT: BIU_ISR_RISC_INT) 233 234 /* BUS SEMAPHORE REGISTER */ 235 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 236 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 237 238 /* NVRAM SEMAPHORE REGISTER */ 239 #define BIU_NVRAM_CLOCK 0x0001 240 #define BIU_NVRAM_SELECT 0x0002 241 #define BIU_NVRAM_DATAOUT 0x0004 242 #define BIU_NVRAM_DATAIN 0x0008 243 #define ISP_NVRAM_READ 6 244 245 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 246 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 247 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 248 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 249 #define DMA_DMA_DIRECTION 0x0001 /* 250 * Set DMA direction: 251 * 0 - DMA FIFO to host 252 * 1 - Host to DMA FIFO 253 */ 254 255 /* COMMAND && DATA DMA CONTROL REGISTER */ 256 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 257 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 258 * Clear FIFO and DMA Channel, 259 * reset DMA registers 260 */ 261 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 262 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 263 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 264 265 /* 266 * Variants of same for 2100 267 */ 268 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004 269 #define DMA_CNTRL2100_RESET_INT 0x0002 270 271 272 273 /* DMA STATUS REGISTER */ 274 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 275 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 276 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 277 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 278 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 279 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 280 281 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 282 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 283 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 284 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 285 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 286 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 287 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 288 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 289 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 290 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 291 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 292 293 /* DMA Status Register, pipeline status bits */ 294 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 295 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 296 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 297 * Pipeline stage 1 Loaded, 298 * stage 2 empty 299 */ 300 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 301 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 302 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 303 * Pipeline stage 1 Loaded, 304 * stage 2 empty 305 */ 306 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 307 308 /* DMA Status Register, channel status bits */ 309 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 310 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 311 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 312 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 313 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 314 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 315 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 316 317 318 /* DMA FIFO STATUS REGISTER */ 319 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 320 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 321 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 322 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 323 324 /* 325 * Mailbox Block Register Offsets 326 */ 327 328 #define INMAILBOX0 (MBOX_BLOCK+0x0) 329 #define INMAILBOX1 (MBOX_BLOCK+0x2) 330 #define INMAILBOX2 (MBOX_BLOCK+0x4) 331 #define INMAILBOX3 (MBOX_BLOCK+0x6) 332 #define INMAILBOX4 (MBOX_BLOCK+0x8) 333 #define INMAILBOX5 (MBOX_BLOCK+0xA) 334 #define INMAILBOX6 (MBOX_BLOCK+0xC) 335 #define INMAILBOX7 (MBOX_BLOCK+0xE) 336 337 #define OUTMAILBOX0 (MBOX_BLOCK+0x0) 338 #define OUTMAILBOX1 (MBOX_BLOCK+0x2) 339 #define OUTMAILBOX2 (MBOX_BLOCK+0x4) 340 #define OUTMAILBOX3 (MBOX_BLOCK+0x6) 341 #define OUTMAILBOX4 (MBOX_BLOCK+0x8) 342 #define OUTMAILBOX5 (MBOX_BLOCK+0xA) 343 #define OUTMAILBOX6 (MBOX_BLOCK+0xC) 344 #define OUTMAILBOX7 (MBOX_BLOCK+0xE) 345 346 #define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 347 #define NMBOX(isp) \ 348 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 349 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 350 #define NMBOX_BMASK(isp) \ 351 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 352 ((isp)->isp_type & ISP_HA_FC))? 0xff : 0x3f) 353 354 #define MAX_MAILBOX 8 355 356 /* 357 * SXP Block Register Offsets 358 */ 359 #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 360 #define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 361 #define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 362 #define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 363 #define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 364 #define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 365 #define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 366 #define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 367 #define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 368 #define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 369 #define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 370 #define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 371 #define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 372 #define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 373 #define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 374 #define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 375 #define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 376 #define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 377 #define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 378 #define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 379 #define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 380 #define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 381 #define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 382 #define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 383 #define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 384 #define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 385 #define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 386 #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 387 #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 388 #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 389 #define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 390 #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 391 #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 392 #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 393 #define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 394 #define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 395 #define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 396 #define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 397 #define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 398 399 /* for 1080/1280/1240 only */ 400 #define SXP_BANK1_SELECT 0x100 401 402 403 /* SXP CONF1 REGISTER */ 404 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 405 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 406 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 407 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 408 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 409 410 /* SXP CONF2 REGISTER */ 411 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 412 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 413 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 414 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 415 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 416 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 417 418 /* SXP INTERRUPT REGISTER */ 419 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 420 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 421 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 422 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 423 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 424 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 425 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 426 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 427 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 428 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 429 430 431 /* SXP GROSS ERROR REGISTER */ 432 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 433 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 434 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 435 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 436 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 437 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 438 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 439 440 /* SXP EXCEPTION REGISTER */ 441 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 442 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 443 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 444 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 445 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 446 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 447 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 448 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 449 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 450 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 451 452 /* SXP OVERRIDE REGISTER */ 453 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 454 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 455 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 456 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 457 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 458 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 459 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 460 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 461 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 462 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 463 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 464 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 465 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 466 467 /* SXP COMMANDS */ 468 #define SXP_RESET_BUS_CMD 0x300b 469 470 /* SXP SCSI ID REGISTER */ 471 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 472 #define SXP_SELECT_ID 0x000F /* Select id */ 473 474 /* SXP DEV CONFIG1 REGISTER */ 475 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 476 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 477 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 478 479 480 /* SXP DEV CONFIG2 REGISTER */ 481 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 482 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 483 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 484 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 485 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 486 487 488 /* SXP PHASE POINTER REGISTER */ 489 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 490 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 491 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 492 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 493 494 495 /* SXP FIFO STATUS REGISTER */ 496 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 497 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 498 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 499 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 500 501 502 /* SXP CONTROL PINS REGISTER */ 503 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 504 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 505 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 506 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 507 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 508 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 509 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 510 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 511 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 512 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 513 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 514 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 515 516 /* 517 * Set the hold time for the SCSI Bus Reset to be 250 ms 518 */ 519 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 520 521 /* SXP DIFF PINS REGISTER */ 522 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 523 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 524 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 525 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 526 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 527 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 528 529 /* Ultra2 only */ 530 #define SXP_PINS_LVD_MODE 0x1000 531 #define SXP_PINS_HVD_MODE 0x0800 532 #define SXP_PINS_SE_MODE 0x0400 533 534 /* The above have to be put together with the DIFFM pin to make sense */ 535 #define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 536 #define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 537 #define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 538 #define ISP1080_MODE_MASK \ 539 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 540 541 /* 542 * RISC and Host Command and Control Block Register Offsets 543 */ 544 545 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 546 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 547 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 548 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 549 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 550 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 551 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 552 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 553 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 554 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 555 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 556 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 557 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 558 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 559 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 560 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 561 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 562 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 563 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 564 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 565 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 566 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 567 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 568 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 569 #define RISC_MTR2100 RISC_BLOCK+0x30 570 571 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 572 #define DUAL_BANK 8 573 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 574 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 575 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 576 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 577 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 578 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 579 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 580 581 582 /* PROCESSOR STATUS REGISTER */ 583 #define RISC_PSR_FORCE_TRUE 0x8000 584 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 585 #define RISC_PSR_RISC_INT 0x2000 586 #define RISC_PSR_TIMER_ROLLOVER 0x1000 587 #define RISC_PSR_ALU_OVERFLOW 0x0800 588 #define RISC_PSR_ALU_MSB 0x0400 589 #define RISC_PSR_ALU_CARRY 0x0200 590 #define RISC_PSR_ALU_ZERO 0x0100 591 592 #define RISC_PSR_PCI_ULTRA 0x0080 593 #define RISC_PSR_SBUS_ULTRA 0x0020 594 595 #define RISC_PSR_DMA_INT 0x0010 596 #define RISC_PSR_SXP_INT 0x0008 597 #define RISC_PSR_HOST_INT 0x0004 598 #define RISC_PSR_INT_PENDING 0x0002 599 #define RISC_PSR_FORCE_FALSE 0x0001 600 601 602 /* Host Command and Control */ 603 #define HCCR_CMD_NOP 0x0000 /* NOP */ 604 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 605 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 606 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 607 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 608 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 609 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 610 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 611 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 612 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 613 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 614 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 615 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 616 617 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 618 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 619 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 620 #define ISP2100_HCCR_PARITY 0x0001 621 622 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 623 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 624 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 625 626 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 627 #define HCCR_RESET 0x0040 /* R : reset in progress */ 628 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 629 630 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 631 632 /* 633 * NVRAM Definitions (PCI cards only) 634 */ 635 636 #define ISPBSMX(c, byte, shift, mask) \ 637 (((c)[(byte)] >> (shift)) & (mask)) 638 /* 639 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 640 * 641 * Some portion of the front of this is for general host adapter properties 642 * This is followed by an array of per-target parameters, and is tailed off 643 * with a checksum xor byte at offset 127. For non-byte entities data is 644 * stored in Little Endian order. 645 */ 646 647 #define ISP_NVRAM_SIZE 128 648 649 #define ISP_NVRAM_VERSION(c) (c)[4] 650 #define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 651 #define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 652 #define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 653 #define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 654 #define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 655 #define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 656 #define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 657 #define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 658 #define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 659 #define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 660 #define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 661 #define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 662 #define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 663 #define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 664 #define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 665 #define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 666 #define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 667 #define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 668 #define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 669 #define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 670 #define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 671 #define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 672 #define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 673 #define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 674 #define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 675 #define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 676 #define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 677 #define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 678 #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 679 680 #define ISP_NVRAM_TARGOFF 28 681 #define ISP_NVARM_TARGSIZE 6 682 #define _IxT(tgt, tidx) \ 683 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 684 #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 685 #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 686 #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 687 #define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 688 #define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 689 #define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 690 #define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 691 #define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 692 #define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 693 #define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 694 #define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 695 #define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 696 #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 697 698 /* 699 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 700 * 701 * Some portion of the front of this is for general host adapter properties 702 * This is followed by an array of per-target parameters, and is tailed off 703 * with a checksum xor byte at offset 256. For non-byte entities data is 704 * stored in Little Endian order. 705 */ 706 707 #define ISP1080_NVRAM_SIZE 256 708 709 #define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 710 711 /* Offset 5 */ 712 /* 713 u_int8_t bios_configuration_mode :2; 714 u_int8_t bios_disable :1; 715 u_int8_t selectable_scsi_boot_enable :1; 716 u_int8_t cd_rom_boot_enable :1; 717 u_int8_t disable_loading_risc_code :1; 718 u_int8_t enable_64bit_addressing :1; 719 u_int8_t unused_7 :1; 720 */ 721 722 /* Offsets 6, 7 */ 723 /* 724 u_int8_t boot_lun_number :5; 725 u_int8_t scsi_bus_number :1; 726 u_int8_t unused_6 :1; 727 u_int8_t unused_7 :1; 728 u_int8_t boot_target_number :4; 729 u_int8_t unused_12 :1; 730 u_int8_t unused_13 :1; 731 u_int8_t unused_14 :1; 732 u_int8_t unused_15 :1; 733 */ 734 735 #define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 736 737 #define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 738 #define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 739 740 #define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 741 #define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 742 #define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 743 744 #define ISP1080_ISP_PARAMETER(c) \ 745 (((c)[18]) | ((c)[19] << 8)) 746 747 #define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 748 #define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 749 750 #define ISP1080_BUS1_OFF 112 751 752 #define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 753 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 754 #define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 755 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 756 #define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 757 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 758 #define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 759 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 760 761 #define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 762 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 763 #define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 764 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 765 #define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 766 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 767 #define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 768 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 769 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 770 #define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 771 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 772 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 773 774 #define ISP1080_NVRAM_TARGOFF(b) \ 775 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 776 #define ISP1080_NVRAM_TARGSIZE 6 777 #define _IxT8(tgt, tidx, b) \ 778 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 779 780 #define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 781 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 782 #define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 783 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 784 #define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 785 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 786 #define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 787 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 788 #define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 789 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 790 #define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 791 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 792 #define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 793 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 794 #define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 795 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 796 #define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 797 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 798 #define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 799 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 800 #define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 801 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 802 #define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 803 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 804 #define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 805 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 806 807 #define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 808 #define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 809 #define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 810 #define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 811 #define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 812 #define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 813 #define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 814 #define ISP12160_FAST_POST ISP1080_FAST_POST 815 #define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 816 817 #define ISP12160_NVRAM_INITIATOR_ID \ 818 ISP1080_NVRAM_INITIATOR_ID 819 #define ISP12160_NVRAM_BUS_RESET_DELAY \ 820 ISP1080_NVRAM_BUS_RESET_DELAY 821 #define ISP12160_NVRAM_BUS_RETRY_COUNT \ 822 ISP1080_NVRAM_BUS_RETRY_COUNT 823 #define ISP12160_NVRAM_BUS_RETRY_DELAY \ 824 ISP1080_NVRAM_BUS_RETRY_DELAY 825 #define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 826 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 827 #define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 828 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 829 #define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 830 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 831 #define ISP12160_NVRAM_SELECTION_TIMEOUT \ 832 ISP1080_NVRAM_SELECTION_TIMEOUT 833 #define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 834 ISP1080_NVRAM_MAX_QUEUE_DEPTH 835 836 837 #define ISP12160_BUS0_OFF 24 838 #define ISP12160_BUS1_OFF 136 839 840 #define ISP12160_NVRAM_TARGOFF(b) \ 841 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 842 843 #define ISP12160_NVRAM_TARGSIZE 6 844 #define _IxT16(tgt, tidx, b) \ 845 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 846 847 #define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 848 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 849 #define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 850 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 851 #define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 852 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 853 #define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 854 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 855 #define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 856 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 857 #define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 858 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 859 #define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 860 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 861 #define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 862 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 863 864 #define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 865 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 866 #define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 867 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 868 869 #define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 870 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 871 #define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 872 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 873 874 #define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 875 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 876 #define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 877 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 878 #define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 879 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 880 881 /* 882 * Qlogic 2XXX NVRAM is an array of 256 bytes. 883 * 884 * Some portion of the front of this is for general RISC engine parameters, 885 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 886 * 887 * This is followed by some general host adapter parameters, and ends with 888 * a checksum xor byte at offset 255. For non-byte entities data is stored 889 * in Little Endian order. 890 */ 891 #define ISP2100_NVRAM_SIZE 256 892 /* ISP_NVRAM_VERSION is in same overall place */ 893 #define ISP2100_NVRAM_RISCVER(c) (c)[6] 894 #define ISP2100_NVRAM_OPTIONS(c) (c)[8] 895 #define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 896 #define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 897 #define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 898 #define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 899 #define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 900 901 #define ISP2100_NVRAM_PORT_NAME(c) (\ 902 (((u_int64_t)(c)[18]) << 56) | \ 903 (((u_int64_t)(c)[19]) << 48) | \ 904 (((u_int64_t)(c)[20]) << 40) | \ 905 (((u_int64_t)(c)[21]) << 32) | \ 906 (((u_int64_t)(c)[22]) << 24) | \ 907 (((u_int64_t)(c)[23]) << 16) | \ 908 (((u_int64_t)(c)[24]) << 8) | \ 909 (((u_int64_t)(c)[25]) << 0)) 910 911 #define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 912 913 #define ISP2100_NVRAM_NODE_NAME(c) (\ 914 (((u_int64_t)(c)[30]) << 56) | \ 915 (((u_int64_t)(c)[31]) << 48) | \ 916 (((u_int64_t)(c)[32]) << 40) | \ 917 (((u_int64_t)(c)[33]) << 32) | \ 918 (((u_int64_t)(c)[34]) << 24) | \ 919 (((u_int64_t)(c)[35]) << 16) | \ 920 (((u_int64_t)(c)[36]) << 8) | \ 921 (((u_int64_t)(c)[37]) << 0)) 922 923 #define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 924 #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 925 #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 926 #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 927 #define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 928 #define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 929 #define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 930 931 #define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 932 (((u_int64_t)(c)[72]) << 56) | \ 933 (((u_int64_t)(c)[73]) << 48) | \ 934 (((u_int64_t)(c)[74]) << 40) | \ 935 (((u_int64_t)(c)[75]) << 32) | \ 936 (((u_int64_t)(c)[76]) << 24) | \ 937 (((u_int64_t)(c)[77]) << 16) | \ 938 (((u_int64_t)(c)[78]) << 8) | \ 939 (((u_int64_t)(c)[79]) << 0)) 940 941 #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 942 943 #endif /* _ISPREG_H */ 944