xref: /freebsd/sys/dev/isp/ispmbox.h (revision eacee0ff7ec955b32e09515246bd97b6edcd2b0f)
1 /* $FreeBSD$ */
2 /*
3  * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters.
4  *
5  * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice immediately at the beginning of the file, without modification,
13  *    this list of conditions, and the following disclaimer.
14  * 2. The name of the author may not be used to endorse or promote products
15  *    derived from this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  */
30 #ifndef	_ISPMBOX_H
31 #define	_ISPMBOX_H
32 
33 /*
34  * Mailbox Command Opcodes
35  */
36 #define MBOX_NO_OP			0x0000
37 #define MBOX_LOAD_RAM			0x0001
38 #define MBOX_EXEC_FIRMWARE		0x0002
39 #define MBOX_DUMP_RAM			0x0003
40 #define MBOX_WRITE_RAM_WORD		0x0004
41 #define MBOX_READ_RAM_WORD		0x0005
42 #define MBOX_MAILBOX_REG_TEST		0x0006
43 #define MBOX_VERIFY_CHECKSUM		0x0007
44 #define MBOX_ABOUT_FIRMWARE		0x0008
45 					/*   9 */
46 					/*   a */
47 					/*   b */
48 					/*   c */
49 					/*   d */
50 #define MBOX_CHECK_FIRMWARE		0x000e
51 #define	MBOX_READ_RAM_WORD_EXTENDED	0x000f
52 #define MBOX_INIT_REQ_QUEUE		0x0010
53 #define MBOX_INIT_RES_QUEUE		0x0011
54 #define MBOX_EXECUTE_IOCB		0x0012
55 #define MBOX_WAKE_UP			0x0013
56 #define MBOX_STOP_FIRMWARE		0x0014
57 #define MBOX_ABORT			0x0015
58 #define MBOX_ABORT_DEVICE		0x0016
59 #define MBOX_ABORT_TARGET		0x0017
60 #define MBOX_BUS_RESET			0x0018
61 #define MBOX_STOP_QUEUE			0x0019
62 #define MBOX_START_QUEUE		0x001a
63 #define MBOX_SINGLE_STEP_QUEUE		0x001b
64 #define MBOX_ABORT_QUEUE		0x001c
65 #define MBOX_GET_DEV_QUEUE_STATUS	0x001d
66 					/*  1e */
67 #define MBOX_GET_FIRMWARE_STATUS	0x001f
68 #define MBOX_GET_INIT_SCSI_ID		0x0020
69 #define MBOX_GET_SELECT_TIMEOUT		0x0021
70 #define MBOX_GET_RETRY_COUNT		0x0022
71 #define MBOX_GET_TAG_AGE_LIMIT		0x0023
72 #define MBOX_GET_CLOCK_RATE		0x0024
73 #define MBOX_GET_ACT_NEG_STATE		0x0025
74 #define MBOX_GET_ASYNC_DATA_SETUP_TIME	0x0026
75 #define MBOX_GET_SBUS_PARAMS		0x0027
76 #define		MBOX_GET_PCI_PARAMS	MBOX_GET_SBUS_PARAMS
77 #define MBOX_GET_TARGET_PARAMS		0x0028
78 #define MBOX_GET_DEV_QUEUE_PARAMS	0x0029
79 #define	MBOX_GET_RESET_DELAY_PARAMS	0x002a
80 					/*  2b */
81 					/*  2c */
82 					/*  2d */
83 					/*  2e */
84 					/*  2f */
85 #define MBOX_SET_INIT_SCSI_ID		0x0030
86 #define MBOX_SET_SELECT_TIMEOUT		0x0031
87 #define MBOX_SET_RETRY_COUNT		0x0032
88 #define MBOX_SET_TAG_AGE_LIMIT		0x0033
89 #define MBOX_SET_CLOCK_RATE		0x0034
90 #define MBOX_SET_ACT_NEG_STATE		0x0035
91 #define MBOX_SET_ASYNC_DATA_SETUP_TIME	0x0036
92 #define MBOX_SET_SBUS_CONTROL_PARAMS	0x0037
93 #define		MBOX_SET_PCI_PARAMETERS	0x0037
94 #define MBOX_SET_TARGET_PARAMS		0x0038
95 #define MBOX_SET_DEV_QUEUE_PARAMS	0x0039
96 #define	MBOX_SET_RESET_DELAY_PARAMS	0x003a
97 					/*  3b */
98 					/*  3c */
99 					/*  3d */
100 					/*  3e */
101 					/*  3f */
102 #define	MBOX_RETURN_BIOS_BLOCK_ADDR	0x0040
103 #define	MBOX_WRITE_FOUR_RAM_WORDS	0x0041
104 #define	MBOX_EXEC_BIOS_IOCB		0x0042
105 #define	MBOX_SET_FW_FEATURES		0x004a
106 #define	MBOX_GET_FW_FEATURES		0x004b
107 #define		FW_FEATURE_FAST_POST	0x1
108 #define		FW_FEATURE_LVD_NOTIFY	0x2
109 #define		FW_FEATURE_RIO_32BIT	0x4
110 #define		FW_FEATURE_RIO_16BIT	0x8
111 
112 #define	MBOX_ENABLE_TARGET_MODE		0x0055
113 #define		ENABLE_TARGET_FLAG	0x8000
114 #define		ENABLE_TQING_FLAG	0x0004
115 #define		ENABLE_MANDATORY_DISC	0x0002
116 #define	MBOX_GET_TARGET_STATUS		0x0056
117 
118 /* These are for the ISP2X00 FC cards */
119 #define	MBOX_GET_LOOP_ID		0x0020
120 #define	MBOX_GET_FIRMWARE_OPTIONS	0x0028
121 #define	MBOX_SET_FIRMWARE_OPTIONS	0x0038
122 #define	MBOX_GET_RESOURCE_COUNT		0x0042
123 #define	MBOX_ENHANCED_GET_PDB		0x0047
124 #define	MBOX_EXEC_COMMAND_IOCB_A64	0x0054
125 #define	MBOX_INIT_FIRMWARE		0x0060
126 #define	MBOX_GET_INIT_CONTROL_BLOCK	0x0061
127 #define	MBOX_INIT_LIP			0x0062
128 #define	MBOX_GET_FC_AL_POSITION_MAP	0x0063
129 #define	MBOX_GET_PORT_DB		0x0064
130 #define	MBOX_CLEAR_ACA			0x0065
131 #define	MBOX_TARGET_RESET		0x0066
132 #define	MBOX_CLEAR_TASK_SET		0x0067
133 #define	MBOX_ABORT_TASK_SET		0x0068
134 #define	MBOX_GET_FW_STATE		0x0069
135 #define	MBOX_GET_PORT_NAME		0x006A
136 #define	MBOX_GET_LINK_STATUS		0x006B
137 #define	MBOX_INIT_LIP_RESET		0x006C
138 #define	MBOX_SEND_SNS			0x006E
139 #define	MBOX_FABRIC_LOGIN		0x006F
140 #define	MBOX_SEND_CHANGE_REQUEST	0x0070
141 #define	MBOX_FABRIC_LOGOUT		0x0071
142 #define	MBOX_INIT_LIP_LOGIN		0x0072
143 
144 #define	MBOX_GET_SET_DATA_RATE		0x005D	/* 23XX only */
145 #define		MBGSD_GET_RATE	0
146 #define		MBGSD_SET_RATE	1
147 #define		MBGSD_ONEGB	0
148 #define		MBGSD_TWOGB	1
149 #define		MBGSD_AUTO	2
150 
151 
152 #define	ISP2100_SET_PCI_PARAM		0x00ff
153 
154 #define	MBOX_BUSY			0x04
155 
156 typedef struct {
157 	u_int16_t param[8];
158 } mbreg_t;
159 
160 /*
161  * Mailbox Command Complete Status Codes
162  */
163 #define	MBOX_COMMAND_COMPLETE		0x4000
164 #define	MBOX_INVALID_COMMAND		0x4001
165 #define	MBOX_HOST_INTERFACE_ERROR	0x4002
166 #define	MBOX_TEST_FAILED		0x4003
167 #define	MBOX_COMMAND_ERROR		0x4005
168 #define	MBOX_COMMAND_PARAM_ERROR	0x4006
169 #define	MBOX_PORT_ID_USED		0x4007
170 #define	MBOX_LOOP_ID_USED		0x4008
171 #define	MBOX_ALL_IDS_USED		0x4009
172 #define	MBOX_NOT_LOGGED_IN		0x400A
173 #define	MBLOGALL			0x000f
174 #define	MBLOGNONE			0x0000
175 #define	MBLOGMASK(x)			((x) & 0xf)
176 
177 /*
178  * Asynchronous event status codes
179  */
180 #define	ASYNC_BUS_RESET			0x8001
181 #define	ASYNC_SYSTEM_ERROR		0x8002
182 #define	ASYNC_RQS_XFER_ERR		0x8003
183 #define	ASYNC_RSP_XFER_ERR		0x8004
184 #define	ASYNC_QWAKEUP			0x8005
185 #define	ASYNC_TIMEOUT_RESET		0x8006
186 #define	ASYNC_DEVICE_RESET		0x8007
187 #define	ASYNC_EXTMSG_UNDERRUN		0x800A
188 #define	ASYNC_SCAM_INT			0x800B
189 #define	ASYNC_HUNG_SCSI			0x800C
190 #define	ASYNC_KILLED_BUS		0x800D
191 #define	ASYNC_BUS_TRANSIT		0x800E	/* LVD -> HVD, eg. */
192 #define	ASYNC_LIP_OCCURRED		0x8010
193 #define	ASYNC_LOOP_UP			0x8011
194 #define	ASYNC_LOOP_DOWN			0x8012
195 #define	ASYNC_LOOP_RESET		0x8013
196 #define	ASYNC_PDB_CHANGED		0x8014
197 #define	ASYNC_CHANGE_NOTIFY		0x8015
198 #define	ASYNC_LIP_F8			0x8016
199 #define	ASYNC_CMD_CMPLT			0x8020
200 #define	ASYNC_CTIO_DONE			0x8021
201 #define	ASYNC_IP_XMIT_DONE		0x8022
202 #define	ASYNC_IP_RECV_DONE		0x8023
203 #define	ASYNC_IP_BROADCAST		0x8024
204 #define	ASYNC_IP_RCVQ_LOW		0x8025
205 #define	ASYNC_IP_RCVQ_EMPTY		0x8026
206 #define	ASYNC_IP_RECV_DONE_ALIGNED	0x8027
207 #define	ASYNC_PTPMODE			0x8030
208 #define	ASYNC_RIO1			0x8031
209 #define	ASYNC_RIO2			0x8032
210 #define	ASYNC_RIO3			0x8033
211 #define	ASYNC_RIO4			0x8034
212 #define	ASYNC_RIO5			0x8035
213 #define	ASYNC_CONNMODE			0x8036
214 #define		ISP_CONN_LOOP		1
215 #define		ISP_CONN_PTP		2
216 #define		ISP_CONN_BADLIP		3
217 #define		ISP_CONN_FATAL		4
218 #define		ISP_CONN_LOOPBACK	5
219 #define	ASYNC_RIO_RESP			0x8040
220 #define	ASYNC_RIO_COMP			0x8042
221 /*
222  * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options
223  * mailbox command to enable this.
224  */
225 #define	ASYNC_QFULL_SENT		0x8049
226 
227 /*
228  * Mailbox Usages
229  */
230 
231 #define	WRITE_REQUEST_QUEUE_IN_POINTER(isp, value)	\
232 	ISP_WRITE(isp, isp->isp_rqstinrp, value)
233 
234 #define	READ_REQUEST_QUEUE_OUT_POINTER(isp)		\
235 	ISP_READ(isp, isp->isp_rqstoutrp)
236 
237 #define	READ_RESPONSE_QUEUE_IN_POINTER(isp)		\
238 	ISP_READ(isp, isp->isp_respinrp)
239 
240 #define	WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value)	\
241 	ISP_WRITE(isp, isp->isp_respoutrp, value)
242 
243 /*
244  * Command Structure Definitions
245  */
246 
247 typedef struct {
248 	u_int32_t	ds_base;
249 	u_int32_t	ds_count;
250 } ispds_t;
251 
252 typedef struct {
253 	u_int32_t	ds_base;
254 	u_int32_t	ds_basehi;
255 	u_int32_t	ds_count;
256 } ispds64_t;
257 
258 #define	DSTYPE_32BIT	0
259 #define	DSTYPE_64BIT	1
260 typedef struct {
261 	u_int16_t	ds_type;	/* 0-> ispds_t, 1-> ispds64_t */
262 	u_int32_t	ds_segment;	/* unused */
263 	u_int32_t	ds_base;	/* 32 bit address of DSD list */
264 } ispdslist_t;
265 
266 
267 /*
268  * These elements get swizzled around for SBus instances.
269  */
270 #define	ISP_SWAP8(a, b)	{		\
271 	u_int8_t tmp;			\
272 	tmp = a;			\
273 	a = b;				\
274 	b = tmp;			\
275 }
276 typedef struct {
277 	u_int8_t	rqs_entry_type;
278 	u_int8_t	rqs_entry_count;
279 	u_int8_t	rqs_seqno;
280 	u_int8_t	rqs_flags;
281 } isphdr_t;
282 
283 /* RQS Flag definitions */
284 #define	RQSFLAG_CONTINUATION	0x01
285 #define	RQSFLAG_FULL		0x02
286 #define	RQSFLAG_BADHEADER	0x04
287 #define	RQSFLAG_BADPACKET	0x08
288 
289 /* RQS entry_type definitions */
290 #define	RQSTYPE_REQUEST		0x01
291 #define	RQSTYPE_DATASEG		0x02
292 #define	RQSTYPE_RESPONSE	0x03
293 #define	RQSTYPE_MARKER		0x04
294 #define	RQSTYPE_CMDONLY		0x05
295 #define	RQSTYPE_ATIO		0x06	/* Target Mode */
296 #define	RQSTYPE_CTIO		0x07	/* Target Mode */
297 #define	RQSTYPE_SCAM		0x08
298 #define	RQSTYPE_A64		0x09
299 #define	RQSTYPE_A64_CONT	0x0a
300 #define	RQSTYPE_ENABLE_LUN	0x0b	/* Target Mode */
301 #define	RQSTYPE_MODIFY_LUN	0x0c	/* Target Mode */
302 #define	RQSTYPE_NOTIFY		0x0d	/* Target Mode */
303 #define	RQSTYPE_NOTIFY_ACK	0x0e	/* Target Mode */
304 #define	RQSTYPE_CTIO1		0x0f	/* Target Mode */
305 #define	RQSTYPE_STATUS_CONT	0x10
306 #define	RQSTYPE_T2RQS		0x11
307 #define	RQSTYPE_IP_XMIT		0x13
308 #define	RQSTYPE_T4RQS		0x15
309 #define	RQSTYPE_ATIO2		0x16	/* Target Mode */
310 #define	RQSTYPE_CTIO2		0x17	/* Target Mode */
311 #define	RQSTYPE_CSET0		0x18
312 #define	RQSTYPE_T3RQS		0x19
313 #define	RQSTYPE_IP_XMIT_64	0x1b
314 #define	RQSTYPE_CTIO4		0x1e	/* Target Mode */
315 #define	RQSTYPE_CTIO3		0x1f	/* Target Mode */
316 #define	RQSTYPE_RIO1		0x21
317 #define	RQSTYPE_RIO2		0x22
318 #define	RQSTYPE_IP_RECV		0x23
319 #define	RQSTYPE_IP_RECV_CONT	0x24
320 
321 
322 #define	ISP_RQDSEG	4
323 typedef struct {
324 	isphdr_t	req_header;
325 	u_int32_t	req_handle;
326 	u_int8_t	req_lun_trn;
327 	u_int8_t	req_target;
328 	u_int16_t	req_cdblen;
329 #define	req_modifier	req_cdblen	/* marker packet */
330 	u_int16_t	req_flags;
331 	u_int16_t	req_reserved;
332 	u_int16_t	req_time;
333 	u_int16_t	req_seg_count;
334 	u_int8_t	req_cdb[12];
335 	ispds_t		req_dataseg[ISP_RQDSEG];
336 } ispreq_t;
337 
338 /*
339  * A request packet can also be a marker packet.
340  */
341 #define SYNC_DEVICE	0
342 #define SYNC_TARGET	1
343 #define SYNC_ALL	2
344 
345 #define	ISP_RQDSEG_T2		3
346 typedef struct {
347 	isphdr_t	req_header;
348 	u_int32_t	req_handle;
349 	u_int8_t	req_lun_trn;
350 	u_int8_t	req_target;
351 	u_int16_t	req_scclun;
352 	u_int16_t	req_flags;
353 	u_int16_t	_res2;
354 	u_int16_t	req_time;
355 	u_int16_t	req_seg_count;
356 	u_int8_t	req_cdb[16];
357 	u_int32_t	req_totalcnt;
358 	ispds_t		req_dataseg[ISP_RQDSEG_T2];
359 } ispreqt2_t;
360 
361 #define	ISP_RQDSEG_T3		2
362 typedef struct {
363 	isphdr_t	req_header;
364 	u_int32_t	req_handle;
365 	u_int8_t	req_lun_trn;
366 	u_int8_t	req_target;
367 	u_int16_t	req_scclun;
368 	u_int16_t	req_flags;
369 	u_int16_t	_res2;
370 	u_int16_t	req_time;
371 	u_int16_t	req_seg_count;
372 	u_int8_t	req_cdb[16];
373 	u_int32_t	req_totalcnt;
374 	ispds64_t	req_dataseg[ISP_RQDSEG_T3];
375 } ispreqt3_t;
376 
377 /* req_flag values */
378 #define	REQFLAG_NODISCON	0x0001
379 #define	REQFLAG_HTAG		0x0002
380 #define	REQFLAG_OTAG		0x0004
381 #define	REQFLAG_STAG		0x0008
382 #define	REQFLAG_TARGET_RTN	0x0010
383 
384 #define	REQFLAG_NODATA		0x0000
385 #define	REQFLAG_DATA_IN		0x0020
386 #define	REQFLAG_DATA_OUT	0x0040
387 #define	REQFLAG_DATA_UNKNOWN	0x0060
388 
389 #define	REQFLAG_DISARQ		0x0100
390 #define	REQFLAG_FRC_ASYNC	0x0200
391 #define	REQFLAG_FRC_SYNC	0x0400
392 #define	REQFLAG_FRC_WIDE	0x0800
393 #define	REQFLAG_NOPARITY	0x1000
394 #define	REQFLAG_STOPQ		0x2000
395 #define	REQFLAG_XTRASNS		0x4000
396 #define	REQFLAG_PRIORITY	0x8000
397 
398 typedef struct {
399 	isphdr_t	req_header;
400 	u_int32_t	req_handle;
401 	u_int8_t	req_lun_trn;
402 	u_int8_t	req_target;
403 	u_int16_t	req_cdblen;
404 	u_int16_t	req_flags;
405 	u_int16_t	_res1;
406 	u_int16_t	req_time;
407 	u_int16_t	req_seg_count;
408 	u_int8_t	req_cdb[44];
409 } ispextreq_t;
410 
411 #define	ISP_CDSEG	7
412 typedef struct {
413 	isphdr_t	req_header;
414 	u_int32_t	_res1;
415 	ispds_t		req_dataseg[ISP_CDSEG];
416 } ispcontreq_t;
417 
418 #define	ISP_CDSEG64	5
419 typedef struct {
420 	isphdr_t	req_header;
421 	ispds64_t	req_dataseg[ISP_CDSEG64];
422 } ispcontreq64_t;
423 
424 typedef struct {
425 	isphdr_t	req_header;
426 	u_int32_t	req_handle;
427 	u_int16_t	req_scsi_status;
428 	u_int16_t	req_completion_status;
429 	u_int16_t	req_state_flags;
430 	u_int16_t	req_status_flags;
431 	u_int16_t	req_time;
432 #define	req_response_len	req_time	/* FC only */
433 	u_int16_t	req_sense_len;
434 	u_int32_t	req_resid;
435 	u_int8_t	req_response[8];	/* FC only */
436 	u_int8_t	req_sense_data[32];
437 } ispstatusreq_t;
438 
439 typedef struct {
440 	isphdr_t	req_header;
441 	u_int8_t	req_sense_data[60];
442 } ispstatus_cont_t;
443 
444 /*
445  * For Qlogic 2X00, the high order byte of SCSI status has
446  * additional meaning.
447  */
448 #define	RQCS_RU	0x800	/* Residual Under */
449 #define	RQCS_RO	0x400	/* Residual Over */
450 #define	RQCS_RESID	(RQCS_RU|RQCS_RO)
451 #define	RQCS_SV	0x200	/* Sense Length Valid */
452 #define	RQCS_RV	0x100	/* FCP Response Length Valid */
453 
454 /*
455  * Completion Status Codes.
456  */
457 #define RQCS_COMPLETE			0x0000
458 #define RQCS_DMA_ERROR			0x0002
459 #define RQCS_RESET_OCCURRED		0x0004
460 #define RQCS_ABORTED			0x0005
461 #define RQCS_TIMEOUT			0x0006
462 #define RQCS_DATA_OVERRUN		0x0007
463 #define RQCS_DATA_UNDERRUN		0x0015
464 #define	RQCS_QUEUE_FULL			0x001C
465 
466 /* 1X00 Only Completion Codes */
467 #define RQCS_INCOMPLETE			0x0001
468 #define RQCS_TRANSPORT_ERROR		0x0003
469 #define RQCS_COMMAND_OVERRUN		0x0008
470 #define RQCS_STATUS_OVERRUN		0x0009
471 #define RQCS_BAD_MESSAGE		0x000a
472 #define RQCS_NO_MESSAGE_OUT		0x000b
473 #define RQCS_EXT_ID_FAILED		0x000c
474 #define RQCS_IDE_MSG_FAILED		0x000d
475 #define RQCS_ABORT_MSG_FAILED		0x000e
476 #define RQCS_REJECT_MSG_FAILED		0x000f
477 #define RQCS_NOP_MSG_FAILED		0x0010
478 #define RQCS_PARITY_ERROR_MSG_FAILED	0x0011
479 #define RQCS_DEVICE_RESET_MSG_FAILED	0x0012
480 #define RQCS_ID_MSG_FAILED		0x0013
481 #define RQCS_UNEXP_BUS_FREE		0x0014
482 #define	RQCS_XACT_ERR1			0x0018
483 #define	RQCS_XACT_ERR2			0x0019
484 #define	RQCS_XACT_ERR3			0x001A
485 #define	RQCS_BAD_ENTRY			0x001B
486 #define	RQCS_PHASE_SKIPPED		0x001D
487 #define	RQCS_ARQS_FAILED		0x001E
488 #define	RQCS_WIDE_FAILED		0x001F
489 #define	RQCS_SYNCXFER_FAILED		0x0020
490 #define	RQCS_LVD_BUSERR			0x0021
491 
492 /* 2X00 Only Completion Codes */
493 #define	RQCS_PORT_UNAVAILABLE		0x0028
494 #define	RQCS_PORT_LOGGED_OUT		0x0029
495 #define	RQCS_PORT_CHANGED		0x002A
496 #define	RQCS_PORT_BUSY			0x002B
497 
498 /*
499  * 1X00 specific State Flags
500  */
501 #define RQSF_GOT_BUS			0x0100
502 #define RQSF_GOT_TARGET			0x0200
503 #define RQSF_SENT_CDB			0x0400
504 #define RQSF_XFRD_DATA			0x0800
505 #define RQSF_GOT_STATUS			0x1000
506 #define RQSF_GOT_SENSE			0x2000
507 #define	RQSF_XFER_COMPLETE		0x4000
508 
509 /*
510  * 2X00 specific State Flags
511  * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available)
512  */
513 #define	RQSF_DATA_IN			0x0020
514 #define	RQSF_DATA_OUT			0x0040
515 #define	RQSF_STAG			0x0008
516 #define	RQSF_OTAG			0x0004
517 #define	RQSF_HTAG			0x0002
518 /*
519  * 1X00 Status Flags
520  */
521 #define RQSTF_DISCONNECT		0x0001
522 #define RQSTF_SYNCHRONOUS		0x0002
523 #define RQSTF_PARITY_ERROR		0x0004
524 #define RQSTF_BUS_RESET			0x0008
525 #define RQSTF_DEVICE_RESET		0x0010
526 #define RQSTF_ABORTED			0x0020
527 #define RQSTF_TIMEOUT			0x0040
528 #define RQSTF_NEGOTIATION		0x0080
529 
530 /*
531  * 2X00 specific state flags
532  */
533 /* RQSF_SENT_CDB	*/
534 /* RQSF_XFRD_DATA	*/
535 /* RQSF_GOT_STATUS	*/
536 /* RQSF_XFER_COMPLETE	*/
537 
538 /*
539  * 2X00 specific status flags
540  */
541 /* RQSTF_ABORTED */
542 /* RQSTF_TIMEOUT */
543 #define	RQSTF_DMA_ERROR			0x0080
544 #define	RQSTF_LOGOUT			0x2000
545 
546 /*
547  * Miscellaneous
548  */
549 #ifndef	ISP_EXEC_THROTTLE
550 #define	ISP_EXEC_THROTTLE	16
551 #endif
552 
553 /*
554  * About Firmware returns an 'attribute' word in mailbox 6.
555  */
556 #define	ISP_FW_ATTR_TMODE	0x01
557 #define	ISP_FW_ATTR_SCCLUN	0x02
558 #define	ISP_FW_ATTR_FABRIC	0x04
559 #define	ISP_FW_ATTR_CLASS2	0x08
560 #define	ISP_FW_ATTR_FCTAPE	0x10
561 #define	ISP_FW_ATTR_IP		0x20
562 
563 /*
564  * Reduced Interrupt Operation Response Queue Entreis
565  */
566 
567 typedef struct {
568 	isphdr_t	req_header;
569 	u_int32_t	req_handles[15];
570 } isp_rio1_t;
571 
572 typedef struct {
573 	isphdr_t	req_header;
574 	u_int16_t	req_handles[30];
575 } isp_rio2_t;
576 
577 /*
578  * FC (ISP2100) specific data structures
579  */
580 
581 /*
582  * Initialization Control Block
583  *
584  * Version One (prime) format.
585  */
586 typedef struct isp_icb {
587 	u_int8_t	icb_version;
588 	u_int8_t	_reserved0;
589 	u_int16_t	icb_fwoptions;
590 	u_int16_t	icb_maxfrmlen;
591 	u_int16_t	icb_maxalloc;
592 	u_int16_t	icb_execthrottle;
593 	u_int8_t	icb_retry_count;
594 	u_int8_t	icb_retry_delay;
595 	u_int8_t	icb_portname[8];
596 	u_int16_t	icb_hardaddr;
597 	u_int8_t	icb_iqdevtype;
598 	u_int8_t	icb_logintime;
599 	u_int8_t	icb_nodename[8];
600 	u_int16_t	icb_rqstout;
601 	u_int16_t	icb_rspnsin;
602 	u_int16_t	icb_rqstqlen;
603 	u_int16_t	icb_rsltqlen;
604 	u_int16_t	icb_rqstaddr[4];
605 	u_int16_t	icb_respaddr[4];
606 	u_int16_t	icb_lunenables;
607 	u_int8_t	icb_ccnt;
608 	u_int8_t	icb_icnt;
609 	u_int16_t	icb_lunetimeout;
610 	u_int16_t	_reserved1;
611 	u_int16_t	icb_xfwoptions;
612 	u_int8_t	icb_racctimer;
613 	u_int8_t	icb_idelaytimer;
614 	u_int16_t	icb_zfwoptions;
615 	u_int16_t	_reserved2[13];
616 } isp_icb_t;
617 #define	ICB_VERSION1	1
618 
619 #define	ICBOPT_HARD_ADDRESS	0x0001
620 #define	ICBOPT_FAIRNESS		0x0002
621 #define	ICBOPT_FULL_DUPLEX	0x0004
622 #define	ICBOPT_FAST_POST	0x0008
623 #define	ICBOPT_TGT_ENABLE	0x0010
624 #define	ICBOPT_INI_DISABLE	0x0020
625 #define	ICBOPT_INI_ADISC	0x0040
626 #define	ICBOPT_INI_TGTTYPE	0x0080
627 #define	ICBOPT_PDBCHANGE_AE	0x0100
628 #define	ICBOPT_NOLIP		0x0200
629 #define	ICBOPT_SRCHDOWN		0x0400
630 #define	ICBOPT_PREVLOOP		0x0800
631 #define	ICBOPT_STOP_ON_QFULL	0x1000
632 #define	ICBOPT_FULL_LOGIN	0x2000
633 #define	ICBOPT_BOTH_WWNS	0x4000
634 #define	ICBOPT_EXTENDED		0x8000
635 
636 #define	ICBXOPT_CLASS2_ACK0	0x0200
637 #define	ICBXOPT_CLASS2		0x0100
638 #define	ICBXOPT_LOOP_ONLY	(0 << 4)
639 #define	ICBXOPT_PTP_ONLY	(1 << 4)
640 #define	ICBXOPT_LOOP_2_PTP	(2 << 4)
641 #define	ICBXOPT_PTP_2_LOOP	(3 << 4)
642 
643 #define	ICBXOPT_RIO_OFF		0
644 #define	ICBXOPT_RIO_16BIT	1
645 #define	ICBXOPT_RIO_32BIT	2
646 #define	ICBXOPT_RIO_16BIT_IOCB	3
647 #define	ICBXOPT_RIO_32BIT_IOCB	4
648 
649 #define	ICBZOPT_ENA_RDXFR_RDY	0x01
650 #define	ICBZOPT_ENA_OOF		(1 << 6) /* out of order frame handling */
651 /* These 3 only apply to the 2300 */
652 #define	ICBZOPT_RATE_ONEGB	(MBGSD_ONEGB << 14)
653 #define	ICBZOPT_RATE_TWOGB	(MBGSD_TWOGB << 14)
654 #define	ICBZOPT_RATE_AUTO	(MBGSD_AUTO << 14)
655 
656 
657 #define	ICB_MIN_FRMLEN		256
658 #define	ICB_MAX_FRMLEN		2112
659 #define	ICB_DFLT_FRMLEN		1024
660 #define	ICB_DFLT_ALLOC		256
661 #define	ICB_DFLT_THROTTLE	16
662 #define	ICB_DFLT_RDELAY		5
663 #define	ICB_DFLT_RCOUNT		3
664 
665 
666 #define	RQRSP_ADDR0015	0
667 #define	RQRSP_ADDR1631	1
668 #define	RQRSP_ADDR3247	2
669 #define	RQRSP_ADDR4863	3
670 
671 
672 #define	ICB_NNM0	7
673 #define	ICB_NNM1	6
674 #define	ICB_NNM2	5
675 #define	ICB_NNM3	4
676 #define	ICB_NNM4	3
677 #define	ICB_NNM5	2
678 #define	ICB_NNM6	1
679 #define	ICB_NNM7	0
680 
681 #define	MAKE_NODE_NAME_FROM_WWN(array, wwn)	\
682 	array[ICB_NNM0] = (u_int8_t) ((wwn >>  0) & 0xff), \
683 	array[ICB_NNM1] = (u_int8_t) ((wwn >>  8) & 0xff), \
684 	array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \
685 	array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \
686 	array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \
687 	array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \
688 	array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \
689 	array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff)
690 
691 /*
692  * FC-AL Position Map
693  *
694  * This is an at most 128 byte map that returns either
695  * the LILP or Firmware generated list of ports.
696  *
697  * We deviate a bit from the returned qlogic format to
698  * use an extra bit to say whether this was a LILP or
699  * f/w generated map.
700  */
701 typedef struct {
702 	u_int8_t	fwmap	: 1,
703 			count	: 7;
704 	u_int8_t	map[127];
705 } fcpos_map_t;
706 
707 /*
708  * Port Data Base Element
709  */
710 
711 typedef struct {
712 	u_int16_t	pdb_options;
713 	u_int8_t	pdb_mstate;
714 	u_int8_t	pdb_sstate;
715 #define	BITS2WORD(x)	((x)[0] << 16 | (x)[3] << 8 | (x)[2])
716 	u_int8_t	pdb_hardaddr_bits[4];
717 	u_int8_t	pdb_portid_bits[4];
718 	u_int8_t	pdb_nodename[8];
719 	u_int8_t	pdb_portname[8];
720 	u_int16_t	pdb_execthrottle;
721 	u_int16_t	pdb_exec_count;
722 	u_int8_t	pdb_retry_count;
723 	u_int8_t	pdb_retry_delay;
724 	u_int16_t	pdb_resalloc;
725 	u_int16_t	pdb_curalloc;
726 	u_int16_t	pdb_qhead;
727 	u_int16_t	pdb_qtail;
728 	u_int16_t	pdb_tl_next;
729 	u_int16_t	pdb_tl_last;
730 	u_int16_t	pdb_features;	/* PLOGI, Common Service */
731 	u_int16_t	pdb_pconcurrnt;	/* PLOGI, Common Service */
732 	u_int16_t	pdb_roi;	/* PLOGI, Common Service */
733 	u_int8_t	pdb_target;
734 	u_int8_t	pdb_initiator;	/* PLOGI, Class 3 Control Flags */
735 	u_int16_t	pdb_rdsiz;	/* PLOGI, Class 3 */
736 	u_int16_t	pdb_ncseq;	/* PLOGI, Class 3 */
737 	u_int16_t	pdb_noseq;	/* PLOGI, Class 3 */
738 	u_int16_t	pdb_labrtflg;
739 	u_int16_t	pdb_lstopflg;
740 	u_int16_t	pdb_sqhead;
741 	u_int16_t	pdb_sqtail;
742 	u_int16_t	pdb_ptimer;
743 	u_int16_t	pdb_nxt_seqid;
744 	u_int16_t	pdb_fcount;
745 	u_int16_t	pdb_prli_len;
746 	u_int16_t	pdb_prli_svc0;
747 	u_int16_t	pdb_prli_svc3;
748 	u_int16_t	pdb_loopid;
749 	u_int16_t	pdb_il_ptr;
750 	u_int16_t	pdb_sl_ptr;
751 } isp_pdb_t;
752 
753 #define	PDB_OPTIONS_XMITTING	(1<<11)
754 #define	PDB_OPTIONS_LNKXMIT	(1<<10)
755 #define	PDB_OPTIONS_ABORTED	(1<<9)
756 #define	PDB_OPTIONS_ADISC	(1<<1)
757 
758 #define	PDB_STATE_DISCOVERY	0
759 #define	PDB_STATE_WDISC_ACK	1
760 #define	PDB_STATE_PLOGI		2
761 #define	PDB_STATE_PLOGI_ACK	3
762 #define	PDB_STATE_PRLI		4
763 #define	PDB_STATE_PRLI_ACK	5
764 #define	PDB_STATE_LOGGED_IN	6
765 #define	PDB_STATE_PORT_UNAVAIL	7
766 #define	PDB_STATE_PRLO		8
767 #define	PDB_STATE_PRLO_ACK	9
768 #define	PDB_STATE_PLOGO		10
769 #define	PDB_STATE_PLOG_ACK	11
770 
771 #define		SVC3_TGT_ROLE		0x10
772 #define 	SVC3_INI_ROLE		0x20
773 #define			SVC3_ROLE_MASK	0x30
774 #define			SVC3_ROLE_SHIFT	4
775 
776 #define	SNS_GAN	0x100
777 #define	SNS_GP3	0x171
778 #define	SNS_RFT	0x217
779 typedef struct {
780 	u_int16_t	snscb_rblen;	/* response buffer length (words) */
781 	u_int16_t	snscb_res0;
782 	u_int16_t	snscb_addr[4];	/* response buffer address */
783 	u_int16_t	snscb_sblen;	/* subcommand buffer length (words) */
784 	u_int16_t	snscb_res1;
785 	u_int16_t	snscb_data[1];	/* variable data */
786 } sns_screq_t;	/* Subcommand Request Structure */
787 #define	SNS_GAN_REQ_SIZE	(sizeof (sns_screq_t)+(5*(sizeof (u_int16_t))))
788 #define	SNS_GP3_REQ_SIZE	(sizeof (sns_screq_t)+(5*(sizeof (u_int16_t))))
789 #define	SNS_RFT_REQ_SIZE	(sizeof (sns_screq_t)+(21*(sizeof (u_int16_t))))
790 
791 typedef struct {
792 	u_int8_t	snscb_cthdr[16];
793 	u_int8_t	snscb_port_type;
794 	u_int8_t	snscb_port_id[3];
795 	u_int8_t	snscb_portname[8];
796 	u_int16_t	snscb_data[1];	/* variable data */
797 } sns_scrsp_t;	/* Subcommand Response Structure */
798 #define	SNS_GAN_RESP_SIZE	608	/* Maximum response size (bytes) */
799 #define	SNS_GP3_RESP_SIZE	532	/* XXX: For 128 ports */
800 #define	SNS_RFT_RESP_SIZE	16
801 
802 typedef struct {
803 	u_int8_t	snscb_cthdr[16];
804 	u_int8_t	snscb_port_type;
805 	u_int8_t	snscb_port_id[3];
806 	u_int8_t	snscb_portname[8];
807 	u_int8_t	snscb_pnlen;		/* symbolic port name length */
808 	u_int8_t	snscb_pname[255];	/* symbolic port name */
809 	u_int8_t	snscb_nodename[8];
810 	u_int8_t	snscb_nnlen;		/* symbolic node name length */
811 	u_int8_t	snscb_nname[255];	/* symbolic node name */
812 	u_int8_t	snscb_ipassoc[8];
813 	u_int8_t	snscb_ipaddr[16];
814 	u_int8_t	snscb_svc_class[4];
815 	u_int8_t	snscb_fc4_types[32];
816 	u_int8_t	snscb_fpname[8];
817 	u_int8_t	snscb_reserved;
818 	u_int8_t	snscb_hardaddr[3];
819 } sns_ganrsp_t;	/* Subcommand Response Structure */
820 
821 #endif	/* _ISPMBOX_H */
822