1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause 4 * 5 * Copyright (c) 2009-2020 Alexander Motin <mav@FreeBSD.org> 6 * Copyright (c) 1997-2009 by Matthew Jacob 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Mailbox and Queue Entry Definitions for Qlogic ISP SCSI adapters. 35 */ 36 #ifndef _ISPMBOX_H 37 #define _ISPMBOX_H 38 39 /* 40 * Mailbox Command Opcodes 41 */ 42 #define MBOX_NO_OP 0x0000 43 #define MBOX_LOAD_RAM 0x0001 44 #define MBOX_EXEC_FIRMWARE 0x0002 45 #define MBOX_DUMP_RAM 0x0003 46 #define MBOX_WRITE_RAM_WORD 0x0004 47 #define MBOX_READ_RAM_WORD 0x0005 48 #define MBOX_MAILBOX_REG_TEST 0x0006 49 #define MBOX_VERIFY_CHECKSUM 0x0007 50 #define MBOX_ABOUT_FIRMWARE 0x0008 51 #define MBOX_LOAD_RISC_RAM_2100 0x0009 52 /* a */ 53 #define MBOX_LOAD_RISC_RAM 0x000b 54 #define MBOX_DUMP_RISC_RAM 0x000c 55 #define MBOX_WRITE_RAM_WORD_EXTENDED 0x000d 56 #define MBOX_CHECK_FIRMWARE 0x000e 57 #define MBOX_READ_RAM_WORD_EXTENDED 0x000f 58 #define MBOX_INIT_REQ_QUEUE 0x0010 59 #define MBOX_INIT_RES_QUEUE 0x0011 60 #define MBOX_EXECUTE_IOCB 0x0012 61 #define MBOX_WAKE_UP 0x0013 62 #define MBOX_STOP_FIRMWARE 0x0014 63 #define MBOX_ABORT 0x0015 64 #define MBOX_ABORT_DEVICE 0x0016 65 #define MBOX_ABORT_TARGET 0x0017 66 #define MBOX_BUS_RESET 0x0018 67 #define MBOX_STOP_QUEUE 0x0019 68 #define MBOX_START_QUEUE 0x001a 69 #define MBOX_SINGLE_STEP_QUEUE 0x001b 70 #define MBOX_ABORT_QUEUE 0x001c 71 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 72 /* 1e */ 73 #define MBOX_GET_FIRMWARE_STATUS 0x001f 74 #define MBOX_GET_INIT_SCSI_ID 0x0020 75 #define MBOX_GET_SELECT_TIMEOUT 0x0021 76 #define MBOX_GET_RETRY_COUNT 0x0022 77 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 78 #define MBOX_GET_CLOCK_RATE 0x0024 79 #define MBOX_GET_ACT_NEG_STATE 0x0025 80 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 81 #define MBOX_GET_SBUS_PARAMS 0x0027 82 #define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS 83 #define MBOX_GET_TARGET_PARAMS 0x0028 84 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 85 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a 86 /* 2b */ 87 /* 2c */ 88 /* 2d */ 89 /* 2e */ 90 /* 2f */ 91 #define MBOX_SET_INIT_SCSI_ID 0x0030 92 #define MBOX_SET_SELECT_TIMEOUT 0x0031 93 #define MBOX_SET_RETRY_COUNT 0x0032 94 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 95 #define MBOX_SET_CLOCK_RATE 0x0034 96 #define MBOX_SET_ACT_NEG_STATE 0x0035 97 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 98 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 99 #define MBOX_SET_PCI_PARAMETERS 0x0037 100 #define MBOX_SET_TARGET_PARAMS 0x0038 101 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 102 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a 103 /* 3b */ 104 /* 3c */ 105 /* 3d */ 106 /* 3e */ 107 /* 3f */ 108 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 109 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 110 #define MBOX_EXEC_BIOS_IOCB 0x0042 111 #define MBOX_SET_FW_FEATURES 0x004a 112 #define MBOX_GET_FW_FEATURES 0x004b 113 #define FW_FEATURE_FAST_POST 0x1 114 #define FW_FEATURE_LVD_NOTIFY 0x2 115 #define FW_FEATURE_RIO_32BIT 0x4 116 #define FW_FEATURE_RIO_16BIT 0x8 117 118 #define MBOX_INIT_REQ_QUEUE_A64 0x0052 119 #define MBOX_INIT_RES_QUEUE_A64 0x0053 120 121 #define MBOX_ENABLE_TARGET_MODE 0x0055 122 #define ENABLE_TARGET_FLAG 0x8000 123 #define ENABLE_TQING_FLAG 0x0004 124 #define ENABLE_MANDATORY_DISC 0x0002 125 #define MBOX_GET_TARGET_STATUS 0x0056 126 127 /* These are for the ISP2X00 FC cards */ 128 #define MBOX_LOAD_FLASH_FIRMWARE 0x0003 129 #define MBOX_WRITE_FC_SERDES_REG 0x0003 /* FC only */ 130 #define MBOX_READ_FC_SERDES_REG 0x0004 /* FC only */ 131 #define MBOX_GET_IO_STATUS 0x0012 132 #define MBOX_SET_TRANSMIT_PARAMS 0x0019 133 #define MBOX_SET_PORT_PARAMS 0x001a 134 #define MBOX_LOAD_OP_FW_PARAMS 0x001b 135 #define MBOX_INIT_MULTIPLE_QUEUE 0x001f 136 #define MBOX_GET_LOOP_ID 0x0020 137 /* for 24XX cards, outgoing mailbox 7 has these values for F or FL topologies */ 138 #define ISP24XX_INORDER 0x0100 139 #define ISP24XX_NPIV_SAN 0x0400 140 #define ISP24XX_VSAN_SAN 0x1000 141 #define ISP24XX_FC_SP_SAN 0x2000 142 #define MBOX_GET_TIMEOUT_PARAMS 0x0022 143 #define MBOX_GET_FIRMWARE_OPTIONS 0x0028 144 #define MBOX_GENERATE_SYSTEM_ERROR 0x002a 145 #define MBOX_WRITE_SFP 0x0030 146 #define MBOX_READ_SFP 0x0031 147 #define MBOX_SET_TIMEOUT_PARAMS 0x0032 148 #define MBOX_SET_FIRMWARE_OPTIONS 0x0038 149 #define MBOX_GET_SET_FC_LED_CONF 0x003b 150 #define MBOX_RESTART_NIC_FIRMWARE 0x003d /* FCoE only */ 151 #define MBOX_ACCESS_CONTROL 0x003e 152 #define MBOX_LOOP_PORT_BYPASS 0x0040 /* FC only */ 153 #define MBOX_LOOP_PORT_ENABLE 0x0041 /* FC only */ 154 #define MBOX_GET_RESOURCE_COUNT 0x0042 155 #define MBOX_REQUEST_OFFLINE_MODE 0x0043 156 #define MBOX_DIAGNOSTIC_ECHO_TEST 0x0044 157 #define MBOX_DIAGNOSTIC_LOOPBACK 0x0045 158 #define MBOX_ENHANCED_GET_PDB 0x0047 159 #define MBOX_INIT_FIRMWARE_MULTI_ID 0x0048 /* 2400 only */ 160 #define MBOX_GET_VP_DATABASE 0x0049 /* 2400 only */ 161 #define MBOX_GET_VP_DATABASE_ENTRY 0x004a /* 2400 only */ 162 #define MBOX_GET_FCF_LIST 0x0050 /* FCoE only */ 163 #define MBOX_GET_DCBX_PARAMETERS 0x0051 /* FCoE only */ 164 #define MBOX_HOST_MEMORY_COPY 0x0053 165 #define MBOX_EXEC_COMMAND_IOCB_A64 0x0054 166 #define MBOX_SEND_RNID 0x0057 167 #define MBOX_SET_PARAMETERS 0x0059 168 #define MBOX_GET_PARAMETERS 0x005a 169 #define MBOX_DRIVER_HEARTBEAT 0x005B /* FC only */ 170 #define MBOX_FW_HEARTBEAT 0x005C 171 #define MBOX_GET_SET_DATA_RATE 0x005D /* >=23XX only */ 172 #define MBGSD_GET_RATE 0 173 #define MBGSD_SET_RATE 1 174 #define MBGSD_SET_RATE_NOW 2 /* 24XX only */ 175 #define MBGSD_1GB 0x00 176 #define MBGSD_2GB 0x01 177 #define MBGSD_AUTO 0x02 178 #define MBGSD_4GB 0x03 /* 24XX only */ 179 #define MBGSD_8GB 0x04 /* 25XX only */ 180 #define MBGSD_16GB 0x05 /* 26XX only */ 181 #define MBGSD_32GB 0x06 /* 27XX only */ 182 #define MBGSD_64GB 0x07 /* 28XX only */ 183 #define MBGSD_10GB 0x13 /* 26XX only */ 184 #define MBOX_SEND_RNFT 0x005e 185 #define MBOX_INIT_FIRMWARE 0x0060 186 #define MBOX_GET_INIT_CONTROL_BLOCK 0x0061 187 #define MBOX_INIT_LIP 0x0062 188 #define MBOX_GET_FC_AL_POSITION_MAP 0x0063 189 #define MBOX_GET_PORT_DB 0x0064 190 #define MBOX_CLEAR_ACA 0x0065 191 #define MBOX_TARGET_RESET 0x0066 192 #define MBOX_CLEAR_TASK_SET 0x0067 193 #define MBOX_ABORT_TASK_SET 0x0068 194 #define MBOX_GET_FW_STATE 0x0069 195 #define MBOX_GET_PORT_NAME 0x006A 196 #define MBOX_GET_LINK_STATUS 0x006B 197 #define MBOX_INIT_LIP_RESET 0x006C 198 #define MBOX_GET_LINK_STAT_PR_DATA_CNT 0x006D 199 #define MBOX_SEND_SNS 0x006E 200 #define MBOX_FABRIC_LOGIN 0x006F 201 #define MBOX_SEND_CHANGE_REQUEST 0x0070 202 #define MBOX_FABRIC_LOGOUT 0x0071 203 #define MBOX_INIT_LIP_LOGIN 0x0072 204 #define MBOX_GET_PORT_NODE_NAME_LIST 0x0075 205 #define MBOX_SET_VENDOR_ID 0x0076 206 #define MBOX_GET_XGMAC_STATS 0x007a 207 #define MBOX_GET_ID_LIST 0x007C 208 #define MBOX_SEND_LFA 0x007d 209 #define MBOX_LUN_RESET 0x007E 210 211 #define ISP2100_SET_PCI_PARAM 0x00ff 212 213 /* 214 * Mailbox Command Complete Status Codes 215 */ 216 #define MBOX_COMMAND_COMPLETE 0x4000 217 #define MBOX_INVALID_COMMAND 0x4001 218 #define MBOX_HOST_INTERFACE_ERROR 0x4002 219 #define MBOX_TEST_FAILED 0x4003 220 #define MBOX_COMMAND_ERROR 0x4005 221 #define MBOX_COMMAND_PARAM_ERROR 0x4006 222 #define MBOX_PORT_ID_USED 0x4007 223 #define MBOX_LOOP_ID_USED 0x4008 224 #define MBOX_ALL_IDS_USED 0x4009 225 #define MBOX_NOT_LOGGED_IN 0x400A 226 #define MBOX_LINK_DOWN_ERROR 0x400B 227 #define MBOX_LOOPBACK_ERROR 0x400C 228 #define MBOX_CHECKSUM_ERROR 0x4010 229 #define MBOX_INVALID_PRODUCT_KEY 0x4020 230 /* pseudo mailbox completion codes */ 231 #define MBOX_REGS_BUSY 0x6000 /* registers in use */ 232 #define MBOX_TIMEOUT 0x6001 /* command timed out */ 233 234 #define MBLOGALL 0xffffffff 235 #define MBLOGNONE 0x00000000 236 #define MBLOGMASK(x) (1 << (((x) - 1) & 0x1f)) 237 238 /* 239 * Asynchronous event status codes 240 */ 241 #define ASYNC_BUS_RESET 0x8001 242 #define ASYNC_SYSTEM_ERROR 0x8002 243 #define ASYNC_RQS_XFER_ERR 0x8003 244 #define ASYNC_RSP_XFER_ERR 0x8004 245 #define ASYNC_ATIO_XFER_ERR 0x8005 246 #define ASYNC_TIMEOUT_RESET 0x8006 247 #define ASYNC_DEVICE_RESET 0x8007 248 #define ASYNC_EXTMSG_UNDERRUN 0x800A 249 #define ASYNC_SCAM_INT 0x800B 250 #define ASYNC_HUNG_SCSI 0x800C 251 #define ASYNC_KILLED_BUS 0x800D 252 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 253 #define ASYNC_LIP_OCCURRED 0x8010 /* FC only */ 254 #define ASYNC_LOOP_UP 0x8011 255 #define ASYNC_LOOP_DOWN 0x8012 256 #define ASYNC_LOOP_RESET 0x8013 /* FC only */ 257 #define ASYNC_PDB_CHANGED 0x8014 258 #define ASYNC_CHANGE_NOTIFY 0x8015 259 #define ASYNC_LIP_NOS_OLS_RECV 0x8016 /* FC only */ 260 #define ASYNC_LIP_ERROR 0x8017 /* FC only */ 261 #define ASYNC_AUTO_PLOGI_RJT 0x8018 262 #define ASYNC_SECURITY_UPDATE 0x801B 263 #define ASYNC_CMD_CMPLT 0x8020 264 #define ASYNC_CTIO_DONE 0x8021 265 #define ASYNC_RIO32_1 0x8021 266 #define ASYNC_RIO32_2 0x8022 267 #define ASYNC_IP_XMIT_DONE 0x8022 268 #define ASYNC_IP_RECV_DONE 0x8023 269 #define ASYNC_IP_BROADCAST 0x8024 270 #define ASYNC_IP_RCVQ_LOW 0x8025 271 #define ASYNC_IP_RCVQ_EMPTY 0x8026 272 #define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 273 #define ASYNC_ERR_LOGGING_DISABLED 0x8029 274 #define ASYNC_PTPMODE 0x8030 /* FC only */ 275 #define ASYNC_RIO16_1 0x8031 276 #define ASYNC_RIO16_2 0x8032 277 #define ASYNC_RIO16_3 0x8033 278 #define ASYNC_RIO16_4 0x8034 279 #define ASYNC_RIO16_5 0x8035 280 #define ASYNC_CONNMODE 0x8036 281 #define ISP_CONN_LOOP 1 282 #define ISP_CONN_PTP 2 283 #define ISP_CONN_BADLIP 3 284 #define ISP_CONN_FATAL 4 285 #define ISP_CONN_LOOPBACK 5 286 #define ASYNC_P2P_INIT_ERR 0x8037 287 #define ASYNC_RIOZIO_STALL 0x8040 /* there's a RIO/ZIO entry that hasn't been serviced */ 288 #define ASYNC_RIO32_2_2200 0x8042 /* same as ASYNC_RIO32_2, but for 2100/2200 */ 289 #define ASYNC_RCV_ERR 0x8048 290 /* 291 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options 292 * mailbox command to enable this. 293 */ 294 #define ASYNC_QFULL_SENT 0x8049 295 #define ASYNC_RJT_SENT 0x8049 /* 24XX only */ 296 #define ASYNC_SEL_CLASS2_P_RJT_SENT 0x804f 297 #define ASYNC_FW_RESTART_COMPLETE 0x8060 298 #define ASYNC_TEMPERATURE_ALERT 0x8070 299 #define ASYNC_INTER_DRIVER_COMP 0x8100 /* FCoE only */ 300 #define ASYNC_INTER_DRIVER_NOTIFY 0x8101 /* FCoE only */ 301 #define ASYNC_INTER_DRIVER_TIME_EXT 0x8102 /* FCoE only */ 302 #define ASYNC_TRANSCEIVER_INSERTION 0x8130 303 #define ASYNC_TRANSCEIVER_REMOVAL 0x8131 304 #define ASYNC_NIC_FW_STATE_CHANGE 0x8200 /* FCoE only */ 305 #define ASYNC_AUTOLOAD_FW_COMPLETE 0x8400 306 #define ASYNC_AUTOLOAD_FW_FAILURE 0x8401 307 308 /* 309 * Firmware Options. There are a lot of them. 310 * 311 * IFCOPTN - ISP Fibre Channel Option Word N 312 */ 313 #define IFCOPT1_EQFQASYNC (1 << 13) /* enable QFULL notification */ 314 #define IFCOPT1_EAABSRCVD (1 << 12) 315 #define IFCOPT1_RJTASYNC (1 << 11) /* enable 8018 notification */ 316 #define IFCOPT1_ENAPURE (1 << 10) 317 #define IFCOPT1_ENA8017 (1 << 7) 318 #define IFCOPT1_DISGPIO67 (1 << 6) 319 #define IFCOPT1_LIPLOSSIMM (1 << 5) 320 #define IFCOPT1_DISF7SWTCH (1 << 4) 321 #define IFCOPT1_CTIO_RETRY (1 << 3) 322 #define IFCOPT1_LIPASYNC (1 << 1) 323 #define IFCOPT1_LIPF8 (1 << 0) 324 325 #define IFCOPT2_LOOPBACK (1 << 1) 326 #define IFCOPT2_ATIO3_ONLY (1 << 0) 327 328 #define IFCOPT3_NOPRLI (1 << 4) /* disable automatic sending of PRLI on local loops */ 329 #define IFCOPT3_RNDASYNC (1 << 1) 330 331 /* 332 * All IOCB Queue entries are this size 333 */ 334 #define QENTRY_LEN 64 335 #define QENTRY_MAX 255 336 337 /* 338 * Command Structure Definitions 339 */ 340 341 typedef struct { 342 uint32_t ds_base; 343 uint32_t ds_basehi; 344 uint32_t ds_count; 345 } ispds64_t; 346 347 typedef struct { 348 uint8_t rqs_entry_type; 349 uint8_t rqs_entry_count; 350 uint8_t rqs_seqno; 351 uint8_t rqs_flags; 352 } isphdr_t; 353 354 /* RQS Flag definitions */ 355 #define RQSFLAG_BADTYPE 0x04 356 #define RQSFLAG_BADPARAM 0x08 357 #define RQSFLAG_BADCOUNT 0x10 358 #define RQSFLAG_BADORDER 0x20 359 #define RQSFLAG_MASK 0x3f 360 361 /* RQS entry_type definitions */ 362 #define RQSTYPE_RESPONSE 0x03 363 #define RQSTYPE_MARKER 0x04 364 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 365 #define RQSTYPE_A64_CONT 0x0a 366 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 367 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 368 #define RQSTYPE_STATUS_CONT 0x10 369 #define RQSTYPE_CTIO7 0x12 370 #define RQSTYPE_TSK_MGMT 0x14 371 #define RQSTYPE_ATIO2 0x16 /* Target Mode */ 372 #define RQSTYPE_T7RQS 0x18 373 #define RQSTYPE_CT_PASSTHRU 0x29 374 #define RQSTYPE_VP_CTRL 0x30 375 #define RQSTYPE_VP_MODIFY 0x31 376 #define RQSTYPE_RPT_ID_ACQ 0x32 377 #define RQSTYPE_ABORT_IO 0x33 378 #define RQSTYPE_MBOX 0x39 379 #define RQSTYPE_T6RQS 0x48 380 #define RQSTYPE_PUREX 0x51 381 #define RQSTYPE_LOGIN 0x52 382 #define RQSTYPE_ELS_PASSTHRU 0x53 383 #define RQSTYPE_ABTS_RCVD 0x54 384 #define RQSTYPE_ABTS_RSP 0x55 385 386 typedef struct { 387 isphdr_t mrk_header; 388 uint32_t mrk_handle; 389 uint16_t mrk_nphdl; 390 uint8_t mrk_modifier; 391 uint8_t mrk_reserved0; 392 uint8_t mrk_reserved1; 393 uint8_t mrk_vphdl; 394 uint16_t mrk_reserved2; 395 uint8_t mrk_lun[8]; 396 uint8_t mrk_reserved3[40]; 397 } isp_marker_24xx_t; 398 399 #define SYNC_DEVICE 0 400 #define SYNC_TARGET 1 401 #define SYNC_ALL 2 402 #define SYNC_LIP 3 403 404 /* 405 * ISP24XX structures 406 */ 407 typedef struct { 408 isphdr_t req_header; 409 uint32_t req_handle; 410 uint16_t req_nphdl; 411 uint16_t req_time; 412 uint16_t req_seg_count; 413 uint16_t req_reserved; 414 uint8_t req_lun[8]; 415 uint8_t req_alen_datadir; 416 uint8_t req_task_management; 417 uint8_t req_task_attribute; 418 uint8_t req_crn; 419 uint8_t req_cdb[16]; 420 uint32_t req_dl; 421 uint16_t req_tidlo; 422 uint8_t req_tidhi; 423 uint8_t req_vpidx; 424 ispds64_t req_dataseg; 425 } ispreqt7_t; 426 427 /* Task Management Request Function */ 428 typedef struct { 429 isphdr_t tmf_header; 430 uint32_t tmf_handle; 431 uint16_t tmf_nphdl; 432 uint8_t tmf_reserved0[2]; 433 uint16_t tmf_delay; 434 uint16_t tmf_timeout; 435 uint8_t tmf_lun[8]; 436 uint32_t tmf_flags; 437 uint8_t tmf_reserved1[20]; 438 uint16_t tmf_tidlo; 439 uint8_t tmf_tidhi; 440 uint8_t tmf_vpidx; 441 uint8_t tmf_reserved2[12]; 442 } isp24xx_tmf_t; 443 444 #define ISP24XX_TMF_NOSEND 0x80000000 445 446 #define ISP24XX_TMF_LUN_RESET 0x00000010 447 #define ISP24XX_TMF_ABORT_TASK_SET 0x00000008 448 #define ISP24XX_TMF_CLEAR_TASK_SET 0x00000004 449 #define ISP24XX_TMF_TARGET_RESET 0x00000002 450 #define ISP24XX_TMF_CLEAR_ACA 0x00000001 451 452 /* I/O Abort Structure */ 453 typedef struct { 454 isphdr_t abrt_header; 455 uint32_t abrt_handle; 456 uint16_t abrt_nphdl; 457 uint16_t abrt_options; 458 uint32_t abrt_cmd_handle; 459 uint16_t abrt_queue_number; 460 uint8_t abrt_reserved[30]; 461 uint16_t abrt_tidlo; 462 uint8_t abrt_tidhi; 463 uint8_t abrt_vpidx; 464 uint8_t abrt_reserved1[12]; 465 } isp24xx_abrt_t; 466 467 #define ISP24XX_ABRT_NOSEND 0x01 /* don't actually send ABTS */ 468 #define ISP24XX_ABRT_OKAY 0x00 /* in nphdl on return */ 469 #define ISP24XX_ABRT_ENXIO 0x31 /* in nphdl on return */ 470 471 #define ISP_CDSEG64 5 472 typedef struct { 473 isphdr_t req_header; 474 ispds64_t req_dataseg[ISP_CDSEG64]; 475 } ispcontreq64_t; 476 477 /* 478 * Status Continuation 479 */ 480 typedef struct { 481 isphdr_t req_header; 482 uint8_t req_sense_data[60]; 483 } ispstatus_cont_t; 484 485 /* 486 * 24XX Type 0 status 487 */ 488 typedef struct { 489 isphdr_t req_header; 490 uint32_t req_handle; 491 uint16_t req_completion_status; 492 uint16_t req_oxid; 493 uint32_t req_resid; 494 uint16_t req_reserved0; 495 uint16_t req_state_flags; 496 uint16_t req_retry_delay; /* aka Status Qualifier */ 497 uint16_t req_scsi_status; 498 uint32_t req_fcp_residual; 499 uint32_t req_sense_len; 500 uint32_t req_response_len; 501 uint8_t req_rsp_sense[28]; 502 } isp24xx_statusreq_t; 503 504 /* 505 * For Qlogic 2X00, the high order byte of SCSI status has 506 * additional meaning. 507 */ 508 #define RQCS_CR 0x1000 /* Confirmation Request */ 509 #define RQCS_RU 0x0800 /* Residual Under */ 510 #define RQCS_RO 0x0400 /* Residual Over */ 511 #define RQCS_RESID (RQCS_RU|RQCS_RO) 512 #define RQCS_SV 0x0200 /* Sense Length Valid */ 513 #define RQCS_RV 0x0100 /* FCP Response Length Valid */ 514 515 /* 516 * CT Passthru IOCB 517 */ 518 typedef struct { 519 isphdr_t ctp_header; 520 uint32_t ctp_handle; 521 uint16_t ctp_status; 522 uint16_t ctp_nphdl; /* n-port handle */ 523 uint16_t ctp_cmd_cnt; /* Command DSD count */ 524 uint8_t ctp_vpidx; 525 uint8_t ctp_reserved0; 526 uint16_t ctp_time; 527 uint16_t ctp_reserved1; 528 uint16_t ctp_rsp_cnt; /* Response DSD count */ 529 uint16_t ctp_reserved2[5]; 530 uint32_t ctp_rsp_bcnt; /* Response byte count */ 531 uint32_t ctp_cmd_bcnt; /* Command byte count */ 532 ispds64_t ctp_dataseg[2]; 533 } isp_ct_pt_t; 534 535 /* 536 * Completion Status Codes. 537 */ 538 #define RQCS_COMPLETE 0x0000 539 #define RQCS_DMA_ERROR 0x0002 540 #define RQCS_TRANSPORT_ERROR 0x0003 541 #define RQCS_RESET_OCCURRED 0x0004 542 #define RQCS_ABORTED 0x0005 543 #define RQCS_TIMEOUT 0x0006 544 #define RQCS_DATA_OVERRUN 0x0007 545 #define RQCS_DRE 0x0011 /* data reassembly error */ 546 #define RQCS_TABORT 0x0013 /* aborted by target */ 547 #define RQCS_DATA_UNDERRUN 0x0015 548 #define RQCS_PORT_UNAVAILABLE 0x0028 549 #define RQCS_PORT_LOGGED_OUT 0x0029 550 #define RQCS_PORT_CHANGED 0x002A 551 #define RQCS_PORT_BUSY 0x002B 552 #define RQCS_ENOMEM 0x002C /* f/w resource unavailable */ 553 #define RQCS_TMO 0x0030 /* task management overrun */ 554 555 /* 556 * About Firmware returns an 'attribute' word. 557 */ 558 #define ISP2400_FW_ATTR_CLASS2 0x0001 559 #define ISP2400_FW_ATTR_IP 0x0002 560 #define ISP2400_FW_ATTR_MULTIID 0x0004 561 #define ISP2400_FW_ATTR_SB2 0x0008 562 #define ISP2400_FW_ATTR_T10CRC 0x0010 563 #define ISP2400_FW_ATTR_VI 0x0020 564 #define ISP2400_FW_ATTR_MQ 0x0040 565 #define ISP2400_FW_ATTR_MSIX 0x0080 566 #define ISP2400_FW_ATTR_FCOE 0x0800 567 #define ISP2400_FW_ATTR_VP0 0x1000 568 #define ISP2400_FW_ATTR_EXPFW 0x2000 569 #define ISP2400_FW_ATTR_HOTFW 0x4000 570 #define ISP2400_FW_ATTR_EXTNDED 0x8000 571 #define ISP2400_FW_ATTR_EXTVP 0x00010000 572 #define ISP2400_FW_ATTR_VN2VN 0x00040000 573 #define ISP2400_FW_ATTR_EXMOFF 0x00080000 574 #define ISP2400_FW_ATTR_NPMOFF 0x00100000 575 #define ISP2400_FW_ATTR_DIFCHOP 0x00400000 576 #define ISP2400_FW_ATTR_SRIOV 0x02000000 577 #define ISP2400_FW_ATTR_ASICTMP 0x0200000000 578 #define ISP2400_FW_ATTR_ATIOMQ 0x0400000000 579 580 /* 581 * This is only true for 24XX cards with this f/w attribute 582 */ 583 #define ISP_CAP_MULTI_ID(isp) \ 584 (isp->isp_fwattr & ISP2400_FW_ATTR_MULTIID) 585 #define ISP_GET_VPIDX(isp, tag) \ 586 (ISP_CAP_MULTI_ID(isp) ? tag : 0) 587 #define ISP_CAP_MSIX(isp) \ 588 (isp->isp_fwattr & ISP2400_FW_ATTR_MSIX) 589 #define ISP_CAP_VP0(isp) \ 590 (isp->isp_fwattr & ISP2400_FW_ATTR_VP0) 591 592 #define ISP_FCTAPE_ENABLED(isp, chan) \ 593 ((FCPARAM(isp, chan)->isp_xfwoptions & ICB2400_OPT2_FCTAPE) != 0) 594 595 /* 596 * FC specific data structures 597 */ 598 599 /* 600 * Initialization Control Block 601 */ 602 603 #define ICB_VERSION1 1 604 605 /* 2400 F/W options */ 606 #define ICB2400_OPT1_BOTH_WWNS 0x00004000 607 #define ICB2400_OPT1_FULL_LOGIN 0x00002000 608 #define ICB2400_OPT1_PREV_ADDRESS 0x00000800 609 #define ICB2400_OPT1_SRCHDOWN 0x00000400 610 #define ICB2400_OPT1_NOLIP 0x00000200 611 #define ICB2400_OPT1_INI_DISABLE 0x00000020 612 #define ICB2400_OPT1_TGT_ENABLE 0x00000010 613 #define ICB2400_OPT1_FULL_DUPLEX 0x00000004 614 #define ICB2400_OPT1_FAIRNESS 0x00000002 615 #define ICB2400_OPT1_HARD_ADDRESS 0x00000001 616 617 #define ICB2400_OPT2_ENA_ATIOMQ 0x08000000 618 #define ICB2400_OPT2_ENA_IHA 0x04000000 619 #define ICB2400_OPT2_QOS 0x02000000 620 #define ICB2400_OPT2_IOCBS 0x01000000 621 #define ICB2400_OPT2_ENA_IHR 0x00400000 622 #define ICB2400_OPT2_ENA_VMS 0x00200000 623 #define ICB2400_OPT2_ENA_TA 0x00100000 624 #define ICB2400_OPT2_TPRLIC 0x00004000 625 #define ICB2400_OPT2_FCTAPE 0x00001000 626 #define ICB2400_OPT2_FCSP 0x00000800 627 #define ICB2400_OPT2_CLASS2_ACK0 0x00000200 628 #define ICB2400_OPT2_CLASS2 0x00000100 629 #define ICB2400_OPT2_NO_PLAY 0x00000080 630 #define ICB2400_OPT2_TOPO_MASK 0x00000070 631 #define ICB2400_OPT2_LOOP_ONLY 0x00000000 632 #define ICB2400_OPT2_PTP_ONLY 0x00000010 633 #define ICB2400_OPT2_LOOP_2_PTP 0x00000020 634 #define ICB2400_OPT2_TIMER_MASK 0x0000000f 635 #define ICB2400_OPT2_ZIO 0x00000005 636 #define ICB2400_OPT2_ZIO1 0x00000006 637 638 #define ICB2400_OPT3_NO_CTXDIS 0x40000000 639 #define ICB2400_OPT3_ENA_ETH_RESP 0x08000000 640 #define ICB2400_OPT3_ENA_ETH_ATIO 0x04000000 641 #define ICB2400_OPT3_ENA_MFCF 0x00020000 642 #define ICB2400_OPT3_SKIP_4GB 0x00010000 643 #define ICB2400_OPT3_RATE_MASK 0x0000E000 644 #define ICB2400_OPT3_RATE_1GB 0x00000000 645 #define ICB2400_OPT3_RATE_2GB 0x00002000 646 #define ICB2400_OPT3_RATE_AUTO 0x00004000 647 #define ICB2400_OPT3_RATE_4GB 0x00006000 648 #define ICB2400_OPT3_RATE_8GB 0x00008000 649 #define ICB2400_OPT3_RATE_16GB 0x0000A000 650 #define ICB2400_OPT3_RATE_32GB 0x0000C000 651 #define ICB2400_OPT3_RATE_64GB 0x0000E000 652 #define ICB2400_OPT3_ENA_OOF_XFRDY 0x00000200 653 #define ICB2400_OPT3_NO_N2N_LOGI 0x00000100 654 #define ICB2400_OPT3_NO_LOCAL_PLOGI 0x00000080 655 #define ICB2400_OPT3_ENA_OOF 0x00000040 656 /* note that a response size flag of zero is reserved! */ 657 #define ICB2400_OPT3_RSPSZ_MASK 0x00000030 658 #define ICB2400_OPT3_RSPSZ_12 0x00000010 659 #define ICB2400_OPT3_RSPSZ_24 0x00000020 660 #define ICB2400_OPT3_RSPSZ_32 0x00000030 661 #define ICB2400_OPT3_SOFTID 0x00000002 662 663 #define ICB_MIN_FRMLEN 256 664 #define ICB_MAX_FRMLEN 2112 665 #define ICB_DFLT_FRMLEN 1024 666 #define ICB_DFLT_FRMLEN_28XX 2048 667 #define ICB_DFLT_RDELAY 5 668 #define ICB_DFLT_RCOUNT 3 669 670 #define ICB_LOGIN_TOV 10 671 #define ICB_LUN_ENABLE_TOV 15 672 673 674 /* 675 * And somebody at QLogic had a great idea that you could just change 676 * the structure *and* keep the version number the same as the other cards. 677 */ 678 typedef struct { 679 uint16_t icb_version; 680 uint16_t icb_reserved0; 681 uint16_t icb_maxfrmlen; 682 uint16_t icb_execthrottle; 683 uint16_t icb_xchgcnt; 684 uint16_t icb_hardaddr; 685 uint8_t icb_portname[8]; 686 uint8_t icb_nodename[8]; 687 uint16_t icb_rspnsin; 688 uint16_t icb_rqstout; 689 uint16_t icb_retry_count; 690 uint16_t icb_priout; 691 uint16_t icb_rsltqlen; 692 uint16_t icb_rqstqlen; 693 uint16_t icb_ldn_nols; 694 uint16_t icb_prqstqlen; 695 uint16_t icb_rqstaddr[4]; 696 uint16_t icb_respaddr[4]; 697 uint16_t icb_priaddr[4]; 698 uint16_t icb_msixresp; 699 uint16_t icb_msixatio; 700 uint16_t icb_reserved1[2]; 701 uint16_t icb_atio_in; 702 uint16_t icb_atioqlen; 703 uint16_t icb_atioqaddr[4]; 704 uint16_t icb_idelaytimer; 705 uint16_t icb_logintime; 706 uint32_t icb_fwoptions1; 707 uint32_t icb_fwoptions2; 708 uint32_t icb_fwoptions3; 709 uint16_t icb_qos; 710 uint16_t icb_reserved2[3]; 711 uint8_t icb_enodemac[6]; 712 uint16_t icb_disctime; 713 uint16_t icb_reserved3[4]; 714 } isp_icb_2400_t; 715 716 #define RQRSP_ADDR0015 0 717 #define RQRSP_ADDR1631 1 718 #define RQRSP_ADDR3247 2 719 #define RQRSP_ADDR4863 3 720 721 722 #define ICB_NNM0 7 723 #define ICB_NNM1 6 724 #define ICB_NNM2 5 725 #define ICB_NNM3 4 726 #define ICB_NNM4 3 727 #define ICB_NNM5 2 728 #define ICB_NNM6 1 729 #define ICB_NNM7 0 730 731 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 732 array[ICB_NNM0] = (uint8_t) ((wwn >> 0) & 0xff), \ 733 array[ICB_NNM1] = (uint8_t) ((wwn >> 8) & 0xff), \ 734 array[ICB_NNM2] = (uint8_t) ((wwn >> 16) & 0xff), \ 735 array[ICB_NNM3] = (uint8_t) ((wwn >> 24) & 0xff), \ 736 array[ICB_NNM4] = (uint8_t) ((wwn >> 32) & 0xff), \ 737 array[ICB_NNM5] = (uint8_t) ((wwn >> 40) & 0xff), \ 738 array[ICB_NNM6] = (uint8_t) ((wwn >> 48) & 0xff), \ 739 array[ICB_NNM7] = (uint8_t) ((wwn >> 56) & 0xff) 740 741 #define MAKE_WWN_FROM_NODE_NAME(wwn, array) \ 742 wwn = ((uint64_t) array[ICB_NNM0]) | \ 743 ((uint64_t) array[ICB_NNM1] << 8) | \ 744 ((uint64_t) array[ICB_NNM2] << 16) | \ 745 ((uint64_t) array[ICB_NNM3] << 24) | \ 746 ((uint64_t) array[ICB_NNM4] << 32) | \ 747 ((uint64_t) array[ICB_NNM5] << 40) | \ 748 ((uint64_t) array[ICB_NNM6] << 48) | \ 749 ((uint64_t) array[ICB_NNM7] << 56) 750 751 752 /* 753 * For MULTI_ID firmware, this describes a 754 * virtual port entity for getting status. 755 */ 756 typedef struct { 757 uint16_t vp_port_status; 758 uint8_t vp_port_options; 759 uint8_t vp_port_loopid; 760 uint8_t vp_port_portname[8]; 761 uint8_t vp_port_nodename[8]; 762 uint16_t vp_port_portid_lo; /* not present when trailing icb */ 763 uint16_t vp_port_portid_hi; /* not present when trailing icb */ 764 } vp_port_info_t; 765 766 #define ICB2400_VPOPT_ENA_SNSLOGIN 0x00000040 /* Enable SNS Login and SCR for Virtual Ports */ 767 #define ICB2400_VPOPT_TGT_DISABLE 0x00000020 /* Target Mode Disabled */ 768 #define ICB2400_VPOPT_INI_ENABLE 0x00000010 /* Initiator Mode Enabled */ 769 #define ICB2400_VPOPT_ENABLED 0x00000008 /* VP Enabled */ 770 #define ICB2400_VPOPT_NOPLAY 0x00000004 /* ID Not Acquired */ 771 #define ICB2400_VPOPT_PREV_ADDRESS 0x00000002 /* Previously Assigned ID */ 772 #define ICB2400_VPOPT_HARD_ADDRESS 0x00000001 /* Hard Assigned ID */ 773 774 #define ICB2400_VPOPT_WRITE_SIZE 20 775 776 /* 777 * For MULTI_ID firmware, we append this structure 778 * to the isp_icb_2400_t above, followed by a list 779 * structures that are *most* of the vp_port_info_t. 780 */ 781 typedef struct { 782 uint16_t vp_count; 783 uint16_t vp_global_options; 784 } isp_icb_2400_vpinfo_t; 785 786 #define ICB2400_VPINFO_OFF 0x80 /* offset from start of ICB */ 787 #define ICB2400_VPINFO_PORT_OFF(chan) \ 788 (ICB2400_VPINFO_OFF + \ 789 sizeof (isp_icb_2400_vpinfo_t) + ((chan) * ICB2400_VPOPT_WRITE_SIZE)) 790 791 #define ICB2400_VPGOPT_FCA 0x01 /* Assume Clean Address bit in FLOGI ACC set (works only in static configurations) */ 792 #define ICB2400_VPGOPT_MID_DISABLE 0x02 /* when set, connection mode2 will work with NPIV-capable switched */ 793 #define ICB2400_VPGOPT_VP0_DECOUPLE 0x04 /* Allow VP0 decoupling if firmware supports it */ 794 #define ICB2400_VPGOPT_SUSP_FDISK 0x10 /* Suspend FDISC for Enabled VPs */ 795 #define ICB2400_VPGOPT_GEN_RIDA 0x20 /* Generate RIDA if FLOGI Fails */ 796 797 typedef struct { 798 isphdr_t vp_ctrl_hdr; 799 uint32_t vp_ctrl_handle; 800 uint16_t vp_ctrl_index_fail; 801 uint16_t vp_ctrl_status; 802 uint16_t vp_ctrl_command; 803 uint16_t vp_ctrl_vp_count; 804 uint16_t vp_ctrl_idmap[16]; 805 uint16_t vp_ctrl_reserved[7]; 806 uint16_t vp_ctrl_fcf_index; 807 } vp_ctrl_info_t; 808 809 #define VP_CTRL_CMD_ENABLE_VP 0x00 810 #define VP_CTRL_CMD_DISABLE_VP 0x08 811 #define VP_CTRL_CMD_DISABLE_VP_REINIT_LINK 0x09 812 #define VP_CTRL_CMD_DISABLE_VP_LOGO 0x0A 813 #define VP_CTRL_CMD_DISABLE_VP_LOGO_ALL 0x0B 814 815 /* 816 * We can use this structure for modifying either one or two VP ports after initialization 817 */ 818 typedef struct { 819 isphdr_t vp_mod_hdr; 820 uint32_t vp_mod_hdl; 821 uint16_t vp_mod_reserved0; 822 uint16_t vp_mod_status; 823 uint8_t vp_mod_cmd; 824 uint8_t vp_mod_cnt; 825 uint8_t vp_mod_idx0; 826 uint8_t vp_mod_idx1; 827 struct { 828 uint8_t options; 829 uint8_t loopid; 830 uint16_t reserved1; 831 uint8_t wwpn[8]; 832 uint8_t wwnn[8]; 833 } vp_mod_ports[2]; 834 uint8_t vp_mod_reserved2[8]; 835 } vp_modify_t; 836 837 #define VP_STS_OK 0x00 838 #define VP_STS_ERR 0x01 839 #define VP_CNT_ERR 0x02 840 #define VP_GEN_ERR 0x03 841 #define VP_IDX_ERR 0x04 842 #define VP_STS_BSY 0x05 843 844 #define VP_MODIFY 0x00 845 #define VP_MODIFY_ENA 0x01 846 #define VP_MODIFY_OPT 0x02 847 #define VP_RESUME 0x03 848 849 /* 850 * Port Data Base Element 851 */ 852 853 #define SVC3_ROLE_MASK 0x30 854 #define SVC3_ROLE_SHIFT 4 855 856 #define BITS2WORD_24XX(x) ((x)[0] << 16 | (x)[1] << 8 | (x)[2]) 857 858 /* 859 * Port Data Base Element- 24XX cards 860 */ 861 typedef struct { 862 uint16_t pdb_flags; 863 uint8_t pdb_curstate; 864 uint8_t pdb_laststate; 865 uint8_t pdb_hardaddr_bits[4]; 866 uint8_t pdb_portid_bits[4]; 867 #define pdb_nxt_seqid_2400 pdb_portid_bits[3] 868 uint16_t pdb_retry_timer; 869 uint16_t pdb_handle; 870 uint16_t pdb_rcv_dsize; 871 uint16_t pdb_reserved0; 872 uint16_t pdb_prli_svc0; 873 uint16_t pdb_prli_svc3; 874 uint8_t pdb_portname[8]; 875 uint8_t pdb_nodename[8]; 876 uint8_t pdb_reserved1[24]; 877 } isp_pdb_24xx_t; 878 879 #define PDB2400_TID_SUPPORTED 0x4000 880 #define PDB2400_FC_TAPE 0x0080 881 #define PDB2400_CLASS2_ACK0 0x0040 882 #define PDB2400_FCP_CONF 0x0020 883 #define PDB2400_CLASS2 0x0010 884 #define PDB2400_ADDR_VALID 0x0002 885 886 #define PDB2400_STATE_PLOGI_PEND 0x03 887 #define PDB2400_STATE_PLOGI_DONE 0x04 888 #define PDB2400_STATE_PRLI_PEND 0x05 889 #define PDB2400_STATE_LOGGED_IN 0x06 890 #define PDB2400_STATE_PORT_UNAVAIL 0x07 891 #define PDB2400_STATE_PRLO_PEND 0x09 892 #define PDB2400_STATE_LOGO_PEND 0x0B 893 894 /* 895 * Common elements from the above two structures that are actually useful to us. 896 */ 897 typedef struct { 898 uint16_t handle; 899 uint16_t prli_word0; 900 uint16_t prli_word3; 901 uint32_t : 8, 902 portid : 24; 903 uint8_t portname[8]; 904 uint8_t nodename[8]; 905 } isp_pdb_t; 906 907 /* 908 * Port and N-Port Handle List Element 909 */ 910 typedef struct { 911 uint16_t pnhle_port_id_lo; 912 uint16_t pnhle_port_id_hi; 913 uint16_t pnhle_handle; 914 uint16_t pnhle_reserved; 915 } isp_pnhle_24xx_t; 916 917 /* 918 * Port Database Changed Async Event information for 24XX cards 919 */ 920 /* N-Port Handle */ 921 #define PDB24XX_AE_GLOBAL 0xFFFF 922 923 /* Reason Codes */ 924 #define PDB24XX_AE_OK 0x00 925 #define PDB24XX_AE_IMPL_LOGO_1 0x01 926 #define PDB24XX_AE_IMPL_LOGO_2 0x02 927 #define PDB24XX_AE_IMPL_LOGO_3 0x03 928 #define PDB24XX_AE_PLOGI_RCVD 0x04 929 #define PDB24XX_AE_PLOGI_RJT 0x05 930 #define PDB24XX_AE_PRLI_RCVD 0x06 931 #define PDB24XX_AE_PRLI_RJT 0x07 932 #define PDB24XX_AE_TPRLO 0x08 933 #define PDB24XX_AE_TPRLO_RJT 0x09 934 #define PDB24XX_AE_PRLO_RCVD 0x0a 935 #define PDB24XX_AE_LOGO_RCVD 0x0b 936 #define PDB24XX_AE_TOPO_CHG 0x0c 937 #define PDB24XX_AE_NPORT_CHG 0x0d 938 #define PDB24XX_AE_FLOGI_RJT 0x0e 939 #define PDB24XX_AE_BAD_FANN 0x0f 940 #define PDB24XX_AE_FLOGI_TIMO 0x10 941 #define PDB24XX_AE_ABX_LOGO 0x11 942 #define PDB24XX_AE_PLOGI_DONE 0x12 943 #define PDB24XX_AE_PRLI_DONE 0x13 944 #define PDB24XX_AE_OPN_1 0x14 945 #define PDB24XX_AE_OPN_2 0x15 946 #define PDB24XX_AE_TXERR 0x16 947 #define PDB24XX_AE_FORCED_LOGO 0x17 948 #define PDB24XX_AE_DISC_TIMO 0x18 949 950 /* 951 * Genericized Port Login/Logout software structure 952 */ 953 typedef struct { 954 uint16_t handle; 955 uint16_t channel; 956 uint32_t 957 flags : 8, 958 portid : 24; 959 } isp_plcmd_t; 960 /* the flags to use are those for PLOGX_FLG_* below */ 961 962 /* 963 * ISP24XX- Login/Logout Port IOCB 964 */ 965 typedef struct { 966 isphdr_t plogx_header; 967 uint32_t plogx_handle; 968 uint16_t plogx_status; 969 uint16_t plogx_nphdl; 970 uint16_t plogx_flags; 971 uint16_t plogx_vphdl; /* low 8 bits */ 972 uint16_t plogx_portlo; /* low 16 bits */ 973 uint16_t plogx_rspsz_porthi; 974 struct { 975 uint16_t lo16; 976 uint16_t hi16; 977 } plogx_ioparm[11]; 978 } isp_plogx_t; 979 980 #define PLOGX_STATUS_OK 0x00 981 #define PLOGX_STATUS_UNAVAIL 0x28 982 #define PLOGX_STATUS_LOGOUT 0x29 983 #define PLOGX_STATUS_IOCBERR 0x31 984 985 #define PLOGX_IOCBERR_NOLINK 0x01 986 #define PLOGX_IOCBERR_NOIOCB 0x02 987 #define PLOGX_IOCBERR_NOXGHG 0x03 988 #define PLOGX_IOCBERR_FAILED 0x04 /* further info in IOPARM 1 */ 989 #define PLOGX_IOCBERR_NOFABRIC 0x05 990 #define PLOGX_IOCBERR_NOTREADY 0x07 991 #define PLOGX_IOCBERR_NOLOGIN 0x09 /* further info in IOPARM 1 */ 992 #define PLOGX_IOCBERR_NOPCB 0x0a 993 #define PLOGX_IOCBERR_REJECT 0x18 /* further info in IOPARM 1 */ 994 #define PLOGX_IOCBERR_EINVAL 0x19 /* further info in IOPARM 1 */ 995 #define PLOGX_IOCBERR_PORTUSED 0x1a /* further info in IOPARM 1 */ 996 #define PLOGX_IOCBERR_HNDLUSED 0x1b /* further info in IOPARM 1 */ 997 #define PLOGX_IOCBERR_NOHANDLE 0x1c 998 #define PLOGX_IOCBERR_NOFLOGI 0x1f /* further info in IOPARM 1 */ 999 1000 #define PLOGX_FLG_CMD_MASK 0xf 1001 #define PLOGX_FLG_CMD_PLOGI 0 1002 #define PLOGX_FLG_CMD_PRLI 1 1003 #define PLOGX_FLG_CMD_PDISC 2 1004 #define PLOGX_FLG_CMD_LOGO 8 1005 #define PLOGX_FLG_CMD_PRLO 9 1006 #define PLOGX_FLG_CMD_TPRLO 10 1007 1008 #define PLOGX_FLG_COND_PLOGI 0x10 /* if with PLOGI */ 1009 #define PLOGX_FLG_IMPLICIT 0x10 /* if with LOGO, PRLO, TPRLO */ 1010 #define PLOGX_FLG_SKIP_PRLI 0x20 /* if with PLOGI */ 1011 #define PLOGX_FLG_IMPLICIT_LOGO_ALL 0x20 /* if with LOGO */ 1012 #define PLOGX_FLG_EXPLICIT_LOGO 0x40 /* if with LOGO */ 1013 #define PLOGX_FLG_COMMON_FEATURES 0x80 /* if with PLOGI */ 1014 #define PLOGX_FLG_FREE_NPHDL 0x80 /* if with with LOGO */ 1015 1016 #define PLOGX_FLG_CLASS2 0x100 /* if with PLOGI */ 1017 #define PLOGX_FLG_FCP2_OVERRIDE 0x200 /* if with PRLOG, PRLI */ 1018 1019 /* 1020 * Report ID Acquisistion (24XX multi-id firmware) 1021 */ 1022 typedef struct { 1023 isphdr_t ridacq_hdr; 1024 uint32_t ridacq_handle; 1025 uint8_t ridacq_vp_acquired; 1026 uint8_t ridacq_vp_setup; 1027 uint8_t ridacq_vp_index; 1028 uint8_t ridacq_vp_status; 1029 uint16_t ridacq_vp_port_lo; 1030 uint8_t ridacq_vp_port_hi; 1031 uint8_t ridacq_format; /* 0 or 1 */ 1032 uint16_t ridacq_map[8]; 1033 uint8_t ridacq_reserved1[32]; 1034 } isp_ridacq_t; 1035 1036 #define RIDACQ_STS_COMPLETE 0 1037 #define RIDACQ_STS_UNACQUIRED 1 1038 #define RIDACQ_STS_CHANGED 2 1039 #define RIDACQ_STS_SNS_TIMEOUT 3 1040 #define RIDACQ_STS_SNS_REJECTED 4 1041 #define RIDACQ_STS_SCR_TIMEOUT 5 1042 #define RIDACQ_STS_SCR_REJECTED 6 1043 1044 /* 1045 * Simple Name Server Data Structures 1046 */ 1047 #define SNS_GA_NXT 0x100 1048 #define SNS_GPN_ID 0x112 1049 #define SNS_GNN_ID 0x113 1050 #define SNS_GFT_ID 0x117 1051 #define SNS_GFF_ID 0x11F 1052 #define SNS_GID_FT 0x171 1053 #define SNS_GID_PT 0x1A1 1054 #define SNS_RFT_ID 0x217 1055 #define SNS_RSPN_ID 0x218 1056 #define SNS_RFF_ID 0x21F 1057 #define SNS_RSNN_NN 0x239 1058 typedef struct { 1059 uint16_t snscb_rblen; /* response buffer length (words) */ 1060 uint16_t snscb_reserved0; 1061 uint16_t snscb_addr[4]; /* response buffer address */ 1062 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1063 uint16_t snscb_reserved1; 1064 uint16_t snscb_data[]; /* variable data */ 1065 } sns_screq_t; /* Subcommand Request Structure */ 1066 1067 typedef struct { 1068 uint16_t snscb_rblen; /* response buffer length (words) */ 1069 uint16_t snscb_reserved0; 1070 uint16_t snscb_addr[4]; /* response buffer address */ 1071 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1072 uint16_t snscb_reserved1; 1073 uint16_t snscb_cmd; 1074 uint16_t snscb_reserved2; 1075 uint32_t snscb_reserved3; 1076 uint32_t snscb_port; 1077 } sns_ga_nxt_req_t; 1078 #define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t)) 1079 1080 typedef struct { /* Used for GFT_ID, GFF_ID, etc. */ 1081 uint16_t snscb_rblen; /* response buffer length (words) */ 1082 uint16_t snscb_reserved0; 1083 uint16_t snscb_addr[4]; /* response buffer address */ 1084 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1085 uint16_t snscb_reserved1; 1086 uint16_t snscb_cmd; 1087 uint16_t snscb_mword_div_2; 1088 uint32_t snscb_reserved3; 1089 uint32_t snscb_portid; 1090 } sns_gxx_id_req_t; 1091 #define SNS_GXX_ID_REQ_SIZE (sizeof (sns_gxx_id_req_t)) 1092 1093 typedef struct { 1094 uint16_t snscb_rblen; /* response buffer length (words) */ 1095 uint16_t snscb_reserved0; 1096 uint16_t snscb_addr[4]; /* response buffer address */ 1097 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1098 uint16_t snscb_reserved1; 1099 uint16_t snscb_cmd; 1100 uint16_t snscb_mword_div_2; 1101 uint32_t snscb_reserved3; 1102 uint32_t snscb_fc4_type; 1103 } sns_gid_ft_req_t; 1104 #define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t)) 1105 1106 typedef struct { 1107 uint16_t snscb_rblen; /* response buffer length (words) */ 1108 uint16_t snscb_reserved0; 1109 uint16_t snscb_addr[4]; /* response buffer address */ 1110 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1111 uint16_t snscb_reserved1; 1112 uint16_t snscb_cmd; 1113 uint16_t snscb_mword_div_2; 1114 uint32_t snscb_reserved3; 1115 uint8_t snscb_port_type; 1116 uint8_t snscb_domain; 1117 uint8_t snscb_area; 1118 uint8_t snscb_flags; 1119 } sns_gid_pt_req_t; 1120 #define SNS_GID_PT_REQ_SIZE (sizeof (sns_gid_pt_req_t)) 1121 1122 typedef struct { 1123 uint16_t snscb_rblen; /* response buffer length (words) */ 1124 uint16_t snscb_reserved0; 1125 uint16_t snscb_addr[4]; /* response buffer address */ 1126 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1127 uint16_t snscb_reserved1; 1128 uint16_t snscb_cmd; 1129 uint16_t snscb_reserved2; 1130 uint32_t snscb_reserved3; 1131 uint32_t snscb_port; 1132 uint32_t snscb_fc4_types[8]; 1133 } sns_rft_id_req_t; 1134 #define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t)) 1135 1136 typedef struct { 1137 ct_hdr_t snscb_cthdr; 1138 uint8_t snscb_port_type; 1139 uint8_t snscb_port_id[3]; 1140 uint8_t snscb_portname[8]; 1141 uint16_t snscb_data[]; /* variable data */ 1142 } sns_scrsp_t; /* Subcommand Response Structure */ 1143 1144 typedef struct { 1145 ct_hdr_t snscb_cthdr; 1146 uint8_t snscb_port_type; 1147 uint8_t snscb_port_id[3]; 1148 uint8_t snscb_portname[8]; 1149 uint8_t snscb_pnlen; /* symbolic port name length */ 1150 uint8_t snscb_pname[255]; /* symbolic port name */ 1151 uint8_t snscb_nodename[8]; 1152 uint8_t snscb_nnlen; /* symbolic node name length */ 1153 uint8_t snscb_nname[255]; /* symbolic node name */ 1154 uint8_t snscb_ipassoc[8]; 1155 uint8_t snscb_ipaddr[16]; 1156 uint8_t snscb_svc_class[4]; 1157 uint8_t snscb_fc4_types[32]; 1158 uint8_t snscb_fpname[8]; 1159 uint8_t snscb_reserved; 1160 uint8_t snscb_hardaddr[3]; 1161 } sns_ga_nxt_rsp_t; /* Subcommand Response Structure */ 1162 #define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t)) 1163 1164 typedef struct { 1165 ct_hdr_t snscb_cthdr; 1166 uint8_t snscb_wwn[8]; 1167 } sns_gxn_id_rsp_t; 1168 #define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t)) 1169 1170 typedef struct { 1171 ct_hdr_t snscb_cthdr; 1172 uint32_t snscb_fc4_types[8]; 1173 } sns_gft_id_rsp_t; 1174 #define SNS_GFT_ID_RESP_SIZE (sizeof (sns_gft_id_rsp_t)) 1175 1176 typedef struct { 1177 ct_hdr_t snscb_cthdr; 1178 uint32_t snscb_fc4_features[32]; 1179 } sns_gff_id_rsp_t; 1180 #define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t)) 1181 1182 typedef struct { /* Used for GID_FT, GID_PT, etc. */ 1183 ct_hdr_t snscb_cthdr; 1184 struct { 1185 uint8_t control; 1186 uint8_t portid[3]; 1187 } snscb_ports[1]; 1188 } sns_gid_xx_rsp_t; 1189 #define SNS_GID_XX_RESP_SIZE(x) ((sizeof (sns_gid_xx_rsp_t)) + ((x - 1) << 2)) 1190 1191 /* 1192 * Other Misc Structures 1193 */ 1194 1195 /* ELS Pass Through */ 1196 typedef struct { 1197 isphdr_t els_hdr; 1198 uint32_t els_handle; 1199 uint16_t els_status; 1200 uint16_t els_nphdl; 1201 uint16_t els_xmit_dsd_count; /* outgoing only */ 1202 uint8_t els_vphdl; 1203 uint8_t els_sof; 1204 uint32_t els_rxid; 1205 uint16_t els_recv_dsd_count; /* outgoing only */ 1206 uint8_t els_opcode; 1207 uint8_t els_reserved1; 1208 uint8_t els_did_lo; 1209 uint8_t els_did_mid; 1210 uint8_t els_did_hi; 1211 uint8_t els_reserved2; 1212 uint16_t els_reserved3; 1213 uint16_t els_ctl_flags; 1214 union { 1215 struct { 1216 uint32_t _els_bytecnt; 1217 uint32_t _els_subcode1; 1218 uint32_t _els_subcode2; 1219 uint8_t _els_reserved4[20]; 1220 } in; 1221 struct { 1222 uint32_t _els_recv_bytecnt; 1223 uint32_t _els_xmit_bytecnt; 1224 uint32_t _els_xmit_dsd_length; 1225 uint16_t _els_xmit_dsd_a1500; 1226 uint16_t _els_xmit_dsd_a3116; 1227 uint16_t _els_xmit_dsd_a4732; 1228 uint16_t _els_xmit_dsd_a6348; 1229 uint32_t _els_recv_dsd_length; 1230 uint16_t _els_recv_dsd_a1500; 1231 uint16_t _els_recv_dsd_a3116; 1232 uint16_t _els_recv_dsd_a4732; 1233 uint16_t _els_recv_dsd_a6348; 1234 } out; 1235 } inout; 1236 #define els_bytecnt inout.in._els_bytecnt 1237 #define els_subcode1 inout.in._els_subcode1 1238 #define els_subcode2 inout.in._els_subcode2 1239 #define els_reserved4 inout.in._els_reserved4 1240 #define els_recv_bytecnt inout.out._els_recv_bytecnt 1241 #define els_xmit_bytecnt inout.out._els_xmit_bytecnt 1242 #define els_xmit_dsd_length inout.out._els_xmit_dsd_length 1243 #define els_xmit_dsd_a1500 inout.out._els_xmit_dsd_a1500 1244 #define els_xmit_dsd_a3116 inout.out._els_xmit_dsd_a3116 1245 #define els_xmit_dsd_a4732 inout.out._els_xmit_dsd_a4732 1246 #define els_xmit_dsd_a6348 inout.out._els_xmit_dsd_a6348 1247 #define els_recv_dsd_length inout.out._els_recv_dsd_length 1248 #define els_recv_dsd_a1500 inout.out._els_recv_dsd_a1500 1249 #define els_recv_dsd_a3116 inout.out._els_recv_dsd_a3116 1250 #define els_recv_dsd_a4732 inout.out._els_recv_dsd_a4732 1251 #define els_recv_dsd_a6348 inout.out._els_recv_dsd_a6348 1252 } els_t; 1253 1254 /* 1255 * Target Mode related definitions 1256 */ 1257 1258 /* 1259 * ISP24XX Immediate Notify 1260 */ 1261 typedef struct { 1262 isphdr_t in_header; 1263 uint32_t in_reserved; 1264 uint16_t in_nphdl; 1265 uint16_t in_reserved1; 1266 uint16_t in_flags; 1267 uint16_t in_srr_rxid; 1268 uint16_t in_status; 1269 uint8_t in_status_subcode; 1270 uint8_t in_fwhandle; 1271 uint32_t in_rxid; 1272 uint16_t in_srr_reloff_lo; 1273 uint16_t in_srr_reloff_hi; 1274 uint16_t in_srr_iu; 1275 uint16_t in_srr_oxid; 1276 /* 1277 * If bit 2 is set in in_flags, the N-Port and 1278 * handle tags are valid. If the received ELS is 1279 * a LOGO, then these tags contain the N Port ID 1280 * from the LOGO payload. If the received ELS 1281 * request is TPRLO, these tags contain the 1282 * Third Party Originator N Port ID. 1283 */ 1284 uint16_t in_nport_id_hi; 1285 #define in_prli_options in_nport_id_hi 1286 uint8_t in_nport_id_lo; 1287 uint8_t in_reserved3; 1288 uint16_t in_np_handle; 1289 uint8_t in_reserved4[12]; 1290 uint8_t in_reserved5; 1291 uint8_t in_vpidx; 1292 uint32_t in_reserved6; 1293 uint16_t in_portid_lo; 1294 uint8_t in_portid_hi; 1295 uint8_t in_reserved7; 1296 uint16_t in_reserved8; 1297 uint16_t in_oxid; 1298 } in_fcentry_24xx_t; 1299 1300 #define IN24XX_FLAG_PUREX_IOCB 0x1 1301 #define IN24XX_FLAG_GLOBAL_LOGOUT 0x2 1302 #define IN24XX_FLAG_NPHDL_VALID 0x4 1303 #define IN24XX_FLAG_N2N_PRLI 0x8 1304 #define IN24XX_FLAG_PN_NN_VALID 0x10 1305 1306 #define IN24XX_LIP_RESET 0x0E 1307 #define IN24XX_LINK_RESET 0x0F 1308 #define IN24XX_PORT_LOGOUT 0x29 1309 #define IN24XX_PORT_CHANGED 0x2A 1310 #define IN24XX_LINK_FAILED 0x2E 1311 #define IN24XX_SRR_RCVD 0x45 1312 #define IN24XX_ELS_RCVD 0x46 /* 1313 * login-affectin ELS received- check 1314 * subcode for specific opcode 1315 */ 1316 1317 /* 1318 * For f/w > 4.0.25, these offsets in the Immediate Notify contain 1319 * the WWNN/WWPN if the ELS is PLOGI, PDISC or ADISC. The WWN is in 1320 * Big Endian format. 1321 */ 1322 #define IN24XX_PRLI_WWNN_OFF 0x18 1323 #define IN24XX_PRLI_WWPN_OFF 0x28 1324 #define IN24XX_PLOGI_WWNN_OFF 0x20 1325 #define IN24XX_PLOGI_WWPN_OFF 0x28 1326 1327 /* 1328 * For f/w > 4.0.25, this offset in the Immediate Notify contain 1329 * the WWPN if the ELS is LOGO. The WWN is in Big Endian format. 1330 */ 1331 #define IN24XX_LOGO_WWPN_OFF 0x28 1332 1333 /* 1334 * Immediate Notify Status Subcodes for IN24XX_PORT_LOGOUT 1335 */ 1336 #define IN24XX_PORT_LOGOUT_PDISC_TMO 0x00 1337 #define IN24XX_PORT_LOGOUT_UXPR_DISC 0x01 1338 #define IN24XX_PORT_LOGOUT_OWN_OPN 0x02 1339 #define IN24XX_PORT_LOGOUT_OWN_OPN_SFT 0x03 1340 #define IN24XX_PORT_LOGOUT_ABTS_TMO 0x04 1341 #define IN24XX_PORT_LOGOUT_DISC_RJT 0x05 1342 #define IN24XX_PORT_LOGOUT_LOGIN_NEEDED 0x06 1343 #define IN24XX_PORT_LOGOUT_BAD_DISC 0x07 1344 #define IN24XX_PORT_LOGOUT_LOST_ALPA 0x08 1345 #define IN24XX_PORT_LOGOUT_XMIT_FAILURE 0x09 1346 1347 /* 1348 * Immediate Notify Status Subcodes for IN24XX_PORT_CHANGED 1349 */ 1350 #define IN24XX_PORT_CHANGED_BADFAN 0x00 1351 #define IN24XX_PORT_CHANGED_TOPO_CHANGE 0x01 1352 #define IN24XX_PORT_CHANGED_FLOGI_ACC 0x02 1353 #define IN24XX_PORT_CHANGED_FLOGI_RJT 0x03 1354 #define IN24XX_PORT_CHANGED_TIMEOUT 0x04 1355 #define IN24XX_PORT_CHANGED_PORT_CHANGE 0x05 1356 1357 /* 1358 * ISP24XX Notify Acknowledge 1359 */ 1360 #define NA_OK 0x01 /* Notify Acknowledge Succeeded */ 1361 typedef struct { 1362 isphdr_t na_header; 1363 uint32_t na_handle; 1364 uint16_t na_nphdl; 1365 uint16_t na_reserved1; 1366 uint16_t na_flags; 1367 uint16_t na_srr_rxid; 1368 uint16_t na_status; 1369 uint8_t na_status_subcode; 1370 uint8_t na_fwhandle; 1371 uint32_t na_rxid; 1372 uint16_t na_srr_reloff_lo; 1373 uint16_t na_srr_reloff_hi; 1374 uint16_t na_srr_iu; 1375 uint16_t na_srr_flags; 1376 uint8_t na_reserved3[18]; 1377 uint8_t na_reserved4; 1378 uint8_t na_vpidx; 1379 uint8_t na_srr_reject_vunique; 1380 uint8_t na_srr_reject_explanation; 1381 uint8_t na_srr_reject_code; 1382 uint8_t na_reserved5; 1383 uint8_t na_reserved6[6]; 1384 uint16_t na_oxid; 1385 } na_fcentry_24xx_t; 1386 1387 /* 1388 * 24XX ATIO Definition 1389 * 1390 * This is *quite* different from other entry types. 1391 * First of all, it has its own queue it comes in on. 1392 * 1393 * Secondly, it doesn't have a normal header. 1394 * 1395 * Thirdly, it's just a passthru of the FCP CMND IU 1396 * which is recorded in big endian mode. 1397 */ 1398 typedef struct { 1399 uint8_t at_type; 1400 uint8_t at_count; 1401 /* 1402 * Task attribute in high four bits, 1403 * the rest is the FCP CMND IU Length. 1404 * NB: the command can extend past the 1405 * length for a single queue entry. 1406 */ 1407 uint16_t at_ta_len; 1408 uint32_t at_rxid; 1409 fc_hdr_t at_hdr; 1410 fcp_cmnd_iu_t at_cmnd; 1411 } at7_entry_t; 1412 #define AT7_NORESRC_RXID 0xffffffff 1413 1414 #define CT_HBA_RESET 0xffff /* pseudo error - command destroyed by HBA reset*/ 1415 1416 /* 1417 * ISP24XX CTIO 1418 */ 1419 #define MAXRESPLEN_24XX 24 1420 typedef struct { 1421 isphdr_t ct_header; 1422 uint32_t ct_syshandle; 1423 uint16_t ct_nphdl; /* status on returned CTIOs */ 1424 uint16_t ct_timeout; 1425 uint16_t ct_seg_count; 1426 uint8_t ct_vpidx; 1427 uint8_t ct_xflags; 1428 uint16_t ct_iid_lo; /* low 16 bits of portid */ 1429 uint8_t ct_iid_hi; /* hi 8 bits of portid */ 1430 uint8_t ct_reserved; 1431 uint32_t ct_rxid; 1432 uint16_t ct_senselen; /* mode 1 only */ 1433 uint16_t ct_flags; 1434 uint32_t ct_resid; /* residual length */ 1435 uint16_t ct_oxid; 1436 uint16_t ct_scsi_status; /* modes 0 && 1 only */ 1437 union { 1438 struct { 1439 uint32_t reloff; 1440 uint32_t reserved0; 1441 uint32_t ct_xfrlen; 1442 uint32_t reserved1; 1443 ispds64_t ds; 1444 } m0; 1445 struct { 1446 uint16_t ct_resplen; 1447 uint16_t reserved; 1448 uint8_t ct_resp[MAXRESPLEN_24XX]; 1449 } m1; 1450 struct { 1451 uint32_t reserved0; 1452 uint32_t reserved1; 1453 uint32_t ct_datalen; 1454 uint32_t reserved2; 1455 ispds64_t ct_fcp_rsp_iudata; 1456 } m2; 1457 } rsp; 1458 } ct7_entry_t; 1459 1460 /* 1461 * ct_flags values for CTIO7 1462 */ 1463 #define CT7_NO_DATA 0x0000 1464 #define CT7_DATA_OUT 0x0001 /* *from* initiator */ 1465 #define CT7_DATA_IN 0x0002 /* *to* initiator */ 1466 #define CT7_DATAMASK 0x3 1467 #define CT7_DSD_ENABLE 0x0004 1468 #define CT7_CONF_STSFD 0x0010 1469 #define CT7_EXPLCT_CONF 0x0020 1470 #define CT7_FLAG_MODE0 0x0000 1471 #define CT7_FLAG_MODE1 0x0040 1472 #define CT7_FLAG_MODE2 0x0080 1473 #define CT7_FLAG_MMASK 0x00C0 1474 #define CT7_NOACK 0x0100 1475 #define CT7_TASK_ATTR_SHIFT 9 1476 #define CT7_CONFIRM 0x2000 1477 #define CT7_TERMINATE 0x4000 1478 #define CT7_SENDSTATUS 0x8000 1479 1480 /* 1481 * Type 7 CTIO status codes 1482 */ 1483 #define CT7_OK 0x01 /* completed without error */ 1484 #define CT7_ABORTED 0x02 /* aborted by host */ 1485 #define CT7_ERR 0x04 /* see sense data for error */ 1486 #define CT7_INVAL 0x06 /* request for disabled lun */ 1487 #define CT7_INVRXID 0x08 /* Invalid RX_ID */ 1488 #define CT7_DATA_OVER 0x09 /* Data Overrun */ 1489 #define CT7_TIMEOUT 0x0B /* timed out */ 1490 #define CT7_RESET 0x0E /* LIP Rset Received */ 1491 #define CT7_BUS_ERROR 0x10 /* DMA PCI Error */ 1492 #define CT7_REASSY_ERR 0x11 /* DMA reassembly error */ 1493 #define CT7_DATA_UNDER 0x15 /* Data Underrun */ 1494 #define CT7_PORTUNAVAIL 0x28 /* port not available */ 1495 #define CT7_LOGOUT 0x29 /* port logout */ 1496 #define CT7_PORTCHANGED 0x2A /* port changed */ 1497 #define CT7_SRR 0x45 /* SRR Received */ 1498 1499 /* 1500 * Other 24XX related target IOCBs 1501 */ 1502 1503 /* 1504 * ABTS Received 1505 */ 1506 typedef struct { 1507 isphdr_t abts_header; 1508 uint8_t abts_reserved0[6]; 1509 uint16_t abts_nphdl; 1510 uint16_t abts_reserved1; 1511 uint16_t abts_sof; 1512 uint32_t abts_rxid_abts; 1513 uint16_t abts_did_lo; 1514 uint8_t abts_did_hi; 1515 uint8_t abts_r_ctl; 1516 uint16_t abts_sid_lo; 1517 uint8_t abts_sid_hi; 1518 uint8_t abts_cs_ctl; 1519 uint16_t abts_fs_ctl; 1520 uint8_t abts_f_ctl; 1521 uint8_t abts_type; 1522 uint16_t abts_seq_cnt; 1523 uint8_t abts_df_ctl; 1524 uint8_t abts_seq_id; 1525 uint16_t abts_rx_id; 1526 uint16_t abts_ox_id; 1527 uint32_t abts_param; 1528 uint8_t abts_reserved2[16]; 1529 uint32_t abts_rxid_task; 1530 } abts_t; 1531 1532 typedef struct { 1533 isphdr_t abts_rsp_header; 1534 uint32_t abts_rsp_handle; 1535 uint16_t abts_rsp_status; 1536 uint16_t abts_rsp_nphdl; 1537 uint16_t abts_rsp_ctl_flags; 1538 uint16_t abts_rsp_sof; 1539 uint32_t abts_rsp_rxid_abts; 1540 uint16_t abts_rsp_did_lo; 1541 uint8_t abts_rsp_did_hi; 1542 uint8_t abts_rsp_r_ctl; 1543 uint16_t abts_rsp_sid_lo; 1544 uint8_t abts_rsp_sid_hi; 1545 uint8_t abts_rsp_cs_ctl; 1546 uint16_t abts_rsp_f_ctl_lo; 1547 uint8_t abts_rsp_f_ctl_hi; 1548 uint8_t abts_rsp_type; 1549 uint16_t abts_rsp_seq_cnt; 1550 uint8_t abts_rsp_df_ctl; 1551 uint8_t abts_rsp_seq_id; 1552 uint16_t abts_rsp_rx_id; 1553 uint16_t abts_rsp_ox_id; 1554 uint32_t abts_rsp_param; 1555 union { 1556 struct { 1557 uint16_t reserved; 1558 uint8_t last_seq_id; 1559 uint8_t seq_id_valid; 1560 uint16_t aborted_rx_id; 1561 uint16_t aborted_ox_id; 1562 uint16_t high_seq_cnt; 1563 uint16_t low_seq_cnt; 1564 uint8_t reserved2[4]; 1565 } ba_acc; 1566 struct { 1567 uint8_t vendor_unique; 1568 uint8_t explanation; 1569 uint8_t reason; 1570 uint8_t reserved; 1571 uint8_t reserved2[12]; 1572 } ba_rjt; 1573 struct { 1574 uint8_t reserved[8]; 1575 uint32_t subcode1; 1576 uint32_t subcode2; 1577 } rsp; 1578 uint8_t reserved[16]; 1579 } abts_rsp_payload; 1580 uint32_t abts_rsp_rxid_task; 1581 } abts_rsp_t; 1582 1583 /* terminate this ABTS exchange */ 1584 #define ISP24XX_ABTS_RSP_TERMINATE 0x01 1585 1586 #define ISP24XX_ABTS_RSP_COMPLETE 0x00 1587 #define ISP24XX_ABTS_RSP_RESET 0x04 1588 #define ISP24XX_ABTS_RSP_ABORTED 0x05 1589 #define ISP24XX_ABTS_RSP_TIMEOUT 0x06 1590 #define ISP24XX_ABTS_RSP_INVXID 0x08 1591 #define ISP24XX_ABTS_RSP_LOGOUT 0x29 1592 #define ISP24XX_ABTS_RSP_SUBCODE 0x31 1593 1594 #define ISP24XX_NO_TASK 0xffffffff 1595 1596 /* 1597 * Miscellaneous 1598 * 1599 * This is the limit of the number of dma segments we can deal with based 1600 * not on the size of the segment counter (which is 16 bits), but on the 1601 * size of the number of queue entries field (which is 8 bits). We assume 1602 * one segment in the first queue entry, plus we can have 5 segments per 1603 * continuation entry, multiplied by maximum of continuation entries. 1604 */ 1605 #define ISP_NSEG64_MAX (1 + (QENTRY_MAX - 1) * 5) 1606 1607 #endif /* _ISPMBOX_H */ 1608