1 /* $FreeBSD$ */ 2 /* 3 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 4 * 5 * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #ifndef _ISPMBOX_H 31 #define _ISPMBOX_H 32 33 /* 34 * Mailbox Command Opcodes 35 */ 36 #define MBOX_NO_OP 0x0000 37 #define MBOX_LOAD_RAM 0x0001 38 #define MBOX_EXEC_FIRMWARE 0x0002 39 #define MBOX_DUMP_RAM 0x0003 40 #define MBOX_WRITE_RAM_WORD 0x0004 41 #define MBOX_READ_RAM_WORD 0x0005 42 #define MBOX_MAILBOX_REG_TEST 0x0006 43 #define MBOX_VERIFY_CHECKSUM 0x0007 44 #define MBOX_ABOUT_FIRMWARE 0x0008 45 /* 9 */ 46 /* a */ 47 /* b */ 48 /* c */ 49 /* d */ 50 #define MBOX_CHECK_FIRMWARE 0x000e 51 /* f */ 52 #define MBOX_INIT_REQ_QUEUE 0x0010 53 #define MBOX_INIT_RES_QUEUE 0x0011 54 #define MBOX_EXECUTE_IOCB 0x0012 55 #define MBOX_WAKE_UP 0x0013 56 #define MBOX_STOP_FIRMWARE 0x0014 57 #define MBOX_ABORT 0x0015 58 #define MBOX_ABORT_DEVICE 0x0016 59 #define MBOX_ABORT_TARGET 0x0017 60 #define MBOX_BUS_RESET 0x0018 61 #define MBOX_STOP_QUEUE 0x0019 62 #define MBOX_START_QUEUE 0x001a 63 #define MBOX_SINGLE_STEP_QUEUE 0x001b 64 #define MBOX_ABORT_QUEUE 0x001c 65 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 66 /* 1e */ 67 #define MBOX_GET_FIRMWARE_STATUS 0x001f 68 #define MBOX_GET_INIT_SCSI_ID 0x0020 69 #define MBOX_GET_SELECT_TIMEOUT 0x0021 70 #define MBOX_GET_RETRY_COUNT 0x0022 71 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 72 #define MBOX_GET_CLOCK_RATE 0x0024 73 #define MBOX_GET_ACT_NEG_STATE 0x0025 74 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 75 #define MBOX_GET_SBUS_PARAMS 0x0027 76 #define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS 77 #define MBOX_GET_TARGET_PARAMS 0x0028 78 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 79 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a 80 /* 2b */ 81 /* 2c */ 82 /* 2d */ 83 /* 2e */ 84 /* 2f */ 85 #define MBOX_SET_INIT_SCSI_ID 0x0030 86 #define MBOX_SET_SELECT_TIMEOUT 0x0031 87 #define MBOX_SET_RETRY_COUNT 0x0032 88 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 89 #define MBOX_SET_CLOCK_RATE 0x0034 90 #define MBOX_SET_ACT_NEG_STATE 0x0035 91 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 92 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 93 #define MBOX_SET_PCI_PARAMETERS 0x0037 94 #define MBOX_SET_TARGET_PARAMS 0x0038 95 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 96 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a 97 /* 3b */ 98 /* 3c */ 99 /* 3d */ 100 /* 3e */ 101 /* 3f */ 102 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 103 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 104 #define MBOX_EXEC_BIOS_IOCB 0x0042 105 #define MBOX_SET_FW_FEATURES 0x004a 106 #define MBOX_GET_FW_FEATURES 0x004b 107 #define FW_FEATURE_LVD_NOTIFY 0x2 108 #define FW_FEATURE_FAST_POST 0x1 109 110 #define MBOX_ENABLE_TARGET_MODE 0x0055 111 #define ENABLE_TARGET_FLAG 0x8000 112 #define ENABLE_TQING_FLAG 0x0004 113 #define ENABLE_MANDATORY_DISC 0x0002 114 #define MBOX_GET_TARGET_STATUS 0x0056 115 116 /* These are for the ISP2X00 FC cards */ 117 #define MBOX_GET_LOOP_ID 0x0020 118 #define MBOX_GET_FIRMWARE_OPTIONS 0x0028 119 #define MBOX_SET_FIRMWARE_OPTIONS 0x0038 120 #define MBOX_GET_RESOURCE_COUNT 0x0042 121 #define MBOX_ENHANCED_GET_PDB 0x0047 122 #define MBOX_EXEC_COMMAND_IOCB_A64 0x0054 123 #define MBOX_INIT_FIRMWARE 0x0060 124 #define MBOX_GET_INIT_CONTROL_BLOCK 0x0061 125 #define MBOX_INIT_LIP 0x0062 126 #define MBOX_GET_FC_AL_POSITION_MAP 0x0063 127 #define MBOX_GET_PORT_DB 0x0064 128 #define MBOX_CLEAR_ACA 0x0065 129 #define MBOX_TARGET_RESET 0x0066 130 #define MBOX_CLEAR_TASK_SET 0x0067 131 #define MBOX_ABORT_TASK_SET 0x0068 132 #define MBOX_GET_FW_STATE 0x0069 133 #define MBOX_GET_PORT_NAME 0x006A 134 #define MBOX_GET_LINK_STATUS 0x006B 135 #define MBOX_INIT_LIP_RESET 0x006C 136 #define MBOX_SEND_SNS 0x006E 137 #define MBOX_FABRIC_LOGIN 0x006F 138 #define MBOX_SEND_CHANGE_REQUEST 0x0070 139 #define MBOX_FABRIC_LOGOUT 0x0071 140 #define MBOX_INIT_LIP_LOGIN 0x0072 141 142 #define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */ 143 #define MBGSD_GET_RATE 0 144 #define MBGSD_SET_RATE 1 145 #define MBGSD_ONEGB 0 146 #define MBGSD_TWOGB 1 147 #define MBGSD_AUTO 2 148 149 150 #define ISP2100_SET_PCI_PARAM 0x00ff 151 152 #define MBOX_BUSY 0x04 153 154 typedef struct { 155 u_int16_t param[8]; 156 } mbreg_t; 157 158 /* 159 * Mailbox Command Complete Status Codes 160 */ 161 #define MBOX_COMMAND_COMPLETE 0x4000 162 #define MBOX_INVALID_COMMAND 0x4001 163 #define MBOX_HOST_INTERFACE_ERROR 0x4002 164 #define MBOX_TEST_FAILED 0x4003 165 #define MBOX_COMMAND_ERROR 0x4005 166 #define MBOX_COMMAND_PARAM_ERROR 0x4006 167 #define MBOX_PORT_ID_USED 0x4007 168 #define MBOX_LOOP_ID_USED 0x4008 169 #define MBOX_ALL_IDS_USED 0x4009 170 #define MBOX_NOT_LOGGED_IN 0x400A 171 #define MBLOGALL 0x000f 172 #define MBLOGNONE 0x0000 173 #define MBLOGMASK(x) ((x) & 0xf) 174 175 /* 176 * Asynchronous event status codes 177 */ 178 #define ASYNC_BUS_RESET 0x8001 179 #define ASYNC_SYSTEM_ERROR 0x8002 180 #define ASYNC_RQS_XFER_ERR 0x8003 181 #define ASYNC_RSP_XFER_ERR 0x8004 182 #define ASYNC_QWAKEUP 0x8005 183 #define ASYNC_TIMEOUT_RESET 0x8006 184 #define ASYNC_DEVICE_RESET 0x8007 185 #define ASYNC_EXTMSG_UNDERRUN 0x800A 186 #define ASYNC_SCAM_INT 0x800B 187 #define ASYNC_HUNG_SCSI 0x800C 188 #define ASYNC_KILLED_BUS 0x800D 189 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 190 #define ASYNC_LIP_OCCURRED 0x8010 191 #define ASYNC_LOOP_UP 0x8011 192 #define ASYNC_LOOP_DOWN 0x8012 193 #define ASYNC_LOOP_RESET 0x8013 194 #define ASYNC_PDB_CHANGED 0x8014 195 #define ASYNC_CHANGE_NOTIFY 0x8015 196 #define ASYNC_LIP_F8 0x8016 197 #define ASYNC_CMD_CMPLT 0x8020 198 #define ASYNC_CTIO_DONE 0x8021 199 #define ASYNC_IP_XMIT_DONE 0x8022 200 #define ASYNC_IP_RECV_DONE 0x8023 201 #define ASYNC_IP_BROADCAST 0x8024 202 #define ASYNC_IP_RCVQ_LOW 0x8025 203 #define ASYNC_IP_RCVQ_EMPTY 0x8026 204 #define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 205 #define ASYNC_PTPMODE 0x8030 206 #define ASYNC_RIO1 0x8031 207 #define ASYNC_RIO2 0x8032 208 #define ASYNC_RIO3 0x8033 209 #define ASYNC_RIO4 0x8034 210 #define ASYNC_RIO5 0x8035 211 #define ASYNC_CONNMODE 0x8036 212 #define ISP_CONN_LOOP 1 213 #define ISP_CONN_PTP 2 214 #define ISP_CONN_BADLIP 3 215 #define ISP_CONN_FATAL 4 216 #define ISP_CONN_LOOPBACK 5 217 #define ASYNC_RIO_RESP 0x8040 218 #define ASYNC_RIO_COMP 0x8042 219 /* 220 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options 221 * mailbox command to enable this. 222 */ 223 #define ASYNC_QFULL_SENT 0x8049 224 225 /* 226 * Mailbox Usages 227 */ 228 229 #define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \ 230 ISP_WRITE(isp, isp->isp_rqstinrp, value) 231 232 #define READ_REQUEST_QUEUE_OUT_POINTER(isp) \ 233 ISP_READ(isp, isp->isp_rqstoutrp) 234 235 #define READ_RESPONSE_QUEUE_IN_POINTER(isp) \ 236 ISP_READ(isp, isp->isp_respinrp) 237 238 #define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \ 239 ISP_WRITE(isp, isp->isp_respoutrp, value) 240 241 /* 242 * Command Structure Definitions 243 */ 244 245 typedef struct { 246 u_int32_t ds_base; 247 u_int32_t ds_count; 248 } ispds_t; 249 250 typedef struct { 251 u_int32_t ds_base; 252 u_int32_t ds_basehi; 253 u_int32_t ds_count; 254 } ispds64_t; 255 256 typedef struct { 257 u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */ 258 u_int32_t ds_segment; /* unused */ 259 u_int32_t ds_base; /* 32 bit address of DSD list */ 260 } ispdslist_t; 261 262 263 /* 264 * These elements get swizzled around for SBus instances. 265 */ 266 #define _ISP_SWAP8(a, b) { \ 267 u_int8_t tmp; \ 268 tmp = a; \ 269 a = b; \ 270 b = tmp; \ 271 } 272 typedef struct { 273 u_int8_t rqs_entry_type; 274 u_int8_t rqs_entry_count; 275 u_int8_t rqs_seqno; 276 u_int8_t rqs_flags; 277 } isphdr_t; 278 /* 279 * There are no (for all intents and purposes) non-sparc SBus machines 280 */ 281 #ifdef __sparc__ 282 #define ISP_SBUSIFY_ISPHDR(isp, hdrp) \ 283 if ((isp)->isp_bustype == ISP_BT_SBUS) { \ 284 _ISP_SWAP8((hdrp)->rqs_entry_count, (hdrp)->rqs_entry_type); \ 285 _ISP_SWAP8((hdrp)->rqs_flags, (hdrp)->rqs_seqno); \ 286 } 287 #else 288 #define ISP_SBUSIFY_ISPHDR(a, b) 289 #endif 290 291 /* RQS Flag definitions */ 292 #define RQSFLAG_CONTINUATION 0x01 293 #define RQSFLAG_FULL 0x02 294 #define RQSFLAG_BADHEADER 0x04 295 #define RQSFLAG_BADPACKET 0x08 296 297 /* RQS entry_type definitions */ 298 #define RQSTYPE_REQUEST 0x01 299 #define RQSTYPE_DATASEG 0x02 300 #define RQSTYPE_RESPONSE 0x03 301 #define RQSTYPE_MARKER 0x04 302 #define RQSTYPE_CMDONLY 0x05 303 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 304 #define RQSTYPE_CTIO 0x07 /* Target Mode */ 305 #define RQSTYPE_SCAM 0x08 306 #define RQSTYPE_A64 0x09 307 #define RQSTYPE_A64_CONT 0x0a 308 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 309 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 310 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 311 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 312 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 313 #define RQSTYPE_STATUS_CONT 0x10 314 #define RQSTYPE_T2RQS 0x11 315 #define RQSTYPE_IP_XMIT 0x13 316 #define RQSTYPE_T4RQS 0x15 317 #define RQSTYPE_ATIO2 0x16 /* Target Mode */ 318 #define RQSTYPE_CTIO2 0x17 /* Target Mode */ 319 #define RQSTYPE_CSET0 0x18 320 #define RQSTYPE_T3RQS 0x19 321 #define RQSTYPE_IP_XMIT_64 0x1b 322 #define RQSTYPE_CTIO4 0x1e /* Target Mode */ 323 #define RQSTYPE_CTIO3 0x1f /* Target Mode */ 324 #define RQSTYPE_RIO1 0x21 325 #define RQSTYPE_RIO2 0x22 326 #define RQSTYPE_IP_RECV 0x23 327 #define RQSTYPE_IP_RECV_CONT 0x24 328 329 330 #define ISP_RQDSEG 4 331 typedef struct { 332 isphdr_t req_header; 333 u_int32_t req_handle; 334 u_int8_t req_lun_trn; 335 u_int8_t req_target; 336 u_int16_t req_cdblen; 337 #define req_modifier req_cdblen /* marker packet */ 338 u_int16_t req_flags; 339 u_int16_t req_reserved; 340 u_int16_t req_time; 341 u_int16_t req_seg_count; 342 u_int8_t req_cdb[12]; 343 ispds_t req_dataseg[ISP_RQDSEG]; 344 } ispreq_t; 345 346 /* 347 * A request packet can also be a marker packet. 348 */ 349 #define SYNC_DEVICE 0 350 #define SYNC_TARGET 1 351 #define SYNC_ALL 2 352 353 /* 354 * There are no (for all intents and purposes) non-sparc SBus machines 355 */ 356 #ifdef __sparc__ 357 #define ISP_SBUSIFY_ISPREQ(isp, rqp) \ 358 if ((isp)->isp_bustype == ISP_BT_SBUS) { \ 359 _ISP_SWAP8((rqp)->req_target, (rqp)->req_lun_trn); \ 360 } 361 #else 362 #define ISP_SBUSIFY_ISPREQ(a, b) 363 #endif 364 365 #define ISP_RQDSEG_T2 3 366 typedef struct { 367 isphdr_t req_header; 368 u_int32_t req_handle; 369 u_int8_t req_lun_trn; 370 u_int8_t req_target; 371 u_int16_t req_scclun; 372 u_int16_t req_flags; 373 u_int16_t _res2; 374 u_int16_t req_time; 375 u_int16_t req_seg_count; 376 u_int32_t req_cdb[4]; 377 u_int32_t req_totalcnt; 378 ispds_t req_dataseg[ISP_RQDSEG_T2]; 379 } ispreqt2_t; 380 381 #define ISP_RQDSEG_T3 2 382 typedef struct { 383 isphdr_t req_header; 384 u_int32_t req_handle; 385 u_int8_t req_lun_trn; 386 u_int8_t req_target; 387 u_int16_t req_scclun; 388 u_int16_t req_flags; 389 u_int16_t _res2; 390 u_int16_t req_time; 391 u_int16_t req_seg_count; 392 u_int32_t req_cdb[4]; 393 u_int32_t req_totalcnt; 394 ispds64_t req_dataseg[ISP_RQDSEG_T3]; 395 } ispreqt3_t; 396 397 /* req_flag values */ 398 #define REQFLAG_NODISCON 0x0001 399 #define REQFLAG_HTAG 0x0002 400 #define REQFLAG_OTAG 0x0004 401 #define REQFLAG_STAG 0x0008 402 #define REQFLAG_TARGET_RTN 0x0010 403 404 #define REQFLAG_NODATA 0x0000 405 #define REQFLAG_DATA_IN 0x0020 406 #define REQFLAG_DATA_OUT 0x0040 407 #define REQFLAG_DATA_UNKNOWN 0x0060 408 409 #define REQFLAG_DISARQ 0x0100 410 #define REQFLAG_FRC_ASYNC 0x0200 411 #define REQFLAG_FRC_SYNC 0x0400 412 #define REQFLAG_FRC_WIDE 0x0800 413 #define REQFLAG_NOPARITY 0x1000 414 #define REQFLAG_STOPQ 0x2000 415 #define REQFLAG_XTRASNS 0x4000 416 #define REQFLAG_PRIORITY 0x8000 417 418 typedef struct { 419 isphdr_t req_header; 420 u_int32_t req_handle; 421 u_int8_t req_lun_trn; 422 u_int8_t req_target; 423 u_int16_t req_cdblen; 424 u_int16_t req_flags; 425 u_int16_t _res1; 426 u_int16_t req_time; 427 u_int16_t req_seg_count; 428 u_int8_t req_cdb[44]; 429 } ispextreq_t; 430 431 #define ISP_CDSEG 7 432 typedef struct { 433 isphdr_t req_header; 434 u_int32_t _res1; 435 ispds_t req_dataseg[ISP_CDSEG]; 436 } ispcontreq_t; 437 438 #define ISP_CDSEG64 5 439 typedef struct { 440 isphdr_t req_header; 441 ispds64_t req_dataseg[ISP_CDSEG64]; 442 } ispcontreq64_t; 443 444 typedef struct { 445 isphdr_t req_header; 446 u_int32_t req_handle; 447 u_int16_t req_scsi_status; 448 u_int16_t req_completion_status; 449 u_int16_t req_state_flags; 450 u_int16_t req_status_flags; 451 u_int16_t req_time; 452 #define req_response_len req_time /* FC only */ 453 u_int16_t req_sense_len; 454 u_int32_t req_resid; 455 u_int8_t req_response[8]; /* FC only */ 456 u_int8_t req_sense_data[32]; 457 } ispstatusreq_t; 458 459 /* 460 * For Qlogic 2X00, the high order byte of SCSI status has 461 * additional meaning. 462 */ 463 #define RQCS_RU 0x800 /* Residual Under */ 464 #define RQCS_RO 0x400 /* Residual Over */ 465 #define RQCS_RESID (RQCS_RU|RQCS_RO) 466 #define RQCS_SV 0x200 /* Sense Length Valid */ 467 #define RQCS_RV 0x100 /* FCP Response Length Valid */ 468 469 /* 470 * Completion Status Codes. 471 */ 472 #define RQCS_COMPLETE 0x0000 473 #define RQCS_DMA_ERROR 0x0002 474 #define RQCS_RESET_OCCURRED 0x0004 475 #define RQCS_ABORTED 0x0005 476 #define RQCS_TIMEOUT 0x0006 477 #define RQCS_DATA_OVERRUN 0x0007 478 #define RQCS_DATA_UNDERRUN 0x0015 479 #define RQCS_QUEUE_FULL 0x001C 480 481 /* 1X00 Only Completion Codes */ 482 #define RQCS_INCOMPLETE 0x0001 483 #define RQCS_TRANSPORT_ERROR 0x0003 484 #define RQCS_COMMAND_OVERRUN 0x0008 485 #define RQCS_STATUS_OVERRUN 0x0009 486 #define RQCS_BAD_MESSAGE 0x000a 487 #define RQCS_NO_MESSAGE_OUT 0x000b 488 #define RQCS_EXT_ID_FAILED 0x000c 489 #define RQCS_IDE_MSG_FAILED 0x000d 490 #define RQCS_ABORT_MSG_FAILED 0x000e 491 #define RQCS_REJECT_MSG_FAILED 0x000f 492 #define RQCS_NOP_MSG_FAILED 0x0010 493 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 494 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 495 #define RQCS_ID_MSG_FAILED 0x0013 496 #define RQCS_UNEXP_BUS_FREE 0x0014 497 #define RQCS_XACT_ERR1 0x0018 498 #define RQCS_XACT_ERR2 0x0019 499 #define RQCS_XACT_ERR3 0x001A 500 #define RQCS_BAD_ENTRY 0x001B 501 #define RQCS_PHASE_SKIPPED 0x001D 502 #define RQCS_ARQS_FAILED 0x001E 503 #define RQCS_WIDE_FAILED 0x001F 504 #define RQCS_SYNCXFER_FAILED 0x0020 505 #define RQCS_LVD_BUSERR 0x0021 506 507 /* 2X00 Only Completion Codes */ 508 #define RQCS_PORT_UNAVAILABLE 0x0028 509 #define RQCS_PORT_LOGGED_OUT 0x0029 510 #define RQCS_PORT_CHANGED 0x002A 511 #define RQCS_PORT_BUSY 0x002B 512 513 /* 514 * 1X00 specific State Flags 515 */ 516 #define RQSF_GOT_BUS 0x0100 517 #define RQSF_GOT_TARGET 0x0200 518 #define RQSF_SENT_CDB 0x0400 519 #define RQSF_XFRD_DATA 0x0800 520 #define RQSF_GOT_STATUS 0x1000 521 #define RQSF_GOT_SENSE 0x2000 522 #define RQSF_XFER_COMPLETE 0x4000 523 524 /* 525 * 2X00 specific State Flags 526 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available) 527 */ 528 #define RQSF_DATA_IN 0x0020 529 #define RQSF_DATA_OUT 0x0040 530 #define RQSF_STAG 0x0008 531 #define RQSF_OTAG 0x0004 532 #define RQSF_HTAG 0x0002 533 /* 534 * 1X00 Status Flags 535 */ 536 #define RQSTF_DISCONNECT 0x0001 537 #define RQSTF_SYNCHRONOUS 0x0002 538 #define RQSTF_PARITY_ERROR 0x0004 539 #define RQSTF_BUS_RESET 0x0008 540 #define RQSTF_DEVICE_RESET 0x0010 541 #define RQSTF_ABORTED 0x0020 542 #define RQSTF_TIMEOUT 0x0040 543 #define RQSTF_NEGOTIATION 0x0080 544 545 /* 546 * 2X00 specific state flags 547 */ 548 /* RQSF_SENT_CDB */ 549 /* RQSF_XFRD_DATA */ 550 /* RQSF_GOT_STATUS */ 551 /* RQSF_XFER_COMPLETE */ 552 553 /* 554 * 2X00 specific status flags 555 */ 556 /* RQSTF_ABORTED */ 557 /* RQSTF_TIMEOUT */ 558 #define RQSTF_DMA_ERROR 0x0080 559 #define RQSTF_LOGOUT 0x2000 560 561 /* 562 * Miscellaneous 563 */ 564 #ifndef ISP_EXEC_THROTTLE 565 #define ISP_EXEC_THROTTLE 16 566 #endif 567 568 /* 569 * About Firmware returns an 'attribute' word in mailbox 6. 570 */ 571 #define ISP_FW_ATTR_TMODE 0x01 572 #define ISP_FW_ATTR_SCCLUN 0x02 573 #define ISP_FW_ATTR_FABRIC 0x04 574 #define ISP_FW_ATTR_CLASS2 0x08 575 #define ISP_FW_ATTR_FCTAPE 0x10 576 #define ISP_FW_ATTR_IP 0x20 577 578 /* 579 * Reduced Interrupt Operation Response Queue Entreis 580 */ 581 582 typedef struct { 583 isphdr_t req_header; 584 u_int32_t req_handles[15]; 585 } isp_rio1_t; 586 587 typedef struct { 588 isphdr_t req_header; 589 u_int16_t req_handles[30]; 590 } isp_rio2_t; 591 592 /* 593 * FC (ISP2100) specific data structures 594 */ 595 596 /* 597 * Initialization Control Block 598 * 599 * Version One (prime) format. 600 */ 601 typedef struct isp_icb { 602 u_int8_t icb_version; 603 u_int8_t _reserved0; 604 u_int16_t icb_fwoptions; 605 u_int16_t icb_maxfrmlen; 606 u_int16_t icb_maxalloc; 607 u_int16_t icb_execthrottle; 608 u_int8_t icb_retry_count; 609 u_int8_t icb_retry_delay; 610 u_int8_t icb_portname[8]; 611 u_int16_t icb_hardaddr; 612 u_int8_t icb_iqdevtype; 613 u_int8_t icb_logintime; 614 u_int8_t icb_nodename[8]; 615 u_int16_t icb_rqstout; 616 u_int16_t icb_rspnsin; 617 u_int16_t icb_rqstqlen; 618 u_int16_t icb_rsltqlen; 619 u_int16_t icb_rqstaddr[4]; 620 u_int16_t icb_respaddr[4]; 621 u_int16_t icb_lunenables; 622 u_int8_t icb_ccnt; 623 u_int8_t icb_icnt; 624 u_int16_t icb_lunetimeout; 625 u_int16_t _reserved1; 626 u_int16_t icb_xfwoptions; 627 u_int8_t icb_racctimer; 628 u_int8_t icb_idelaytimer; 629 u_int16_t icb_zfwoptions; 630 u_int16_t _reserved2[13]; 631 } isp_icb_t; 632 #define ICB_VERSION1 1 633 634 #define ICBOPT_HARD_ADDRESS 0x0001 635 #define ICBOPT_FAIRNESS 0x0002 636 #define ICBOPT_FULL_DUPLEX 0x0004 637 #define ICBOPT_FAST_POST 0x0008 638 #define ICBOPT_TGT_ENABLE 0x0010 639 #define ICBOPT_INI_DISABLE 0x0020 640 #define ICBOPT_INI_ADISC 0x0040 641 #define ICBOPT_INI_TGTTYPE 0x0080 642 #define ICBOPT_PDBCHANGE_AE 0x0100 643 #define ICBOPT_NOLIP 0x0200 644 #define ICBOPT_SRCHDOWN 0x0400 645 #define ICBOPT_PREVLOOP 0x0800 646 #define ICBOPT_STOP_ON_QFULL 0x1000 647 #define ICBOPT_FULL_LOGIN 0x2000 648 #define ICBOPT_BOTH_WWNS 0x4000 649 #define ICBOPT_EXTENDED 0x8000 650 651 #define ICBXOPT_CLASS2_ACK0 0x0200 652 #define ICBXOPT_CLASS2 0x0100 653 #define ICBXOPT_LOOP_ONLY (0 << 4) 654 #define ICBXOPT_PTP_ONLY (1 << 4) 655 #define ICBXOPT_LOOP_2_PTP (2 << 4) 656 #define ICBXOPT_PTP_2_LOOP (3 << 4) 657 658 #define ICBXOPT_RIO_OFF 0 659 #define ICBXOPT_RIO_16BIT 1 660 #define ICBXOPT_RIO_32BIT 2 661 #define ICBXOPT_RIO_16BIT_DELAY 3 662 #define ICBXOPT_RIO_32BIT_DELAY 4 663 664 /* These 3 only apply to the 2300 */ 665 #define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14) 666 #define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14) 667 #define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14) 668 669 670 #define ICB_MIN_FRMLEN 256 671 #define ICB_MAX_FRMLEN 2112 672 #define ICB_DFLT_FRMLEN 1024 673 #define ICB_DFLT_ALLOC 256 674 #define ICB_DFLT_THROTTLE 16 675 #define ICB_DFLT_RDELAY 5 676 #define ICB_DFLT_RCOUNT 3 677 678 679 #define RQRSP_ADDR0015 0 680 #define RQRSP_ADDR1631 1 681 #define RQRSP_ADDR3247 2 682 #define RQRSP_ADDR4863 3 683 684 685 #define ICB_NNM0 7 686 #define ICB_NNM1 6 687 #define ICB_NNM2 5 688 #define ICB_NNM3 4 689 #define ICB_NNM4 3 690 #define ICB_NNM5 2 691 #define ICB_NNM6 1 692 #define ICB_NNM7 0 693 694 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 695 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 696 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 697 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 698 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 699 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 700 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 701 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 702 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 703 704 /* 705 * FC-AL Position Map 706 * 707 * This is an at most 128 byte map that returns either 708 * the LILP or Firmware generated list of ports. 709 * 710 * We deviate a bit from the returned qlogic format to 711 * use an extra bit to say whether this was a LILP or 712 * f/w generated map. 713 */ 714 typedef struct { 715 u_int8_t fwmap : 1, 716 count : 7; 717 u_int8_t map[127]; 718 } fcpos_map_t; 719 720 /* 721 * Port Data Base Element 722 */ 723 724 typedef struct { 725 u_int16_t pdb_options; 726 u_int8_t pdb_mstate; 727 u_int8_t pdb_sstate; 728 #define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2]) 729 u_int8_t pdb_hardaddr_bits[4]; 730 u_int8_t pdb_portid_bits[4]; 731 u_int8_t pdb_nodename[8]; 732 u_int8_t pdb_portname[8]; 733 u_int16_t pdb_execthrottle; 734 u_int16_t pdb_exec_count; 735 u_int8_t pdb_retry_count; 736 u_int8_t pdb_retry_delay; 737 u_int16_t pdb_resalloc; 738 u_int16_t pdb_curalloc; 739 u_int16_t pdb_qhead; 740 u_int16_t pdb_qtail; 741 u_int16_t pdb_tl_next; 742 u_int16_t pdb_tl_last; 743 u_int16_t pdb_features; /* PLOGI, Common Service */ 744 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */ 745 u_int16_t pdb_roi; /* PLOGI, Common Service */ 746 u_int8_t pdb_target; 747 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ 748 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */ 749 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */ 750 u_int16_t pdb_noseq; /* PLOGI, Class 3 */ 751 u_int16_t pdb_labrtflg; 752 u_int16_t pdb_lstopflg; 753 u_int16_t pdb_sqhead; 754 u_int16_t pdb_sqtail; 755 u_int16_t pdb_ptimer; 756 u_int16_t pdb_nxt_seqid; 757 u_int16_t pdb_fcount; 758 u_int16_t pdb_prli_len; 759 u_int16_t pdb_prli_svc0; 760 u_int16_t pdb_prli_svc3; 761 u_int16_t pdb_loopid; 762 u_int16_t pdb_il_ptr; 763 u_int16_t pdb_sl_ptr; 764 } isp_pdb_t; 765 766 #define PDB_OPTIONS_XMITTING (1<<11) 767 #define PDB_OPTIONS_LNKXMIT (1<<10) 768 #define PDB_OPTIONS_ABORTED (1<<9) 769 #define PDB_OPTIONS_ADISC (1<<1) 770 771 #define PDB_STATE_DISCOVERY 0 772 #define PDB_STATE_WDISC_ACK 1 773 #define PDB_STATE_PLOGI 2 774 #define PDB_STATE_PLOGI_ACK 3 775 #define PDB_STATE_PRLI 4 776 #define PDB_STATE_PRLI_ACK 5 777 #define PDB_STATE_LOGGED_IN 6 778 #define PDB_STATE_PORT_UNAVAIL 7 779 #define PDB_STATE_PRLO 8 780 #define PDB_STATE_PRLO_ACK 9 781 #define PDB_STATE_PLOGO 10 782 #define PDB_STATE_PLOG_ACK 11 783 784 #define SVC3_TGT_ROLE 0x10 785 #define SVC3_INI_ROLE 0x20 786 #define SVC3_ROLE_MASK 0x30 787 #define SVC3_ROLE_SHIFT 4 788 789 #define SNS_GAN 0x100 790 #define SNS_GP3 0x171 791 #define SNS_RFT 0x217 792 typedef struct { 793 u_int16_t snscb_rblen; /* response buffer length (words) */ 794 u_int16_t snscb_res0; 795 u_int16_t snscb_addr[4]; /* response buffer address */ 796 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 797 u_int16_t snscb_res1; 798 u_int16_t snscb_data[1]; /* variable data */ 799 } sns_screq_t; /* Subcommand Request Structure */ 800 #define SNS_GAN_REQ_SIZE (sizeof (sns_screq_t)+(5*(sizeof (u_int16_t)))) 801 #define SNS_GP3_REQ_SIZE (sizeof (sns_screq_t)+(5*(sizeof (u_int16_t)))) 802 #define SNS_RFT_REQ_SIZE (sizeof (sns_screq_t)+(21*(sizeof (u_int16_t)))) 803 804 typedef struct { 805 u_int8_t snscb_cthdr[16]; 806 u_int8_t snscb_port_type; 807 u_int8_t snscb_port_id[3]; 808 u_int8_t snscb_portname[8]; 809 u_int16_t snscb_data[1]; /* variable data */ 810 } sns_scrsp_t; /* Subcommand Response Structure */ 811 #define SNS_GAN_RESP_SIZE 608 /* Maximum response size (bytes) */ 812 #define SNS_GP3_RESP_SIZE 532 /* XXX: For 128 ports */ 813 #define SNS_RFT_RESP_SIZE 16 814 815 typedef struct { 816 u_int8_t snscb_cthdr[16]; 817 u_int8_t snscb_port_type; 818 u_int8_t snscb_port_id[3]; 819 u_int8_t snscb_portname[8]; 820 u_int8_t snscb_pnlen; /* symbolic port name length */ 821 u_int8_t snscb_pname[255]; /* symbolic port name */ 822 u_int8_t snscb_nodename[8]; 823 u_int8_t snscb_nnlen; /* symbolic node name length */ 824 u_int8_t snscb_nname[255]; /* symbolic node name */ 825 u_int8_t snscb_ipassoc[8]; 826 u_int8_t snscb_ipaddr[16]; 827 u_int8_t snscb_svc_class[4]; 828 u_int8_t snscb_fc4_types[32]; 829 u_int8_t snscb_fpname[8]; 830 u_int8_t snscb_reserved; 831 u_int8_t snscb_hardaddr[3]; 832 } sns_ganrsp_t; /* Subcommand Response Structure */ 833 834 #endif /* _ISPMBOX_H */ 835