1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2009-2020 Alexander Motin <mav@FreeBSD.org> 6 * Copyright (c) 1997-2009 by Matthew Jacob 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 35 */ 36 #ifndef _ISPMBOX_H 37 #define _ISPMBOX_H 38 39 /* 40 * Mailbox Command Opcodes 41 */ 42 #define MBOX_NO_OP 0x0000 43 #define MBOX_LOAD_RAM 0x0001 44 #define MBOX_EXEC_FIRMWARE 0x0002 45 #define MBOX_DUMP_RAM 0x0003 46 #define MBOX_WRITE_RAM_WORD 0x0004 47 #define MBOX_READ_RAM_WORD 0x0005 48 #define MBOX_MAILBOX_REG_TEST 0x0006 49 #define MBOX_VERIFY_CHECKSUM 0x0007 50 #define MBOX_ABOUT_FIRMWARE 0x0008 51 #define MBOX_LOAD_RISC_RAM_2100 0x0009 52 /* a */ 53 #define MBOX_LOAD_RISC_RAM 0x000b 54 #define MBOX_DUMP_RISC_RAM 0x000c 55 #define MBOX_WRITE_RAM_WORD_EXTENDED 0x000d 56 #define MBOX_CHECK_FIRMWARE 0x000e 57 #define MBOX_READ_RAM_WORD_EXTENDED 0x000f 58 #define MBOX_INIT_REQ_QUEUE 0x0010 59 #define MBOX_INIT_RES_QUEUE 0x0011 60 #define MBOX_EXECUTE_IOCB 0x0012 61 #define MBOX_WAKE_UP 0x0013 62 #define MBOX_STOP_FIRMWARE 0x0014 63 #define MBOX_ABORT 0x0015 64 #define MBOX_ABORT_DEVICE 0x0016 65 #define MBOX_ABORT_TARGET 0x0017 66 #define MBOX_BUS_RESET 0x0018 67 #define MBOX_STOP_QUEUE 0x0019 68 #define MBOX_START_QUEUE 0x001a 69 #define MBOX_SINGLE_STEP_QUEUE 0x001b 70 #define MBOX_ABORT_QUEUE 0x001c 71 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 72 /* 1e */ 73 #define MBOX_GET_FIRMWARE_STATUS 0x001f 74 #define MBOX_GET_INIT_SCSI_ID 0x0020 75 #define MBOX_GET_SELECT_TIMEOUT 0x0021 76 #define MBOX_GET_RETRY_COUNT 0x0022 77 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 78 #define MBOX_GET_CLOCK_RATE 0x0024 79 #define MBOX_GET_ACT_NEG_STATE 0x0025 80 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 81 #define MBOX_GET_SBUS_PARAMS 0x0027 82 #define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS 83 #define MBOX_GET_TARGET_PARAMS 0x0028 84 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 85 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a 86 /* 2b */ 87 /* 2c */ 88 /* 2d */ 89 /* 2e */ 90 /* 2f */ 91 #define MBOX_SET_INIT_SCSI_ID 0x0030 92 #define MBOX_SET_SELECT_TIMEOUT 0x0031 93 #define MBOX_SET_RETRY_COUNT 0x0032 94 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 95 #define MBOX_SET_CLOCK_RATE 0x0034 96 #define MBOX_SET_ACT_NEG_STATE 0x0035 97 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 98 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 99 #define MBOX_SET_PCI_PARAMETERS 0x0037 100 #define MBOX_SET_TARGET_PARAMS 0x0038 101 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 102 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a 103 /* 3b */ 104 /* 3c */ 105 /* 3d */ 106 /* 3e */ 107 /* 3f */ 108 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 109 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 110 #define MBOX_EXEC_BIOS_IOCB 0x0042 111 #define MBOX_SET_FW_FEATURES 0x004a 112 #define MBOX_GET_FW_FEATURES 0x004b 113 #define FW_FEATURE_FAST_POST 0x1 114 #define FW_FEATURE_LVD_NOTIFY 0x2 115 #define FW_FEATURE_RIO_32BIT 0x4 116 #define FW_FEATURE_RIO_16BIT 0x8 117 118 #define MBOX_INIT_REQ_QUEUE_A64 0x0052 119 #define MBOX_INIT_RES_QUEUE_A64 0x0053 120 121 #define MBOX_ENABLE_TARGET_MODE 0x0055 122 #define ENABLE_TARGET_FLAG 0x8000 123 #define ENABLE_TQING_FLAG 0x0004 124 #define ENABLE_MANDATORY_DISC 0x0002 125 #define MBOX_GET_TARGET_STATUS 0x0056 126 127 /* These are for the ISP2X00 FC cards */ 128 #define MBOX_LOAD_FLASH_FIRMWARE 0x0003 129 #define MBOX_WRITE_FC_SERDES_REG 0x0003 /* FC only */ 130 #define MBOX_READ_FC_SERDES_REG 0x0004 /* FC only */ 131 #define MBOX_GET_IO_STATUS 0x0012 132 #define MBOX_SET_TRANSMIT_PARAMS 0x0019 133 #define MBOX_SET_PORT_PARAMS 0x001a 134 #define MBOX_LOAD_OP_FW_PARAMS 0x001b 135 #define MBOX_INIT_MULTIPLE_QUEUE 0x001f 136 #define MBOX_GET_LOOP_ID 0x0020 137 /* for 24XX cards, outgoing mailbox 7 has these values for F or FL topologies */ 138 #define ISP24XX_INORDER 0x0100 139 #define ISP24XX_NPIV_SAN 0x0400 140 #define ISP24XX_VSAN_SAN 0x1000 141 #define ISP24XX_FC_SP_SAN 0x2000 142 #define MBOX_GET_TIMEOUT_PARAMS 0x0022 143 #define MBOX_GET_FIRMWARE_OPTIONS 0x0028 144 #define MBOX_GENERATE_SYSTEM_ERROR 0x002a 145 #define MBOX_WRITE_SFP 0x0030 146 #define MBOX_READ_SFP 0x0031 147 #define MBOX_SET_TIMEOUT_PARAMS 0x0032 148 #define MBOX_SET_FIRMWARE_OPTIONS 0x0038 149 #define MBOX_GET_SET_FC_LED_CONF 0x003b 150 #define MBOX_RESTART_NIC_FIRMWARE 0x003d /* FCoE only */ 151 #define MBOX_ACCESS_CONTROL 0x003e 152 #define MBOX_LOOP_PORT_BYPASS 0x0040 /* FC only */ 153 #define MBOX_LOOP_PORT_ENABLE 0x0041 /* FC only */ 154 #define MBOX_GET_RESOURCE_COUNT 0x0042 155 #define MBOX_REQUEST_OFFLINE_MODE 0x0043 156 #define MBOX_DIAGNOSTIC_ECHO_TEST 0x0044 157 #define MBOX_DIAGNOSTIC_LOOPBACK 0x0045 158 #define MBOX_ENHANCED_GET_PDB 0x0047 159 #define MBOX_INIT_FIRMWARE_MULTI_ID 0x0048 /* 2400 only */ 160 #define MBOX_GET_VP_DATABASE 0x0049 /* 2400 only */ 161 #define MBOX_GET_VP_DATABASE_ENTRY 0x004a /* 2400 only */ 162 #define MBOX_GET_FCF_LIST 0x0050 /* FCoE only */ 163 #define MBOX_GET_DCBX_PARAMETERS 0x0051 /* FCoE only */ 164 #define MBOX_HOST_MEMORY_COPY 0x0053 165 #define MBOX_EXEC_COMMAND_IOCB_A64 0x0054 166 #define MBOX_SEND_RNID 0x0057 167 #define MBOX_SET_PARAMETERS 0x0059 168 #define MBOX_GET_PARAMETERS 0x005a 169 #define MBOX_DRIVER_HEARTBEAT 0x005B /* FC only */ 170 #define MBOX_FW_HEARTBEAT 0x005C 171 #define MBOX_GET_SET_DATA_RATE 0x005D /* >=23XX only */ 172 #define MBGSD_GET_RATE 0 173 #define MBGSD_SET_RATE 1 174 #define MBGSD_SET_RATE_NOW 2 /* 24XX only */ 175 #define MBGSD_1GB 0x00 176 #define MBGSD_2GB 0x01 177 #define MBGSD_AUTO 0x02 178 #define MBGSD_4GB 0x03 /* 24XX only */ 179 #define MBGSD_8GB 0x04 /* 25XX only */ 180 #define MBGSD_16GB 0x05 /* 26XX only */ 181 #define MBGSD_32GB 0x06 /* 27XX only */ 182 #define MBGSD_10GB 0x13 /* 26XX only */ 183 #define MBOX_SEND_RNFT 0x005e 184 #define MBOX_INIT_FIRMWARE 0x0060 185 #define MBOX_GET_INIT_CONTROL_BLOCK 0x0061 186 #define MBOX_INIT_LIP 0x0062 187 #define MBOX_GET_FC_AL_POSITION_MAP 0x0063 188 #define MBOX_GET_PORT_DB 0x0064 189 #define MBOX_CLEAR_ACA 0x0065 190 #define MBOX_TARGET_RESET 0x0066 191 #define MBOX_CLEAR_TASK_SET 0x0067 192 #define MBOX_ABORT_TASK_SET 0x0068 193 #define MBOX_GET_FW_STATE 0x0069 194 #define MBOX_GET_PORT_NAME 0x006A 195 #define MBOX_GET_LINK_STATUS 0x006B 196 #define MBOX_INIT_LIP_RESET 0x006C 197 #define MBOX_GET_LINK_STAT_PR_DATA_CNT 0x006D 198 #define MBOX_SEND_SNS 0x006E 199 #define MBOX_FABRIC_LOGIN 0x006F 200 #define MBOX_SEND_CHANGE_REQUEST 0x0070 201 #define MBOX_FABRIC_LOGOUT 0x0071 202 #define MBOX_INIT_LIP_LOGIN 0x0072 203 #define MBOX_GET_PORT_NODE_NAME_LIST 0x0075 204 #define MBOX_SET_VENDOR_ID 0x0076 205 #define MBOX_GET_XGMAC_STATS 0x007a 206 #define MBOX_GET_ID_LIST 0x007C 207 #define MBOX_SEND_LFA 0x007d 208 #define MBOX_LUN_RESET 0x007E 209 210 #define ISP2100_SET_PCI_PARAM 0x00ff 211 212 #define MBOX_BUSY 0x04 213 214 /* 215 * Mailbox Command Complete Status Codes 216 */ 217 #define MBOX_COMMAND_COMPLETE 0x4000 218 #define MBOX_INVALID_COMMAND 0x4001 219 #define MBOX_HOST_INTERFACE_ERROR 0x4002 220 #define MBOX_TEST_FAILED 0x4003 221 #define MBOX_COMMAND_ERROR 0x4005 222 #define MBOX_COMMAND_PARAM_ERROR 0x4006 223 #define MBOX_PORT_ID_USED 0x4007 224 #define MBOX_LOOP_ID_USED 0x4008 225 #define MBOX_ALL_IDS_USED 0x4009 226 #define MBOX_NOT_LOGGED_IN 0x400A 227 #define MBOX_LINK_DOWN_ERROR 0x400B 228 #define MBOX_LOOPBACK_ERROR 0x400C 229 #define MBOX_CHECKSUM_ERROR 0x4010 230 #define MBOX_INVALID_PRODUCT_KEY 0x4020 231 /* pseudo mailbox completion codes */ 232 #define MBOX_REGS_BUSY 0x6000 /* registers in use */ 233 #define MBOX_TIMEOUT 0x6001 /* command timed out */ 234 235 #define MBLOGALL 0xffffffff 236 #define MBLOGNONE 0x00000000 237 #define MBLOGMASK(x) (1 << (((x) - 1) & 0x1f)) 238 239 /* 240 * Asynchronous event status codes 241 */ 242 #define ASYNC_BUS_RESET 0x8001 243 #define ASYNC_SYSTEM_ERROR 0x8002 244 #define ASYNC_RQS_XFER_ERR 0x8003 245 #define ASYNC_RSP_XFER_ERR 0x8004 246 #define ASYNC_ATIO_XFER_ERR 0x8005 247 #define ASYNC_TIMEOUT_RESET 0x8006 248 #define ASYNC_DEVICE_RESET 0x8007 249 #define ASYNC_EXTMSG_UNDERRUN 0x800A 250 #define ASYNC_SCAM_INT 0x800B 251 #define ASYNC_HUNG_SCSI 0x800C 252 #define ASYNC_KILLED_BUS 0x800D 253 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 254 #define ASYNC_LIP_OCCURRED 0x8010 /* FC only */ 255 #define ASYNC_LOOP_UP 0x8011 256 #define ASYNC_LOOP_DOWN 0x8012 257 #define ASYNC_LOOP_RESET 0x8013 /* FC only */ 258 #define ASYNC_PDB_CHANGED 0x8014 259 #define ASYNC_CHANGE_NOTIFY 0x8015 260 #define ASYNC_LIP_NOS_OLS_RECV 0x8016 /* FC only */ 261 #define ASYNC_LIP_ERROR 0x8017 /* FC only */ 262 #define ASYNC_AUTO_PLOGI_RJT 0x8018 263 #define ASYNC_SECURITY_UPDATE 0x801B 264 #define ASYNC_CMD_CMPLT 0x8020 265 #define ASYNC_CTIO_DONE 0x8021 266 #define ASYNC_RIO32_1 0x8021 267 #define ASYNC_RIO32_2 0x8022 268 #define ASYNC_IP_XMIT_DONE 0x8022 269 #define ASYNC_IP_RECV_DONE 0x8023 270 #define ASYNC_IP_BROADCAST 0x8024 271 #define ASYNC_IP_RCVQ_LOW 0x8025 272 #define ASYNC_IP_RCVQ_EMPTY 0x8026 273 #define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 274 #define ASYNC_ERR_LOGGING_DISABLED 0x8029 275 #define ASYNC_PTPMODE 0x8030 /* FC only */ 276 #define ASYNC_RIO16_1 0x8031 277 #define ASYNC_RIO16_2 0x8032 278 #define ASYNC_RIO16_3 0x8033 279 #define ASYNC_RIO16_4 0x8034 280 #define ASYNC_RIO16_5 0x8035 281 #define ASYNC_CONNMODE 0x8036 282 #define ISP_CONN_LOOP 1 283 #define ISP_CONN_PTP 2 284 #define ISP_CONN_BADLIP 3 285 #define ISP_CONN_FATAL 4 286 #define ISP_CONN_LOOPBACK 5 287 #define ASYNC_P2P_INIT_ERR 0x8037 288 #define ASYNC_RIOZIO_STALL 0x8040 /* there's a RIO/ZIO entry that hasn't been serviced */ 289 #define ASYNC_RIO32_2_2200 0x8042 /* same as ASYNC_RIO32_2, but for 2100/2200 */ 290 #define ASYNC_RCV_ERR 0x8048 291 /* 292 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options 293 * mailbox command to enable this. 294 */ 295 #define ASYNC_QFULL_SENT 0x8049 296 #define ASYNC_RJT_SENT 0x8049 /* 24XX only */ 297 #define ASYNC_SEL_CLASS2_P_RJT_SENT 0x804f 298 #define ASYNC_FW_RESTART_COMPLETE 0x8060 299 #define ASYNC_TEMPERATURE_ALERT 0x8070 300 #define ASYNC_INTER_DRIVER_COMP 0x8100 /* FCoE only */ 301 #define ASYNC_INTER_DRIVER_NOTIFY 0x8101 /* FCoE only */ 302 #define ASYNC_INTER_DRIVER_TIME_EXT 0x8102 /* FCoE only */ 303 #define ASYNC_TRANSCEIVER_INSERTION 0x8130 304 #define ASYNC_TRANSCEIVER_REMOVAL 0x8131 305 #define ASYNC_NIC_FW_STATE_CHANGE 0x8200 /* FCoE only */ 306 #define ASYNC_AUTOLOAD_FW_COMPLETE 0x8400 307 #define ASYNC_AUTOLOAD_FW_FAILURE 0x8401 308 309 /* 310 * Firmware Options. There are a lot of them. 311 * 312 * IFCOPTN - ISP Fibre Channel Option Word N 313 */ 314 #define IFCOPT1_EQFQASYNC (1 << 13) /* enable QFULL notification */ 315 #define IFCOPT1_EAABSRCVD (1 << 12) 316 #define IFCOPT1_RJTASYNC (1 << 11) /* enable 8018 notification */ 317 #define IFCOPT1_ENAPURE (1 << 10) 318 #define IFCOPT1_ENA8017 (1 << 7) 319 #define IFCOPT1_DISGPIO67 (1 << 6) 320 #define IFCOPT1_LIPLOSSIMM (1 << 5) 321 #define IFCOPT1_DISF7SWTCH (1 << 4) 322 #define IFCOPT1_CTIO_RETRY (1 << 3) 323 #define IFCOPT1_LIPASYNC (1 << 1) 324 #define IFCOPT1_LIPF8 (1 << 0) 325 326 #define IFCOPT2_LOOPBACK (1 << 1) 327 #define IFCOPT2_ATIO3_ONLY (1 << 0) 328 329 #define IFCOPT3_NOPRLI (1 << 4) /* disable automatic sending of PRLI on local loops */ 330 #define IFCOPT3_RNDASYNC (1 << 1) 331 332 /* 333 * All IOCB Queue entries are this size 334 */ 335 #define QENTRY_LEN 64 336 337 /* 338 * Command Structure Definitions 339 */ 340 341 typedef struct { 342 uint32_t ds_base; 343 uint32_t ds_basehi; 344 uint32_t ds_count; 345 } ispds64_t; 346 347 typedef struct { 348 uint8_t rqs_entry_type; 349 uint8_t rqs_entry_count; 350 uint8_t rqs_seqno; 351 uint8_t rqs_flags; 352 } isphdr_t; 353 354 /* RQS Flag definitions */ 355 #define RQSFLAG_CONTINUATION 0x01 356 #define RQSFLAG_FULL 0x02 357 #define RQSFLAG_BADHEADER 0x04 358 #define RQSFLAG_BADPACKET 0x08 359 #define RQSFLAG_BADCOUNT 0x10 360 #define RQSFLAG_BADORDER 0x20 361 #define RQSFLAG_MASK 0x3f 362 363 /* RQS entry_type definitions */ 364 #define RQSTYPE_REQUEST 0x01 365 #define RQSTYPE_DATASEG 0x02 366 #define RQSTYPE_RESPONSE 0x03 367 #define RQSTYPE_MARKER 0x04 368 #define RQSTYPE_CMDONLY 0x05 369 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 370 #define RQSTYPE_CTIO 0x07 /* Target Mode */ 371 #define RQSTYPE_SCAM 0x08 372 #define RQSTYPE_A64 0x09 373 #define RQSTYPE_A64_CONT 0x0a 374 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 375 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 376 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 377 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 378 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 379 #define RQSTYPE_STATUS_CONT 0x10 380 #define RQSTYPE_T2RQS 0x11 381 #define RQSTYPE_CTIO7 0x12 382 #define RQSTYPE_IP_XMIT 0x13 383 #define RQSTYPE_TSK_MGMT 0x14 384 #define RQSTYPE_T4RQS 0x15 385 #define RQSTYPE_ATIO2 0x16 /* Target Mode */ 386 #define RQSTYPE_CTIO2 0x17 /* Target Mode */ 387 #define RQSTYPE_T7RQS 0x18 388 #define RQSTYPE_T3RQS 0x19 389 #define RQSTYPE_IP_XMIT_64 0x1b 390 #define RQSTYPE_CTIO4 0x1e /* Target Mode */ 391 #define RQSTYPE_CTIO3 0x1f /* Target Mode */ 392 #define RQSTYPE_RIO1 0x21 393 #define RQSTYPE_RIO2 0x22 394 #define RQSTYPE_IP_RECV 0x23 395 #define RQSTYPE_IP_RECV_CONT 0x24 396 #define RQSTYPE_CT_PASSTHRU 0x29 397 #define RQSTYPE_MS_PASSTHRU 0x29 398 #define RQSTYPE_VP_CTRL 0x30 /* 24XX only */ 399 #define RQSTYPE_VP_MODIFY 0x31 /* 24XX only */ 400 #define RQSTYPE_RPT_ID_ACQ 0x32 /* 24XX only */ 401 #define RQSTYPE_ABORT_IO 0x33 402 #define RQSTYPE_T6RQS 0x48 403 #define RQSTYPE_LOGIN 0x52 404 #define RQSTYPE_ABTS_RCVD 0x54 /* 24XX only */ 405 #define RQSTYPE_ABTS_RSP 0x55 /* 24XX only */ 406 407 typedef struct { 408 isphdr_t mrk_header; 409 uint32_t mrk_handle; 410 uint16_t mrk_nphdl; 411 uint8_t mrk_modifier; 412 uint8_t mrk_reserved0; 413 uint8_t mrk_reserved1; 414 uint8_t mrk_vphdl; 415 uint16_t mrk_reserved2; 416 uint8_t mrk_lun[8]; 417 uint8_t mrk_reserved3[40]; 418 } isp_marker_24xx_t; 419 420 #define SYNC_DEVICE 0 421 #define SYNC_TARGET 1 422 #define SYNC_ALL 2 423 #define SYNC_LIP 3 424 425 /* 426 * ISP24XX structures 427 */ 428 typedef struct { 429 isphdr_t req_header; 430 uint32_t req_handle; 431 uint16_t req_nphdl; 432 uint16_t req_time; 433 uint16_t req_seg_count; 434 uint16_t req_reserved; 435 uint8_t req_lun[8]; 436 uint8_t req_alen_datadir; 437 uint8_t req_task_management; 438 uint8_t req_task_attribute; 439 uint8_t req_crn; 440 uint8_t req_cdb[16]; 441 uint32_t req_dl; 442 uint16_t req_tidlo; 443 uint8_t req_tidhi; 444 uint8_t req_vpidx; 445 ispds64_t req_dataseg; 446 } ispreqt7_t; 447 448 /* Task Management Request Function */ 449 typedef struct { 450 isphdr_t tmf_header; 451 uint32_t tmf_handle; 452 uint16_t tmf_nphdl; 453 uint8_t tmf_reserved0[2]; 454 uint16_t tmf_delay; 455 uint16_t tmf_timeout; 456 uint8_t tmf_lun[8]; 457 uint32_t tmf_flags; 458 uint8_t tmf_reserved1[20]; 459 uint16_t tmf_tidlo; 460 uint8_t tmf_tidhi; 461 uint8_t tmf_vpidx; 462 uint8_t tmf_reserved2[12]; 463 } isp24xx_tmf_t; 464 465 #define ISP24XX_TMF_NOSEND 0x80000000 466 467 #define ISP24XX_TMF_LUN_RESET 0x00000010 468 #define ISP24XX_TMF_ABORT_TASK_SET 0x00000008 469 #define ISP24XX_TMF_CLEAR_TASK_SET 0x00000004 470 #define ISP24XX_TMF_TARGET_RESET 0x00000002 471 #define ISP24XX_TMF_CLEAR_ACA 0x00000001 472 473 /* I/O Abort Structure */ 474 typedef struct { 475 isphdr_t abrt_header; 476 uint32_t abrt_handle; 477 uint16_t abrt_nphdl; 478 uint16_t abrt_options; 479 uint32_t abrt_cmd_handle; 480 uint16_t abrt_queue_number; 481 uint8_t abrt_reserved[30]; 482 uint16_t abrt_tidlo; 483 uint8_t abrt_tidhi; 484 uint8_t abrt_vpidx; 485 uint8_t abrt_reserved1[12]; 486 } isp24xx_abrt_t; 487 488 #define ISP24XX_ABRT_NOSEND 0x01 /* don't actually send ABTS */ 489 #define ISP24XX_ABRT_OKAY 0x00 /* in nphdl on return */ 490 #define ISP24XX_ABRT_ENXIO 0x31 /* in nphdl on return */ 491 492 #define ISP_CDSEG64 5 493 typedef struct { 494 isphdr_t req_header; 495 ispds64_t req_dataseg[ISP_CDSEG64]; 496 } ispcontreq64_t; 497 498 /* 499 * Status Continuation 500 */ 501 typedef struct { 502 isphdr_t req_header; 503 uint8_t req_sense_data[60]; 504 } ispstatus_cont_t; 505 506 /* 507 * 24XX Type 0 status 508 */ 509 typedef struct { 510 isphdr_t req_header; 511 uint32_t req_handle; 512 uint16_t req_completion_status; 513 uint16_t req_oxid; 514 uint32_t req_resid; 515 uint16_t req_reserved0; 516 uint16_t req_state_flags; 517 uint16_t req_retry_delay; /* aka Status Qualifier */ 518 uint16_t req_scsi_status; 519 uint32_t req_fcp_residual; 520 uint32_t req_sense_len; 521 uint32_t req_response_len; 522 uint8_t req_rsp_sense[28]; 523 } isp24xx_statusreq_t; 524 525 /* 526 * For Qlogic 2X00, the high order byte of SCSI status has 527 * additional meaning. 528 */ 529 #define RQCS_CR 0x1000 /* Confirmation Request */ 530 #define RQCS_RU 0x0800 /* Residual Under */ 531 #define RQCS_RO 0x0400 /* Residual Over */ 532 #define RQCS_RESID (RQCS_RU|RQCS_RO) 533 #define RQCS_SV 0x0200 /* Sense Length Valid */ 534 #define RQCS_RV 0x0100 /* FCP Response Length Valid */ 535 536 /* 537 * CT Passthru IOCB 538 */ 539 typedef struct { 540 isphdr_t ctp_header; 541 uint32_t ctp_handle; 542 uint16_t ctp_status; 543 uint16_t ctp_nphdl; /* n-port handle */ 544 uint16_t ctp_cmd_cnt; /* Command DSD count */ 545 uint8_t ctp_vpidx; 546 uint8_t ctp_reserved0; 547 uint16_t ctp_time; 548 uint16_t ctp_reserved1; 549 uint16_t ctp_rsp_cnt; /* Response DSD count */ 550 uint16_t ctp_reserved2[5]; 551 uint32_t ctp_rsp_bcnt; /* Response byte count */ 552 uint32_t ctp_cmd_bcnt; /* Command byte count */ 553 ispds64_t ctp_dataseg[2]; 554 } isp_ct_pt_t; 555 556 /* 557 * Completion Status Codes. 558 */ 559 #define RQCS_COMPLETE 0x0000 560 #define RQCS_DMA_ERROR 0x0002 561 #define RQCS_RESET_OCCURRED 0x0004 562 #define RQCS_ABORTED 0x0005 563 #define RQCS_TIMEOUT 0x0006 564 #define RQCS_DATA_OVERRUN 0x0007 565 #define RQCS_DATA_UNDERRUN 0x0015 566 #define RQCS_QUEUE_FULL 0x001C 567 568 /* 1X00 Only Completion Codes */ 569 #define RQCS_INCOMPLETE 0x0001 570 #define RQCS_TRANSPORT_ERROR 0x0003 571 #define RQCS_COMMAND_OVERRUN 0x0008 572 #define RQCS_STATUS_OVERRUN 0x0009 573 #define RQCS_BAD_MESSAGE 0x000a 574 #define RQCS_NO_MESSAGE_OUT 0x000b 575 #define RQCS_EXT_ID_FAILED 0x000c 576 #define RQCS_IDE_MSG_FAILED 0x000d 577 #define RQCS_ABORT_MSG_FAILED 0x000e 578 #define RQCS_REJECT_MSG_FAILED 0x000f 579 #define RQCS_NOP_MSG_FAILED 0x0010 580 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 581 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 582 #define RQCS_ID_MSG_FAILED 0x0013 583 #define RQCS_UNEXP_BUS_FREE 0x0014 584 #define RQCS_XACT_ERR1 0x0018 585 #define RQCS_XACT_ERR2 0x0019 586 #define RQCS_XACT_ERR3 0x001A 587 #define RQCS_BAD_ENTRY 0x001B 588 #define RQCS_PHASE_SKIPPED 0x001D 589 #define RQCS_ARQS_FAILED 0x001E 590 #define RQCS_WIDE_FAILED 0x001F 591 #define RQCS_SYNCXFER_FAILED 0x0020 592 #define RQCS_LVD_BUSERR 0x0021 593 594 /* 2X00 Only Completion Codes */ 595 #define RQCS_PORT_UNAVAILABLE 0x0028 596 #define RQCS_PORT_LOGGED_OUT 0x0029 597 #define RQCS_PORT_CHANGED 0x002A 598 #define RQCS_PORT_BUSY 0x002B 599 600 /* 24XX Only Completion Codes */ 601 #define RQCS_24XX_DRE 0x0011 /* data reassembly error */ 602 #define RQCS_24XX_TABORT 0x0013 /* aborted by target */ 603 #define RQCS_24XX_ENOMEM 0x002C /* f/w resource unavailable */ 604 #define RQCS_24XX_TMO 0x0030 /* task management overrun */ 605 606 607 /* 608 * 1X00 specific State Flags 609 */ 610 #define RQSF_GOT_BUS 0x0100 611 #define RQSF_GOT_TARGET 0x0200 612 #define RQSF_SENT_CDB 0x0400 613 #define RQSF_XFRD_DATA 0x0800 614 #define RQSF_GOT_STATUS 0x1000 615 #define RQSF_GOT_SENSE 0x2000 616 #define RQSF_XFER_COMPLETE 0x4000 617 618 /* 619 * 2X00 specific State Flags 620 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available) 621 */ 622 #define RQSF_DATA_IN 0x0020 623 #define RQSF_DATA_OUT 0x0040 624 #define RQSF_STAG 0x0008 625 #define RQSF_OTAG 0x0004 626 #define RQSF_HTAG 0x0002 627 /* 628 * 1X00 Status Flags 629 */ 630 #define RQSTF_DISCONNECT 0x0001 631 #define RQSTF_SYNCHRONOUS 0x0002 632 #define RQSTF_PARITY_ERROR 0x0004 633 #define RQSTF_BUS_RESET 0x0008 634 #define RQSTF_DEVICE_RESET 0x0010 635 #define RQSTF_ABORTED 0x0020 636 #define RQSTF_TIMEOUT 0x0040 637 #define RQSTF_NEGOTIATION 0x0080 638 639 /* 640 * 2X00 specific state flags 641 */ 642 /* RQSF_SENT_CDB */ 643 /* RQSF_XFRD_DATA */ 644 /* RQSF_GOT_STATUS */ 645 /* RQSF_XFER_COMPLETE */ 646 647 /* 648 * 2X00 specific status flags 649 */ 650 /* RQSTF_ABORTED */ 651 /* RQSTF_TIMEOUT */ 652 #define RQSTF_DMA_ERROR 0x0080 653 #define RQSTF_LOGOUT 0x2000 654 655 /* 656 * About Firmware returns an 'attribute' word. 657 */ 658 #define ISP2400_FW_ATTR_CLASS2 0x0001 659 #define ISP2400_FW_ATTR_IP 0x0002 660 #define ISP2400_FW_ATTR_MULTIID 0x0004 661 #define ISP2400_FW_ATTR_SB2 0x0008 662 #define ISP2400_FW_ATTR_T10CRC 0x0010 663 #define ISP2400_FW_ATTR_VI 0x0020 664 #define ISP2400_FW_ATTR_MQ 0x0040 665 #define ISP2400_FW_ATTR_MSIX 0x0080 666 #define ISP2400_FW_ATTR_FCOE 0x0800 667 #define ISP2400_FW_ATTR_VP0 0x1000 668 #define ISP2400_FW_ATTR_EXPFW 0x2000 669 #define ISP2400_FW_ATTR_HOTFW 0x4000 670 #define ISP2400_FW_ATTR_EXTNDED 0x8000 671 #define ISP2400_FW_ATTR_EXTVP 0x00010000 672 #define ISP2400_FW_ATTR_VN2VN 0x00040000 673 #define ISP2400_FW_ATTR_EXMOFF 0x00080000 674 #define ISP2400_FW_ATTR_NPMOFF 0x00100000 675 #define ISP2400_FW_ATTR_DIFCHOP 0x00400000 676 #define ISP2400_FW_ATTR_SRIOV 0x02000000 677 #define ISP2400_FW_ATTR_ASICTMP 0x0200000000 678 #define ISP2400_FW_ATTR_ATIOMQ 0x0400000000 679 680 /* 681 * This is only true for 24XX cards with this f/w attribute 682 */ 683 #define ISP_CAP_MULTI_ID(isp) \ 684 (isp->isp_fwattr & ISP2400_FW_ATTR_MULTIID) 685 #define ISP_GET_VPIDX(isp, tag) \ 686 (ISP_CAP_MULTI_ID(isp) ? tag : 0) 687 #define ISP_CAP_MSIX(isp) \ 688 (isp->isp_fwattr & ISP2400_FW_ATTR_MSIX) 689 #define ISP_CAP_VP0(isp) \ 690 (isp->isp_fwattr & ISP2400_FW_ATTR_VP0) 691 692 #define ISP_FCTAPE_ENABLED(isp, chan) \ 693 ((FCPARAM(isp, chan)->isp_xfwoptions & ICB2400_OPT2_FCTAPE) != 0) 694 695 /* 696 * FC specific data structures 697 */ 698 699 /* 700 * Initialization Control Block 701 */ 702 703 #define ICB_VERSION1 1 704 705 /* 2400 F/W options */ 706 #define ICB2400_OPT1_BOTH_WWNS 0x00004000 707 #define ICB2400_OPT1_FULL_LOGIN 0x00002000 708 #define ICB2400_OPT1_PREV_ADDRESS 0x00000800 709 #define ICB2400_OPT1_SRCHDOWN 0x00000400 710 #define ICB2400_OPT1_NOLIP 0x00000200 711 #define ICB2400_OPT1_INI_DISABLE 0x00000020 712 #define ICB2400_OPT1_TGT_ENABLE 0x00000010 713 #define ICB2400_OPT1_FULL_DUPLEX 0x00000004 714 #define ICB2400_OPT1_FAIRNESS 0x00000002 715 #define ICB2400_OPT1_HARD_ADDRESS 0x00000001 716 717 #define ICB2400_OPT2_ENA_ATIOMQ 0x08000000 718 #define ICB2400_OPT2_ENA_IHA 0x04000000 719 #define ICB2400_OPT2_QOS 0x02000000 720 #define ICB2400_OPT2_IOCBS 0x01000000 721 #define ICB2400_OPT2_ENA_IHR 0x00400000 722 #define ICB2400_OPT2_ENA_VMS 0x00200000 723 #define ICB2400_OPT2_ENA_TA 0x00100000 724 #define ICB2400_OPT2_TPRLIC 0x00004000 725 #define ICB2400_OPT2_FCTAPE 0x00001000 726 #define ICB2400_OPT2_FCSP 0x00000800 727 #define ICB2400_OPT2_CLASS2_ACK0 0x00000200 728 #define ICB2400_OPT2_CLASS2 0x00000100 729 #define ICB2400_OPT2_NO_PLAY 0x00000080 730 #define ICB2400_OPT2_TOPO_MASK 0x00000070 731 #define ICB2400_OPT2_LOOP_ONLY 0x00000000 732 #define ICB2400_OPT2_PTP_ONLY 0x00000010 733 #define ICB2400_OPT2_LOOP_2_PTP 0x00000020 734 #define ICB2400_OPT2_TIMER_MASK 0x0000000f 735 #define ICB2400_OPT2_ZIO 0x00000005 736 #define ICB2400_OPT2_ZIO1 0x00000006 737 738 #define ICB2400_OPT3_NO_CTXDIS 0x40000000 739 #define ICB2400_OPT3_ENA_ETH_RESP 0x08000000 740 #define ICB2400_OPT3_ENA_ETH_ATIO 0x04000000 741 #define ICB2400_OPT3_ENA_MFCF 0x00020000 742 #define ICB2400_OPT3_SKIP_4GB 0x00010000 743 #define ICB2400_OPT3_RATE_MASK 0x0000E000 744 #define ICB2400_OPT3_RATE_1GB 0x00000000 745 #define ICB2400_OPT3_RATE_2GB 0x00002000 746 #define ICB2400_OPT3_RATE_AUTO 0x00004000 747 #define ICB2400_OPT3_RATE_4GB 0x00006000 748 #define ICB2400_OPT3_RATE_8GB 0x00008000 749 #define ICB2400_OPT3_RATE_16GB 0x0000A000 750 #define ICB2400_OPT3_RATE_32GB 0x0000C000 751 #define ICB2400_OPT3_ENA_OOF_XFRDY 0x00000200 752 #define ICB2400_OPT3_NO_N2N_LOGI 0x00000100 753 #define ICB2400_OPT3_NO_LOCAL_PLOGI 0x00000080 754 #define ICB2400_OPT3_ENA_OOF 0x00000040 755 /* note that a response size flag of zero is reserved! */ 756 #define ICB2400_OPT3_RSPSZ_MASK 0x00000030 757 #define ICB2400_OPT3_RSPSZ_12 0x00000010 758 #define ICB2400_OPT3_RSPSZ_24 0x00000020 759 #define ICB2400_OPT3_RSPSZ_32 0x00000030 760 #define ICB2400_OPT3_SOFTID 0x00000002 761 762 #define ICB_MIN_FRMLEN 256 763 #define ICB_MAX_FRMLEN 2112 764 #define ICB_DFLT_FRMLEN 1024 765 #define ICB_DFLT_RDELAY 5 766 #define ICB_DFLT_RCOUNT 3 767 768 #define ICB_LOGIN_TOV 10 769 #define ICB_LUN_ENABLE_TOV 15 770 771 772 /* 773 * And somebody at QLogic had a great idea that you could just change 774 * the structure *and* keep the version number the same as the other cards. 775 */ 776 typedef struct { 777 uint16_t icb_version; 778 uint16_t icb_reserved0; 779 uint16_t icb_maxfrmlen; 780 uint16_t icb_execthrottle; 781 uint16_t icb_xchgcnt; 782 uint16_t icb_hardaddr; 783 uint8_t icb_portname[8]; 784 uint8_t icb_nodename[8]; 785 uint16_t icb_rspnsin; 786 uint16_t icb_rqstout; 787 uint16_t icb_retry_count; 788 uint16_t icb_priout; 789 uint16_t icb_rsltqlen; 790 uint16_t icb_rqstqlen; 791 uint16_t icb_ldn_nols; 792 uint16_t icb_prqstqlen; 793 uint16_t icb_rqstaddr[4]; 794 uint16_t icb_respaddr[4]; 795 uint16_t icb_priaddr[4]; 796 uint16_t icb_msixresp; 797 uint16_t icb_msixatio; 798 uint16_t icb_reserved1[2]; 799 uint16_t icb_atio_in; 800 uint16_t icb_atioqlen; 801 uint16_t icb_atioqaddr[4]; 802 uint16_t icb_idelaytimer; 803 uint16_t icb_logintime; 804 uint32_t icb_fwoptions1; 805 uint32_t icb_fwoptions2; 806 uint32_t icb_fwoptions3; 807 uint16_t icb_qos; 808 uint16_t icb_reserved2[3]; 809 uint16_t icb_enodemac[3]; 810 uint16_t icb_disctime; 811 uint16_t icb_reserved3[4]; 812 } isp_icb_2400_t; 813 814 #define RQRSP_ADDR0015 0 815 #define RQRSP_ADDR1631 1 816 #define RQRSP_ADDR3247 2 817 #define RQRSP_ADDR4863 3 818 819 820 #define ICB_NNM0 7 821 #define ICB_NNM1 6 822 #define ICB_NNM2 5 823 #define ICB_NNM3 4 824 #define ICB_NNM4 3 825 #define ICB_NNM5 2 826 #define ICB_NNM6 1 827 #define ICB_NNM7 0 828 829 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 830 array[ICB_NNM0] = (uint8_t) ((wwn >> 0) & 0xff), \ 831 array[ICB_NNM1] = (uint8_t) ((wwn >> 8) & 0xff), \ 832 array[ICB_NNM2] = (uint8_t) ((wwn >> 16) & 0xff), \ 833 array[ICB_NNM3] = (uint8_t) ((wwn >> 24) & 0xff), \ 834 array[ICB_NNM4] = (uint8_t) ((wwn >> 32) & 0xff), \ 835 array[ICB_NNM5] = (uint8_t) ((wwn >> 40) & 0xff), \ 836 array[ICB_NNM6] = (uint8_t) ((wwn >> 48) & 0xff), \ 837 array[ICB_NNM7] = (uint8_t) ((wwn >> 56) & 0xff) 838 839 #define MAKE_WWN_FROM_NODE_NAME(wwn, array) \ 840 wwn = ((uint64_t) array[ICB_NNM0]) | \ 841 ((uint64_t) array[ICB_NNM1] << 8) | \ 842 ((uint64_t) array[ICB_NNM2] << 16) | \ 843 ((uint64_t) array[ICB_NNM3] << 24) | \ 844 ((uint64_t) array[ICB_NNM4] << 32) | \ 845 ((uint64_t) array[ICB_NNM5] << 40) | \ 846 ((uint64_t) array[ICB_NNM6] << 48) | \ 847 ((uint64_t) array[ICB_NNM7] << 56) 848 849 850 /* 851 * For MULTI_ID firmware, this describes a 852 * virtual port entity for getting status. 853 */ 854 typedef struct { 855 uint16_t vp_port_status; 856 uint8_t vp_port_options; 857 uint8_t vp_port_loopid; 858 uint8_t vp_port_portname[8]; 859 uint8_t vp_port_nodename[8]; 860 uint16_t vp_port_portid_lo; /* not present when trailing icb */ 861 uint16_t vp_port_portid_hi; /* not present when trailing icb */ 862 } vp_port_info_t; 863 864 #define ICB2400_VPOPT_ENA_SNSLOGIN 0x00000040 /* Enable SNS Login and SCR for Virtual Ports */ 865 #define ICB2400_VPOPT_TGT_DISABLE 0x00000020 /* Target Mode Disabled */ 866 #define ICB2400_VPOPT_INI_ENABLE 0x00000010 /* Initiator Mode Enabled */ 867 #define ICB2400_VPOPT_ENABLED 0x00000008 /* VP Enabled */ 868 #define ICB2400_VPOPT_NOPLAY 0x00000004 /* ID Not Acquired */ 869 #define ICB2400_VPOPT_PREV_ADDRESS 0x00000002 /* Previously Assigned ID */ 870 #define ICB2400_VPOPT_HARD_ADDRESS 0x00000001 /* Hard Assigned ID */ 871 872 #define ICB2400_VPOPT_WRITE_SIZE 20 873 874 /* 875 * For MULTI_ID firmware, we append this structure 876 * to the isp_icb_2400_t above, followed by a list 877 * structures that are *most* of the vp_port_info_t. 878 */ 879 typedef struct { 880 uint16_t vp_count; 881 uint16_t vp_global_options; 882 } isp_icb_2400_vpinfo_t; 883 884 #define ICB2400_VPINFO_OFF 0x80 /* offset from start of ICB */ 885 #define ICB2400_VPINFO_PORT_OFF(chan) \ 886 (ICB2400_VPINFO_OFF + \ 887 sizeof (isp_icb_2400_vpinfo_t) + ((chan) * ICB2400_VPOPT_WRITE_SIZE)) 888 889 #define ICB2400_VPGOPT_FCA 0x01 /* Assume Clean Address bit in FLOGI ACC set (works only in static configurations) */ 890 #define ICB2400_VPGOPT_MID_DISABLE 0x02 /* when set, connection mode2 will work with NPIV-capable switched */ 891 #define ICB2400_VPGOPT_VP0_DECOUPLE 0x04 /* Allow VP0 decoupling if firmware supports it */ 892 #define ICB2400_VPGOPT_SUSP_FDISK 0x10 /* Suspend FDISC for Enabled VPs */ 893 #define ICB2400_VPGOPT_GEN_RIDA 0x20 /* Generate RIDA if FLOGI Fails */ 894 895 typedef struct { 896 isphdr_t vp_ctrl_hdr; 897 uint32_t vp_ctrl_handle; 898 uint16_t vp_ctrl_index_fail; 899 uint16_t vp_ctrl_status; 900 uint16_t vp_ctrl_command; 901 uint16_t vp_ctrl_vp_count; 902 uint16_t vp_ctrl_idmap[16]; 903 uint16_t vp_ctrl_reserved[7]; 904 uint16_t vp_ctrl_fcf_index; 905 } vp_ctrl_info_t; 906 907 #define VP_CTRL_CMD_ENABLE_VP 0x00 908 #define VP_CTRL_CMD_DISABLE_VP 0x08 909 #define VP_CTRL_CMD_DISABLE_VP_REINIT_LINK 0x09 910 #define VP_CTRL_CMD_DISABLE_VP_LOGO 0x0A 911 #define VP_CTRL_CMD_DISABLE_VP_LOGO_ALL 0x0B 912 913 /* 914 * We can use this structure for modifying either one or two VP ports after initialization 915 */ 916 typedef struct { 917 isphdr_t vp_mod_hdr; 918 uint32_t vp_mod_hdl; 919 uint16_t vp_mod_reserved0; 920 uint16_t vp_mod_status; 921 uint8_t vp_mod_cmd; 922 uint8_t vp_mod_cnt; 923 uint8_t vp_mod_idx0; 924 uint8_t vp_mod_idx1; 925 struct { 926 uint8_t options; 927 uint8_t loopid; 928 uint16_t reserved1; 929 uint8_t wwpn[8]; 930 uint8_t wwnn[8]; 931 } vp_mod_ports[2]; 932 uint8_t vp_mod_reserved2[8]; 933 } vp_modify_t; 934 935 #define VP_STS_OK 0x00 936 #define VP_STS_ERR 0x01 937 #define VP_CNT_ERR 0x02 938 #define VP_GEN_ERR 0x03 939 #define VP_IDX_ERR 0x04 940 #define VP_STS_BSY 0x05 941 942 #define VP_MODIFY 0x00 943 #define VP_MODIFY_ENA 0x01 944 #define VP_MODIFY_OPT 0x02 945 #define VP_RESUME 0x03 946 947 /* 948 * Port Data Base Element 949 */ 950 951 #define SVC3_ROLE_MASK 0x30 952 #define SVC3_ROLE_SHIFT 4 953 954 #define BITS2WORD_24XX(x) ((x)[0] << 16 | (x)[1] << 8 | (x)[2]) 955 956 /* 957 * Port Data Base Element- 24XX cards 958 */ 959 typedef struct { 960 uint16_t pdb_flags; 961 uint8_t pdb_curstate; 962 uint8_t pdb_laststate; 963 uint8_t pdb_hardaddr_bits[4]; 964 uint8_t pdb_portid_bits[4]; 965 #define pdb_nxt_seqid_2400 pdb_portid_bits[3] 966 uint16_t pdb_retry_timer; 967 uint16_t pdb_handle; 968 uint16_t pdb_rcv_dsize; 969 uint16_t pdb_reserved0; 970 uint16_t pdb_prli_svc0; 971 uint16_t pdb_prli_svc3; 972 uint8_t pdb_portname[8]; 973 uint8_t pdb_nodename[8]; 974 uint8_t pdb_reserved1[24]; 975 } isp_pdb_24xx_t; 976 977 #define PDB2400_TID_SUPPORTED 0x4000 978 #define PDB2400_FC_TAPE 0x0080 979 #define PDB2400_CLASS2_ACK0 0x0040 980 #define PDB2400_FCP_CONF 0x0020 981 #define PDB2400_CLASS2 0x0010 982 #define PDB2400_ADDR_VALID 0x0002 983 984 #define PDB2400_STATE_PLOGI_PEND 0x03 985 #define PDB2400_STATE_PLOGI_DONE 0x04 986 #define PDB2400_STATE_PRLI_PEND 0x05 987 #define PDB2400_STATE_LOGGED_IN 0x06 988 #define PDB2400_STATE_PORT_UNAVAIL 0x07 989 #define PDB2400_STATE_PRLO_PEND 0x09 990 #define PDB2400_STATE_LOGO_PEND 0x0B 991 992 /* 993 * Common elements from the above two structures that are actually useful to us. 994 */ 995 typedef struct { 996 uint16_t handle; 997 uint16_t prli_word0; 998 uint16_t prli_word3; 999 uint32_t : 8, 1000 portid : 24; 1001 uint8_t portname[8]; 1002 uint8_t nodename[8]; 1003 } isp_pdb_t; 1004 1005 /* 1006 * Port and N-Port Handle List Element 1007 */ 1008 typedef struct { 1009 uint16_t pnhle_port_id_lo; 1010 uint16_t pnhle_port_id_hi; 1011 uint16_t pnhle_handle; 1012 uint16_t pnhle_reserved; 1013 } isp_pnhle_24xx_t; 1014 1015 /* 1016 * Port Database Changed Async Event information for 24XX cards 1017 */ 1018 /* N-Port Handle */ 1019 #define PDB24XX_AE_GLOBAL 0xFFFF 1020 1021 /* Reason Codes */ 1022 #define PDB24XX_AE_OK 0x00 1023 #define PDB24XX_AE_IMPL_LOGO_1 0x01 1024 #define PDB24XX_AE_IMPL_LOGO_2 0x02 1025 #define PDB24XX_AE_IMPL_LOGO_3 0x03 1026 #define PDB24XX_AE_PLOGI_RCVD 0x04 1027 #define PDB24XX_AE_PLOGI_RJT 0x05 1028 #define PDB24XX_AE_PRLI_RCVD 0x06 1029 #define PDB24XX_AE_PRLI_RJT 0x07 1030 #define PDB24XX_AE_TPRLO 0x08 1031 #define PDB24XX_AE_TPRLO_RJT 0x09 1032 #define PDB24XX_AE_PRLO_RCVD 0x0a 1033 #define PDB24XX_AE_LOGO_RCVD 0x0b 1034 #define PDB24XX_AE_TOPO_CHG 0x0c 1035 #define PDB24XX_AE_NPORT_CHG 0x0d 1036 #define PDB24XX_AE_FLOGI_RJT 0x0e 1037 #define PDB24XX_AE_BAD_FANN 0x0f 1038 #define PDB24XX_AE_FLOGI_TIMO 0x10 1039 #define PDB24XX_AE_ABX_LOGO 0x11 1040 #define PDB24XX_AE_PLOGI_DONE 0x12 1041 #define PDB24XX_AE_PRLI_DONE 0x13 1042 #define PDB24XX_AE_OPN_1 0x14 1043 #define PDB24XX_AE_OPN_2 0x15 1044 #define PDB24XX_AE_TXERR 0x16 1045 #define PDB24XX_AE_FORCED_LOGO 0x17 1046 #define PDB24XX_AE_DISC_TIMO 0x18 1047 1048 /* 1049 * Genericized Port Login/Logout software structure 1050 */ 1051 typedef struct { 1052 uint16_t handle; 1053 uint16_t channel; 1054 uint32_t 1055 flags : 8, 1056 portid : 24; 1057 } isp_plcmd_t; 1058 /* the flags to use are those for PLOGX_FLG_* below */ 1059 1060 /* 1061 * ISP24XX- Login/Logout Port IOCB 1062 */ 1063 typedef struct { 1064 isphdr_t plogx_header; 1065 uint32_t plogx_handle; 1066 uint16_t plogx_status; 1067 uint16_t plogx_nphdl; 1068 uint16_t plogx_flags; 1069 uint16_t plogx_vphdl; /* low 8 bits */ 1070 uint16_t plogx_portlo; /* low 16 bits */ 1071 uint16_t plogx_rspsz_porthi; 1072 struct { 1073 uint16_t lo16; 1074 uint16_t hi16; 1075 } plogx_ioparm[11]; 1076 } isp_plogx_t; 1077 1078 #define PLOGX_STATUS_OK 0x00 1079 #define PLOGX_STATUS_UNAVAIL 0x28 1080 #define PLOGX_STATUS_LOGOUT 0x29 1081 #define PLOGX_STATUS_IOCBERR 0x31 1082 1083 #define PLOGX_IOCBERR_NOLINK 0x01 1084 #define PLOGX_IOCBERR_NOIOCB 0x02 1085 #define PLOGX_IOCBERR_NOXGHG 0x03 1086 #define PLOGX_IOCBERR_FAILED 0x04 /* further info in IOPARM 1 */ 1087 #define PLOGX_IOCBERR_NOFABRIC 0x05 1088 #define PLOGX_IOCBERR_NOTREADY 0x07 1089 #define PLOGX_IOCBERR_NOLOGIN 0x09 /* further info in IOPARM 1 */ 1090 #define PLOGX_IOCBERR_NOPCB 0x0a 1091 #define PLOGX_IOCBERR_REJECT 0x18 /* further info in IOPARM 1 */ 1092 #define PLOGX_IOCBERR_EINVAL 0x19 /* further info in IOPARM 1 */ 1093 #define PLOGX_IOCBERR_PORTUSED 0x1a /* further info in IOPARM 1 */ 1094 #define PLOGX_IOCBERR_HNDLUSED 0x1b /* further info in IOPARM 1 */ 1095 #define PLOGX_IOCBERR_NOHANDLE 0x1c 1096 #define PLOGX_IOCBERR_NOFLOGI 0x1f /* further info in IOPARM 1 */ 1097 1098 #define PLOGX_FLG_CMD_MASK 0xf 1099 #define PLOGX_FLG_CMD_PLOGI 0 1100 #define PLOGX_FLG_CMD_PRLI 1 1101 #define PLOGX_FLG_CMD_PDISC 2 1102 #define PLOGX_FLG_CMD_LOGO 8 1103 #define PLOGX_FLG_CMD_PRLO 9 1104 #define PLOGX_FLG_CMD_TPRLO 10 1105 1106 #define PLOGX_FLG_COND_PLOGI 0x10 /* if with PLOGI */ 1107 #define PLOGX_FLG_IMPLICIT 0x10 /* if with LOGO, PRLO, TPRLO */ 1108 #define PLOGX_FLG_SKIP_PRLI 0x20 /* if with PLOGI */ 1109 #define PLOGX_FLG_IMPLICIT_LOGO_ALL 0x20 /* if with LOGO */ 1110 #define PLOGX_FLG_EXPLICIT_LOGO 0x40 /* if with LOGO */ 1111 #define PLOGX_FLG_COMMON_FEATURES 0x80 /* if with PLOGI */ 1112 #define PLOGX_FLG_FREE_NPHDL 0x80 /* if with with LOGO */ 1113 1114 #define PLOGX_FLG_CLASS2 0x100 /* if with PLOGI */ 1115 #define PLOGX_FLG_FCP2_OVERRIDE 0x200 /* if with PRLOG, PRLI */ 1116 1117 /* 1118 * Report ID Acquisistion (24XX multi-id firmware) 1119 */ 1120 typedef struct { 1121 isphdr_t ridacq_hdr; 1122 uint32_t ridacq_handle; 1123 uint8_t ridacq_vp_acquired; 1124 uint8_t ridacq_vp_setup; 1125 uint8_t ridacq_vp_index; 1126 uint8_t ridacq_vp_status; 1127 uint16_t ridacq_vp_port_lo; 1128 uint8_t ridacq_vp_port_hi; 1129 uint8_t ridacq_format; /* 0 or 1 */ 1130 uint16_t ridacq_map[8]; 1131 uint8_t ridacq_reserved1[32]; 1132 } isp_ridacq_t; 1133 1134 #define RIDACQ_STS_COMPLETE 0 1135 #define RIDACQ_STS_UNACQUIRED 1 1136 #define RIDACQ_STS_CHANGED 2 1137 #define RIDACQ_STS_SNS_TIMEOUT 3 1138 #define RIDACQ_STS_SNS_REJECTED 4 1139 #define RIDACQ_STS_SCR_TIMEOUT 5 1140 #define RIDACQ_STS_SCR_REJECTED 6 1141 1142 /* 1143 * Simple Name Server Data Structures 1144 */ 1145 #define SNS_GA_NXT 0x100 1146 #define SNS_GPN_ID 0x112 1147 #define SNS_GNN_ID 0x113 1148 #define SNS_GFT_ID 0x117 1149 #define SNS_GFF_ID 0x11F 1150 #define SNS_GID_FT 0x171 1151 #define SNS_GID_PT 0x1A1 1152 #define SNS_RFT_ID 0x217 1153 #define SNS_RSPN_ID 0x218 1154 #define SNS_RFF_ID 0x21F 1155 #define SNS_RSNN_NN 0x239 1156 typedef struct { 1157 uint16_t snscb_rblen; /* response buffer length (words) */ 1158 uint16_t snscb_reserved0; 1159 uint16_t snscb_addr[4]; /* response buffer address */ 1160 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1161 uint16_t snscb_reserved1; 1162 uint16_t snscb_data[]; /* variable data */ 1163 } sns_screq_t; /* Subcommand Request Structure */ 1164 1165 typedef struct { 1166 uint16_t snscb_rblen; /* response buffer length (words) */ 1167 uint16_t snscb_reserved0; 1168 uint16_t snscb_addr[4]; /* response buffer address */ 1169 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1170 uint16_t snscb_reserved1; 1171 uint16_t snscb_cmd; 1172 uint16_t snscb_reserved2; 1173 uint32_t snscb_reserved3; 1174 uint32_t snscb_port; 1175 } sns_ga_nxt_req_t; 1176 #define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t)) 1177 1178 typedef struct { /* Used for GFT_ID, GFF_ID, etc. */ 1179 uint16_t snscb_rblen; /* response buffer length (words) */ 1180 uint16_t snscb_reserved0; 1181 uint16_t snscb_addr[4]; /* response buffer address */ 1182 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1183 uint16_t snscb_reserved1; 1184 uint16_t snscb_cmd; 1185 uint16_t snscb_mword_div_2; 1186 uint32_t snscb_reserved3; 1187 uint32_t snscb_portid; 1188 } sns_gxx_id_req_t; 1189 #define SNS_GXX_ID_REQ_SIZE (sizeof (sns_gxx_id_req_t)) 1190 1191 typedef struct { 1192 uint16_t snscb_rblen; /* response buffer length (words) */ 1193 uint16_t snscb_reserved0; 1194 uint16_t snscb_addr[4]; /* response buffer address */ 1195 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1196 uint16_t snscb_reserved1; 1197 uint16_t snscb_cmd; 1198 uint16_t snscb_mword_div_2; 1199 uint32_t snscb_reserved3; 1200 uint32_t snscb_fc4_type; 1201 } sns_gid_ft_req_t; 1202 #define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t)) 1203 1204 typedef struct { 1205 uint16_t snscb_rblen; /* response buffer length (words) */ 1206 uint16_t snscb_reserved0; 1207 uint16_t snscb_addr[4]; /* response buffer address */ 1208 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1209 uint16_t snscb_reserved1; 1210 uint16_t snscb_cmd; 1211 uint16_t snscb_mword_div_2; 1212 uint32_t snscb_reserved3; 1213 uint8_t snscb_port_type; 1214 uint8_t snscb_domain; 1215 uint8_t snscb_area; 1216 uint8_t snscb_flags; 1217 } sns_gid_pt_req_t; 1218 #define SNS_GID_PT_REQ_SIZE (sizeof (sns_gid_pt_req_t)) 1219 1220 typedef struct { 1221 uint16_t snscb_rblen; /* response buffer length (words) */ 1222 uint16_t snscb_reserved0; 1223 uint16_t snscb_addr[4]; /* response buffer address */ 1224 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1225 uint16_t snscb_reserved1; 1226 uint16_t snscb_cmd; 1227 uint16_t snscb_reserved2; 1228 uint32_t snscb_reserved3; 1229 uint32_t snscb_port; 1230 uint32_t snscb_fc4_types[8]; 1231 } sns_rft_id_req_t; 1232 #define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t)) 1233 1234 typedef struct { 1235 ct_hdr_t snscb_cthdr; 1236 uint8_t snscb_port_type; 1237 uint8_t snscb_port_id[3]; 1238 uint8_t snscb_portname[8]; 1239 uint16_t snscb_data[]; /* variable data */ 1240 } sns_scrsp_t; /* Subcommand Response Structure */ 1241 1242 typedef struct { 1243 ct_hdr_t snscb_cthdr; 1244 uint8_t snscb_port_type; 1245 uint8_t snscb_port_id[3]; 1246 uint8_t snscb_portname[8]; 1247 uint8_t snscb_pnlen; /* symbolic port name length */ 1248 uint8_t snscb_pname[255]; /* symbolic port name */ 1249 uint8_t snscb_nodename[8]; 1250 uint8_t snscb_nnlen; /* symbolic node name length */ 1251 uint8_t snscb_nname[255]; /* symbolic node name */ 1252 uint8_t snscb_ipassoc[8]; 1253 uint8_t snscb_ipaddr[16]; 1254 uint8_t snscb_svc_class[4]; 1255 uint8_t snscb_fc4_types[32]; 1256 uint8_t snscb_fpname[8]; 1257 uint8_t snscb_reserved; 1258 uint8_t snscb_hardaddr[3]; 1259 } sns_ga_nxt_rsp_t; /* Subcommand Response Structure */ 1260 #define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t)) 1261 1262 typedef struct { 1263 ct_hdr_t snscb_cthdr; 1264 uint8_t snscb_wwn[8]; 1265 } sns_gxn_id_rsp_t; 1266 #define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t)) 1267 1268 typedef struct { 1269 ct_hdr_t snscb_cthdr; 1270 uint32_t snscb_fc4_types[8]; 1271 } sns_gft_id_rsp_t; 1272 #define SNS_GFT_ID_RESP_SIZE (sizeof (sns_gft_id_rsp_t)) 1273 1274 typedef struct { 1275 ct_hdr_t snscb_cthdr; 1276 uint32_t snscb_fc4_features[32]; 1277 } sns_gff_id_rsp_t; 1278 #define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t)) 1279 1280 typedef struct { /* Used for GID_FT, GID_PT, etc. */ 1281 ct_hdr_t snscb_cthdr; 1282 struct { 1283 uint8_t control; 1284 uint8_t portid[3]; 1285 } snscb_ports[1]; 1286 } sns_gid_xx_rsp_t; 1287 #define SNS_GID_XX_RESP_SIZE(x) ((sizeof (sns_gid_xx_rsp_t)) + ((x - 1) << 2)) 1288 1289 /* 1290 * Other Misc Structures 1291 */ 1292 1293 /* ELS Pass Through */ 1294 typedef struct { 1295 isphdr_t els_hdr; 1296 uint32_t els_handle; 1297 uint16_t els_status; 1298 uint16_t els_nphdl; 1299 uint16_t els_xmit_dsd_count; /* outgoing only */ 1300 uint8_t els_vphdl; 1301 uint8_t els_sof; 1302 uint32_t els_rxid; 1303 uint16_t els_recv_dsd_count; /* outgoing only */ 1304 uint8_t els_opcode; 1305 uint8_t els_reserved1; 1306 uint8_t els_did_lo; 1307 uint8_t els_did_mid; 1308 uint8_t els_did_hi; 1309 uint8_t els_reserved2; 1310 uint16_t els_reserved3; 1311 uint16_t els_ctl_flags; 1312 union { 1313 struct { 1314 uint32_t _els_bytecnt; 1315 uint32_t _els_subcode1; 1316 uint32_t _els_subcode2; 1317 uint8_t _els_reserved4[20]; 1318 } in; 1319 struct { 1320 uint32_t _els_recv_bytecnt; 1321 uint32_t _els_xmit_bytecnt; 1322 uint32_t _els_xmit_dsd_length; 1323 uint16_t _els_xmit_dsd_a1500; 1324 uint16_t _els_xmit_dsd_a3116; 1325 uint16_t _els_xmit_dsd_a4732; 1326 uint16_t _els_xmit_dsd_a6348; 1327 uint32_t _els_recv_dsd_length; 1328 uint16_t _els_recv_dsd_a1500; 1329 uint16_t _els_recv_dsd_a3116; 1330 uint16_t _els_recv_dsd_a4732; 1331 uint16_t _els_recv_dsd_a6348; 1332 } out; 1333 } inout; 1334 #define els_bytecnt inout.in._els_bytecnt 1335 #define els_subcode1 inout.in._els_subcode1 1336 #define els_subcode2 inout.in._els_subcode2 1337 #define els_reserved4 inout.in._els_reserved4 1338 #define els_recv_bytecnt inout.out._els_recv_bytecnt 1339 #define els_xmit_bytecnt inout.out._els_xmit_bytecnt 1340 #define els_xmit_dsd_length inout.out._els_xmit_dsd_length 1341 #define els_xmit_dsd_a1500 inout.out._els_xmit_dsd_a1500 1342 #define els_xmit_dsd_a3116 inout.out._els_xmit_dsd_a3116 1343 #define els_xmit_dsd_a4732 inout.out._els_xmit_dsd_a4732 1344 #define els_xmit_dsd_a6348 inout.out._els_xmit_dsd_a6348 1345 #define els_recv_dsd_length inout.out._els_recv_dsd_length 1346 #define els_recv_dsd_a1500 inout.out._els_recv_dsd_a1500 1347 #define els_recv_dsd_a3116 inout.out._els_recv_dsd_a3116 1348 #define els_recv_dsd_a4732 inout.out._els_recv_dsd_a4732 1349 #define els_recv_dsd_a6348 inout.out._els_recv_dsd_a6348 1350 } els_t; 1351 1352 /* 1353 * Target Mode related definitions 1354 */ 1355 1356 /* 1357 * ISP24XX Immediate Notify 1358 */ 1359 typedef struct { 1360 isphdr_t in_header; 1361 uint32_t in_reserved; 1362 uint16_t in_nphdl; 1363 uint16_t in_reserved1; 1364 uint16_t in_flags; 1365 uint16_t in_srr_rxid; 1366 uint16_t in_status; 1367 uint8_t in_status_subcode; 1368 uint8_t in_fwhandle; 1369 uint32_t in_rxid; 1370 uint16_t in_srr_reloff_lo; 1371 uint16_t in_srr_reloff_hi; 1372 uint16_t in_srr_iu; 1373 uint16_t in_srr_oxid; 1374 /* 1375 * If bit 2 is set in in_flags, the N-Port and 1376 * handle tags are valid. If the received ELS is 1377 * a LOGO, then these tags contain the N Port ID 1378 * from the LOGO payload. If the received ELS 1379 * request is TPRLO, these tags contain the 1380 * Third Party Originator N Port ID. 1381 */ 1382 uint16_t in_nport_id_hi; 1383 #define in_prli_options in_nport_id_hi 1384 uint8_t in_nport_id_lo; 1385 uint8_t in_reserved3; 1386 uint16_t in_np_handle; 1387 uint8_t in_reserved4[12]; 1388 uint8_t in_reserved5; 1389 uint8_t in_vpidx; 1390 uint32_t in_reserved6; 1391 uint16_t in_portid_lo; 1392 uint8_t in_portid_hi; 1393 uint8_t in_reserved7; 1394 uint16_t in_reserved8; 1395 uint16_t in_oxid; 1396 } in_fcentry_24xx_t; 1397 1398 #define IN24XX_FLAG_PUREX_IOCB 0x1 1399 #define IN24XX_FLAG_GLOBAL_LOGOUT 0x2 1400 #define IN24XX_FLAG_NPHDL_VALID 0x4 1401 #define IN24XX_FLAG_N2N_PRLI 0x8 1402 #define IN24XX_FLAG_PN_NN_VALID 0x10 1403 1404 #define IN24XX_LIP_RESET 0x0E 1405 #define IN24XX_LINK_RESET 0x0F 1406 #define IN24XX_PORT_LOGOUT 0x29 1407 #define IN24XX_PORT_CHANGED 0x2A 1408 #define IN24XX_LINK_FAILED 0x2E 1409 #define IN24XX_SRR_RCVD 0x45 1410 #define IN24XX_ELS_RCVD 0x46 /* 1411 * login-affectin ELS received- check 1412 * subcode for specific opcode 1413 */ 1414 1415 /* 1416 * For f/w > 4.0.25, these offsets in the Immediate Notify contain 1417 * the WWNN/WWPN if the ELS is PLOGI, PDISC or ADISC. The WWN is in 1418 * Big Endian format. 1419 */ 1420 #define IN24XX_PRLI_WWNN_OFF 0x18 1421 #define IN24XX_PRLI_WWPN_OFF 0x28 1422 #define IN24XX_PLOGI_WWNN_OFF 0x20 1423 #define IN24XX_PLOGI_WWPN_OFF 0x28 1424 1425 /* 1426 * For f/w > 4.0.25, this offset in the Immediate Notify contain 1427 * the WWPN if the ELS is LOGO. The WWN is in Big Endian format. 1428 */ 1429 #define IN24XX_LOGO_WWPN_OFF 0x28 1430 1431 /* 1432 * Immediate Notify Status Subcodes for IN24XX_PORT_LOGOUT 1433 */ 1434 #define IN24XX_PORT_LOGOUT_PDISC_TMO 0x00 1435 #define IN24XX_PORT_LOGOUT_UXPR_DISC 0x01 1436 #define IN24XX_PORT_LOGOUT_OWN_OPN 0x02 1437 #define IN24XX_PORT_LOGOUT_OWN_OPN_SFT 0x03 1438 #define IN24XX_PORT_LOGOUT_ABTS_TMO 0x04 1439 #define IN24XX_PORT_LOGOUT_DISC_RJT 0x05 1440 #define IN24XX_PORT_LOGOUT_LOGIN_NEEDED 0x06 1441 #define IN24XX_PORT_LOGOUT_BAD_DISC 0x07 1442 #define IN24XX_PORT_LOGOUT_LOST_ALPA 0x08 1443 #define IN24XX_PORT_LOGOUT_XMIT_FAILURE 0x09 1444 1445 /* 1446 * Immediate Notify Status Subcodes for IN24XX_PORT_CHANGED 1447 */ 1448 #define IN24XX_PORT_CHANGED_BADFAN 0x00 1449 #define IN24XX_PORT_CHANGED_TOPO_CHANGE 0x01 1450 #define IN24XX_PORT_CHANGED_FLOGI_ACC 0x02 1451 #define IN24XX_PORT_CHANGED_FLOGI_RJT 0x03 1452 #define IN24XX_PORT_CHANGED_TIMEOUT 0x04 1453 #define IN24XX_PORT_CHANGED_PORT_CHANGE 0x05 1454 1455 /* 1456 * ISP24XX Notify Acknowledge 1457 */ 1458 #define NA_OK 0x01 /* Notify Acknowledge Succeeded */ 1459 typedef struct { 1460 isphdr_t na_header; 1461 uint32_t na_handle; 1462 uint16_t na_nphdl; 1463 uint16_t na_reserved1; 1464 uint16_t na_flags; 1465 uint16_t na_srr_rxid; 1466 uint16_t na_status; 1467 uint8_t na_status_subcode; 1468 uint8_t na_fwhandle; 1469 uint32_t na_rxid; 1470 uint16_t na_srr_reloff_lo; 1471 uint16_t na_srr_reloff_hi; 1472 uint16_t na_srr_iu; 1473 uint16_t na_srr_flags; 1474 uint8_t na_reserved3[18]; 1475 uint8_t na_reserved4; 1476 uint8_t na_vpidx; 1477 uint8_t na_srr_reject_vunique; 1478 uint8_t na_srr_reject_explanation; 1479 uint8_t na_srr_reject_code; 1480 uint8_t na_reserved5; 1481 uint8_t na_reserved6[6]; 1482 uint16_t na_oxid; 1483 } na_fcentry_24xx_t; 1484 1485 /* 1486 * 24XX ATIO Definition 1487 * 1488 * This is *quite* different from other entry types. 1489 * First of all, it has its own queue it comes in on. 1490 * 1491 * Secondly, it doesn't have a normal header. 1492 * 1493 * Thirdly, it's just a passthru of the FCP CMND IU 1494 * which is recorded in big endian mode. 1495 */ 1496 typedef struct { 1497 uint8_t at_type; 1498 uint8_t at_count; 1499 /* 1500 * Task attribute in high four bits, 1501 * the rest is the FCP CMND IU Length. 1502 * NB: the command can extend past the 1503 * length for a single queue entry. 1504 */ 1505 uint16_t at_ta_len; 1506 uint32_t at_rxid; 1507 fc_hdr_t at_hdr; 1508 fcp_cmnd_iu_t at_cmnd; 1509 } at7_entry_t; 1510 #define AT7_NORESRC_RXID 0xffffffff 1511 1512 #define CT_HBA_RESET 0xffff /* pseudo error - command destroyed by HBA reset*/ 1513 1514 /* 1515 * ISP24XX CTIO 1516 */ 1517 #define MAXRESPLEN_24XX 24 1518 typedef struct { 1519 isphdr_t ct_header; 1520 uint32_t ct_syshandle; 1521 uint16_t ct_nphdl; /* status on returned CTIOs */ 1522 uint16_t ct_timeout; 1523 uint16_t ct_seg_count; 1524 uint8_t ct_vpidx; 1525 uint8_t ct_xflags; 1526 uint16_t ct_iid_lo; /* low 16 bits of portid */ 1527 uint8_t ct_iid_hi; /* hi 8 bits of portid */ 1528 uint8_t ct_reserved; 1529 uint32_t ct_rxid; 1530 uint16_t ct_senselen; /* mode 1 only */ 1531 uint16_t ct_flags; 1532 uint32_t ct_resid; /* residual length */ 1533 uint16_t ct_oxid; 1534 uint16_t ct_scsi_status; /* modes 0 && 1 only */ 1535 union { 1536 struct { 1537 uint32_t reloff; 1538 uint32_t reserved0; 1539 uint32_t ct_xfrlen; 1540 uint32_t reserved1; 1541 ispds64_t ds; 1542 } m0; 1543 struct { 1544 uint16_t ct_resplen; 1545 uint16_t reserved; 1546 uint8_t ct_resp[MAXRESPLEN_24XX]; 1547 } m1; 1548 struct { 1549 uint32_t reserved0; 1550 uint32_t reserved1; 1551 uint32_t ct_datalen; 1552 uint32_t reserved2; 1553 ispds64_t ct_fcp_rsp_iudata; 1554 } m2; 1555 } rsp; 1556 } ct7_entry_t; 1557 1558 /* 1559 * ct_flags values for CTIO7 1560 */ 1561 #define CT7_NO_DATA 0x0000 1562 #define CT7_DATA_OUT 0x0001 /* *from* initiator */ 1563 #define CT7_DATA_IN 0x0002 /* *to* initiator */ 1564 #define CT7_DATAMASK 0x3 1565 #define CT7_DSD_ENABLE 0x0004 1566 #define CT7_CONF_STSFD 0x0010 1567 #define CT7_EXPLCT_CONF 0x0020 1568 #define CT7_FLAG_MODE0 0x0000 1569 #define CT7_FLAG_MODE1 0x0040 1570 #define CT7_FLAG_MODE2 0x0080 1571 #define CT7_FLAG_MMASK 0x00C0 1572 #define CT7_NOACK 0x0100 1573 #define CT7_TASK_ATTR_SHIFT 9 1574 #define CT7_CONFIRM 0x2000 1575 #define CT7_TERMINATE 0x4000 1576 #define CT7_SENDSTATUS 0x8000 1577 1578 /* 1579 * Type 7 CTIO status codes 1580 */ 1581 #define CT7_OK 0x01 /* completed without error */ 1582 #define CT7_ABORTED 0x02 /* aborted by host */ 1583 #define CT7_ERR 0x04 /* see sense data for error */ 1584 #define CT7_INVAL 0x06 /* request for disabled lun */ 1585 #define CT7_INVRXID 0x08 /* Invalid RX_ID */ 1586 #define CT7_DATA_OVER 0x09 /* Data Overrun */ 1587 #define CT7_TIMEOUT 0x0B /* timed out */ 1588 #define CT7_RESET 0x0E /* LIP Rset Received */ 1589 #define CT7_BUS_ERROR 0x10 /* DMA PCI Error */ 1590 #define CT7_REASSY_ERR 0x11 /* DMA reassembly error */ 1591 #define CT7_DATA_UNDER 0x15 /* Data Underrun */ 1592 #define CT7_PORTUNAVAIL 0x28 /* port not available */ 1593 #define CT7_LOGOUT 0x29 /* port logout */ 1594 #define CT7_PORTCHANGED 0x2A /* port changed */ 1595 #define CT7_SRR 0x45 /* SRR Received */ 1596 1597 /* 1598 * Other 24XX related target IOCBs 1599 */ 1600 1601 /* 1602 * ABTS Received 1603 */ 1604 typedef struct { 1605 isphdr_t abts_header; 1606 uint8_t abts_reserved0[6]; 1607 uint16_t abts_nphdl; 1608 uint16_t abts_reserved1; 1609 uint16_t abts_sof; 1610 uint32_t abts_rxid_abts; 1611 uint16_t abts_did_lo; 1612 uint8_t abts_did_hi; 1613 uint8_t abts_r_ctl; 1614 uint16_t abts_sid_lo; 1615 uint8_t abts_sid_hi; 1616 uint8_t abts_cs_ctl; 1617 uint16_t abts_fs_ctl; 1618 uint8_t abts_f_ctl; 1619 uint8_t abts_type; 1620 uint16_t abts_seq_cnt; 1621 uint8_t abts_df_ctl; 1622 uint8_t abts_seq_id; 1623 uint16_t abts_rx_id; 1624 uint16_t abts_ox_id; 1625 uint32_t abts_param; 1626 uint8_t abts_reserved2[16]; 1627 uint32_t abts_rxid_task; 1628 } abts_t; 1629 1630 typedef struct { 1631 isphdr_t abts_rsp_header; 1632 uint32_t abts_rsp_handle; 1633 uint16_t abts_rsp_status; 1634 uint16_t abts_rsp_nphdl; 1635 uint16_t abts_rsp_ctl_flags; 1636 uint16_t abts_rsp_sof; 1637 uint32_t abts_rsp_rxid_abts; 1638 uint16_t abts_rsp_did_lo; 1639 uint8_t abts_rsp_did_hi; 1640 uint8_t abts_rsp_r_ctl; 1641 uint16_t abts_rsp_sid_lo; 1642 uint8_t abts_rsp_sid_hi; 1643 uint8_t abts_rsp_cs_ctl; 1644 uint16_t abts_rsp_f_ctl_lo; 1645 uint8_t abts_rsp_f_ctl_hi; 1646 uint8_t abts_rsp_type; 1647 uint16_t abts_rsp_seq_cnt; 1648 uint8_t abts_rsp_df_ctl; 1649 uint8_t abts_rsp_seq_id; 1650 uint16_t abts_rsp_rx_id; 1651 uint16_t abts_rsp_ox_id; 1652 uint32_t abts_rsp_param; 1653 union { 1654 struct { 1655 uint16_t reserved; 1656 uint8_t last_seq_id; 1657 uint8_t seq_id_valid; 1658 uint16_t aborted_rx_id; 1659 uint16_t aborted_ox_id; 1660 uint16_t high_seq_cnt; 1661 uint16_t low_seq_cnt; 1662 uint8_t reserved2[4]; 1663 } ba_acc; 1664 struct { 1665 uint8_t vendor_unique; 1666 uint8_t explanation; 1667 uint8_t reason; 1668 uint8_t reserved; 1669 uint8_t reserved2[12]; 1670 } ba_rjt; 1671 struct { 1672 uint8_t reserved[8]; 1673 uint32_t subcode1; 1674 uint32_t subcode2; 1675 } rsp; 1676 uint8_t reserved[16]; 1677 } abts_rsp_payload; 1678 uint32_t abts_rsp_rxid_task; 1679 } abts_rsp_t; 1680 1681 /* terminate this ABTS exchange */ 1682 #define ISP24XX_ABTS_RSP_TERMINATE 0x01 1683 1684 #define ISP24XX_ABTS_RSP_COMPLETE 0x00 1685 #define ISP24XX_ABTS_RSP_RESET 0x04 1686 #define ISP24XX_ABTS_RSP_ABORTED 0x05 1687 #define ISP24XX_ABTS_RSP_TIMEOUT 0x06 1688 #define ISP24XX_ABTS_RSP_INVXID 0x08 1689 #define ISP24XX_ABTS_RSP_LOGOUT 0x29 1690 #define ISP24XX_ABTS_RSP_SUBCODE 0x31 1691 1692 #define ISP24XX_NO_TASK 0xffffffff 1693 1694 /* 1695 * Miscellaneous 1696 * 1697 * These are the limits of the number of dma segments we 1698 * can deal with based not on the size of the segment counter 1699 * (which is 16 bits), but on the size of the number of 1700 * queue entries field (which is 8 bits). We assume no 1701 * segments in the first queue entry, so we can have 1702 * have 5 dma segments per continuation entry... 1703 * multiplying out by 254.... 1704 */ 1705 #define ISP_NSEG64_MAX 1270 1706 1707 #endif /* _ISPMBOX_H */ 1708