1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009-2020 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 1997-2009 by Matthew Jacob 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Mailbox and Queue Entry Definitions for Qlogic ISP SCSI adapters. 34 */ 35 #ifndef _ISPMBOX_H 36 #define _ISPMBOX_H 37 38 /* 39 * Mailbox Command Opcodes 40 */ 41 #define MBOX_NO_OP 0x0000 42 #define MBOX_LOAD_RAM 0x0001 43 #define MBOX_EXEC_FIRMWARE 0x0002 44 #define MBOX_LOAD_FLASH_FIRMWARE 0x0003 45 #define MBOX_WRITE_RAM_WORD 0x0004 46 #define MBOX_READ_RAM_WORD 0x0005 47 #define MBOX_MAILBOX_REG_TEST 0x0006 48 #define MBOX_VERIFY_CHECKSUM 0x0007 49 #define MBOX_ABOUT_FIRMWARE 0x0008 50 #define MBOX_LOAD_RISC_RAM_2100 0x0009 51 #define MBOX_DUMP_RISC_RAM_2100 0x000a 52 #define MBOX_SECURE_FLASH_UPDATE 0x000a /* Secure Flash Update(28xx) */ 53 #define MBOX_LOAD_RISC_RAM 0x000b 54 #define MBOX_DUMP_RISC_RAM 0x000c 55 #define MBOX_WRITE_RAM_WORD_EXTENDED 0x000d 56 #define MBOX_CHECK_FIRMWARE 0x000e 57 #define MBOX_READ_RAM_WORD_EXTENDED 0x000f 58 #define MBOX_INIT_REQ_QUEUE 0x0010 59 #define MBOX_INIT_RES_QUEUE 0x0011 60 #define MBOX_EXECUTE_IOCB 0x0012 61 #define MBOX_WAKE_UP 0x0013 62 #define MBOX_STOP_FIRMWARE 0x0014 63 #define MBOX_ABORT 0x0015 64 #define MBOX_ABORT_DEVICE 0x0016 65 #define MBOX_ABORT_TARGET 0x0017 66 #define MBOX_BUS_RESET 0x0018 67 #define MBOX_STOP_QUEUE 0x0019 68 #define MBOX_START_QUEUE 0x001a 69 #define MBOX_SINGLE_STEP_QUEUE 0x001b 70 #define MBOX_ABORT_QUEUE 0x001c 71 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 72 /* 1e */ 73 #define MBOX_GET_FIRMWARE_STATUS 0x001f 74 #define MBOX_GET_INIT_SCSI_ID 0x0020 75 #define MBOX_GET_SELECT_TIMEOUT 0x0021 76 #define MBOX_GET_RETRY_COUNT 0x0022 77 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 78 #define MBOX_GET_CLOCK_RATE 0x0024 79 #define MBOX_GET_ACT_NEG_STATE 0x0025 80 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 81 #define MBOX_GET_SBUS_PARAMS 0x0027 82 #define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS 83 #define MBOX_GET_TARGET_PARAMS 0x0028 84 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 85 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a 86 /* 2b */ 87 /* 2c */ 88 /* 2d */ 89 /* 2e */ 90 /* 2f */ 91 #define MBOX_SET_INIT_SCSI_ID 0x0030 92 #define MBOX_SET_SELECT_TIMEOUT 0x0031 93 #define MBOX_SET_RETRY_COUNT 0x0032 94 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 95 #define MBOX_SET_CLOCK_RATE 0x0034 96 #define MBOX_SET_ACT_NEG_STATE 0x0035 97 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 98 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 99 #define MBOX_SET_PCI_PARAMETERS 0x0037 100 #define MBOX_SET_TARGET_PARAMS 0x0038 101 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 102 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a 103 /* 3b */ 104 /* 3c */ 105 /* 3d */ 106 /* 3e */ 107 /* 3f */ 108 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 109 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 110 #define MBOX_EXEC_BIOS_IOCB 0x0042 111 #define MBOX_SET_FW_FEATURES 0x004a 112 #define MBOX_GET_FW_FEATURES 0x004b 113 #define FW_FEATURE_FAST_POST 0x1 114 #define FW_FEATURE_LVD_NOTIFY 0x2 115 #define FW_FEATURE_RIO_32BIT 0x4 116 #define FW_FEATURE_RIO_16BIT 0x8 117 118 #define MBOX_INIT_REQ_QUEUE_A64 0x0052 119 #define MBOX_INIT_RES_QUEUE_A64 0x0053 120 121 #define MBOX_ENABLE_TARGET_MODE 0x0055 122 #define ENABLE_TARGET_FLAG 0x8000 123 #define ENABLE_TQING_FLAG 0x0004 124 #define ENABLE_MANDATORY_DISC 0x0002 125 #define MBOX_GET_TARGET_STATUS 0x0056 126 127 /* These are for the ISP2X00 FC cards */ 128 #define MBOX_WRITE_FC_SERDES_REG 0x0003 /* FC only */ 129 #define MBOX_READ_FC_SERDES_REG 0x0004 /* FC only */ 130 #define MBOX_GET_IO_STATUS 0x0012 131 #define MBOX_SET_TRANSMIT_PARAMS 0x0019 132 #define MBOX_SET_PORT_PARAMS 0x001a 133 #define MBOX_LOAD_OP_FW_PARAMS 0x001b 134 #define MBOX_INIT_MULTIPLE_QUEUE 0x001f 135 #define MBOX_GET_LOOP_ID 0x0020 136 /* for 24XX cards, outgoing mailbox 7 has these values for F or FL topologies */ 137 #define ISP24XX_INORDER 0x0100 138 #define ISP24XX_NPIV_SAN 0x0400 139 #define ISP24XX_VSAN_SAN 0x1000 140 #define ISP24XX_FC_SP_SAN 0x2000 141 #define MBOX_GET_TIMEOUT_PARAMS 0x0022 142 #define MBOX_GET_FIRMWARE_OPTIONS 0x0028 143 #define MBOX_GENERATE_SYSTEM_ERROR 0x002a 144 #define MBOX_WRITE_SFP 0x0030 145 #define MBOX_READ_SFP 0x0031 146 #define MBOX_SET_TIMEOUT_PARAMS 0x0032 147 #define MBOX_SET_FIRMWARE_OPTIONS 0x0038 148 #define MBOX_GET_SET_FC_LED_CONF 0x003b 149 #define MBOX_RESTART_NIC_FIRMWARE 0x003d /* FCoE only */ 150 #define MBOX_ACCESS_CONTROL 0x003e 151 #define MBOX_LOOP_PORT_BYPASS 0x0040 /* FC only */ 152 #define MBOX_LOOP_PORT_ENABLE 0x0041 /* FC only */ 153 #define MBOX_GET_RESOURCE_COUNT 0x0042 154 #define MBOX_REQUEST_OFFLINE_MODE 0x0043 155 #define MBOX_DIAGNOSTIC_ECHO_TEST 0x0044 156 #define MBOX_DIAGNOSTIC_LOOPBACK 0x0045 157 #define MBOX_ENHANCED_GET_PDB 0x0047 158 #define MBOX_INIT_FIRMWARE_MULTI_ID 0x0048 /* 2400 only */ 159 #define MBOX_GET_VP_DATABASE 0x0049 /* 2400 only */ 160 #define MBOX_GET_VP_DATABASE_ENTRY 0x004a /* 2400 only */ 161 #define MBOX_GET_FCF_LIST 0x0050 /* FCoE only */ 162 #define MBOX_GET_DCBX_PARAMETERS 0x0051 /* FCoE only */ 163 #define MBOX_HOST_MEMORY_COPY 0x0053 164 #define MBOX_EXEC_COMMAND_IOCB_A64 0x0054 165 #define MBOX_SEND_RNID 0x0057 166 #define MBOX_SET_PARAMETERS 0x0059 167 #define MBOX_GET_PARAMETERS 0x005a 168 #define MBOX_DRIVER_HEARTBEAT 0x005B /* FC only */ 169 #define MBOX_FW_HEARTBEAT 0x005C 170 #define MBOX_GET_SET_DATA_RATE 0x005D /* >=23XX only */ 171 #define MBGSD_GET_RATE 0 172 #define MBGSD_SET_RATE 1 173 #define MBGSD_SET_RATE_NOW 2 /* 24XX only */ 174 #define MBGSD_1GB 0x00 175 #define MBGSD_2GB 0x01 176 #define MBGSD_AUTO 0x02 177 #define MBGSD_4GB 0x03 /* 24XX only */ 178 #define MBGSD_8GB 0x04 /* 25XX only */ 179 #define MBGSD_16GB 0x05 /* 26XX only */ 180 #define MBGSD_32GB 0x06 /* 27XX only */ 181 #define MBGSD_64GB 0x07 /* 28XX only */ 182 #define MBGSD_10GB 0x13 /* 26XX only */ 183 #define MBOX_SEND_RNFT 0x005e 184 #define MBOX_INIT_FIRMWARE 0x0060 185 #define MBOX_GET_INIT_CONTROL_BLOCK 0x0061 186 #define MBOX_INIT_LIP 0x0062 187 #define MBOX_GET_FC_AL_POSITION_MAP 0x0063 188 #define MBOX_GET_PORT_DB 0x0064 189 #define MBOX_CLEAR_ACA 0x0065 190 #define MBOX_TARGET_RESET 0x0066 191 #define MBOX_CLEAR_TASK_SET 0x0067 192 #define MBOX_ABORT_TASK_SET 0x0068 193 #define MBOX_GET_FW_STATE 0x0069 194 #define MBOX_GET_PORT_NAME 0x006A 195 #define MBOX_GET_LINK_STATUS 0x006B 196 #define MBOX_INIT_LIP_RESET 0x006C 197 #define MBOX_GET_LINK_STAT_PR_DATA_CNT 0x006D 198 #define MBOX_SEND_SNS 0x006E 199 #define MBOX_FABRIC_LOGIN 0x006F 200 #define MBOX_SEND_CHANGE_REQUEST 0x0070 201 #define MBOX_FABRIC_LOGOUT 0x0071 202 #define MBOX_INIT_LIP_LOGIN 0x0072 203 #define MBOX_GET_PORT_NODE_NAME_LIST 0x0075 204 #define MBOX_SET_VENDOR_ID 0x0076 205 #define MBOX_GET_XGMAC_STATS 0x007a 206 #define MBOX_GET_ID_LIST 0x007C 207 #define MBOX_SEND_LFA 0x007d 208 #define MBOX_LUN_RESET 0x007E 209 210 #define ISP2100_SET_PCI_PARAM 0x00ff 211 212 /* 213 * Mailbox Command Complete Status Codes 214 */ 215 #define MBOX_COMMAND_COMPLETE 0x4000 216 #define MBOX_INVALID_COMMAND 0x4001 217 #define MBOX_HOST_INTERFACE_ERROR 0x4002 218 #define MBOX_TEST_FAILED 0x4003 219 #define MBOX_COMMAND_ERROR 0x4005 220 #define MBOX_COMMAND_PARAM_ERROR 0x4006 221 #define MBOX_PORT_ID_USED 0x4007 222 #define MBOX_LOOP_ID_USED 0x4008 223 #define MBOX_ALL_IDS_USED 0x4009 224 #define MBOX_NOT_LOGGED_IN 0x400A 225 #define MBOX_LINK_DOWN_ERROR 0x400B 226 #define MBOX_LOOPBACK_ERROR 0x400C 227 #define MBOX_CHECKSUM_ERROR 0x4010 228 #define MBOX_INVALID_PRODUCT_KEY 0x4020 229 /* pseudo mailbox completion codes */ 230 #define MBOX_REGS_BUSY 0x6000 /* registers in use */ 231 #define MBOX_TIMEOUT 0x6001 /* command timed out */ 232 233 #define MBLOGALL 0xffffffff 234 #define MBLOGNONE 0x00000000 235 #define MBLOGMASK(x) (1 << (((x) - 1) & 0x1f)) 236 237 /* 238 * Asynchronous event status codes 239 */ 240 #define ASYNC_BUS_RESET 0x8001 241 #define ASYNC_SYSTEM_ERROR 0x8002 242 #define ASYNC_RQS_XFER_ERR 0x8003 243 #define ASYNC_RSP_XFER_ERR 0x8004 244 #define ASYNC_ATIO_XFER_ERR 0x8005 245 #define ASYNC_TIMEOUT_RESET 0x8006 246 #define ASYNC_DEVICE_RESET 0x8007 247 #define ASYNC_EXTMSG_UNDERRUN 0x800A 248 #define ASYNC_SCAM_INT 0x800B 249 #define ASYNC_HUNG_SCSI 0x800C 250 #define ASYNC_KILLED_BUS 0x800D 251 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 252 #define ASYNC_LIP_OCCURRED 0x8010 /* FC only */ 253 #define ASYNC_LOOP_UP 0x8011 254 #define ASYNC_LOOP_DOWN 0x8012 255 #define ASYNC_LOOP_RESET 0x8013 /* FC only */ 256 #define ASYNC_PDB_CHANGED 0x8014 257 #define ASYNC_CHANGE_NOTIFY 0x8015 258 #define ASYNC_LIP_NOS_OLS_RECV 0x8016 /* FC only */ 259 #define ASYNC_LIP_ERROR 0x8017 /* FC only */ 260 #define ASYNC_AUTO_PLOGI_RJT 0x8018 261 #define ASYNC_SECURITY_UPDATE 0x801B 262 #define ASYNC_CMD_CMPLT 0x8020 263 #define ASYNC_CTIO_DONE 0x8021 264 #define ASYNC_RIO32_1 0x8021 265 #define ASYNC_RIO32_2 0x8022 266 #define ASYNC_IP_XMIT_DONE 0x8022 267 #define ASYNC_IP_RECV_DONE 0x8023 268 #define ASYNC_IP_BROADCAST 0x8024 269 #define ASYNC_IP_RCVQ_LOW 0x8025 270 #define ASYNC_IP_RCVQ_EMPTY 0x8026 271 #define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 272 #define ASYNC_ERR_LOGGING_DISABLED 0x8029 273 #define ASYNC_PTPMODE 0x8030 /* FC only */ 274 #define ASYNC_RIO16_1 0x8031 275 #define ASYNC_RIO16_2 0x8032 276 #define ASYNC_RIO16_3 0x8033 277 #define ASYNC_RIO16_4 0x8034 278 #define ASYNC_RIO16_5 0x8035 279 #define ASYNC_CONNMODE 0x8036 280 #define ISP_CONN_LOOP 1 281 #define ISP_CONN_PTP 2 282 #define ISP_CONN_BADLIP 3 283 #define ISP_CONN_FATAL 4 284 #define ISP_CONN_LOOPBACK 5 285 #define ASYNC_P2P_INIT_ERR 0x8037 286 #define ASYNC_RIOZIO_STALL 0x8040 /* there's a RIO/ZIO entry that hasn't been serviced */ 287 #define ASYNC_RIO32_2_2200 0x8042 /* same as ASYNC_RIO32_2, but for 2100/2200 */ 288 #define ASYNC_RCV_ERR 0x8048 289 /* 290 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options 291 * mailbox command to enable this. 292 */ 293 #define ASYNC_QFULL_SENT 0x8049 294 #define ASYNC_RJT_SENT 0x8049 /* 24XX only */ 295 #define ASYNC_SEL_CLASS2_P_RJT_SENT 0x804f 296 #define ASYNC_FW_RESTART_COMPLETE 0x8060 297 #define ASYNC_TEMPERATURE_ALERT 0x8070 298 #define ASYNC_INTER_DRIVER_COMP 0x8100 /* FCoE only */ 299 #define ASYNC_INTER_DRIVER_NOTIFY 0x8101 /* FCoE only */ 300 #define ASYNC_INTER_DRIVER_TIME_EXT 0x8102 /* FCoE only */ 301 #define ASYNC_TRANSCEIVER_INSERTION 0x8130 302 #define ASYNC_TRANSCEIVER_REMOVAL 0x8131 303 #define ASYNC_NIC_FW_STATE_CHANGE 0x8200 /* FCoE only */ 304 #define ASYNC_AUTOLOAD_FW_COMPLETE 0x8400 305 #define ASYNC_AUTOLOAD_FW_FAILURE 0x8401 306 307 /* 308 * Firmware Options. There are a lot of them. 309 * 310 * IFCOPTN - ISP Fibre Channel Option Word N 311 */ 312 #define IFCOPT1_EQFQASYNC (1 << 13) /* enable QFULL notification */ 313 #define IFCOPT1_EAABSRCVD (1 << 12) 314 #define IFCOPT1_RJTASYNC (1 << 11) /* enable 8018 notification */ 315 #define IFCOPT1_ENAPURE (1 << 10) 316 #define IFCOPT1_ENA8017 (1 << 7) 317 #define IFCOPT1_DISGPIO67 (1 << 6) 318 #define IFCOPT1_LIPLOSSIMM (1 << 5) 319 #define IFCOPT1_DISF7SWTCH (1 << 4) 320 #define IFCOPT1_CTIO_RETRY (1 << 3) 321 #define IFCOPT1_LIPASYNC (1 << 1) 322 #define IFCOPT1_LIPF8 (1 << 0) 323 324 #define IFCOPT2_LOOPBACK (1 << 1) 325 #define IFCOPT2_ATIO3_ONLY (1 << 0) 326 327 #define IFCOPT3_NOPRLI (1 << 4) /* disable automatic sending of PRLI on local loops */ 328 #define IFCOPT3_RNDASYNC (1 << 1) 329 330 /* 331 * All IOCB Queue entries are this size 332 */ 333 #define QENTRY_LEN 64 334 #define QENTRY_MAX 255 335 336 /* 337 * Command Structure Definitions 338 */ 339 340 typedef struct { 341 uint32_t ds_base; 342 uint32_t ds_basehi; 343 uint32_t ds_count; 344 } ispds64_t; 345 346 typedef struct { 347 uint8_t rqs_entry_type; 348 uint8_t rqs_entry_count; 349 uint8_t rqs_seqno; 350 uint8_t rqs_flags; 351 } isphdr_t; 352 353 /* RQS Flag definitions */ 354 #define RQSFLAG_BADTYPE 0x04 355 #define RQSFLAG_BADPARAM 0x08 356 #define RQSFLAG_BADCOUNT 0x10 357 #define RQSFLAG_BADORDER 0x20 358 #define RQSFLAG_MASK 0x3f 359 360 /* RQS entry_type definitions */ 361 #define RQSTYPE_RESPONSE 0x03 362 #define RQSTYPE_MARKER 0x04 363 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 364 #define RQSTYPE_A64_CONT 0x0a 365 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 366 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 367 #define RQSTYPE_STATUS_CONT 0x10 368 #define RQSTYPE_CTIO7 0x12 369 #define RQSTYPE_TSK_MGMT 0x14 370 #define RQSTYPE_ATIO2 0x16 /* Target Mode */ 371 #define RQSTYPE_T7RQS 0x18 372 #define RQSTYPE_CT_PASSTHRU 0x29 373 #define RQSTYPE_VP_CTRL 0x30 374 #define RQSTYPE_VP_MODIFY 0x31 375 #define RQSTYPE_RPT_ID_ACQ 0x32 376 #define RQSTYPE_ABORT_IO 0x33 377 #define RQSTYPE_MBOX 0x39 378 #define RQSTYPE_T6RQS 0x48 379 #define RQSTYPE_PUREX 0x51 380 #define RQSTYPE_LOGIN 0x52 381 #define RQSTYPE_ELS_PASSTHRU 0x53 382 #define RQSTYPE_ABTS_RCVD 0x54 383 #define RQSTYPE_ABTS_RSP 0x55 384 385 typedef struct { 386 isphdr_t mrk_header; 387 uint32_t mrk_handle; 388 uint16_t mrk_nphdl; 389 uint8_t mrk_modifier; 390 uint8_t mrk_reserved0; 391 uint8_t mrk_reserved1; 392 uint8_t mrk_vphdl; 393 uint16_t mrk_reserved2; 394 uint8_t mrk_lun[8]; 395 uint8_t mrk_reserved3[40]; 396 } isp_marker_24xx_t; 397 398 #define SYNC_DEVICE 0 399 #define SYNC_TARGET 1 400 #define SYNC_ALL 2 401 #define SYNC_LIP 3 402 403 /* 404 * ISP24XX structures 405 */ 406 typedef struct { 407 isphdr_t req_header; 408 uint32_t req_handle; 409 uint16_t req_nphdl; 410 uint16_t req_time; 411 uint16_t req_seg_count; 412 uint16_t req_reserved; 413 uint8_t req_lun[8]; 414 uint8_t req_alen_datadir; 415 uint8_t req_task_management; 416 uint8_t req_task_attribute; 417 uint8_t req_crn; 418 uint8_t req_cdb[16]; 419 uint32_t req_dl; 420 uint16_t req_tidlo; 421 uint8_t req_tidhi; 422 uint8_t req_vpidx; 423 ispds64_t req_dataseg; 424 } ispreqt7_t; 425 426 /* Task Management Request Function */ 427 typedef struct { 428 isphdr_t tmf_header; 429 uint32_t tmf_handle; 430 uint16_t tmf_nphdl; 431 uint8_t tmf_reserved0[2]; 432 uint16_t tmf_delay; 433 uint16_t tmf_timeout; 434 uint8_t tmf_lun[8]; 435 uint32_t tmf_flags; 436 uint8_t tmf_reserved1[20]; 437 uint16_t tmf_tidlo; 438 uint8_t tmf_tidhi; 439 uint8_t tmf_vpidx; 440 uint8_t tmf_reserved2[12]; 441 } isp24xx_tmf_t; 442 443 #define ISP24XX_TMF_NOSEND 0x80000000 444 445 #define ISP24XX_TMF_LUN_RESET 0x00000010 446 #define ISP24XX_TMF_ABORT_TASK_SET 0x00000008 447 #define ISP24XX_TMF_CLEAR_TASK_SET 0x00000004 448 #define ISP24XX_TMF_TARGET_RESET 0x00000002 449 #define ISP24XX_TMF_CLEAR_ACA 0x00000001 450 451 /* I/O Abort Structure */ 452 typedef struct { 453 isphdr_t abrt_header; 454 uint32_t abrt_handle; 455 uint16_t abrt_nphdl; 456 uint16_t abrt_options; 457 uint32_t abrt_cmd_handle; 458 uint16_t abrt_queue_number; 459 uint8_t abrt_reserved[30]; 460 uint16_t abrt_tidlo; 461 uint8_t abrt_tidhi; 462 uint8_t abrt_vpidx; 463 uint8_t abrt_reserved1[12]; 464 } isp24xx_abrt_t; 465 466 #define ISP24XX_ABRT_NOSEND 0x01 /* don't actually send ABTS */ 467 #define ISP24XX_ABRT_OKAY 0x00 /* in nphdl on return */ 468 #define ISP24XX_ABRT_ENXIO 0x31 /* in nphdl on return */ 469 470 #define ISP_CDSEG64 5 471 typedef struct { 472 isphdr_t req_header; 473 ispds64_t req_dataseg[ISP_CDSEG64]; 474 } ispcontreq64_t; 475 476 /* 477 * Status Continuation 478 */ 479 typedef struct { 480 isphdr_t req_header; 481 uint8_t req_sense_data[60]; 482 } ispstatus_cont_t; 483 484 /* 485 * 24XX Type 0 status 486 */ 487 typedef struct { 488 isphdr_t req_header; 489 uint32_t req_handle; 490 uint16_t req_completion_status; 491 uint16_t req_oxid; 492 uint32_t req_resid; 493 uint16_t req_reserved0; 494 uint16_t req_state_flags; 495 uint16_t req_retry_delay; /* aka Status Qualifier */ 496 uint16_t req_scsi_status; 497 uint32_t req_fcp_residual; 498 uint32_t req_sense_len; 499 uint32_t req_response_len; 500 uint8_t req_rsp_sense[28]; 501 } isp24xx_statusreq_t; 502 503 /* 504 * For Qlogic 2X00, the high order byte of SCSI status has 505 * additional meaning. 506 */ 507 #define RQCS_CR 0x1000 /* Confirmation Request */ 508 #define RQCS_RU 0x0800 /* Residual Under */ 509 #define RQCS_RO 0x0400 /* Residual Over */ 510 #define RQCS_RESID (RQCS_RU|RQCS_RO) 511 #define RQCS_SV 0x0200 /* Sense Length Valid */ 512 #define RQCS_RV 0x0100 /* FCP Response Length Valid */ 513 514 /* 515 * CT Passthru IOCB 516 */ 517 typedef struct { 518 isphdr_t ctp_header; 519 uint32_t ctp_handle; 520 uint16_t ctp_status; 521 uint16_t ctp_nphdl; /* n-port handle */ 522 uint16_t ctp_cmd_cnt; /* Command DSD count */ 523 uint8_t ctp_vpidx; 524 uint8_t ctp_reserved0; 525 uint16_t ctp_time; 526 uint16_t ctp_reserved1; 527 uint16_t ctp_rsp_cnt; /* Response DSD count */ 528 uint16_t ctp_reserved2[5]; 529 uint32_t ctp_rsp_bcnt; /* Response byte count */ 530 uint32_t ctp_cmd_bcnt; /* Command byte count */ 531 ispds64_t ctp_dataseg[2]; 532 } isp_ct_pt_t; 533 534 /* 535 * Completion Status Codes. 536 */ 537 #define RQCS_COMPLETE 0x0000 538 #define RQCS_DMA_ERROR 0x0002 539 #define RQCS_TRANSPORT_ERROR 0x0003 540 #define RQCS_RESET_OCCURRED 0x0004 541 #define RQCS_ABORTED 0x0005 542 #define RQCS_TIMEOUT 0x0006 543 #define RQCS_DATA_OVERRUN 0x0007 544 #define RQCS_DRE 0x0011 /* data reassembly error */ 545 #define RQCS_TABORT 0x0013 /* aborted by target */ 546 #define RQCS_DATA_UNDERRUN 0x0015 547 #define RQCS_PORT_UNAVAILABLE 0x0028 548 #define RQCS_PORT_LOGGED_OUT 0x0029 549 #define RQCS_PORT_CHANGED 0x002A 550 #define RQCS_PORT_BUSY 0x002B 551 #define RQCS_ENOMEM 0x002C /* f/w resource unavailable */ 552 #define RQCS_TMO 0x0030 /* task management overrun */ 553 554 /* 555 * About Firmware returns an 'attribute' word. 556 */ 557 #define ISP_FW_ATTR_CLASS2 0x0001 558 #define ISP_FW_ATTR_IP 0x0002 559 #define ISP_FW_ATTR_MULTIID 0x0004 560 #define ISP_FW_ATTR_SB2 0x0008 561 #define ISP_FW_ATTR_T10CRC 0x0010 562 #define ISP_FW_ATTR_VI 0x0020 563 #define ISP_FW_ATTR_MQ 0x0040 564 #define ISP_FW_ATTR_MSIX 0x0080 565 #define ISP_FW_ATTR_FCOE 0x0800 566 #define ISP_FW_ATTR_VP0 0x1000 567 #define ISP_FW_ATTR_EXPFW 0x2000 568 #define ISP_FW_ATTR_HOTFW 0x4000 569 #define ISP_FW_ATTR_EXTNDED 0x8000 570 571 #define ISP_FW_ATTR_H_EXTVP 0x0001 572 #define ISP_FW_ATTR_H_NVME_FB 0x0002 /* NVMe first burst */ 573 #define ISP_FW_ATTR_H_VN2VN 0x0004 /* Extended login */ 574 #define ISP_FW_ATTR_H_EXMOFF 0x0008 /* Exchange offload */ 575 #define ISP_FW_ATTR_H_NPMOFF 0x0010 576 #define ISP_FW_ATTR_H_DIFCHOP 0x0040 577 #define ISP_FW_ATTR_H_SRIOV 0x0200 578 #define ISP_FW_ATTR_H_NVME 0x0400 /* FC-NVMe */ 579 #define ISP_FW_ATTR_H_NVME_UP 0x4000 /* FC-NVMe updated */ 580 581 #define ISP_FW_ATTR_E0_ASICTMP 0x0002 582 #define ISP_FW_ATTR_E0_ATIOMQ 0x0004 583 #define ISP_FW_ATTR_E0_EDIF 0x0020 /* Encryption of data in flight */ 584 #define ISP_FW_ATTR_E0_SCM 0x1000 /* Simplified Configuration and Management */ 585 #define ISP_FW_ATTR_E0_NVME2 0x2000 /* NVMe2 */ 586 587 /* 588 * This is only true for 24XX cards with this f/w attribute 589 */ 590 #define ISP_CAP_MULTI_ID(isp) \ 591 (isp->isp_fwattr & ISP_FW_ATTR_MULTIID) 592 #define ISP_GET_VPIDX(isp, tag) \ 593 (ISP_CAP_MULTI_ID(isp) ? tag : 0) 594 #define ISP_CAP_MSIX(isp) \ 595 (isp->isp_fwattr & ISP_FW_ATTR_MSIX) 596 #define ISP_CAP_VP0(isp) \ 597 (isp->isp_fwattr & ISP_FW_ATTR_VP0) 598 599 #define ISP_FCTAPE_ENABLED(isp, chan) \ 600 ((FCPARAM(isp, chan)->isp_xfwoptions & ICB2400_OPT2_FCTAPE) != 0) 601 602 /* 603 * FC specific data structures 604 */ 605 606 /* 607 * Initialization Control Block 608 */ 609 610 #define ICB_VERSION1 1 611 612 /* 2400 F/W options */ 613 #define ICB2400_OPT1_BOTH_WWNS 0x00004000 614 #define ICB2400_OPT1_FULL_LOGIN 0x00002000 615 #define ICB2400_OPT1_PREV_ADDRESS 0x00000800 616 #define ICB2400_OPT1_SRCHDOWN 0x00000400 617 #define ICB2400_OPT1_NOLIP 0x00000200 618 #define ICB2400_OPT1_INI_DISABLE 0x00000020 619 #define ICB2400_OPT1_TGT_ENABLE 0x00000010 620 #define ICB2400_OPT1_FULL_DUPLEX 0x00000004 621 #define ICB2400_OPT1_FAIRNESS 0x00000002 622 #define ICB2400_OPT1_HARD_ADDRESS 0x00000001 623 624 #define ICB2400_OPT2_ENA_ATIOMQ 0x08000000 625 #define ICB2400_OPT2_ENA_IHA 0x04000000 626 #define ICB2400_OPT2_QOS 0x02000000 627 #define ICB2400_OPT2_IOCBS 0x01000000 628 #define ICB2400_OPT2_ENA_IHR 0x00400000 629 #define ICB2400_OPT2_ENA_VMS 0x00200000 630 #define ICB2400_OPT2_ENA_TA 0x00100000 631 #define ICB2400_OPT2_TPRLIC 0x00004000 632 #define ICB2400_OPT2_FCTAPE 0x00001000 633 #define ICB2400_OPT2_FCSP 0x00000800 634 #define ICB2400_OPT2_CLASS2_ACK0 0x00000200 635 #define ICB2400_OPT2_CLASS2 0x00000100 636 #define ICB2400_OPT2_NO_PLAY 0x00000080 637 #define ICB2400_OPT2_TOPO_MASK 0x00000070 638 #define ICB2400_OPT2_LOOP_ONLY 0x00000000 639 #define ICB2400_OPT2_PTP_ONLY 0x00000010 640 #define ICB2400_OPT2_LOOP_2_PTP 0x00000020 641 #define ICB2400_OPT2_TIMER_MASK 0x0000000f 642 #define ICB2400_OPT2_ZIO 0x00000005 643 #define ICB2400_OPT2_ZIO1 0x00000006 644 645 #define ICB2400_OPT3_NO_CTXDIS 0x40000000 646 #define ICB2400_OPT3_ENA_ETH_RESP 0x08000000 647 #define ICB2400_OPT3_ENA_ETH_ATIO 0x04000000 648 #define ICB2400_OPT3_ENA_MFCF 0x00020000 649 #define ICB2400_OPT3_SKIP_4GB 0x00010000 650 #define ICB2400_OPT3_RATE_MASK 0x0000E000 651 #define ICB2400_OPT3_RATE_1GB 0x00000000 652 #define ICB2400_OPT3_RATE_2GB 0x00002000 653 #define ICB2400_OPT3_RATE_AUTO 0x00004000 654 #define ICB2400_OPT3_RATE_4GB 0x00006000 655 #define ICB2400_OPT3_RATE_8GB 0x00008000 656 #define ICB2400_OPT3_RATE_16GB 0x0000A000 657 #define ICB2400_OPT3_RATE_32GB 0x0000C000 658 #define ICB2400_OPT3_RATE_64GB 0x0000E000 659 #define ICB2400_OPT3_ENA_OOF_XFRDY 0x00000200 660 #define ICB2400_OPT3_NO_N2N_LOGI 0x00000100 661 #define ICB2400_OPT3_NO_LOCAL_PLOGI 0x00000080 662 #define ICB2400_OPT3_ENA_OOF 0x00000040 663 /* note that a response size flag of zero is reserved! */ 664 #define ICB2400_OPT3_RSPSZ_MASK 0x00000030 665 #define ICB2400_OPT3_RSPSZ_12 0x00000010 666 #define ICB2400_OPT3_RSPSZ_24 0x00000020 667 #define ICB2400_OPT3_RSPSZ_32 0x00000030 668 #define ICB2400_OPT3_SOFTID 0x00000002 669 670 #define ICB_MIN_FRMLEN 256 671 #define ICB_MAX_FRMLEN 2112 672 #define ICB_DFLT_FRMLEN 1024 673 #define ICB_DFLT_FRMLEN_28XX 2048 674 #define ICB_DFLT_RDELAY 5 675 #define ICB_DFLT_RCOUNT 3 676 677 #define ICB_LOGIN_TOV 10 678 #define ICB_LUN_ENABLE_TOV 15 679 680 681 /* 682 * And somebody at QLogic had a great idea that you could just change 683 * the structure *and* keep the version number the same as the other cards. 684 */ 685 typedef struct { 686 uint16_t icb_version; 687 uint16_t icb_reserved0; 688 uint16_t icb_maxfrmlen; 689 uint16_t icb_execthrottle; 690 uint16_t icb_xchgcnt; 691 uint16_t icb_hardaddr; 692 uint8_t icb_portname[8]; 693 uint8_t icb_nodename[8]; 694 uint16_t icb_rspnsin; 695 uint16_t icb_rqstout; 696 uint16_t icb_retry_count; 697 uint16_t icb_priout; 698 uint16_t icb_rsltqlen; 699 uint16_t icb_rqstqlen; 700 uint16_t icb_ldn_nols; 701 uint16_t icb_prqstqlen; 702 uint16_t icb_rqstaddr[4]; 703 uint16_t icb_respaddr[4]; 704 uint16_t icb_priaddr[4]; 705 uint16_t icb_msixresp; 706 uint16_t icb_msixatio; 707 uint16_t icb_reserved1[2]; 708 uint16_t icb_atio_in; 709 uint16_t icb_atioqlen; 710 uint16_t icb_atioqaddr[4]; 711 uint16_t icb_idelaytimer; 712 uint16_t icb_logintime; 713 uint32_t icb_fwoptions1; 714 uint32_t icb_fwoptions2; 715 uint32_t icb_fwoptions3; 716 uint16_t icb_qos; 717 uint16_t icb_reserved2[3]; 718 uint8_t icb_enodemac[6]; 719 uint16_t icb_disctime; 720 uint16_t icb_reserved3[4]; 721 } isp_icb_2400_t; 722 723 #define RQRSP_ADDR0015 0 724 #define RQRSP_ADDR1631 1 725 #define RQRSP_ADDR3247 2 726 #define RQRSP_ADDR4863 3 727 728 729 #define ICB_NNM0 7 730 #define ICB_NNM1 6 731 #define ICB_NNM2 5 732 #define ICB_NNM3 4 733 #define ICB_NNM4 3 734 #define ICB_NNM5 2 735 #define ICB_NNM6 1 736 #define ICB_NNM7 0 737 738 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 739 array[ICB_NNM0] = (uint8_t) ((wwn >> 0) & 0xff), \ 740 array[ICB_NNM1] = (uint8_t) ((wwn >> 8) & 0xff), \ 741 array[ICB_NNM2] = (uint8_t) ((wwn >> 16) & 0xff), \ 742 array[ICB_NNM3] = (uint8_t) ((wwn >> 24) & 0xff), \ 743 array[ICB_NNM4] = (uint8_t) ((wwn >> 32) & 0xff), \ 744 array[ICB_NNM5] = (uint8_t) ((wwn >> 40) & 0xff), \ 745 array[ICB_NNM6] = (uint8_t) ((wwn >> 48) & 0xff), \ 746 array[ICB_NNM7] = (uint8_t) ((wwn >> 56) & 0xff) 747 748 #define MAKE_WWN_FROM_NODE_NAME(wwn, array) \ 749 wwn = ((uint64_t) array[ICB_NNM0]) | \ 750 ((uint64_t) array[ICB_NNM1] << 8) | \ 751 ((uint64_t) array[ICB_NNM2] << 16) | \ 752 ((uint64_t) array[ICB_NNM3] << 24) | \ 753 ((uint64_t) array[ICB_NNM4] << 32) | \ 754 ((uint64_t) array[ICB_NNM5] << 40) | \ 755 ((uint64_t) array[ICB_NNM6] << 48) | \ 756 ((uint64_t) array[ICB_NNM7] << 56) 757 758 759 /* 760 * For MULTI_ID firmware, this describes a 761 * virtual port entity for getting status. 762 */ 763 typedef struct { 764 uint16_t vp_port_status; 765 uint8_t vp_port_options; 766 uint8_t vp_port_loopid; 767 uint8_t vp_port_portname[8]; 768 uint8_t vp_port_nodename[8]; 769 uint16_t vp_port_portid_lo; /* not present when trailing icb */ 770 uint16_t vp_port_portid_hi; /* not present when trailing icb */ 771 } vp_port_info_t; 772 773 #define ICB2400_VPOPT_ENA_SNSLOGIN 0x00000040 /* Enable SNS Login and SCR for Virtual Ports */ 774 #define ICB2400_VPOPT_TGT_DISABLE 0x00000020 /* Target Mode Disabled */ 775 #define ICB2400_VPOPT_INI_ENABLE 0x00000010 /* Initiator Mode Enabled */ 776 #define ICB2400_VPOPT_ENABLED 0x00000008 /* VP Enabled */ 777 #define ICB2400_VPOPT_NOPLAY 0x00000004 /* ID Not Acquired */ 778 #define ICB2400_VPOPT_PREV_ADDRESS 0x00000002 /* Previously Assigned ID */ 779 #define ICB2400_VPOPT_HARD_ADDRESS 0x00000001 /* Hard Assigned ID */ 780 781 #define ICB2400_VPOPT_WRITE_SIZE 20 782 783 /* 784 * For MULTI_ID firmware, we append this structure 785 * to the isp_icb_2400_t above, followed by a list 786 * structures that are *most* of the vp_port_info_t. 787 */ 788 typedef struct { 789 uint16_t vp_count; 790 uint16_t vp_global_options; 791 } isp_icb_2400_vpinfo_t; 792 793 #define ICB2400_VPINFO_OFF 0x80 /* offset from start of ICB */ 794 #define ICB2400_VPINFO_PORT_OFF(chan) \ 795 (ICB2400_VPINFO_OFF + \ 796 sizeof (isp_icb_2400_vpinfo_t) + ((chan) * ICB2400_VPOPT_WRITE_SIZE)) 797 798 #define ICB2400_VPGOPT_FCA 0x01 /* Assume Clean Address bit in FLOGI ACC set (works only in static configurations) */ 799 #define ICB2400_VPGOPT_MID_DISABLE 0x02 /* when set, connection mode2 will work with NPIV-capable switched */ 800 #define ICB2400_VPGOPT_VP0_DECOUPLE 0x04 /* Allow VP0 decoupling if firmware supports it */ 801 #define ICB2400_VPGOPT_SUSP_FDISK 0x10 /* Suspend FDISC for Enabled VPs */ 802 #define ICB2400_VPGOPT_GEN_RIDA 0x20 /* Generate RIDA if FLOGI Fails */ 803 804 typedef struct { 805 isphdr_t vp_ctrl_hdr; 806 uint32_t vp_ctrl_handle; 807 uint16_t vp_ctrl_index_fail; 808 uint16_t vp_ctrl_status; 809 uint16_t vp_ctrl_command; 810 uint16_t vp_ctrl_vp_count; 811 uint16_t vp_ctrl_idmap[16]; 812 uint16_t vp_ctrl_reserved[7]; 813 uint16_t vp_ctrl_fcf_index; 814 } vp_ctrl_info_t; 815 816 #define VP_CTRL_CMD_ENABLE_VP 0x00 817 #define VP_CTRL_CMD_DISABLE_VP 0x08 818 #define VP_CTRL_CMD_DISABLE_VP_REINIT_LINK 0x09 819 #define VP_CTRL_CMD_DISABLE_VP_LOGO 0x0A 820 #define VP_CTRL_CMD_DISABLE_VP_LOGO_ALL 0x0B 821 822 /* 823 * We can use this structure for modifying either one or two VP ports after initialization 824 */ 825 typedef struct { 826 isphdr_t vp_mod_hdr; 827 uint32_t vp_mod_hdl; 828 uint16_t vp_mod_reserved0; 829 uint16_t vp_mod_status; 830 uint8_t vp_mod_cmd; 831 uint8_t vp_mod_cnt; 832 uint8_t vp_mod_idx0; 833 uint8_t vp_mod_idx1; 834 struct { 835 uint8_t options; 836 uint8_t loopid; 837 uint16_t reserved1; 838 uint8_t wwpn[8]; 839 uint8_t wwnn[8]; 840 } vp_mod_ports[2]; 841 uint8_t vp_mod_reserved2[8]; 842 } vp_modify_t; 843 844 #define VP_STS_OK 0x00 845 #define VP_STS_ERR 0x01 846 #define VP_CNT_ERR 0x02 847 #define VP_GEN_ERR 0x03 848 #define VP_IDX_ERR 0x04 849 #define VP_STS_BSY 0x05 850 851 #define VP_MODIFY 0x00 852 #define VP_MODIFY_ENA 0x01 853 #define VP_MODIFY_OPT 0x02 854 #define VP_RESUME 0x03 855 856 /* 857 * Port Data Base Element 858 */ 859 860 #define SVC3_ROLE_MASK 0x30 861 #define SVC3_ROLE_SHIFT 4 862 863 #define BITS2WORD_24XX(x) ((x)[0] << 16 | (x)[1] << 8 | (x)[2]) 864 865 /* 866 * Port Data Base Element- 24XX cards 867 */ 868 typedef struct { 869 uint16_t pdb_flags; 870 uint8_t pdb_curstate; 871 uint8_t pdb_laststate; 872 uint8_t pdb_hardaddr_bits[4]; 873 uint8_t pdb_portid_bits[4]; 874 #define pdb_nxt_seqid_2400 pdb_portid_bits[3] 875 uint16_t pdb_retry_timer; 876 uint16_t pdb_handle; 877 uint16_t pdb_rcv_dsize; 878 uint16_t pdb_reserved0; 879 uint16_t pdb_prli_svc0; 880 uint16_t pdb_prli_svc3; 881 uint8_t pdb_portname[8]; 882 uint8_t pdb_nodename[8]; 883 uint8_t pdb_reserved1[24]; 884 } isp_pdb_24xx_t; 885 886 #define PDB2400_TID_SUPPORTED 0x4000 887 #define PDB2400_FC_TAPE 0x0080 888 #define PDB2400_CLASS2_ACK0 0x0040 889 #define PDB2400_FCP_CONF 0x0020 890 #define PDB2400_CLASS2 0x0010 891 #define PDB2400_ADDR_VALID 0x0002 892 893 /* 894 * For NVMe, the state is the high nibble. For FCP, the state is the low 895 * nibble. This appears to have changed with the 9.x firmware. 896 */ 897 #define PDB2400_STATE_PLOGI_PEND 0x03 898 #define PDB2400_STATE_PLOGI_DONE 0x04 899 #define PDB2400_STATE_PRLI_PEND 0x05 900 #define PDB2400_STATE_LOGGED_IN 0x06 901 #define PDB2400_STATE_PORT_UNAVAIL 0x07 902 #define PDB2400_STATE_PRLO_PEND 0x09 903 #define PDB2400_STATE_LOGO_PEND 0x0B 904 #define PDB2400_STATE_FCP_MASK 0x0f 905 #define PDB2400_STATE_NVME_SHIFT 4 906 907 /* 908 * Common elements from the above two structures that are actually useful to us. 909 */ 910 typedef struct { 911 uint16_t handle; 912 uint16_t prli_word0; 913 uint16_t prli_word3; 914 uint32_t : 8, 915 portid : 24; 916 uint8_t portname[8]; 917 uint8_t nodename[8]; 918 } isp_pdb_t; 919 920 /* 921 * Port and N-Port Handle List Element 922 */ 923 typedef struct { 924 uint16_t pnhle_port_id_lo; 925 uint16_t pnhle_port_id_hi; 926 uint16_t pnhle_handle; 927 uint16_t pnhle_reserved; 928 } isp_pnhle_24xx_t; 929 930 /* 931 * Port Database Changed Async Event information for 24XX cards 932 */ 933 /* N-Port Handle */ 934 #define PDB24XX_AE_GLOBAL 0xFFFF 935 936 /* Reason Codes */ 937 #define PDB24XX_AE_OK 0x00 938 #define PDB24XX_AE_IMPL_LOGO_1 0x01 939 #define PDB24XX_AE_IMPL_LOGO_2 0x02 940 #define PDB24XX_AE_IMPL_LOGO_3 0x03 941 #define PDB24XX_AE_PLOGI_RCVD 0x04 942 #define PDB24XX_AE_PLOGI_RJT 0x05 943 #define PDB24XX_AE_PRLI_RCVD 0x06 944 #define PDB24XX_AE_PRLI_RJT 0x07 945 #define PDB24XX_AE_TPRLO 0x08 946 #define PDB24XX_AE_TPRLO_RJT 0x09 947 #define PDB24XX_AE_PRLO_RCVD 0x0a 948 #define PDB24XX_AE_LOGO_RCVD 0x0b 949 #define PDB24XX_AE_TOPO_CHG 0x0c 950 #define PDB24XX_AE_NPORT_CHG 0x0d 951 #define PDB24XX_AE_FLOGI_RJT 0x0e 952 #define PDB24XX_AE_BAD_FANN 0x0f 953 #define PDB24XX_AE_FLOGI_TIMO 0x10 954 #define PDB24XX_AE_ABX_LOGO 0x11 955 #define PDB24XX_AE_PLOGI_DONE 0x12 956 #define PDB24XX_AE_PRLI_DONE 0x13 957 #define PDB24XX_AE_OPN_1 0x14 958 #define PDB24XX_AE_OPN_2 0x15 959 #define PDB24XX_AE_TXERR 0x16 960 #define PDB24XX_AE_FORCED_LOGO 0x17 961 #define PDB24XX_AE_DISC_TIMO 0x18 962 963 /* 964 * Genericized Port Login/Logout software structure 965 */ 966 typedef struct { 967 uint16_t handle; 968 uint16_t channel; 969 uint32_t 970 flags : 8, 971 portid : 24; 972 } isp_plcmd_t; 973 /* the flags to use are those for PLOGX_FLG_* below */ 974 975 /* 976 * ISP24XX- Login/Logout Port IOCB 977 */ 978 typedef struct { 979 isphdr_t plogx_header; 980 uint32_t plogx_handle; 981 uint16_t plogx_status; 982 uint16_t plogx_nphdl; 983 uint16_t plogx_flags; 984 uint16_t plogx_vphdl; /* low 8 bits */ 985 uint16_t plogx_portlo; /* low 16 bits */ 986 uint16_t plogx_rspsz_porthi; 987 struct { 988 uint16_t lo16; 989 uint16_t hi16; 990 } plogx_ioparm[11]; 991 } isp_plogx_t; 992 993 #define PLOGX_STATUS_OK 0x00 994 #define PLOGX_STATUS_UNAVAIL 0x28 995 #define PLOGX_STATUS_LOGOUT 0x29 996 #define PLOGX_STATUS_IOCBERR 0x31 997 998 #define PLOGX_IOCBERR_NOLINK 0x01 999 #define PLOGX_IOCBERR_NOIOCB 0x02 1000 #define PLOGX_IOCBERR_NOXGHG 0x03 1001 #define PLOGX_IOCBERR_FAILED 0x04 /* further info in IOPARM 1 */ 1002 #define PLOGX_IOCBERR_NOFABRIC 0x05 1003 #define PLOGX_IOCBERR_NOTREADY 0x07 1004 #define PLOGX_IOCBERR_NOLOGIN 0x09 /* further info in IOPARM 1 */ 1005 #define PLOGX_IOCBERR_NOPCB 0x0a 1006 #define PLOGX_IOCBERR_REJECT 0x18 /* further info in IOPARM 1 */ 1007 #define PLOGX_IOCBERR_EINVAL 0x19 /* further info in IOPARM 1 */ 1008 #define PLOGX_IOCBERR_PORTUSED 0x1a /* further info in IOPARM 1 */ 1009 #define PLOGX_IOCBERR_HNDLUSED 0x1b /* further info in IOPARM 1 */ 1010 #define PLOGX_IOCBERR_NOHANDLE 0x1c 1011 #define PLOGX_IOCBERR_NOFLOGI 0x1f /* further info in IOPARM 1 */ 1012 1013 #define PLOGX_FLG_CMD_MASK 0xf 1014 #define PLOGX_FLG_CMD_PLOGI 0 1015 #define PLOGX_FLG_CMD_PRLI 1 1016 #define PLOGX_FLG_CMD_PDISC 2 1017 #define PLOGX_FLG_CMD_LOGO 8 1018 #define PLOGX_FLG_CMD_PRLO 9 1019 #define PLOGX_FLG_CMD_TPRLO 10 1020 1021 #define PLOGX_FLG_COND_PLOGI 0x10 /* if with PLOGI */ 1022 #define PLOGX_FLG_IMPLICIT 0x10 /* if with LOGO, PRLO, TPRLO */ 1023 #define PLOGX_FLG_SKIP_PRLI 0x20 /* if with PLOGI */ 1024 #define PLOGX_FLG_IMPLICIT_LOGO_ALL 0x20 /* if with LOGO */ 1025 #define PLOGX_FLG_EXPLICIT_LOGO 0x40 /* if with LOGO */ 1026 #define PLOGX_FLG_COMMON_FEATURES 0x80 /* if with PLOGI */ 1027 #define PLOGX_FLG_FREE_NPHDL 0x80 /* if with with LOGO */ 1028 1029 #define PLOGX_FLG_CLASS2 0x100 /* if with PLOGI */ 1030 #define PLOGX_FLG_FCP2_OVERRIDE 0x200 /* if with PRLOG, PRLI */ 1031 1032 /* 1033 * Report ID Acquisistion (24XX multi-id firmware) 1034 */ 1035 typedef struct { 1036 isphdr_t ridacq_hdr; 1037 uint32_t ridacq_handle; 1038 uint8_t ridacq_vp_acquired; 1039 uint8_t ridacq_vp_setup; 1040 uint8_t ridacq_vp_index; 1041 uint8_t ridacq_vp_status; 1042 uint16_t ridacq_vp_port_lo; 1043 uint8_t ridacq_vp_port_hi; 1044 uint8_t ridacq_format; /* 0 or 1 */ 1045 uint16_t ridacq_map[8]; 1046 uint8_t ridacq_reserved1[32]; 1047 } isp_ridacq_t; 1048 1049 #define RIDACQ_STS_COMPLETE 0 1050 #define RIDACQ_STS_UNACQUIRED 1 1051 #define RIDACQ_STS_CHANGED 2 1052 #define RIDACQ_STS_SNS_TIMEOUT 3 1053 #define RIDACQ_STS_SNS_REJECTED 4 1054 #define RIDACQ_STS_SCR_TIMEOUT 5 1055 #define RIDACQ_STS_SCR_REJECTED 6 1056 1057 /* 1058 * Simple Name Server Data Structures 1059 */ 1060 #define SNS_GA_NXT 0x100 1061 #define SNS_GPN_ID 0x112 1062 #define SNS_GNN_ID 0x113 1063 #define SNS_GFT_ID 0x117 1064 #define SNS_GFF_ID 0x11F 1065 #define SNS_GID_FT 0x171 1066 #define SNS_GID_PT 0x1A1 1067 #define SNS_RFT_ID 0x217 1068 #define SNS_RSPN_ID 0x218 1069 #define SNS_RFF_ID 0x21F 1070 #define SNS_RSNN_NN 0x239 1071 typedef struct { 1072 uint16_t snscb_rblen; /* response buffer length (words) */ 1073 uint16_t snscb_reserved0; 1074 uint16_t snscb_addr[4]; /* response buffer address */ 1075 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1076 uint16_t snscb_reserved1; 1077 uint16_t snscb_data[]; /* variable data */ 1078 } sns_screq_t; /* Subcommand Request Structure */ 1079 1080 typedef struct { 1081 uint16_t snscb_rblen; /* response buffer length (words) */ 1082 uint16_t snscb_reserved0; 1083 uint16_t snscb_addr[4]; /* response buffer address */ 1084 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1085 uint16_t snscb_reserved1; 1086 uint16_t snscb_cmd; 1087 uint16_t snscb_reserved2; 1088 uint32_t snscb_reserved3; 1089 uint32_t snscb_port; 1090 } sns_ga_nxt_req_t; 1091 #define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t)) 1092 1093 typedef struct { /* Used for GFT_ID, GFF_ID, etc. */ 1094 uint16_t snscb_rblen; /* response buffer length (words) */ 1095 uint16_t snscb_reserved0; 1096 uint16_t snscb_addr[4]; /* response buffer address */ 1097 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1098 uint16_t snscb_reserved1; 1099 uint16_t snscb_cmd; 1100 uint16_t snscb_mword_div_2; 1101 uint32_t snscb_reserved3; 1102 uint32_t snscb_portid; 1103 } sns_gxx_id_req_t; 1104 #define SNS_GXX_ID_REQ_SIZE (sizeof (sns_gxx_id_req_t)) 1105 1106 typedef struct { 1107 uint16_t snscb_rblen; /* response buffer length (words) */ 1108 uint16_t snscb_reserved0; 1109 uint16_t snscb_addr[4]; /* response buffer address */ 1110 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1111 uint16_t snscb_reserved1; 1112 uint16_t snscb_cmd; 1113 uint16_t snscb_mword_div_2; 1114 uint32_t snscb_reserved3; 1115 uint32_t snscb_fc4_type; 1116 } sns_gid_ft_req_t; 1117 #define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t)) 1118 1119 typedef struct { 1120 uint16_t snscb_rblen; /* response buffer length (words) */ 1121 uint16_t snscb_reserved0; 1122 uint16_t snscb_addr[4]; /* response buffer address */ 1123 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1124 uint16_t snscb_reserved1; 1125 uint16_t snscb_cmd; 1126 uint16_t snscb_mword_div_2; 1127 uint32_t snscb_reserved3; 1128 uint8_t snscb_port_type; 1129 uint8_t snscb_domain; 1130 uint8_t snscb_area; 1131 uint8_t snscb_flags; 1132 } sns_gid_pt_req_t; 1133 #define SNS_GID_PT_REQ_SIZE (sizeof (sns_gid_pt_req_t)) 1134 1135 typedef struct { 1136 uint16_t snscb_rblen; /* response buffer length (words) */ 1137 uint16_t snscb_reserved0; 1138 uint16_t snscb_addr[4]; /* response buffer address */ 1139 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 1140 uint16_t snscb_reserved1; 1141 uint16_t snscb_cmd; 1142 uint16_t snscb_reserved2; 1143 uint32_t snscb_reserved3; 1144 uint32_t snscb_port; 1145 uint32_t snscb_fc4_types[8]; 1146 } sns_rft_id_req_t; 1147 #define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t)) 1148 1149 typedef struct { 1150 ct_hdr_t snscb_cthdr; 1151 uint8_t snscb_port_type; 1152 uint8_t snscb_port_id[3]; 1153 uint8_t snscb_portname[8]; 1154 uint16_t snscb_data[]; /* variable data */ 1155 } sns_scrsp_t; /* Subcommand Response Structure */ 1156 1157 typedef struct { 1158 ct_hdr_t snscb_cthdr; 1159 uint8_t snscb_port_type; 1160 uint8_t snscb_port_id[3]; 1161 uint8_t snscb_portname[8]; 1162 uint8_t snscb_pnlen; /* symbolic port name length */ 1163 uint8_t snscb_pname[255]; /* symbolic port name */ 1164 uint8_t snscb_nodename[8]; 1165 uint8_t snscb_nnlen; /* symbolic node name length */ 1166 uint8_t snscb_nname[255]; /* symbolic node name */ 1167 uint8_t snscb_ipassoc[8]; 1168 uint8_t snscb_ipaddr[16]; 1169 uint8_t snscb_svc_class[4]; 1170 uint8_t snscb_fc4_types[32]; 1171 uint8_t snscb_fpname[8]; 1172 uint8_t snscb_reserved; 1173 uint8_t snscb_hardaddr[3]; 1174 } sns_ga_nxt_rsp_t; /* Subcommand Response Structure */ 1175 #define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t)) 1176 1177 typedef struct { 1178 ct_hdr_t snscb_cthdr; 1179 uint8_t snscb_wwn[8]; 1180 } sns_gxn_id_rsp_t; 1181 #define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t)) 1182 1183 typedef struct { 1184 ct_hdr_t snscb_cthdr; 1185 uint32_t snscb_fc4_types[8]; 1186 } sns_gft_id_rsp_t; 1187 #define SNS_GFT_ID_RESP_SIZE (sizeof (sns_gft_id_rsp_t)) 1188 1189 typedef struct { 1190 ct_hdr_t snscb_cthdr; 1191 uint32_t snscb_fc4_features[32]; 1192 } sns_gff_id_rsp_t; 1193 #define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t)) 1194 1195 typedef struct { /* Used for GID_FT, GID_PT, etc. */ 1196 ct_hdr_t snscb_cthdr; 1197 struct { 1198 uint8_t control; 1199 uint8_t portid[3]; 1200 } snscb_ports[1]; 1201 } sns_gid_xx_rsp_t; 1202 #define SNS_GID_XX_RESP_SIZE(x) ((sizeof (sns_gid_xx_rsp_t)) + ((x - 1) << 2)) 1203 1204 /* 1205 * Other Misc Structures 1206 */ 1207 1208 /* ELS Pass Through */ 1209 typedef struct { 1210 isphdr_t els_hdr; 1211 uint32_t els_handle; 1212 uint16_t els_status; 1213 uint16_t els_nphdl; 1214 uint16_t els_xmit_dsd_count; /* outgoing only */ 1215 uint8_t els_vphdl; 1216 uint8_t els_sof; 1217 uint32_t els_rxid; 1218 uint16_t els_recv_dsd_count; /* outgoing only */ 1219 uint8_t els_opcode; 1220 uint8_t els_reserved1; 1221 uint8_t els_did_lo; 1222 uint8_t els_did_mid; 1223 uint8_t els_did_hi; 1224 uint8_t els_reserved2; 1225 uint16_t els_reserved3; 1226 uint16_t els_ctl_flags; 1227 union { 1228 struct { 1229 uint32_t _els_bytecnt; 1230 uint32_t _els_subcode1; 1231 uint32_t _els_subcode2; 1232 uint8_t _els_reserved4[20]; 1233 } in; 1234 struct { 1235 uint32_t _els_recv_bytecnt; 1236 uint32_t _els_xmit_bytecnt; 1237 uint32_t _els_xmit_dsd_length; 1238 uint16_t _els_xmit_dsd_a1500; 1239 uint16_t _els_xmit_dsd_a3116; 1240 uint16_t _els_xmit_dsd_a4732; 1241 uint16_t _els_xmit_dsd_a6348; 1242 uint32_t _els_recv_dsd_length; 1243 uint16_t _els_recv_dsd_a1500; 1244 uint16_t _els_recv_dsd_a3116; 1245 uint16_t _els_recv_dsd_a4732; 1246 uint16_t _els_recv_dsd_a6348; 1247 } out; 1248 } inout; 1249 #define els_bytecnt inout.in._els_bytecnt 1250 #define els_subcode1 inout.in._els_subcode1 1251 #define els_subcode2 inout.in._els_subcode2 1252 #define els_reserved4 inout.in._els_reserved4 1253 #define els_recv_bytecnt inout.out._els_recv_bytecnt 1254 #define els_xmit_bytecnt inout.out._els_xmit_bytecnt 1255 #define els_xmit_dsd_length inout.out._els_xmit_dsd_length 1256 #define els_xmit_dsd_a1500 inout.out._els_xmit_dsd_a1500 1257 #define els_xmit_dsd_a3116 inout.out._els_xmit_dsd_a3116 1258 #define els_xmit_dsd_a4732 inout.out._els_xmit_dsd_a4732 1259 #define els_xmit_dsd_a6348 inout.out._els_xmit_dsd_a6348 1260 #define els_recv_dsd_length inout.out._els_recv_dsd_length 1261 #define els_recv_dsd_a1500 inout.out._els_recv_dsd_a1500 1262 #define els_recv_dsd_a3116 inout.out._els_recv_dsd_a3116 1263 #define els_recv_dsd_a4732 inout.out._els_recv_dsd_a4732 1264 #define els_recv_dsd_a6348 inout.out._els_recv_dsd_a6348 1265 } els_t; 1266 1267 /* 1268 * Target Mode related definitions 1269 */ 1270 1271 /* 1272 * ISP24XX Immediate Notify 1273 */ 1274 typedef struct { 1275 isphdr_t in_header; 1276 uint32_t in_reserved; 1277 uint16_t in_nphdl; 1278 uint16_t in_reserved1; 1279 uint16_t in_flags; 1280 uint16_t in_srr_rxid; 1281 uint16_t in_status; 1282 uint8_t in_status_subcode; 1283 uint8_t in_fwhandle; 1284 uint32_t in_rxid; 1285 uint16_t in_srr_reloff_lo; 1286 uint16_t in_srr_reloff_hi; 1287 uint16_t in_srr_iu; 1288 uint16_t in_srr_oxid; 1289 /* 1290 * If bit 2 is set in in_flags, the N-Port and 1291 * handle tags are valid. If the received ELS is 1292 * a LOGO, then these tags contain the N Port ID 1293 * from the LOGO payload. If the received ELS 1294 * request is TPRLO, these tags contain the 1295 * Third Party Originator N Port ID. 1296 */ 1297 uint16_t in_nport_id_hi; 1298 #define in_prli_options in_nport_id_hi 1299 uint8_t in_nport_id_lo; 1300 uint8_t in_reserved3; 1301 uint16_t in_np_handle; 1302 uint8_t in_reserved4[12]; 1303 uint8_t in_reserved5; 1304 uint8_t in_vpidx; 1305 uint32_t in_reserved6; 1306 uint16_t in_portid_lo; 1307 uint8_t in_portid_hi; 1308 uint8_t in_reserved7; 1309 uint16_t in_reserved8; 1310 uint16_t in_oxid; 1311 } in_fcentry_24xx_t; 1312 1313 #define IN24XX_FLAG_PUREX_IOCB 0x1 1314 #define IN24XX_FLAG_GLOBAL_LOGOUT 0x2 1315 #define IN24XX_FLAG_NPHDL_VALID 0x4 1316 #define IN24XX_FLAG_N2N_PRLI 0x8 1317 #define IN24XX_FLAG_PN_NN_VALID 0x10 1318 1319 #define IN24XX_LIP_RESET 0x0E 1320 #define IN24XX_LINK_RESET 0x0F 1321 #define IN24XX_PORT_LOGOUT 0x29 1322 #define IN24XX_PORT_CHANGED 0x2A 1323 #define IN24XX_LINK_FAILED 0x2E 1324 #define IN24XX_SRR_RCVD 0x45 1325 #define IN24XX_ELS_RCVD 0x46 /* 1326 * login-affectin ELS received- check 1327 * subcode for specific opcode 1328 */ 1329 1330 /* 1331 * For f/w > 4.0.25, these offsets in the Immediate Notify contain 1332 * the WWNN/WWPN if the ELS is PLOGI, PDISC or ADISC. The WWN is in 1333 * Big Endian format. 1334 */ 1335 #define IN24XX_PRLI_WWNN_OFF 0x18 1336 #define IN24XX_PRLI_WWPN_OFF 0x28 1337 #define IN24XX_PLOGI_WWNN_OFF 0x20 1338 #define IN24XX_PLOGI_WWPN_OFF 0x28 1339 1340 /* 1341 * For f/w > 4.0.25, this offset in the Immediate Notify contain 1342 * the WWPN if the ELS is LOGO. The WWN is in Big Endian format. 1343 */ 1344 #define IN24XX_LOGO_WWPN_OFF 0x28 1345 1346 /* 1347 * Immediate Notify Status Subcodes for IN24XX_PORT_LOGOUT 1348 */ 1349 #define IN24XX_PORT_LOGOUT_PDISC_TMO 0x00 1350 #define IN24XX_PORT_LOGOUT_UXPR_DISC 0x01 1351 #define IN24XX_PORT_LOGOUT_OWN_OPN 0x02 1352 #define IN24XX_PORT_LOGOUT_OWN_OPN_SFT 0x03 1353 #define IN24XX_PORT_LOGOUT_ABTS_TMO 0x04 1354 #define IN24XX_PORT_LOGOUT_DISC_RJT 0x05 1355 #define IN24XX_PORT_LOGOUT_LOGIN_NEEDED 0x06 1356 #define IN24XX_PORT_LOGOUT_BAD_DISC 0x07 1357 #define IN24XX_PORT_LOGOUT_LOST_ALPA 0x08 1358 #define IN24XX_PORT_LOGOUT_XMIT_FAILURE 0x09 1359 1360 /* 1361 * Immediate Notify Status Subcodes for IN24XX_PORT_CHANGED 1362 */ 1363 #define IN24XX_PORT_CHANGED_BADFAN 0x00 1364 #define IN24XX_PORT_CHANGED_TOPO_CHANGE 0x01 1365 #define IN24XX_PORT_CHANGED_FLOGI_ACC 0x02 1366 #define IN24XX_PORT_CHANGED_FLOGI_RJT 0x03 1367 #define IN24XX_PORT_CHANGED_TIMEOUT 0x04 1368 #define IN24XX_PORT_CHANGED_PORT_CHANGE 0x05 1369 1370 /* 1371 * ISP24XX Notify Acknowledge 1372 */ 1373 #define NA_OK 0x01 /* Notify Acknowledge Succeeded */ 1374 typedef struct { 1375 isphdr_t na_header; 1376 uint32_t na_handle; 1377 uint16_t na_nphdl; 1378 uint16_t na_reserved1; 1379 uint16_t na_flags; 1380 uint16_t na_srr_rxid; 1381 uint16_t na_status; 1382 uint8_t na_status_subcode; 1383 uint8_t na_fwhandle; 1384 uint32_t na_rxid; 1385 uint16_t na_srr_reloff_lo; 1386 uint16_t na_srr_reloff_hi; 1387 uint16_t na_srr_iu; 1388 uint16_t na_srr_flags; 1389 uint8_t na_reserved3[18]; 1390 uint8_t na_reserved4; 1391 uint8_t na_vpidx; 1392 uint8_t na_srr_reject_vunique; 1393 uint8_t na_srr_reject_explanation; 1394 uint8_t na_srr_reject_code; 1395 uint8_t na_reserved5; 1396 uint8_t na_reserved6[6]; 1397 uint16_t na_oxid; 1398 } na_fcentry_24xx_t; 1399 1400 /* 1401 * 24XX ATIO Definition 1402 * 1403 * This is *quite* different from other entry types. 1404 * First of all, it has its own queue it comes in on. 1405 * 1406 * Secondly, it doesn't have a normal header. 1407 * 1408 * Thirdly, it's just a passthru of the FCP CMND IU 1409 * which is recorded in big endian mode. 1410 */ 1411 typedef struct { 1412 uint8_t at_type; 1413 uint8_t at_count; 1414 /* 1415 * Task attribute in high four bits, 1416 * the rest is the FCP CMND IU Length. 1417 * NB: the command can extend past the 1418 * length for a single queue entry. 1419 */ 1420 uint16_t at_ta_len; 1421 uint32_t at_rxid; 1422 fc_hdr_t at_hdr; 1423 fcp_cmnd_iu_t at_cmnd; 1424 } at7_entry_t; 1425 #define AT7_NORESRC_RXID 0xffffffff 1426 1427 #define CT_HBA_RESET 0xffff /* pseudo error - command destroyed by HBA reset*/ 1428 1429 /* 1430 * ISP24XX CTIO 1431 */ 1432 #define MAXRESPLEN_24XX 24 1433 typedef struct { 1434 isphdr_t ct_header; 1435 uint32_t ct_syshandle; 1436 uint16_t ct_nphdl; /* status on returned CTIOs */ 1437 uint16_t ct_timeout; 1438 uint16_t ct_seg_count; 1439 uint8_t ct_vpidx; 1440 uint8_t ct_xflags; 1441 uint16_t ct_iid_lo; /* low 16 bits of portid */ 1442 uint8_t ct_iid_hi; /* hi 8 bits of portid */ 1443 uint8_t ct_reserved; 1444 uint32_t ct_rxid; 1445 uint16_t ct_senselen; /* mode 1 only */ 1446 uint16_t ct_flags; 1447 uint32_t ct_resid; /* residual length */ 1448 uint16_t ct_oxid; 1449 uint16_t ct_scsi_status; /* modes 0 && 1 only */ 1450 union { 1451 struct { 1452 uint32_t reloff; 1453 uint32_t reserved0; 1454 uint32_t ct_xfrlen; 1455 uint32_t reserved1; 1456 ispds64_t ds; 1457 } m0; 1458 struct { 1459 uint16_t ct_resplen; 1460 uint16_t reserved; 1461 uint8_t ct_resp[MAXRESPLEN_24XX]; 1462 } m1; 1463 struct { 1464 uint32_t reserved0; 1465 uint32_t reserved1; 1466 uint32_t ct_datalen; 1467 uint32_t reserved2; 1468 ispds64_t ct_fcp_rsp_iudata; 1469 } m2; 1470 } rsp; 1471 } ct7_entry_t; 1472 1473 /* 1474 * ct_flags values for CTIO7 1475 */ 1476 #define CT7_NO_DATA 0x0000 1477 #define CT7_DATA_OUT 0x0001 /* *from* initiator */ 1478 #define CT7_DATA_IN 0x0002 /* *to* initiator */ 1479 #define CT7_DATAMASK 0x3 1480 #define CT7_DSD_ENABLE 0x0004 1481 #define CT7_CONF_STSFD 0x0010 1482 #define CT7_EXPLCT_CONF 0x0020 1483 #define CT7_FLAG_MODE0 0x0000 1484 #define CT7_FLAG_MODE1 0x0040 1485 #define CT7_FLAG_MODE2 0x0080 1486 #define CT7_FLAG_MMASK 0x00C0 1487 #define CT7_NOACK 0x0100 1488 #define CT7_TASK_ATTR_SHIFT 9 1489 #define CT7_CONFIRM 0x2000 1490 #define CT7_TERMINATE 0x4000 1491 #define CT7_SENDSTATUS 0x8000 1492 1493 /* 1494 * Type 7 CTIO status codes 1495 */ 1496 #define CT7_OK 0x01 /* completed without error */ 1497 #define CT7_ABORTED 0x02 /* aborted by host */ 1498 #define CT7_ERR 0x04 /* see sense data for error */ 1499 #define CT7_INVAL 0x06 /* request for disabled lun */ 1500 #define CT7_INVRXID 0x08 /* Invalid RX_ID */ 1501 #define CT7_DATA_OVER 0x09 /* Data Overrun */ 1502 #define CT7_TIMEOUT 0x0B /* timed out */ 1503 #define CT7_RESET 0x0E /* LIP Rset Received */ 1504 #define CT7_BUS_ERROR 0x10 /* DMA PCI Error */ 1505 #define CT7_REASSY_ERR 0x11 /* DMA reassembly error */ 1506 #define CT7_DATA_UNDER 0x15 /* Data Underrun */ 1507 #define CT7_PORTUNAVAIL 0x28 /* port not available */ 1508 #define CT7_LOGOUT 0x29 /* port logout */ 1509 #define CT7_PORTCHANGED 0x2A /* port changed */ 1510 #define CT7_SRR 0x45 /* SRR Received */ 1511 1512 /* 1513 * Other 24XX related target IOCBs 1514 */ 1515 1516 /* 1517 * ABTS Received 1518 */ 1519 typedef struct { 1520 isphdr_t abts_header; 1521 uint8_t abts_reserved0[6]; 1522 uint16_t abts_nphdl; 1523 uint16_t abts_reserved1; 1524 uint16_t abts_sof; 1525 uint32_t abts_rxid_abts; 1526 uint16_t abts_did_lo; 1527 uint8_t abts_did_hi; 1528 uint8_t abts_r_ctl; 1529 uint16_t abts_sid_lo; 1530 uint8_t abts_sid_hi; 1531 uint8_t abts_cs_ctl; 1532 uint16_t abts_fs_ctl; 1533 uint8_t abts_f_ctl; 1534 uint8_t abts_type; 1535 uint16_t abts_seq_cnt; 1536 uint8_t abts_df_ctl; 1537 uint8_t abts_seq_id; 1538 uint16_t abts_rx_id; 1539 uint16_t abts_ox_id; 1540 uint32_t abts_param; 1541 uint8_t abts_reserved2[16]; 1542 uint32_t abts_rxid_task; 1543 } abts_t; 1544 1545 typedef struct { 1546 isphdr_t abts_rsp_header; 1547 uint32_t abts_rsp_handle; 1548 uint16_t abts_rsp_status; 1549 uint16_t abts_rsp_nphdl; 1550 uint16_t abts_rsp_ctl_flags; 1551 uint16_t abts_rsp_sof; 1552 uint32_t abts_rsp_rxid_abts; 1553 uint16_t abts_rsp_did_lo; 1554 uint8_t abts_rsp_did_hi; 1555 uint8_t abts_rsp_r_ctl; 1556 uint16_t abts_rsp_sid_lo; 1557 uint8_t abts_rsp_sid_hi; 1558 uint8_t abts_rsp_cs_ctl; 1559 uint16_t abts_rsp_f_ctl_lo; 1560 uint8_t abts_rsp_f_ctl_hi; 1561 uint8_t abts_rsp_type; 1562 uint16_t abts_rsp_seq_cnt; 1563 uint8_t abts_rsp_df_ctl; 1564 uint8_t abts_rsp_seq_id; 1565 uint16_t abts_rsp_rx_id; 1566 uint16_t abts_rsp_ox_id; 1567 uint32_t abts_rsp_param; 1568 union { 1569 struct { 1570 uint16_t reserved; 1571 uint8_t last_seq_id; 1572 uint8_t seq_id_valid; 1573 uint16_t aborted_rx_id; 1574 uint16_t aborted_ox_id; 1575 uint16_t high_seq_cnt; 1576 uint16_t low_seq_cnt; 1577 uint8_t reserved2[4]; 1578 } ba_acc; 1579 struct { 1580 uint8_t vendor_unique; 1581 uint8_t explanation; 1582 uint8_t reason; 1583 uint8_t reserved; 1584 uint8_t reserved2[12]; 1585 } ba_rjt; 1586 struct { 1587 uint8_t reserved[8]; 1588 uint32_t subcode1; 1589 uint32_t subcode2; 1590 } rsp; 1591 uint8_t reserved[16]; 1592 } abts_rsp_payload; 1593 uint32_t abts_rsp_rxid_task; 1594 } abts_rsp_t; 1595 1596 /* terminate this ABTS exchange */ 1597 #define ISP24XX_ABTS_RSP_TERMINATE 0x01 1598 1599 #define ISP24XX_ABTS_RSP_COMPLETE 0x00 1600 #define ISP24XX_ABTS_RSP_RESET 0x04 1601 #define ISP24XX_ABTS_RSP_ABORTED 0x05 1602 #define ISP24XX_ABTS_RSP_TIMEOUT 0x06 1603 #define ISP24XX_ABTS_RSP_INVXID 0x08 1604 #define ISP24XX_ABTS_RSP_LOGOUT 0x29 1605 #define ISP24XX_ABTS_RSP_SUBCODE 0x31 1606 1607 #define ISP24XX_NO_TASK 0xffffffff 1608 1609 /* 1610 * Miscellaneous 1611 * 1612 * This is the limit of the number of dma segments we can deal with based 1613 * not on the size of the segment counter (which is 16 bits), but on the 1614 * size of the number of queue entries field (which is 8 bits). We assume 1615 * one segment in the first queue entry, plus we can have 5 segments per 1616 * continuation entry, multiplied by maximum of continuation entries. 1617 */ 1618 #define ISP_NSEG64_MAX (1 + (QENTRY_MAX - 1) * 5) 1619 1620 #endif /* _ISPMBOX_H */ 1621