1 /* $FreeBSD$ */ 2 /* 3 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 4 * 5 * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #ifndef _ISPMBOX_H 31 #define _ISPMBOX_H 32 33 /* 34 * Mailbox Command Opcodes 35 */ 36 #define MBOX_NO_OP 0x0000 37 #define MBOX_LOAD_RAM 0x0001 38 #define MBOX_EXEC_FIRMWARE 0x0002 39 #define MBOX_DUMP_RAM 0x0003 40 #define MBOX_WRITE_RAM_WORD 0x0004 41 #define MBOX_READ_RAM_WORD 0x0005 42 #define MBOX_MAILBOX_REG_TEST 0x0006 43 #define MBOX_VERIFY_CHECKSUM 0x0007 44 #define MBOX_ABOUT_FIRMWARE 0x0008 45 /* 9 */ 46 /* a */ 47 /* b */ 48 /* c */ 49 /* d */ 50 #define MBOX_CHECK_FIRMWARE 0x000e 51 /* f */ 52 #define MBOX_INIT_REQ_QUEUE 0x0010 53 #define MBOX_INIT_RES_QUEUE 0x0011 54 #define MBOX_EXECUTE_IOCB 0x0012 55 #define MBOX_WAKE_UP 0x0013 56 #define MBOX_STOP_FIRMWARE 0x0014 57 #define MBOX_ABORT 0x0015 58 #define MBOX_ABORT_DEVICE 0x0016 59 #define MBOX_ABORT_TARGET 0x0017 60 #define MBOX_BUS_RESET 0x0018 61 #define MBOX_STOP_QUEUE 0x0019 62 #define MBOX_START_QUEUE 0x001a 63 #define MBOX_SINGLE_STEP_QUEUE 0x001b 64 #define MBOX_ABORT_QUEUE 0x001c 65 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 66 /* 1e */ 67 #define MBOX_GET_FIRMWARE_STATUS 0x001f 68 #define MBOX_GET_INIT_SCSI_ID 0x0020 69 #define MBOX_GET_SELECT_TIMEOUT 0x0021 70 #define MBOX_GET_RETRY_COUNT 0x0022 71 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 72 #define MBOX_GET_CLOCK_RATE 0x0024 73 #define MBOX_GET_ACT_NEG_STATE 0x0025 74 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 75 #define MBOX_GET_SBUS_PARAMS 0x0027 76 #define MBOX_GET_TARGET_PARAMS 0x0028 77 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 78 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a 79 /* 2b */ 80 /* 2c */ 81 /* 2d */ 82 /* 2e */ 83 /* 2f */ 84 #define MBOX_SET_INIT_SCSI_ID 0x0030 85 #define MBOX_SET_SELECT_TIMEOUT 0x0031 86 #define MBOX_SET_RETRY_COUNT 0x0032 87 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 88 #define MBOX_SET_CLOCK_RATE 0x0034 89 #define MBOX_SET_ACT_NEG_STATE 0x0035 90 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 91 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 92 #define MBOX_SET_PCI_PARAMETERS 0x0037 93 #define MBOX_SET_TARGET_PARAMS 0x0038 94 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 95 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a 96 /* 3b */ 97 /* 3c */ 98 /* 3d */ 99 /* 3e */ 100 /* 3f */ 101 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 102 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 103 #define MBOX_EXEC_BIOS_IOCB 0x0042 104 #define MBOX_SET_FW_FEATURES 0x004a 105 #define MBOX_GET_FW_FEATURES 0x004b 106 #define FW_FEATURE_LVD_NOTIFY 0x2 107 #define FW_FEATURE_FAST_POST 0x1 108 109 #define MBOX_ENABLE_TARGET_MODE 0x55 110 #define ENABLE_TARGET_FLAG 0x8000 111 #define ENABLE_TQING_FLAG 0x0004 112 #define ENABLE_MANDATORY_DISC 0x0002 113 #define MBOX_GET_TARGET_STATUS 0x56 114 115 /* These are for the ISP2100 FC cards */ 116 #define MBOX_GET_LOOP_ID 0x20 117 #define MBOX_GET_RESOURCE_COUNT 0x42 118 #define MBOX_EXEC_COMMAND_IOCB_A64 0x54 119 #define MBOX_INIT_FIRMWARE 0x60 120 #define MBOX_GET_INIT_CONTROL_BLOCK 0x61 121 #define MBOX_INIT_LIP 0x62 122 #define MBOX_GET_FC_AL_POSITION_MAP 0x63 123 #define MBOX_GET_PORT_DB 0x64 124 #define MBOX_CLEAR_ACA 0x65 125 #define MBOX_TARGET_RESET 0x66 126 #define MBOX_CLEAR_TASK_SET 0x67 127 #define MBOX_ABORT_TASK_SET 0x68 128 #define MBOX_GET_FW_STATE 0x69 129 #define MBOX_GET_PORT_NAME 0x6a 130 #define MBOX_GET_LINK_STATUS 0x6b 131 #define MBOX_INIT_LIP_RESET 0x6c 132 #define MBOX_SEND_SNS 0x6e 133 #define MBOX_FABRIC_LOGIN 0x6f 134 #define MBOX_SEND_CHANGE_REQUEST 0x70 135 #define MBOX_FABRIC_LOGOUT 0x71 136 #define MBOX_INIT_LIP_LOGIN 0x72 137 138 #define ISP2100_SET_PCI_PARAM 0x00ff 139 140 #define MBOX_BUSY 0x04 141 142 typedef struct { 143 u_int16_t param[8]; 144 } mbreg_t; 145 146 /* 147 * Mailbox Command Complete Status Codes 148 */ 149 #define MBOX_COMMAND_COMPLETE 0x4000 150 #define MBOX_INVALID_COMMAND 0x4001 151 #define MBOX_HOST_INTERFACE_ERROR 0x4002 152 #define MBOX_TEST_FAILED 0x4003 153 #define MBOX_COMMAND_ERROR 0x4005 154 #define MBOX_COMMAND_PARAM_ERROR 0x4006 155 #define MBOX_PORT_ID_USED 0x4007 156 #define MBOX_LOOP_ID_USED 0x4008 157 #define MBOX_ALL_IDS_USED 0x4009 158 #define MBOX_NOT_LOGGED_IN 0x400A 159 #define MBLOGALL 0x000f 160 #define MBLOGNONE 0x0000 161 #define MBLOGMASK(x) ((x) & 0xf) 162 163 /* 164 * Asynchronous event status codes 165 */ 166 #define ASYNC_BUS_RESET 0x8001 167 #define ASYNC_SYSTEM_ERROR 0x8002 168 #define ASYNC_RQS_XFER_ERR 0x8003 169 #define ASYNC_RSP_XFER_ERR 0x8004 170 #define ASYNC_QWAKEUP 0x8005 171 #define ASYNC_TIMEOUT_RESET 0x8006 172 #define ASYNC_DEVICE_RESET 0x8007 173 #define ASYNC_EXTMSG_UNDERRUN 0x800A 174 #define ASYNC_SCAM_INT 0x800B 175 #define ASYNC_HUNG_SCSI 0x800C 176 #define ASYNC_KILLED_BUS 0x800D 177 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 178 #define ASYNC_LIP_OCCURRED 0x8010 179 #define ASYNC_LOOP_UP 0x8011 180 #define ASYNC_LOOP_DOWN 0x8012 181 #define ASYNC_LOOP_RESET 0x8013 182 #define ASYNC_PDB_CHANGED 0x8014 183 #define ASYNC_CHANGE_NOTIFY 0x8015 184 #define ASYNC_CMD_CMPLT 0x8020 185 #define ASYNC_CTIO_DONE 0x8021 186 #define ASYNC_IP_XMIT_DONE 0x8022 187 #define ASYNC_IP_RECV_DONE 0x8023 188 #define ASYNC_IP_BROADCAST 0x8024 189 #define ASYNC_IP_RCVQ_LOW 0x8025 190 #define ASYNC_IP_RCVQ_EMPTY 0x8026 191 #define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 192 #define ASYNC_PTPMODE 0x8030 193 #define ASYNC_RIO1 0x8031 194 #define ASYNC_RIO2 0x8032 195 #define ASYNC_RIO3 0x8033 196 #define ASYNC_RIO4 0x8034 197 #define ASYNC_RIO5 0x8035 198 #define ASYNC_CONNMODE 0x8036 199 #define ISP_CONN_LOOP 1 200 #define ISP_CONN_PTP 2 201 #define ISP_CONN_BADLIP 3 202 #define ISP_CONN_FATAL 4 203 #define ISP_CONN_LOOPBACK 5 204 #define ASYNC_RIO_RESP 0x8040 205 #define ASYNC_RIO_COMP 0x8042 206 /* 207 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options 208 * mailbox command to enable this. 209 */ 210 #define ASYNC_QFULL_SENT 0x8049 211 212 /* 213 * Mailbox Usages 214 */ 215 216 #define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \ 217 ISP_WRITE(isp, INMAILBOX4, value) 218 219 #define READ_REQUEST_QUEUE_OUT_POINTER(isp) \ 220 ISP_READ(isp, OUTMAILBOX4) 221 222 #define WRITE_RESPONSE_QUEUE_IN_POINTER(isp, value) \ 223 ISP_WRITE(isp, INMAILBOX5, value) 224 225 #define READ_RESPONSE_QUEUE_OUT_POINTER(isp) \ 226 ISP_READ(isp, OUTMAILBOX5) 227 228 /* 229 * Command Structure Definitions 230 */ 231 232 typedef struct { 233 u_int32_t ds_base; 234 u_int32_t ds_count; 235 } ispds_t; 236 237 typedef struct { 238 u_int64_t ds_base; 239 u_int32_t ds_count; 240 } ispds64_t; 241 242 typedef struct { 243 u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */ 244 u_int32_t ds_segment; /* unused */ 245 u_int32_t ds_base; /* 32 bit address of DSD list */ 246 } ispdslist_t; 247 248 249 /* 250 * These elements get swizzled around for SBus instances. 251 */ 252 #define _ISP_SWAP8(a, b) { \ 253 u_int8_t tmp; \ 254 tmp = a; \ 255 a = b; \ 256 b = tmp; \ 257 } 258 typedef struct { 259 u_int8_t rqs_entry_type; 260 u_int8_t rqs_entry_count; 261 u_int8_t rqs_seqno; 262 u_int8_t rqs_flags; 263 } isphdr_t; 264 /* 265 * There are no (for all intents and purposes) non-sparc SBus machines 266 */ 267 #ifdef __sparc__ 268 #define ISP_SBUSIFY_ISPHDR(isp, hdrp) \ 269 if ((isp)->isp_bustype == ISP_BT_SBUS) { \ 270 _ISP_SWAP8((hdrp)->rqs_entry_count, (hdrp)->rqs_entry_type); \ 271 _ISP_SWAP8((hdrp)->rqs_flags, (hdrp)->rqs_seqno); \ 272 } 273 #else 274 #define ISP_SBUSIFY_ISPHDR(a, b) 275 #endif 276 277 /* RQS Flag definitions */ 278 #define RQSFLAG_CONTINUATION 0x01 279 #define RQSFLAG_FULL 0x02 280 #define RQSFLAG_BADHEADER 0x04 281 #define RQSFLAG_BADPACKET 0x08 282 283 /* RQS entry_type definitions */ 284 #define RQSTYPE_REQUEST 0x01 285 #define RQSTYPE_DATASEG 0x02 286 #define RQSTYPE_RESPONSE 0x03 287 #define RQSTYPE_MARKER 0x04 288 #define RQSTYPE_CMDONLY 0x05 289 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 290 #define RQSTYPE_CTIO 0x07 /* Target Mode */ 291 #define RQSTYPE_SCAM 0x08 292 #define RQSTYPE_A64 0x09 293 #define RQSTYPE_A64_CONT 0x0a 294 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 295 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 296 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 297 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 298 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 299 #define RQSTYPE_STATUS_CONT 0x10 300 #define RQSTYPE_T2RQS 0x11 301 #define RQSTYPE_IP_XMIT 0x13 302 #define RQSTYPE_T4RQS 0x15 303 #define RQSTYPE_ATIO2 0x16 /* Target Mode */ 304 #define RQSTYPE_CTIO2 0x17 /* Target Mode */ 305 #define RQSTYPE_CSET0 0x18 306 #define RQSTYPE_T3RQS 0x19 307 #define RQSTYPE_IP_XMIT_64 0x1b 308 #define RQSTYPE_CTIO4 0x1e /* Target Mode */ 309 #define RQSTYPE_CTIO3 0x1f /* Target Mode */ 310 #define RQSTYPE_RIO1 0x21 311 #define RQSTYPE_RIO2 0x22 312 #define RQSTYPE_IP_RECV 0x23 313 #define RQSTYPE_IP_RECV_CONT 0x24 314 315 316 #define ISP_RQDSEG 4 317 typedef struct { 318 isphdr_t req_header; 319 u_int32_t req_handle; 320 u_int8_t req_lun_trn; 321 u_int8_t req_target; 322 u_int16_t req_cdblen; 323 #define req_modifier req_cdblen /* marker packet */ 324 u_int16_t req_flags; 325 u_int16_t req_reserved; 326 u_int16_t req_time; 327 u_int16_t req_seg_count; 328 u_int8_t req_cdb[12]; 329 ispds_t req_dataseg[ISP_RQDSEG]; 330 } ispreq_t; 331 332 /* 333 * A request packet can also be a marker packet. 334 */ 335 #define SYNC_DEVICE 0 336 #define SYNC_TARGET 1 337 #define SYNC_ALL 2 338 339 /* 340 * There are no (for all intents and purposes) non-sparc SBus machines 341 */ 342 #ifdef __sparc__ 343 #define ISP_SBUSIFY_ISPREQ(isp, rqp) \ 344 if ((isp)->isp_bustype == ISP_BT_SBUS) { \ 345 _ISP_SWAP8((rqp)->req_target, (rqp)->req_lun_trn); \ 346 } 347 #else 348 #define ISP_SBUSIFY_ISPREQ(a, b) 349 #endif 350 351 #define ISP_RQDSEG_T2 3 352 typedef struct { 353 isphdr_t req_header; 354 u_int32_t req_handle; 355 u_int8_t req_lun_trn; 356 u_int8_t req_target; 357 u_int16_t req_scclun; 358 u_int16_t req_flags; 359 u_int16_t _res2; 360 u_int16_t req_time; 361 u_int16_t req_seg_count; 362 u_int32_t req_cdb[4]; 363 u_int32_t req_totalcnt; 364 ispds_t req_dataseg[ISP_RQDSEG_T2]; 365 } ispreqt2_t; 366 367 /* req_flag values */ 368 #define REQFLAG_NODISCON 0x0001 369 #define REQFLAG_HTAG 0x0002 370 #define REQFLAG_OTAG 0x0004 371 #define REQFLAG_STAG 0x0008 372 #define REQFLAG_TARGET_RTN 0x0010 373 374 #define REQFLAG_NODATA 0x0000 375 #define REQFLAG_DATA_IN 0x0020 376 #define REQFLAG_DATA_OUT 0x0040 377 #define REQFLAG_DATA_UNKNOWN 0x0060 378 379 #define REQFLAG_DISARQ 0x0100 380 #define REQFLAG_FRC_ASYNC 0x0200 381 #define REQFLAG_FRC_SYNC 0x0400 382 #define REQFLAG_FRC_WIDE 0x0800 383 #define REQFLAG_NOPARITY 0x1000 384 #define REQFLAG_STOPQ 0x2000 385 #define REQFLAG_XTRASNS 0x4000 386 #define REQFLAG_PRIORITY 0x8000 387 388 typedef struct { 389 isphdr_t req_header; 390 u_int32_t req_handle; 391 u_int8_t req_lun_trn; 392 u_int8_t req_target; 393 u_int16_t req_cdblen; 394 u_int16_t req_flags; 395 u_int16_t _res1; 396 u_int16_t req_time; 397 u_int16_t req_seg_count; 398 u_int8_t req_cdb[44]; 399 } ispextreq_t; 400 401 #define ISP_CDSEG 7 402 typedef struct { 403 isphdr_t req_header; 404 u_int32_t _res1; 405 ispds_t req_dataseg[ISP_CDSEG]; 406 } ispcontreq_t; 407 408 typedef struct { 409 isphdr_t req_header; 410 u_int32_t req_handle; 411 u_int16_t req_scsi_status; 412 u_int16_t req_completion_status; 413 u_int16_t req_state_flags; 414 u_int16_t req_status_flags; 415 u_int16_t req_time; 416 #define req_response_len req_time /* FC only */ 417 u_int16_t req_sense_len; 418 u_int32_t req_resid; 419 u_int8_t req_response[8]; /* FC only */ 420 u_int8_t req_sense_data[32]; 421 } ispstatusreq_t; 422 423 /* 424 * For Qlogic 2X00, the high order byte of SCSI status has 425 * additional meaning. 426 */ 427 #define RQCS_RU 0x800 /* Residual Under */ 428 #define RQCS_RO 0x400 /* Residual Over */ 429 #define RQCS_RESID (RQCS_RU|RQCS_RO) 430 #define RQCS_SV 0x200 /* Sense Length Valid */ 431 #define RQCS_RV 0x100 /* FCP Response Length Valid */ 432 433 /* 434 * Completion Status Codes. 435 */ 436 #define RQCS_COMPLETE 0x0000 437 #define RQCS_DMA_ERROR 0x0002 438 #define RQCS_RESET_OCCURRED 0x0004 439 #define RQCS_ABORTED 0x0005 440 #define RQCS_TIMEOUT 0x0006 441 #define RQCS_DATA_OVERRUN 0x0007 442 #define RQCS_DATA_UNDERRUN 0x0015 443 #define RQCS_QUEUE_FULL 0x001C 444 445 /* 1X00 Only Completion Codes */ 446 #define RQCS_INCOMPLETE 0x0001 447 #define RQCS_TRANSPORT_ERROR 0x0003 448 #define RQCS_COMMAND_OVERRUN 0x0008 449 #define RQCS_STATUS_OVERRUN 0x0009 450 #define RQCS_BAD_MESSAGE 0x000a 451 #define RQCS_NO_MESSAGE_OUT 0x000b 452 #define RQCS_EXT_ID_FAILED 0x000c 453 #define RQCS_IDE_MSG_FAILED 0x000d 454 #define RQCS_ABORT_MSG_FAILED 0x000e 455 #define RQCS_REJECT_MSG_FAILED 0x000f 456 #define RQCS_NOP_MSG_FAILED 0x0010 457 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 458 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 459 #define RQCS_ID_MSG_FAILED 0x0013 460 #define RQCS_UNEXP_BUS_FREE 0x0014 461 #define RQCS_XACT_ERR1 0x0018 462 #define RQCS_XACT_ERR2 0x0019 463 #define RQCS_XACT_ERR3 0x001A 464 #define RQCS_BAD_ENTRY 0x001B 465 #define RQCS_PHASE_SKIPPED 0x001D 466 #define RQCS_ARQS_FAILED 0x001E 467 #define RQCS_WIDE_FAILED 0x001F 468 #define RQCS_SYNCXFER_FAILED 0x0020 469 #define RQCS_LVD_BUSERR 0x0021 470 471 /* 2X00 Only Completion Codes */ 472 #define RQCS_PORT_UNAVAILABLE 0x0028 473 #define RQCS_PORT_LOGGED_OUT 0x0029 474 #define RQCS_PORT_CHANGED 0x002A 475 #define RQCS_PORT_BUSY 0x002B 476 477 /* 478 * 1X00 specific State Flags 479 */ 480 #define RQSF_GOT_BUS 0x0100 481 #define RQSF_GOT_TARGET 0x0200 482 #define RQSF_SENT_CDB 0x0400 483 #define RQSF_XFRD_DATA 0x0800 484 #define RQSF_GOT_STATUS 0x1000 485 #define RQSF_GOT_SENSE 0x2000 486 #define RQSF_XFER_COMPLETE 0x4000 487 488 /* 489 * 2X00 specific State Flags 490 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available) 491 */ 492 #define RQSF_DATA_IN 0x0020 493 #define RQSF_DATA_OUT 0x0040 494 #define RQSF_STAG 0x0008 495 #define RQSF_OTAG 0x0004 496 #define RQSF_HTAG 0x0002 497 /* 498 * 1X00 Status Flags 499 */ 500 #define RQSTF_DISCONNECT 0x0001 501 #define RQSTF_SYNCHRONOUS 0x0002 502 #define RQSTF_PARITY_ERROR 0x0004 503 #define RQSTF_BUS_RESET 0x0008 504 #define RQSTF_DEVICE_RESET 0x0010 505 #define RQSTF_ABORTED 0x0020 506 #define RQSTF_TIMEOUT 0x0040 507 #define RQSTF_NEGOTIATION 0x0080 508 509 /* 510 * 2X00 specific state flags 511 */ 512 /* RQSF_SENT_CDB */ 513 /* RQSF_XFRD_DATA */ 514 /* RQSF_GOT_STATUS */ 515 /* RQSF_XFER_COMPLETE */ 516 517 /* 518 * 2X00 specific status flags 519 */ 520 /* RQSTF_ABORTED */ 521 /* RQSTF_TIMEOUT */ 522 #define RQSTF_DMA_ERROR 0x0080 523 #define RQSTF_LOGOUT 0x2000 524 525 /* 526 * Miscellaneous 527 */ 528 #ifndef ISP_EXEC_THROTTLE 529 #define ISP_EXEC_THROTTLE 16 530 #endif 531 532 /* 533 * About Firmware returns an 'attribute' word in mailbox 6. 534 */ 535 #define ISP_FW_ATTR_TMODE 0x01 536 #define ISP_FW_ATTR_SCCLUN 0x02 537 #define ISP_FW_ATTR_FABRIC 0x04 538 #define ISP_FW_ATTR_CLASS2 0x08 539 #define ISP_FW_ATTR_FCTAPE 0x10 540 #define ISP_FW_ATTR_IP 0x20 541 542 /* 543 * Reduced Interrupt Operation Response Queue Entreis 544 */ 545 546 typedef struct { 547 isphdr_t req_header; 548 u_int32_t req_handles[15]; 549 } isp_rio1_t; 550 551 typedef struct { 552 isphdr_t req_header; 553 u_int16_t req_handles[30]; 554 } isp_rio2_t; 555 556 /* 557 * FC (ISP2100) specific data structures 558 */ 559 560 /* 561 * Initialization Control Block 562 * 563 * Version One (prime) format. 564 */ 565 typedef struct isp_icb { 566 u_int8_t icb_version; 567 u_int8_t _reserved0; 568 u_int16_t icb_fwoptions; 569 u_int16_t icb_maxfrmlen; 570 u_int16_t icb_maxalloc; 571 u_int16_t icb_execthrottle; 572 u_int8_t icb_retry_count; 573 u_int8_t icb_retry_delay; 574 u_int8_t icb_portname[8]; 575 u_int16_t icb_hardaddr; 576 u_int8_t icb_iqdevtype; 577 u_int8_t icb_logintime; 578 u_int8_t icb_nodename[8]; 579 u_int16_t icb_rqstout; 580 u_int16_t icb_rspnsin; 581 u_int16_t icb_rqstqlen; 582 u_int16_t icb_rsltqlen; 583 u_int16_t icb_rqstaddr[4]; 584 u_int16_t icb_respaddr[4]; 585 u_int16_t icb_lunenables; 586 u_int8_t icb_ccnt; 587 u_int8_t icb_icnt; 588 u_int16_t icb_lunetimeout; 589 u_int16_t _reserved1; 590 u_int16_t icb_xfwoptions; 591 u_int8_t icb_racctimer; 592 u_int8_t icb_idelaytimer; 593 u_int16_t icb_zfwoptions; 594 u_int16_t _reserved2[13]; 595 } isp_icb_t; 596 #define ICB_VERSION1 1 597 598 #define ICBOPT_HARD_ADDRESS 0x0001 599 #define ICBOPT_FAIRNESS 0x0002 600 #define ICBOPT_FULL_DUPLEX 0x0004 601 #define ICBOPT_FAST_POST 0x0008 602 #define ICBOPT_TGT_ENABLE 0x0010 603 #define ICBOPT_INI_DISABLE 0x0020 604 #define ICBOPT_INI_ADISC 0x0040 605 #define ICBOPT_INI_TGTTYPE 0x0080 606 #define ICBOPT_PDBCHANGE_AE 0x0100 607 #define ICBOPT_NOLIP 0x0200 608 #define ICBOPT_SRCHDOWN 0x0400 609 #define ICBOPT_PREVLOOP 0x0800 610 #define ICBOPT_STOP_ON_QFULL 0x1000 611 #define ICBOPT_FULL_LOGIN 0x2000 612 #define ICBOPT_BOTH_WWNS 0x4000 613 #define ICBOPT_EXTENDED 0x8000 614 615 #define ICBXOPT_CLASS2_ACK0 0x0200 616 #define ICBXOPT_CLASS2 0x0100 617 #define ICBXOPT_LOOP_ONLY (0 << 4) 618 #define ICBXOPT_PTP_ONLY (1 << 4) 619 #define ICBXOPT_LOOP_2_PTP (2 << 4) 620 #define ICBXOPT_PTP_2_LOOP (3 << 4) 621 622 #define ICBXOPT_RIO_OFF 0 623 #define ICBXOPT_RIO_16BIT 1 624 #define ICBXOPT_RIO_32BIT 2 625 #define ICBXOPT_RIO_16BIT_DELAY 3 626 #define ICBXOPT_RIO_32BIT_DELAY 4 627 628 629 630 #define ICB_MIN_FRMLEN 256 631 #define ICB_MAX_FRMLEN 2112 632 #define ICB_DFLT_FRMLEN 1024 633 #define ICB_DFLT_ALLOC 256 634 #define ICB_DFLT_THROTTLE 16 635 #define ICB_DFLT_RDELAY 5 636 #define ICB_DFLT_RCOUNT 3 637 638 639 #define RQRSP_ADDR0015 0 640 #define RQRSP_ADDR1631 1 641 #define RQRSP_ADDR3247 2 642 #define RQRSP_ADDR4863 3 643 644 645 #define ICB_NNM0 7 646 #define ICB_NNM1 6 647 #define ICB_NNM2 5 648 #define ICB_NNM3 4 649 #define ICB_NNM4 3 650 #define ICB_NNM5 2 651 #define ICB_NNM6 1 652 #define ICB_NNM7 0 653 654 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 655 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 656 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 657 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 658 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 659 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 660 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 661 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 662 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 663 664 /* 665 * FC-AL Position Map 666 * 667 * This is an at most 128 byte map that returns either 668 * the LILP or Firmware generated list of ports. 669 * 670 * We deviate a bit from the returned qlogic format to 671 * use an extra bit to say whether this was a LILP or 672 * f/w generated map. 673 */ 674 typedef struct { 675 u_int8_t fwmap : 1, 676 count : 7; 677 u_int8_t map[127]; 678 } fcpos_map_t; 679 680 /* 681 * Port Data Base Element 682 */ 683 684 typedef struct { 685 u_int16_t pdb_options; 686 u_int8_t pdb_mstate; 687 u_int8_t pdb_sstate; 688 #define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2]) 689 u_int8_t pdb_hardaddr_bits[4]; 690 u_int8_t pdb_portid_bits[4]; 691 u_int8_t pdb_nodename[8]; 692 u_int8_t pdb_portname[8]; 693 u_int16_t pdb_execthrottle; 694 u_int16_t pdb_exec_count; 695 u_int8_t pdb_retry_count; 696 u_int8_t pdb_retry_delay; 697 u_int16_t pdb_resalloc; 698 u_int16_t pdb_curalloc; 699 u_int16_t pdb_qhead; 700 u_int16_t pdb_qtail; 701 u_int16_t pdb_tl_next; 702 u_int16_t pdb_tl_last; 703 u_int16_t pdb_features; /* PLOGI, Common Service */ 704 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */ 705 u_int16_t pdb_roi; /* PLOGI, Common Service */ 706 u_int8_t pdb_target; 707 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ 708 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */ 709 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */ 710 u_int16_t pdb_noseq; /* PLOGI, Class 3 */ 711 u_int16_t pdb_labrtflg; 712 u_int16_t pdb_lstopflg; 713 u_int16_t pdb_sqhead; 714 u_int16_t pdb_sqtail; 715 u_int16_t pdb_ptimer; 716 u_int16_t pdb_nxt_seqid; 717 u_int16_t pdb_fcount; 718 u_int16_t pdb_prli_len; 719 u_int16_t pdb_prli_svc0; 720 u_int16_t pdb_prli_svc3; 721 u_int16_t pdb_loopid; 722 u_int16_t pdb_il_ptr; 723 u_int16_t pdb_sl_ptr; 724 } isp_pdb_t; 725 726 #define PDB_OPTIONS_XMITTING (1<<11) 727 #define PDB_OPTIONS_LNKXMIT (1<<10) 728 #define PDB_OPTIONS_ABORTED (1<<9) 729 #define PDB_OPTIONS_ADISC (1<<1) 730 731 #define PDB_STATE_DISCOVERY 0 732 #define PDB_STATE_WDISC_ACK 1 733 #define PDB_STATE_PLOGI 2 734 #define PDB_STATE_PLOGI_ACK 3 735 #define PDB_STATE_PRLI 4 736 #define PDB_STATE_PRLI_ACK 5 737 #define PDB_STATE_LOGGED_IN 6 738 #define PDB_STATE_PORT_UNAVAIL 7 739 #define PDB_STATE_PRLO 8 740 #define PDB_STATE_PRLO_ACK 9 741 #define PDB_STATE_PLOGO 10 742 #define PDB_STATE_PLOG_ACK 11 743 744 #define SVC3_TGT_ROLE 0x10 745 #define SVC3_INI_ROLE 0x20 746 #define SVC3_ROLE_MASK 0x30 747 #define SVC3_ROLE_SHIFT 4 748 749 #define SNS_GAN 0x100 750 #define SNS_GP3 0x171 751 #define SNS_RFT 0x217 752 typedef struct { 753 u_int16_t snscb_rblen; /* response buffer length (words) */ 754 u_int16_t snscb_res0; 755 u_int16_t snscb_addr[4]; /* response buffer address */ 756 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 757 u_int16_t snscb_res1; 758 u_int16_t snscb_data[1]; /* variable data */ 759 } sns_screq_t; /* Subcommand Request Structure */ 760 #define SNS_GAN_REQ_SIZE (sizeof (sns_screq_t)+(5*(sizeof (u_int16_t)))) 761 #define SNS_GP3_REQ_SIZE (sizeof (sns_screq_t)+(5*(sizeof (u_int16_t)))) 762 #define SNS_RFT_REQ_SIZE (sizeof (sns_screq_t)+(21*(sizeof (u_int16_t)))) 763 764 typedef struct { 765 u_int8_t snscb_cthdr[16]; 766 u_int8_t snscb_port_type; 767 u_int8_t snscb_port_id[3]; 768 u_int8_t snscb_portname[8]; 769 u_int16_t snscb_data[1]; /* variable data */ 770 } sns_scrsp_t; /* Subcommand Response Structure */ 771 #define SNS_GAN_RESP_SIZE 608 /* Maximum response size (bytes) */ 772 #define SNS_GP3_RESP_SIZE 532 /* XXX: For 128 ports */ 773 #define SNS_RFT_RESP_SIZE 16 774 775 typedef struct { 776 u_int8_t snscb_cthdr[16]; 777 u_int8_t snscb_port_type; 778 u_int8_t snscb_port_id[3]; 779 u_int8_t snscb_portname[8]; 780 u_int8_t snscb_pnlen; /* symbolic port name length */ 781 u_int8_t snscb_pname[255]; /* symbolic port name */ 782 u_int8_t snscb_nodename[8]; 783 u_int8_t snscb_nnlen; /* symbolic node name length */ 784 u_int8_t snscb_nname[255]; /* symbolic node name */ 785 u_int8_t snscb_ipassoc[8]; 786 u_int8_t snscb_ipaddr[16]; 787 u_int8_t snscb_svc_class[4]; 788 u_int8_t snscb_fc4_types[32]; 789 u_int8_t snscb_fpname[8]; 790 u_int8_t snscb_reserved; 791 u_int8_t snscb_hardaddr[3]; 792 } sns_ganrsp_t; /* Subcommand Response Structure */ 793 794 #endif /* _ISPMBOX_H */ 795