1 /* $FreeBSD$ */ 2 /* 3 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 4 * 5 * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #ifndef _ISPMBOX_H 31 #define _ISPMBOX_H 32 33 /* 34 * Mailbox Command Opcodes 35 */ 36 37 #define MBOX_NO_OP 0x0000 38 #define MBOX_LOAD_RAM 0x0001 39 #define MBOX_EXEC_FIRMWARE 0x0002 40 #define MBOX_DUMP_RAM 0x0003 41 #define MBOX_WRITE_RAM_WORD 0x0004 42 #define MBOX_READ_RAM_WORD 0x0005 43 #define MBOX_MAILBOX_REG_TEST 0x0006 44 #define MBOX_VERIFY_CHECKSUM 0x0007 45 #define MBOX_ABOUT_FIRMWARE 0x0008 46 /* 9 */ 47 /* a */ 48 /* b */ 49 /* c */ 50 /* d */ 51 #define MBOX_CHECK_FIRMWARE 0x000e 52 /* f */ 53 #define MBOX_INIT_REQ_QUEUE 0x0010 54 #define MBOX_INIT_RES_QUEUE 0x0011 55 #define MBOX_EXECUTE_IOCB 0x0012 56 #define MBOX_WAKE_UP 0x0013 57 #define MBOX_STOP_FIRMWARE 0x0014 58 #define MBOX_ABORT 0x0015 59 #define MBOX_ABORT_DEVICE 0x0016 60 #define MBOX_ABORT_TARGET 0x0017 61 #define MBOX_BUS_RESET 0x0018 62 #define MBOX_STOP_QUEUE 0x0019 63 #define MBOX_START_QUEUE 0x001a 64 #define MBOX_SINGLE_STEP_QUEUE 0x001b 65 #define MBOX_ABORT_QUEUE 0x001c 66 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 67 /* 1e */ 68 #define MBOX_GET_FIRMWARE_STATUS 0x001f 69 #define MBOX_GET_INIT_SCSI_ID 0x0020 70 #define MBOX_GET_SELECT_TIMEOUT 0x0021 71 #define MBOX_GET_RETRY_COUNT 0x0022 72 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 73 #define MBOX_GET_CLOCK_RATE 0x0024 74 #define MBOX_GET_ACT_NEG_STATE 0x0025 75 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 76 #define MBOX_GET_SBUS_PARAMS 0x0027 77 #define MBOX_GET_TARGET_PARAMS 0x0028 78 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 79 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a 80 /* 2b */ 81 /* 2c */ 82 /* 2d */ 83 /* 2e */ 84 /* 2f */ 85 #define MBOX_SET_INIT_SCSI_ID 0x0030 86 #define MBOX_SET_SELECT_TIMEOUT 0x0031 87 #define MBOX_SET_RETRY_COUNT 0x0032 88 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 89 #define MBOX_SET_CLOCK_RATE 0x0034 90 #define MBOX_SET_ACT_NEG_STATE 0x0035 91 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 92 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 93 #define MBOX_SET_PCI_PARAMETERS 0x0037 94 #define MBOX_SET_TARGET_PARAMS 0x0038 95 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 96 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a 97 /* 3b */ 98 /* 3c */ 99 /* 3d */ 100 /* 3e */ 101 /* 3f */ 102 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 103 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 104 #define MBOX_EXEC_BIOS_IOCB 0x0042 105 #define MBOX_SET_FW_FEATURES 0x004a 106 #define MBOX_GET_FW_FEATURES 0x004b 107 #define FW_FEATURE_LVD_NOTIFY 0x2 108 #define FW_FEATURE_FAST_POST 0x1 109 110 #define MBOX_ENABLE_TARGET_MODE 0x55 111 #define ENABLE_TARGET_FLAG 0x8000 112 #define ENABLE_TQING_FLAG 0x0004 113 #define ENABLE_MANDATORY_DISC 0x0002 114 #define MBOX_GET_TARGET_STATUS 0x56 115 116 /* These are for the ISP2100 FC cards */ 117 #define MBOX_GET_LOOP_ID 0x20 118 #define MBOX_GET_RESOURCE_COUNT 0x42 119 #define MBOX_EXEC_COMMAND_IOCB_A64 0x54 120 #define MBOX_INIT_FIRMWARE 0x60 121 #define MBOX_GET_INIT_CONTROL_BLOCK 0x61 122 #define MBOX_INIT_LIP 0x62 123 #define MBOX_GET_FC_AL_POSITION_MAP 0x63 124 #define MBOX_GET_PORT_DB 0x64 125 #define MBOX_CLEAR_ACA 0x65 126 #define MBOX_TARGET_RESET 0x66 127 #define MBOX_CLEAR_TASK_SET 0x67 128 #define MBOX_ABORT_TASK_SET 0x68 129 #define MBOX_GET_FW_STATE 0x69 130 #define MBOX_GET_PORT_NAME 0x6a 131 #define MBOX_GET_LINK_STATUS 0x6b 132 #define MBOX_INIT_LIP_RESET 0x6c 133 #define MBOX_SEND_SNS 0x6e 134 #define MBOX_FABRIC_LOGIN 0x6f 135 #define MBOX_SEND_CHANGE_REQUEST 0x70 136 #define MBOX_FABRIC_LOGOUT 0x71 137 #define MBOX_INIT_LIP_LOGIN 0x72 138 139 #define ISP2100_SET_PCI_PARAM 0x00ff 140 141 #define MBOX_BUSY 0x04 142 143 typedef struct { 144 u_int16_t param[8]; 145 } mbreg_t; 146 147 /* 148 * Mailbox Command Complete Status Codes 149 */ 150 #define MBOX_COMMAND_COMPLETE 0x4000 151 #define MBOX_INVALID_COMMAND 0x4001 152 #define MBOX_HOST_INTERFACE_ERROR 0x4002 153 #define MBOX_TEST_FAILED 0x4003 154 #define MBOX_COMMAND_ERROR 0x4005 155 #define MBOX_COMMAND_PARAM_ERROR 0x4006 156 #define MBOX_PORT_ID_USED 0x4007 157 #define MBOX_LOOP_ID_USED 0x4008 158 #define MBOX_ALL_IDS_USED 0x4009 159 #define MBOX_NOT_LOGGED_IN 0x400A 160 #define MBLOGALL 0x000f 161 #define MBLOGNONE 0x0000 162 #define MBLOGMASK(x) ((x) & 0xf) 163 164 /* 165 * Asynchronous event status codes 166 */ 167 #define ASYNC_BUS_RESET 0x8001 168 #define ASYNC_SYSTEM_ERROR 0x8002 169 #define ASYNC_RQS_XFER_ERR 0x8003 170 #define ASYNC_RSP_XFER_ERR 0x8004 171 #define ASYNC_QWAKEUP 0x8005 172 #define ASYNC_TIMEOUT_RESET 0x8006 173 #define ASYNC_DEVICE_RESET 0x8007 174 #define ASYNC_EXTMSG_UNDERRUN 0x800A 175 #define ASYNC_SCAM_INT 0x800B 176 #define ASYNC_HUNG_SCSI 0x800C 177 #define ASYNC_KILLED_BUS 0x800D 178 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 179 #define ASYNC_CMD_CMPLT 0x8020 180 #define ASYNC_CTIO_DONE 0x8021 181 182 /* for ISP2100 only */ 183 #define ASYNC_LIP_OCCURRED 0x8010 184 #define ASYNC_LOOP_UP 0x8011 185 #define ASYNC_LOOP_DOWN 0x8012 186 #define ASYNC_LOOP_RESET 0x8013 187 #define ASYNC_PDB_CHANGED 0x8014 188 #define ASYNC_CHANGE_NOTIFY 0x8015 189 190 /* for ISP2200 only */ 191 #define ASYNC_PTPMODE 0x8030 192 #define ASYNC_CONNMODE 0x8036 193 #define ISP_CONN_LOOP 1 194 #define ISP_CONN_PTP 2 195 #define ISP_CONN_BADLIP 3 196 #define ISP_CONN_FATAL 4 197 #define ISP_CONN_LOOPBACK 5 198 199 /* 200 * Command Structure Definitions 201 */ 202 203 typedef struct { 204 u_int32_t ds_base; 205 u_int32_t ds_count; 206 } ispds_t; 207 208 #define _ISP_SWAP8(a, b) { \ 209 u_int8_t tmp; \ 210 tmp = a; \ 211 a = b; \ 212 b = tmp; \ 213 } 214 215 /* 216 * These elements get swizzled around for SBus instances. 217 */ 218 typedef struct { 219 u_int8_t rqs_entry_type; 220 u_int8_t rqs_entry_count; 221 u_int8_t rqs_seqno; 222 u_int8_t rqs_flags; 223 } isphdr_t; 224 /* 225 * There are no (for all intents and purposes) non-sparc SBus machines 226 */ 227 #ifdef __sparc__ 228 #define ISP_SBUSIFY_ISPHDR(isp, hdrp) \ 229 if ((isp)->isp_bustype == ISP_BT_SBUS) { \ 230 _ISP_SWAP8((hdrp)->rqs_entry_count, (hdrp)->rqs_entry_type); \ 231 _ISP_SWAP8((hdrp)->rqs_flags, (hdrp)->rqs_seqno); \ 232 } 233 #else 234 #define ISP_SBUSIFY_ISPHDR(a, b) 235 #endif 236 237 /* RQS Flag definitions */ 238 #define RQSFLAG_CONTINUATION 0x01 239 #define RQSFLAG_FULL 0x02 240 #define RQSFLAG_BADHEADER 0x04 241 #define RQSFLAG_BADPACKET 0x08 242 243 /* RQS entry_type definitions */ 244 #define RQSTYPE_REQUEST 0x01 245 #define RQSTYPE_DATASEG 0x02 246 #define RQSTYPE_RESPONSE 0x03 247 #define RQSTYPE_MARKER 0x04 248 #define RQSTYPE_CMDONLY 0x05 249 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 250 #define RQSTYPE_CTIO 0x07 /* Target Mode */ 251 #define RQSTYPE_SCAM 0x08 252 #define RQSTYPE_A64 0x09 253 #define RQSTYPE_A64_CONT 0x0a 254 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 255 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 256 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 257 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 258 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 259 #define RQSTYPE_STATUS_CONT 0x10 260 #define RQSTYPE_T2RQS 0x11 261 262 #define RQSTYPE_T4RQS 0x15 263 #define RQSTYPE_ATIO2 0x16 264 #define RQSTYPE_CTIO2 0x17 265 #define RQSTYPE_CSET0 0x18 266 #define RQSTYPE_T3RQS 0x19 267 268 #define RQSTYPE_CTIO3 0x1f 269 270 271 #define ISP_RQDSEG 4 272 typedef struct { 273 isphdr_t req_header; 274 u_int32_t req_handle; 275 u_int8_t req_lun_trn; 276 u_int8_t req_target; 277 u_int16_t req_cdblen; 278 #define req_modifier req_cdblen /* marker packet */ 279 u_int16_t req_flags; 280 u_int16_t req_reserved; 281 u_int16_t req_time; 282 u_int16_t req_seg_count; 283 u_int8_t req_cdb[12]; 284 ispds_t req_dataseg[ISP_RQDSEG]; 285 } ispreq_t; 286 287 /* 288 * A request packet can also be a marker packet. 289 */ 290 #define SYNC_DEVICE 0 291 #define SYNC_TARGET 1 292 #define SYNC_ALL 2 293 294 /* 295 * There are no (for all intents and purposes) non-sparc SBus machines 296 */ 297 #ifdef __sparc__ 298 #define ISP_SBUSIFY_ISPREQ(isp, rqp) \ 299 if ((isp)->isp_bustype == ISP_BT_SBUS) { \ 300 _ISP_SWAP8((rqp)->req_target, (rqp)->req_lun_trn); \ 301 } 302 #else 303 #define ISP_SBUSIFY_ISPREQ(a, b) 304 #endif 305 306 #define ISP_RQDSEG_T2 3 307 typedef struct { 308 isphdr_t req_header; 309 u_int32_t req_handle; 310 u_int8_t req_lun_trn; 311 u_int8_t req_target; 312 u_int16_t req_scclun; 313 u_int16_t req_flags; 314 u_int16_t _res2; 315 u_int16_t req_time; 316 u_int16_t req_seg_count; 317 u_int32_t req_cdb[4]; 318 u_int32_t req_totalcnt; 319 ispds_t req_dataseg[ISP_RQDSEG_T2]; 320 } ispreqt2_t; 321 322 /* req_flag values */ 323 #define REQFLAG_NODISCON 0x0001 324 #define REQFLAG_HTAG 0x0002 325 #define REQFLAG_OTAG 0x0004 326 #define REQFLAG_STAG 0x0008 327 #define REQFLAG_TARGET_RTN 0x0010 328 329 #define REQFLAG_NODATA 0x0000 330 #define REQFLAG_DATA_IN 0x0020 331 #define REQFLAG_DATA_OUT 0x0040 332 #define REQFLAG_DATA_UNKNOWN 0x0060 333 334 #define REQFLAG_DISARQ 0x0100 335 #define REQFLAG_FRC_ASYNC 0x0200 336 #define REQFLAG_FRC_SYNC 0x0400 337 #define REQFLAG_FRC_WIDE 0x0800 338 #define REQFLAG_NOPARITY 0x1000 339 #define REQFLAG_STOPQ 0x2000 340 #define REQFLAG_XTRASNS 0x4000 341 #define REQFLAG_PRIORITY 0x8000 342 343 typedef struct { 344 isphdr_t req_header; 345 u_int32_t req_handle; 346 u_int8_t req_lun_trn; 347 u_int8_t req_target; 348 u_int16_t req_cdblen; 349 u_int16_t req_flags; 350 u_int16_t _res1; 351 u_int16_t req_time; 352 u_int16_t req_seg_count; 353 u_int8_t req_cdb[44]; 354 } ispextreq_t; 355 356 #define ISP_CDSEG 7 357 typedef struct { 358 isphdr_t req_header; 359 u_int32_t _res1; 360 ispds_t req_dataseg[ISP_CDSEG]; 361 } ispcontreq_t; 362 363 typedef struct { 364 isphdr_t req_header; 365 u_int32_t req_handle; 366 u_int16_t req_scsi_status; 367 u_int16_t req_completion_status; 368 u_int16_t req_state_flags; 369 u_int16_t req_status_flags; 370 u_int16_t req_time; 371 #define req_response_len req_time /* FC only */ 372 u_int16_t req_sense_len; 373 u_int32_t req_resid; 374 u_int8_t req_response[8]; /* FC only */ 375 u_int8_t req_sense_data[32]; 376 } ispstatusreq_t; 377 378 /* 379 * For Qlogic 2X00, the high order byte of SCSI status has 380 * additional meaning. 381 */ 382 #define RQCS_RU 0x800 /* Residual Under */ 383 #define RQCS_RO 0x400 /* Residual Over */ 384 #define RQCS_RESID (RQCS_RU|RQCS_RO) 385 #define RQCS_SV 0x200 /* Sense Length Valid */ 386 #define RQCS_RV 0x100 /* FCP Response Length Valid */ 387 388 /* 389 * Completion Status Codes. 390 */ 391 #define RQCS_COMPLETE 0x0000 392 #define RQCS_DMA_ERROR 0x0002 393 #define RQCS_RESET_OCCURRED 0x0004 394 #define RQCS_ABORTED 0x0005 395 #define RQCS_TIMEOUT 0x0006 396 #define RQCS_DATA_OVERRUN 0x0007 397 #define RQCS_DATA_UNDERRUN 0x0015 398 #define RQCS_QUEUE_FULL 0x001C 399 400 /* 1X00 Only Completion Codes */ 401 #define RQCS_INCOMPLETE 0x0001 402 #define RQCS_TRANSPORT_ERROR 0x0003 403 #define RQCS_COMMAND_OVERRUN 0x0008 404 #define RQCS_STATUS_OVERRUN 0x0009 405 #define RQCS_BAD_MESSAGE 0x000a 406 #define RQCS_NO_MESSAGE_OUT 0x000b 407 #define RQCS_EXT_ID_FAILED 0x000c 408 #define RQCS_IDE_MSG_FAILED 0x000d 409 #define RQCS_ABORT_MSG_FAILED 0x000e 410 #define RQCS_REJECT_MSG_FAILED 0x000f 411 #define RQCS_NOP_MSG_FAILED 0x0010 412 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 413 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 414 #define RQCS_ID_MSG_FAILED 0x0013 415 #define RQCS_UNEXP_BUS_FREE 0x0014 416 #define RQCS_XACT_ERR1 0x0018 417 #define RQCS_XACT_ERR2 0x0019 418 #define RQCS_XACT_ERR3 0x001A 419 #define RQCS_BAD_ENTRY 0x001B 420 #define RQCS_PHASE_SKIPPED 0x001D 421 #define RQCS_ARQS_FAILED 0x001E 422 #define RQCS_WIDE_FAILED 0x001F 423 #define RQCS_SYNCXFER_FAILED 0x0020 424 #define RQCS_LVD_BUSERR 0x0021 425 426 /* 2X00 Only Completion Codes */ 427 #define RQCS_PORT_UNAVAILABLE 0x0028 428 #define RQCS_PORT_LOGGED_OUT 0x0029 429 #define RQCS_PORT_CHANGED 0x002A 430 #define RQCS_PORT_BUSY 0x002B 431 432 /* 433 * 1X00 specific State Flags 434 */ 435 #define RQSF_GOT_BUS 0x0100 436 #define RQSF_GOT_TARGET 0x0200 437 #define RQSF_SENT_CDB 0x0400 438 #define RQSF_XFRD_DATA 0x0800 439 #define RQSF_GOT_STATUS 0x1000 440 #define RQSF_GOT_SENSE 0x2000 441 #define RQSF_XFER_COMPLETE 0x4000 442 443 /* 444 * 2X00 specific State Flags 445 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available) 446 */ 447 #define RQSF_DATA_IN 0x0020 448 #define RQSF_DATA_OUT 0x0040 449 #define RQSF_STAG 0x0008 450 #define RQSF_OTAG 0x0004 451 #define RQSF_HTAG 0x0002 452 /* 453 * 1X00 Status Flags 454 */ 455 #define RQSTF_DISCONNECT 0x0001 456 #define RQSTF_SYNCHRONOUS 0x0002 457 #define RQSTF_PARITY_ERROR 0x0004 458 #define RQSTF_BUS_RESET 0x0008 459 #define RQSTF_DEVICE_RESET 0x0010 460 #define RQSTF_ABORTED 0x0020 461 #define RQSTF_TIMEOUT 0x0040 462 #define RQSTF_NEGOTIATION 0x0080 463 464 /* 465 * 2X00 specific state flags 466 */ 467 /* RQSF_SENT_CDB */ 468 /* RQSF_XFRD_DATA */ 469 /* RQSF_GOT_STATUS */ 470 /* RQSF_XFER_COMPLETE */ 471 472 /* 473 * 2X00 specific status flags 474 */ 475 /* RQSTF_ABORTED */ 476 /* RQSTF_TIMEOUT */ 477 #define RQSTF_DMA_ERROR 0x0080 478 #define RQSTF_LOGOUT 0x2000 479 480 /* 481 * Miscellaneous 482 */ 483 #ifndef ISP_EXEC_THROTTLE 484 #define ISP_EXEC_THROTTLE 16 485 #endif 486 487 /* 488 * About Firmware returns an 'attribute' word in mailbox 6. 489 */ 490 #define ISP_FW_ATTR_TMODE 0x01 491 #define ISP_FW_ATTR_SCCLUN 0x02 492 #define ISP_FW_ATTR_FABRIC 0x04 493 #define ISP_FW_ATTR_CLASS2 0x08 494 #define ISP_FW_ATTR_FCTAPE 0x10 495 #define ISP_FW_ATTR_IP 0x20 496 497 /* 498 * FC (ISP2100) specific data structures 499 */ 500 501 /* 502 * Initialization Control Block 503 * 504 * Version One (prime) format. 505 */ 506 typedef struct isp_icb { 507 u_int8_t icb_version; 508 u_int8_t _reserved0; 509 u_int16_t icb_fwoptions; 510 u_int16_t icb_maxfrmlen; 511 u_int16_t icb_maxalloc; 512 u_int16_t icb_execthrottle; 513 u_int8_t icb_retry_count; 514 u_int8_t icb_retry_delay; 515 u_int8_t icb_portname[8]; 516 u_int16_t icb_hardaddr; 517 u_int8_t icb_iqdevtype; 518 u_int8_t icb_logintime; 519 u_int8_t icb_nodename[8]; 520 u_int16_t icb_rqstout; 521 u_int16_t icb_rspnsin; 522 u_int16_t icb_rqstqlen; 523 u_int16_t icb_rsltqlen; 524 u_int16_t icb_rqstaddr[4]; 525 u_int16_t icb_respaddr[4]; 526 u_int16_t icb_lunenables; 527 u_int8_t icb_ccnt; 528 u_int8_t icb_icnt; 529 u_int16_t icb_lunetimeout; 530 u_int16_t _reserved1; 531 u_int16_t icb_xfwoptions; 532 u_int8_t icb_racctimer; 533 u_int8_t icb_idelaytimer; 534 u_int16_t icb_zfwoptions; 535 u_int16_t _reserved2[13]; 536 } isp_icb_t; 537 #define ICB_VERSION1 1 538 539 #define ICBOPT_HARD_ADDRESS 0x0001 540 #define ICBOPT_FAIRNESS 0x0002 541 #define ICBOPT_FULL_DUPLEX 0x0004 542 #define ICBOPT_FAST_POST 0x0008 543 #define ICBOPT_TGT_ENABLE 0x0010 544 #define ICBOPT_INI_DISABLE 0x0020 545 #define ICBOPT_INI_ADISC 0x0040 546 #define ICBOPT_INI_TGTTYPE 0x0080 547 #define ICBOPT_PDBCHANGE_AE 0x0100 548 #define ICBOPT_NOLIP 0x0200 549 #define ICBOPT_SRCHDOWN 0x0400 550 #define ICBOPT_PREVLOOP 0x0800 551 #define ICBOPT_STOP_ON_QFULL 0x1000 552 #define ICBOPT_FULL_LOGIN 0x2000 553 #define ICBOPT_BOTH_WWNS 0x4000 554 #define ICBOPT_EXTENDED 0x8000 555 556 #define ICBXOPT_CLASS2_ACK0 0x0200 557 #define ICBXOPT_CLASS2 0x0100 558 #define ICBXOPT_LOOP_ONLY (0 << 4) 559 #define ICBXOPT_PTP_ONLY (1 << 4) 560 #define ICBXOPT_LOOP_2_PTP (2 << 4) 561 #define ICBXOPT_PTP_2_LOOP (3 << 4) 562 563 #define ICBXOPT_RIO_OFF 0 564 #define ICBXOPT_RIO_16BIT 1 565 #define ICBXOPT_RIO_32BIT 2 566 #define ICBXOPT_RIO_16BIT_DELAY 3 567 #define ICBXOPT_RIO_32BIT_DELAY 4 568 569 570 571 #define ICB_MIN_FRMLEN 256 572 #define ICB_MAX_FRMLEN 2112 573 #define ICB_DFLT_FRMLEN 1024 574 #define ICB_DFLT_ALLOC 256 575 #define ICB_DFLT_THROTTLE 16 576 #define ICB_DFLT_RDELAY 5 577 #define ICB_DFLT_RCOUNT 3 578 579 580 #define RQRSP_ADDR0015 0 581 #define RQRSP_ADDR1631 1 582 #define RQRSP_ADDR3247 2 583 #define RQRSP_ADDR4863 3 584 585 586 #define ICB_NNM0 7 587 #define ICB_NNM1 6 588 #define ICB_NNM2 5 589 #define ICB_NNM3 4 590 #define ICB_NNM4 3 591 #define ICB_NNM5 2 592 #define ICB_NNM6 1 593 #define ICB_NNM7 0 594 595 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 596 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 597 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 598 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 599 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 600 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 601 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 602 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 603 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 604 605 /* 606 * FC-AL Position Map 607 * 608 * This is an at most 128 byte map that returns either 609 * the LILP or Firmware generated list of ports. 610 * 611 * We deviate a bit from the returned qlogic format to 612 * use an extra bit to say whether this was a LILP or 613 * f/w generated map. 614 */ 615 typedef struct { 616 u_int8_t fwmap : 1, 617 count : 7; 618 u_int8_t map[127]; 619 } fcpos_map_t; 620 621 /* 622 * Port Data Base Element 623 */ 624 625 typedef struct { 626 u_int16_t pdb_options; 627 u_int8_t pdb_mstate; 628 u_int8_t pdb_sstate; 629 #define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2]) 630 u_int8_t pdb_hardaddr_bits[4]; 631 u_int8_t pdb_portid_bits[4]; 632 u_int8_t pdb_nodename[8]; 633 u_int8_t pdb_portname[8]; 634 u_int16_t pdb_execthrottle; 635 u_int16_t pdb_exec_count; 636 u_int8_t pdb_retry_count; 637 u_int8_t pdb_retry_delay; 638 u_int16_t pdb_resalloc; 639 u_int16_t pdb_curalloc; 640 u_int16_t pdb_qhead; 641 u_int16_t pdb_qtail; 642 u_int16_t pdb_tl_next; 643 u_int16_t pdb_tl_last; 644 u_int16_t pdb_features; /* PLOGI, Common Service */ 645 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */ 646 u_int16_t pdb_roi; /* PLOGI, Common Service */ 647 u_int8_t pdb_target; 648 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ 649 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */ 650 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */ 651 u_int16_t pdb_noseq; /* PLOGI, Class 3 */ 652 u_int16_t pdb_labrtflg; 653 u_int16_t pdb_lstopflg; 654 u_int16_t pdb_sqhead; 655 u_int16_t pdb_sqtail; 656 u_int16_t pdb_ptimer; 657 u_int16_t pdb_nxt_seqid; 658 u_int16_t pdb_fcount; 659 u_int16_t pdb_prli_len; 660 u_int16_t pdb_prli_svc0; 661 u_int16_t pdb_prli_svc3; 662 u_int16_t pdb_loopid; 663 u_int16_t pdb_il_ptr; 664 u_int16_t pdb_sl_ptr; 665 } isp_pdb_t; 666 667 #define PDB_OPTIONS_XMITTING (1<<11) 668 #define PDB_OPTIONS_LNKXMIT (1<<10) 669 #define PDB_OPTIONS_ABORTED (1<<9) 670 #define PDB_OPTIONS_ADISC (1<<1) 671 672 #define PDB_STATE_DISCOVERY 0 673 #define PDB_STATE_WDISC_ACK 1 674 #define PDB_STATE_PLOGI 2 675 #define PDB_STATE_PLOGI_ACK 3 676 #define PDB_STATE_PRLI 4 677 #define PDB_STATE_PRLI_ACK 5 678 #define PDB_STATE_LOGGED_IN 6 679 #define PDB_STATE_PORT_UNAVAIL 7 680 #define PDB_STATE_PRLO 8 681 #define PDB_STATE_PRLO_ACK 9 682 #define PDB_STATE_PLOGO 10 683 #define PDB_STATE_PLOG_ACK 11 684 685 #define SVC3_TGT_ROLE 0x10 686 #define SVC3_INI_ROLE 0x20 687 #define SVC3_ROLE_MASK 0x30 688 #define SVC3_ROLE_SHIFT 4 689 690 #define SNS_GAN 0x100 691 #define SNS_GP3 0x171 692 #define SNS_RFT 0x217 693 typedef struct { 694 u_int16_t snscb_rblen; /* response buffer length (words) */ 695 u_int16_t snscb_res0; 696 u_int16_t snscb_addr[4]; /* response buffer address */ 697 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 698 u_int16_t snscb_res1; 699 u_int16_t snscb_data[1]; /* variable data */ 700 } sns_screq_t; /* Subcommand Request Structure */ 701 #define SNS_GAN_REQ_SIZE (sizeof (sns_screq_t)+(5*(sizeof (u_int16_t)))) 702 #define SNS_GP3_REQ_SIZE (sizeof (sns_screq_t)+(5*(sizeof (u_int16_t)))) 703 #define SNS_RFT_REQ_SIZE (sizeof (sns_screq_t)+(21*(sizeof (u_int16_t)))) 704 705 typedef struct { 706 u_int8_t snscb_cthdr[16]; 707 u_int8_t snscb_port_type; 708 u_int8_t snscb_port_id[3]; 709 u_int8_t snscb_portname[8]; 710 u_int16_t snscb_data[1]; /* variable data */ 711 } sns_scrsp_t; /* Subcommand Response Structure */ 712 #define SNS_GAN_RESP_SIZE 608 /* Maximum response size (bytes) */ 713 #define SNS_GP3_RESP_SIZE 532 /* XXX: For 128 ports */ 714 #define SNS_RFT_RESP_SIZE 16 715 716 typedef struct { 717 u_int8_t snscb_cthdr[16]; 718 u_int8_t snscb_port_type; 719 u_int8_t snscb_port_id[3]; 720 u_int8_t snscb_portname[8]; 721 u_int8_t snscb_pnlen; /* symbolic port name length */ 722 u_int8_t snscb_pname[255]; /* symbolic port name */ 723 u_int8_t snscb_nodename[8]; 724 u_int8_t snscb_nnlen; /* symbolic node name length */ 725 u_int8_t snscb_nname[255]; /* symbolic node name */ 726 u_int8_t snscb_ipassoc[8]; 727 u_int8_t snscb_ipaddr[16]; 728 u_int8_t snscb_svc_class[4]; 729 u_int8_t snscb_fc4_types[32]; 730 u_int8_t snscb_fpname[8]; 731 u_int8_t snscb_reserved; 732 u_int8_t snscb_hardaddr[3]; 733 } sns_ganrsp_t; /* Subcommand Response Structure */ 734 735 #endif /* _ISPMBOX_H */ 736