1 /* $Id: ispmbox.h,v 1.3 1998/04/14 17:51:32 mjacob Exp $ */ 2 /* 3 * Mailbox and Command Definitions for for Qlogic ISP SCSI adapters. 4 * 5 *--------------------------------------- 6 * Copyright (c) 1997, 1998 by Matthew Jacob 7 * NASA/Ames Research Center 8 * All rights reserved. 9 *--------------------------------------- 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 #ifndef _ISPMBOX_H 37 #define _ISPMBOX_H 38 39 /* 40 * Mailbox Command Opcodes 41 */ 42 43 #define MBOX_NO_OP 0x0000 44 #define MBOX_LOAD_RAM 0x0001 45 #define MBOX_EXEC_FIRMWARE 0x0002 46 #define MBOX_DUMP_RAM 0x0003 47 #define MBOX_WRITE_RAM_WORD 0x0004 48 #define MBOX_READ_RAM_WORD 0x0005 49 #define MBOX_MAILBOX_REG_TEST 0x0006 50 #define MBOX_VERIFY_CHECKSUM 0x0007 51 #define MBOX_ABOUT_FIRMWARE 0x0008 52 /* 9 */ 53 /* a */ 54 /* b */ 55 /* c */ 56 /* d */ 57 #define MBOX_CHECK_FIRMWARE 0x000e 58 /* f */ 59 #define MBOX_INIT_REQ_QUEUE 0x0010 60 #define MBOX_INIT_RES_QUEUE 0x0011 61 #define MBOX_EXECUTE_IOCB 0x0012 62 #define MBOX_WAKE_UP 0x0013 63 #define MBOX_STOP_FIRMWARE 0x0014 64 #define MBOX_ABORT 0x0015 65 #define MBOX_ABORT_DEVICE 0x0016 66 #define MBOX_ABORT_TARGET 0x0017 67 #define MBOX_BUS_RESET 0x0018 68 #define MBOX_STOP_QUEUE 0x0019 69 #define MBOX_START_QUEUE 0x001a 70 #define MBOX_SINGLE_STEP_QUEUE 0x001b 71 #define MBOX_ABORT_QUEUE 0x001c 72 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 73 /* 1e */ 74 #define MBOX_GET_FIRMWARE_STATUS 0x001f 75 #define MBOX_GET_INIT_SCSI_ID 0x0020 76 #define MBOX_GET_SELECT_TIMEOUT 0x0021 77 #define MBOX_GET_RETRY_COUNT 0x0022 78 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 79 #define MBOX_GET_CLOCK_RATE 0x0024 80 #define MBOX_GET_ACT_NEG_STATE 0x0025 81 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 82 #define MBOX_GET_SBUS_PARAMS 0x0027 83 #define MBOX_GET_TARGET_PARAMS 0x0028 84 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 85 /* 2a */ 86 /* 2b */ 87 /* 2c */ 88 /* 2d */ 89 /* 2e */ 90 /* 2f */ 91 #define MBOX_SET_INIT_SCSI_ID 0x0030 92 #define MBOX_SET_SELECT_TIMEOUT 0x0031 93 #define MBOX_SET_RETRY_COUNT 0x0032 94 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 95 #define MBOX_SET_CLOCK_RATE 0x0034 96 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035 97 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 98 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 99 #define MBOX_SET_PCI_PARAMETERS 0x0037 100 #define MBOX_SET_TARGET_PARAMS 0x0038 101 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 102 /* 3a */ 103 /* 3b */ 104 /* 3c */ 105 /* 3d */ 106 /* 3e */ 107 /* 3f */ 108 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 109 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 110 #define MBOX_EXEC_BIOS_IOCB 0x0042 111 112 /* These are for the ISP2100 FC cards */ 113 #define MBOX_GET_LOOP_ID 0x20 114 #define MBOX_EXEC_COMMAND_IOCB_A64 0x54 115 #define MBOX_INIT_FIRMWARE 0x60 116 #define MBOX_GET_INIT_CONTROL_BLOCK 0x61 117 #define MBOX_INIT_LIP 0x62 118 #define MBOX_GET_FC_AL_POSITION_MAP 0x63 119 #define MBOX_GET_PORT_DB 0x64 120 #define MBOX_CLEAR_ACA 0x65 121 #define MBOX_TARGET_RESET 0x66 122 #define MBOX_CLEAR_TASK_SET 0x67 123 #define MBOX_ABORT_TASK_SET 0x68 124 #define MBOX_GET_FW_STATE 0x69 125 126 #define ISP2100_SET_PCI_PARAM 0x00ff 127 128 #define MBOX_BUSY 0x04 129 130 typedef struct { 131 u_int16_t param[8]; 132 } mbreg_t; 133 134 /* 135 * Command Structure Definitions 136 */ 137 138 typedef struct { 139 u_int32_t ds_base; 140 u_int32_t ds_count; 141 } ispds_t; 142 143 typedef struct { 144 #if BYTE_ORDER == BIG_ENDIAN 145 u_int8_t rqs_entry_count; 146 u_int8_t rqs_entry_type; 147 u_int8_t rqs_flags; 148 u_int8_t rqs_seqno; 149 #else 150 u_int8_t rqs_entry_type; 151 u_int8_t rqs_entry_count; 152 u_int8_t rqs_seqno; 153 u_int8_t rqs_flags; 154 #endif 155 } isphdr_t; 156 157 /* RQS Flag definitions */ 158 #define RQSFLAG_CONTINUATION 0x01 159 #define RQSFLAG_FULL 0x02 160 #define RQSFLAG_BADHEADER 0x04 161 #define RQSFLAG_BADPACKET 0x08 162 163 /* RQS entry_type definitions */ 164 #define RQSTYPE_REQUEST 1 165 #define RQSTYPE_DATASEG 2 166 #define RQSTYPE_RESPONSE 3 167 #define RQSTYPE_MARKER 4 168 #define RQSTYPE_CMDONLY 5 169 #define RQSTYPE_T2RQS 17 170 #define RQSTYPE_T3RQS 25 171 #define RQSTYPE_T1DSEG 10 172 173 174 #define ISP_RQDSEG 4 175 typedef struct { 176 isphdr_t req_header; 177 u_int32_t req_handle; 178 #if BYTE_ORDER == BIG_ENDIAN 179 u_int8_t req_target; 180 u_int8_t req_lun_trn; 181 #else 182 u_int8_t req_lun_trn; 183 u_int8_t req_target; 184 #endif 185 u_int16_t req_cdblen; 186 #define req_modifier req_cdblen /* marker packet */ 187 u_int16_t req_flags; 188 u_int16_t _res1; 189 u_int16_t req_time; 190 u_int16_t req_seg_count; 191 u_int8_t req_cdb[12]; 192 ispds_t req_dataseg[ISP_RQDSEG]; 193 } ispreq_t; 194 195 #define ISP_RQDSEG_T2 3 196 typedef struct { 197 isphdr_t req_header; 198 u_int32_t req_handle; 199 #if BYTE_ORDER == BIG_ENDIAN 200 u_int8_t req_target; 201 u_int8_t req_lun_trn; 202 #else 203 u_int8_t req_lun_trn; 204 u_int8_t req_target; 205 #endif 206 u_int16_t _res1; 207 u_int16_t req_flags; 208 u_int16_t _res2; 209 u_int16_t req_time; 210 u_int16_t req_seg_count; 211 u_int32_t req_cdb[4]; 212 u_int32_t req_totalcnt; 213 ispds_t req_dataseg[ISP_RQDSEG_T2]; 214 } ispreqt2_t; 215 216 /* req_flag values */ 217 #define REQFLAG_NODISCON 0x0001 218 #define REQFLAG_HTAG 0x0002 219 #define REQFLAG_OTAG 0x0004 220 #define REQFLAG_STAG 0x0008 221 #define REQFLAG_TARGET_RTN 0x0010 222 223 #define REQFLAG_NODATA 0x0000 224 #define REQFLAG_DATA_IN 0x0020 225 #define REQFLAG_DATA_OUT 0x0040 226 #define REQFLAG_DATA_UNKNOWN 0x0060 227 228 #define REQFLAG_DISARQ 0x0100 229 230 typedef struct { 231 isphdr_t req_header; 232 u_int32_t req_handle; 233 #if BYTE_ORDER == BIG_ENDIAN 234 u_int8_t req_target; 235 u_int8_t req_lun_trn; 236 #else 237 u_int8_t req_lun_trn; 238 u_int8_t req_target; 239 #endif 240 u_int16_t req_cdblen; 241 u_int16_t req_flags; 242 u_int16_t _res1; 243 u_int16_t req_time; 244 u_int16_t req_seg_count; 245 u_int8_t req_cdb[44]; 246 } ispextreq_t; 247 248 #define ISP_CDSEG 7 249 typedef struct { 250 isphdr_t req_header; 251 u_int32_t _res1; 252 ispds_t req_dataseg[ISP_CDSEG]; 253 } ispcontreq_t; 254 255 typedef struct { 256 isphdr_t req_header; 257 u_int32_t _res1; 258 #if BYTE_ORDER == BIG_ENDIAN 259 u_int8_t req_target; 260 u_int8_t req_lun_trn; 261 u_int8_t _res2; 262 u_int8_t req_modifier; 263 #else 264 u_int8_t req_lun_trn; 265 u_int8_t req_target; 266 u_int8_t req_modifier; 267 u_int8_t _res2; 268 #endif 269 } ispmarkreq_t; 270 271 #define SYNC_DEVICE 0 272 #define SYNC_TARGET 1 273 #define SYNC_ALL 2 274 275 typedef struct { 276 isphdr_t req_header; 277 u_int32_t req_handle; 278 u_int16_t req_scsi_status; 279 u_int16_t req_completion_status; 280 u_int16_t req_state_flags; 281 u_int16_t req_status_flags; 282 u_int16_t req_time; 283 u_int16_t req_sense_len; 284 u_int32_t req_resid; 285 u_int8_t _res1[8]; 286 u_int8_t req_sense_data[32]; 287 } ispstatusreq_t; 288 289 /* 290 * For Qlogic 2100, the high order byte of SCSI status has 291 * additional meaning. 292 */ 293 #define RQCS_RU 0x800 /* Residual Under */ 294 #define RQCS_RO 0x400 /* Residual Over */ 295 #define RQCS_SV 0x200 /* Sense Length Valid */ 296 #define RQCS_RV 0x100 /* Residual Valid */ 297 298 /* 299 * Completion Status Codes. 300 */ 301 #define RQCS_COMPLETE 0x0000 302 #define RQCS_INCOMPLETE 0x0001 303 #define RQCS_DMA_ERROR 0x0002 304 #define RQCS_TRANSPORT_ERROR 0x0003 305 #define RQCS_RESET_OCCURRED 0x0004 306 #define RQCS_ABORTED 0x0005 307 #define RQCS_TIMEOUT 0x0006 308 #define RQCS_DATA_OVERRUN 0x0007 309 #define RQCS_COMMAND_OVERRUN 0x0008 310 #define RQCS_STATUS_OVERRUN 0x0009 311 #define RQCS_BAD_MESSAGE 0x000a 312 #define RQCS_NO_MESSAGE_OUT 0x000b 313 #define RQCS_EXT_ID_FAILED 0x000c 314 #define RQCS_IDE_MSG_FAILED 0x000d 315 #define RQCS_ABORT_MSG_FAILED 0x000e 316 #define RQCS_REJECT_MSG_FAILED 0x000f 317 #define RQCS_NOP_MSG_FAILED 0x0010 318 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 319 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 320 #define RQCS_ID_MSG_FAILED 0x0013 321 #define RQCS_UNEXP_BUS_FREE 0x0014 322 #define RQCS_DATA_UNDERRUN 0x0015 323 /* 2100 Only Completion Codes */ 324 #define RQCS_PORT_UNAVAILABLE 0x0028 325 #define RQCS_PORT_LOGGED_OUT 0x0029 326 #define RQCS_PORT_CHANGED 0x002A 327 #define RQCS_PORT_BUSY 0x002B 328 329 /* 330 * State Flags (not applicable to 2100) 331 */ 332 #define RQSF_GOT_BUS 0x0100 333 #define RQSF_GOT_TARGET 0x0200 334 #define RQSF_SENT_CDB 0x0400 335 #define RQSF_XFRD_DATA 0x0800 336 #define RQSF_GOT_STATUS 0x1000 337 #define RQSF_GOT_SENSE 0x2000 338 #define RQSF_XFER_COMPLETE 0x4000 339 340 /* 341 * Status Flags (not applicable to 2100) 342 */ 343 #define RQSTF_DISCONNECT 0x0001 344 #define RQSTF_SYNCHRONOUS 0x0002 345 #define RQSTF_PARITY_ERROR 0x0004 346 #define RQSTF_BUS_RESET 0x0008 347 #define RQSTF_DEVICE_RESET 0x0010 348 #define RQSTF_ABORTED 0x0020 349 #define RQSTF_TIMEOUT 0x0040 350 #define RQSTF_NEGOTIATION 0x0080 351 352 /* 353 * FC (ISP2100) specific data structures 354 */ 355 356 /* 357 * Initialization Control Block 358 */ 359 typedef struct { 360 #if BYTE_ORDER == BIG_ENDIAN 361 u_int8_t _reserved0; 362 u_int8_t icb_version; 363 #else 364 u_int8_t icb_version; 365 u_int8_t _reserved0; 366 #endif 367 u_int16_t icb_fwoptions; 368 u_int16_t icb_maxfrmlen; 369 u_int16_t icb_maxalloc; 370 u_int16_t icb_execthrottle; 371 #if BYTE_ORDER == BIG_ENDIAN 372 u_int8_t icb_retry_delay; 373 u_int8_t icb_retry_count; 374 #else 375 u_int8_t icb_retry_count; 376 u_int8_t icb_retry_delay; 377 #endif 378 u_int16_t icb_nodename[4]; 379 u_int16_t icb_hardaddr; 380 u_int16_t _reserved1[5]; 381 u_int16_t icb_rqstout; 382 u_int16_t icb_rspnsin; 383 u_int16_t icb_rqstqlen; 384 u_int16_t icb_rsltqlen; 385 u_int16_t icb_rqstaddr[4]; 386 u_int16_t icb_respaddr[4]; 387 } isp_icb_t; 388 389 #define ICB_DFLT_FRMLEN 1024 390 #define MAKE_NODE_NAME(isp, icbp) \ 391 (icbp)->icb_nodename[0] = 0, (icbp)->icb_nodename[1] = 0x5355,\ 392 (icbp)->icb_nodename[2] = 0x4E57, (icbp)->icb_nodename[3] = 0 393 394 #endif /* _ISPMBOX_H */ 395