1 /* $FreeBSD$ */ 2 /* 3 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 4 * 5 * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #ifndef _ISPMBOX_H 31 #define _ISPMBOX_H 32 33 /* 34 * Mailbox Command Opcodes 35 */ 36 #define MBOX_NO_OP 0x0000 37 #define MBOX_LOAD_RAM 0x0001 38 #define MBOX_EXEC_FIRMWARE 0x0002 39 #define MBOX_DUMP_RAM 0x0003 40 #define MBOX_WRITE_RAM_WORD 0x0004 41 #define MBOX_READ_RAM_WORD 0x0005 42 #define MBOX_MAILBOX_REG_TEST 0x0006 43 #define MBOX_VERIFY_CHECKSUM 0x0007 44 #define MBOX_ABOUT_FIRMWARE 0x0008 45 /* 9 */ 46 /* a */ 47 /* b */ 48 /* c */ 49 /* d */ 50 #define MBOX_CHECK_FIRMWARE 0x000e 51 #define MBOX_READ_RAM_WORD_EXTENDED 0x000f 52 #define MBOX_INIT_REQ_QUEUE 0x0010 53 #define MBOX_INIT_RES_QUEUE 0x0011 54 #define MBOX_EXECUTE_IOCB 0x0012 55 #define MBOX_WAKE_UP 0x0013 56 #define MBOX_STOP_FIRMWARE 0x0014 57 #define MBOX_ABORT 0x0015 58 #define MBOX_ABORT_DEVICE 0x0016 59 #define MBOX_ABORT_TARGET 0x0017 60 #define MBOX_BUS_RESET 0x0018 61 #define MBOX_STOP_QUEUE 0x0019 62 #define MBOX_START_QUEUE 0x001a 63 #define MBOX_SINGLE_STEP_QUEUE 0x001b 64 #define MBOX_ABORT_QUEUE 0x001c 65 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d 66 /* 1e */ 67 #define MBOX_GET_FIRMWARE_STATUS 0x001f 68 #define MBOX_GET_INIT_SCSI_ID 0x0020 69 #define MBOX_GET_SELECT_TIMEOUT 0x0021 70 #define MBOX_GET_RETRY_COUNT 0x0022 71 #define MBOX_GET_TAG_AGE_LIMIT 0x0023 72 #define MBOX_GET_CLOCK_RATE 0x0024 73 #define MBOX_GET_ACT_NEG_STATE 0x0025 74 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 75 #define MBOX_GET_SBUS_PARAMS 0x0027 76 #define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS 77 #define MBOX_GET_TARGET_PARAMS 0x0028 78 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 79 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a 80 /* 2b */ 81 /* 2c */ 82 /* 2d */ 83 /* 2e */ 84 /* 2f */ 85 #define MBOX_SET_INIT_SCSI_ID 0x0030 86 #define MBOX_SET_SELECT_TIMEOUT 0x0031 87 #define MBOX_SET_RETRY_COUNT 0x0032 88 #define MBOX_SET_TAG_AGE_LIMIT 0x0033 89 #define MBOX_SET_CLOCK_RATE 0x0034 90 #define MBOX_SET_ACT_NEG_STATE 0x0035 91 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 92 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 93 #define MBOX_SET_PCI_PARAMETERS 0x0037 94 #define MBOX_SET_TARGET_PARAMS 0x0038 95 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 96 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a 97 /* 3b */ 98 /* 3c */ 99 /* 3d */ 100 /* 3e */ 101 /* 3f */ 102 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 103 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 104 #define MBOX_EXEC_BIOS_IOCB 0x0042 105 #define MBOX_SET_FW_FEATURES 0x004a 106 #define MBOX_GET_FW_FEATURES 0x004b 107 #define FW_FEATURE_FAST_POST 0x1 108 #define FW_FEATURE_LVD_NOTIFY 0x2 109 #define FW_FEATURE_RIO_32BIT 0x4 110 #define FW_FEATURE_RIO_16BIT 0x8 111 112 #define MBOX_ENABLE_TARGET_MODE 0x0055 113 #define ENABLE_TARGET_FLAG 0x8000 114 #define ENABLE_TQING_FLAG 0x0004 115 #define ENABLE_MANDATORY_DISC 0x0002 116 #define MBOX_GET_TARGET_STATUS 0x0056 117 118 /* These are for the ISP2X00 FC cards */ 119 #define MBOX_GET_LOOP_ID 0x0020 120 #define MBOX_GET_FIRMWARE_OPTIONS 0x0028 121 #define MBOX_SET_FIRMWARE_OPTIONS 0x0038 122 #define MBOX_GET_RESOURCE_COUNT 0x0042 123 #define MBOX_ENHANCED_GET_PDB 0x0047 124 #define MBOX_EXEC_COMMAND_IOCB_A64 0x0054 125 #define MBOX_INIT_FIRMWARE 0x0060 126 #define MBOX_GET_INIT_CONTROL_BLOCK 0x0061 127 #define MBOX_INIT_LIP 0x0062 128 #define MBOX_GET_FC_AL_POSITION_MAP 0x0063 129 #define MBOX_GET_PORT_DB 0x0064 130 #define MBOX_CLEAR_ACA 0x0065 131 #define MBOX_TARGET_RESET 0x0066 132 #define MBOX_CLEAR_TASK_SET 0x0067 133 #define MBOX_ABORT_TASK_SET 0x0068 134 #define MBOX_GET_FW_STATE 0x0069 135 #define MBOX_GET_PORT_NAME 0x006A 136 #define MBOX_GET_LINK_STATUS 0x006B 137 #define MBOX_INIT_LIP_RESET 0x006C 138 #define MBOX_SEND_SNS 0x006E 139 #define MBOX_FABRIC_LOGIN 0x006F 140 #define MBOX_SEND_CHANGE_REQUEST 0x0070 141 #define MBOX_FABRIC_LOGOUT 0x0071 142 #define MBOX_INIT_LIP_LOGIN 0x0072 143 144 #define MBOX_DRIVER_HEARTBEAT 0x005B 145 #define MBOX_FW_HEARTBEAT 0x005C 146 147 #define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */ 148 #define MBGSD_GET_RATE 0 149 #define MBGSD_SET_RATE 1 150 #define MBGSD_ONEGB 0 151 #define MBGSD_TWOGB 1 152 #define MBGSD_AUTO 2 153 154 155 #define ISP2100_SET_PCI_PARAM 0x00ff 156 157 #define MBOX_BUSY 0x04 158 159 typedef struct { 160 u_int16_t param[8]; 161 } mbreg_t; 162 163 /* 164 * Mailbox Command Complete Status Codes 165 */ 166 #define MBOX_COMMAND_COMPLETE 0x4000 167 #define MBOX_INVALID_COMMAND 0x4001 168 #define MBOX_HOST_INTERFACE_ERROR 0x4002 169 #define MBOX_TEST_FAILED 0x4003 170 #define MBOX_COMMAND_ERROR 0x4005 171 #define MBOX_COMMAND_PARAM_ERROR 0x4006 172 #define MBOX_PORT_ID_USED 0x4007 173 #define MBOX_LOOP_ID_USED 0x4008 174 #define MBOX_ALL_IDS_USED 0x4009 175 #define MBOX_NOT_LOGGED_IN 0x400A 176 #define MBLOGALL 0x000f 177 #define MBLOGNONE 0x0000 178 #define MBLOGMASK(x) ((x) & 0xf) 179 180 /* 181 * Asynchronous event status codes 182 */ 183 #define ASYNC_BUS_RESET 0x8001 184 #define ASYNC_SYSTEM_ERROR 0x8002 185 #define ASYNC_RQS_XFER_ERR 0x8003 186 #define ASYNC_RSP_XFER_ERR 0x8004 187 #define ASYNC_QWAKEUP 0x8005 188 #define ASYNC_TIMEOUT_RESET 0x8006 189 #define ASYNC_DEVICE_RESET 0x8007 190 #define ASYNC_EXTMSG_UNDERRUN 0x800A 191 #define ASYNC_SCAM_INT 0x800B 192 #define ASYNC_HUNG_SCSI 0x800C 193 #define ASYNC_KILLED_BUS 0x800D 194 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 195 #define ASYNC_LIP_OCCURRED 0x8010 196 #define ASYNC_LOOP_UP 0x8011 197 #define ASYNC_LOOP_DOWN 0x8012 198 #define ASYNC_LOOP_RESET 0x8013 199 #define ASYNC_PDB_CHANGED 0x8014 200 #define ASYNC_CHANGE_NOTIFY 0x8015 201 #define ASYNC_LIP_F8 0x8016 202 #define ASYNC_CMD_CMPLT 0x8020 203 #define ASYNC_CTIO_DONE 0x8021 204 #define ASYNC_IP_XMIT_DONE 0x8022 205 #define ASYNC_IP_RECV_DONE 0x8023 206 #define ASYNC_IP_BROADCAST 0x8024 207 #define ASYNC_IP_RCVQ_LOW 0x8025 208 #define ASYNC_IP_RCVQ_EMPTY 0x8026 209 #define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 210 #define ASYNC_PTPMODE 0x8030 211 #define ASYNC_RIO1 0x8031 212 #define ASYNC_RIO2 0x8032 213 #define ASYNC_RIO3 0x8033 214 #define ASYNC_RIO4 0x8034 215 #define ASYNC_RIO5 0x8035 216 #define ASYNC_CONNMODE 0x8036 217 #define ISP_CONN_LOOP 1 218 #define ISP_CONN_PTP 2 219 #define ISP_CONN_BADLIP 3 220 #define ISP_CONN_FATAL 4 221 #define ISP_CONN_LOOPBACK 5 222 #define ASYNC_RIO_RESP 0x8040 223 #define ASYNC_RIO_COMP 0x8042 224 /* 225 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options 226 * mailbox command to enable this. 227 */ 228 #define ASYNC_QFULL_SENT 0x8049 229 230 /* 231 * Mailbox Usages 232 */ 233 234 #define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \ 235 ISP_WRITE(isp, isp->isp_rqstinrp, value) 236 237 #define READ_REQUEST_QUEUE_OUT_POINTER(isp) \ 238 ISP_READ(isp, isp->isp_rqstoutrp) 239 240 #define READ_RESPONSE_QUEUE_IN_POINTER(isp) \ 241 ISP_READ(isp, isp->isp_respinrp) 242 243 #define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \ 244 ISP_WRITE(isp, isp->isp_respoutrp, value) 245 246 /* 247 * Command Structure Definitions 248 */ 249 250 typedef struct { 251 u_int32_t ds_base; 252 u_int32_t ds_count; 253 } ispds_t; 254 255 typedef struct { 256 u_int32_t ds_base; 257 u_int32_t ds_basehi; 258 u_int32_t ds_count; 259 } ispds64_t; 260 261 #define DSTYPE_32BIT 0 262 #define DSTYPE_64BIT 1 263 typedef struct { 264 u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */ 265 u_int32_t ds_segment; /* unused */ 266 u_int32_t ds_base; /* 32 bit address of DSD list */ 267 } ispdslist_t; 268 269 270 /* 271 * These elements get swizzled around for SBus instances. 272 */ 273 #define ISP_SWAP8(a, b) { \ 274 u_int8_t tmp; \ 275 tmp = a; \ 276 a = b; \ 277 b = tmp; \ 278 } 279 typedef struct { 280 u_int8_t rqs_entry_type; 281 u_int8_t rqs_entry_count; 282 u_int8_t rqs_seqno; 283 u_int8_t rqs_flags; 284 } isphdr_t; 285 286 /* RQS Flag definitions */ 287 #define RQSFLAG_CONTINUATION 0x01 288 #define RQSFLAG_FULL 0x02 289 #define RQSFLAG_BADHEADER 0x04 290 #define RQSFLAG_BADPACKET 0x08 291 292 /* RQS entry_type definitions */ 293 #define RQSTYPE_REQUEST 0x01 294 #define RQSTYPE_DATASEG 0x02 295 #define RQSTYPE_RESPONSE 0x03 296 #define RQSTYPE_MARKER 0x04 297 #define RQSTYPE_CMDONLY 0x05 298 #define RQSTYPE_ATIO 0x06 /* Target Mode */ 299 #define RQSTYPE_CTIO 0x07 /* Target Mode */ 300 #define RQSTYPE_SCAM 0x08 301 #define RQSTYPE_A64 0x09 302 #define RQSTYPE_A64_CONT 0x0a 303 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 304 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 305 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 306 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 307 #define RQSTYPE_CTIO1 0x0f /* Target Mode */ 308 #define RQSTYPE_STATUS_CONT 0x10 309 #define RQSTYPE_T2RQS 0x11 310 #define RQSTYPE_IP_XMIT 0x13 311 #define RQSTYPE_T4RQS 0x15 312 #define RQSTYPE_ATIO2 0x16 /* Target Mode */ 313 #define RQSTYPE_CTIO2 0x17 /* Target Mode */ 314 #define RQSTYPE_CSET0 0x18 315 #define RQSTYPE_T3RQS 0x19 316 #define RQSTYPE_IP_XMIT_64 0x1b 317 #define RQSTYPE_CTIO4 0x1e /* Target Mode */ 318 #define RQSTYPE_CTIO3 0x1f /* Target Mode */ 319 #define RQSTYPE_RIO1 0x21 320 #define RQSTYPE_RIO2 0x22 321 #define RQSTYPE_IP_RECV 0x23 322 #define RQSTYPE_IP_RECV_CONT 0x24 323 324 325 #define ISP_RQDSEG 4 326 typedef struct { 327 isphdr_t req_header; 328 u_int32_t req_handle; 329 u_int8_t req_lun_trn; 330 u_int8_t req_target; 331 u_int16_t req_cdblen; 332 #define req_modifier req_cdblen /* marker packet */ 333 u_int16_t req_flags; 334 u_int16_t req_reserved; 335 u_int16_t req_time; 336 u_int16_t req_seg_count; 337 u_int8_t req_cdb[12]; 338 ispds_t req_dataseg[ISP_RQDSEG]; 339 } ispreq_t; 340 341 /* 342 * A request packet can also be a marker packet. 343 */ 344 #define SYNC_DEVICE 0 345 #define SYNC_TARGET 1 346 #define SYNC_ALL 2 347 348 #define ISP_RQDSEG_T2 3 349 typedef struct { 350 isphdr_t req_header; 351 u_int32_t req_handle; 352 u_int8_t req_lun_trn; 353 u_int8_t req_target; 354 u_int16_t req_scclun; 355 u_int16_t req_flags; 356 u_int16_t _res2; 357 u_int16_t req_time; 358 u_int16_t req_seg_count; 359 u_int8_t req_cdb[16]; 360 u_int32_t req_totalcnt; 361 ispds_t req_dataseg[ISP_RQDSEG_T2]; 362 } ispreqt2_t; 363 364 #define ISP_RQDSEG_T3 2 365 typedef struct { 366 isphdr_t req_header; 367 u_int32_t req_handle; 368 u_int8_t req_lun_trn; 369 u_int8_t req_target; 370 u_int16_t req_scclun; 371 u_int16_t req_flags; 372 u_int16_t _res2; 373 u_int16_t req_time; 374 u_int16_t req_seg_count; 375 u_int8_t req_cdb[16]; 376 u_int32_t req_totalcnt; 377 ispds64_t req_dataseg[ISP_RQDSEG_T3]; 378 } ispreqt3_t; 379 380 /* req_flag values */ 381 #define REQFLAG_NODISCON 0x0001 382 #define REQFLAG_HTAG 0x0002 383 #define REQFLAG_OTAG 0x0004 384 #define REQFLAG_STAG 0x0008 385 #define REQFLAG_TARGET_RTN 0x0010 386 387 #define REQFLAG_NODATA 0x0000 388 #define REQFLAG_DATA_IN 0x0020 389 #define REQFLAG_DATA_OUT 0x0040 390 #define REQFLAG_DATA_UNKNOWN 0x0060 391 392 #define REQFLAG_DISARQ 0x0100 393 #define REQFLAG_FRC_ASYNC 0x0200 394 #define REQFLAG_FRC_SYNC 0x0400 395 #define REQFLAG_FRC_WIDE 0x0800 396 #define REQFLAG_NOPARITY 0x1000 397 #define REQFLAG_STOPQ 0x2000 398 #define REQFLAG_XTRASNS 0x4000 399 #define REQFLAG_PRIORITY 0x8000 400 401 typedef struct { 402 isphdr_t req_header; 403 u_int32_t req_handle; 404 u_int8_t req_lun_trn; 405 u_int8_t req_target; 406 u_int16_t req_cdblen; 407 u_int16_t req_flags; 408 u_int16_t _res1; 409 u_int16_t req_time; 410 u_int16_t req_seg_count; 411 u_int8_t req_cdb[44]; 412 } ispextreq_t; 413 414 #define ISP_CDSEG 7 415 typedef struct { 416 isphdr_t req_header; 417 u_int32_t _res1; 418 ispds_t req_dataseg[ISP_CDSEG]; 419 } ispcontreq_t; 420 421 #define ISP_CDSEG64 5 422 typedef struct { 423 isphdr_t req_header; 424 ispds64_t req_dataseg[ISP_CDSEG64]; 425 } ispcontreq64_t; 426 427 typedef struct { 428 isphdr_t req_header; 429 u_int32_t req_handle; 430 u_int16_t req_scsi_status; 431 u_int16_t req_completion_status; 432 u_int16_t req_state_flags; 433 u_int16_t req_status_flags; 434 u_int16_t req_time; 435 #define req_response_len req_time /* FC only */ 436 u_int16_t req_sense_len; 437 u_int32_t req_resid; 438 u_int8_t req_response[8]; /* FC only */ 439 u_int8_t req_sense_data[32]; 440 } ispstatusreq_t; 441 442 typedef struct { 443 isphdr_t req_header; 444 u_int8_t req_sense_data[60]; 445 } ispstatus_cont_t; 446 447 /* 448 * For Qlogic 2X00, the high order byte of SCSI status has 449 * additional meaning. 450 */ 451 #define RQCS_RU 0x800 /* Residual Under */ 452 #define RQCS_RO 0x400 /* Residual Over */ 453 #define RQCS_RESID (RQCS_RU|RQCS_RO) 454 #define RQCS_SV 0x200 /* Sense Length Valid */ 455 #define RQCS_RV 0x100 /* FCP Response Length Valid */ 456 457 /* 458 * Completion Status Codes. 459 */ 460 #define RQCS_COMPLETE 0x0000 461 #define RQCS_DMA_ERROR 0x0002 462 #define RQCS_RESET_OCCURRED 0x0004 463 #define RQCS_ABORTED 0x0005 464 #define RQCS_TIMEOUT 0x0006 465 #define RQCS_DATA_OVERRUN 0x0007 466 #define RQCS_DATA_UNDERRUN 0x0015 467 #define RQCS_QUEUE_FULL 0x001C 468 469 /* 1X00 Only Completion Codes */ 470 #define RQCS_INCOMPLETE 0x0001 471 #define RQCS_TRANSPORT_ERROR 0x0003 472 #define RQCS_COMMAND_OVERRUN 0x0008 473 #define RQCS_STATUS_OVERRUN 0x0009 474 #define RQCS_BAD_MESSAGE 0x000a 475 #define RQCS_NO_MESSAGE_OUT 0x000b 476 #define RQCS_EXT_ID_FAILED 0x000c 477 #define RQCS_IDE_MSG_FAILED 0x000d 478 #define RQCS_ABORT_MSG_FAILED 0x000e 479 #define RQCS_REJECT_MSG_FAILED 0x000f 480 #define RQCS_NOP_MSG_FAILED 0x0010 481 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 482 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 483 #define RQCS_ID_MSG_FAILED 0x0013 484 #define RQCS_UNEXP_BUS_FREE 0x0014 485 #define RQCS_XACT_ERR1 0x0018 486 #define RQCS_XACT_ERR2 0x0019 487 #define RQCS_XACT_ERR3 0x001A 488 #define RQCS_BAD_ENTRY 0x001B 489 #define RQCS_PHASE_SKIPPED 0x001D 490 #define RQCS_ARQS_FAILED 0x001E 491 #define RQCS_WIDE_FAILED 0x001F 492 #define RQCS_SYNCXFER_FAILED 0x0020 493 #define RQCS_LVD_BUSERR 0x0021 494 495 /* 2X00 Only Completion Codes */ 496 #define RQCS_PORT_UNAVAILABLE 0x0028 497 #define RQCS_PORT_LOGGED_OUT 0x0029 498 #define RQCS_PORT_CHANGED 0x002A 499 #define RQCS_PORT_BUSY 0x002B 500 501 /* 502 * 1X00 specific State Flags 503 */ 504 #define RQSF_GOT_BUS 0x0100 505 #define RQSF_GOT_TARGET 0x0200 506 #define RQSF_SENT_CDB 0x0400 507 #define RQSF_XFRD_DATA 0x0800 508 #define RQSF_GOT_STATUS 0x1000 509 #define RQSF_GOT_SENSE 0x2000 510 #define RQSF_XFER_COMPLETE 0x4000 511 512 /* 513 * 2X00 specific State Flags 514 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available) 515 */ 516 #define RQSF_DATA_IN 0x0020 517 #define RQSF_DATA_OUT 0x0040 518 #define RQSF_STAG 0x0008 519 #define RQSF_OTAG 0x0004 520 #define RQSF_HTAG 0x0002 521 /* 522 * 1X00 Status Flags 523 */ 524 #define RQSTF_DISCONNECT 0x0001 525 #define RQSTF_SYNCHRONOUS 0x0002 526 #define RQSTF_PARITY_ERROR 0x0004 527 #define RQSTF_BUS_RESET 0x0008 528 #define RQSTF_DEVICE_RESET 0x0010 529 #define RQSTF_ABORTED 0x0020 530 #define RQSTF_TIMEOUT 0x0040 531 #define RQSTF_NEGOTIATION 0x0080 532 533 /* 534 * 2X00 specific state flags 535 */ 536 /* RQSF_SENT_CDB */ 537 /* RQSF_XFRD_DATA */ 538 /* RQSF_GOT_STATUS */ 539 /* RQSF_XFER_COMPLETE */ 540 541 /* 542 * 2X00 specific status flags 543 */ 544 /* RQSTF_ABORTED */ 545 /* RQSTF_TIMEOUT */ 546 #define RQSTF_DMA_ERROR 0x0080 547 #define RQSTF_LOGOUT 0x2000 548 549 /* 550 * Miscellaneous 551 */ 552 #ifndef ISP_EXEC_THROTTLE 553 #define ISP_EXEC_THROTTLE 16 554 #endif 555 556 /* 557 * About Firmware returns an 'attribute' word in mailbox 6. 558 */ 559 #define ISP_FW_ATTR_TMODE 0x01 560 #define ISP_FW_ATTR_SCCLUN 0x02 561 #define ISP_FW_ATTR_FABRIC 0x04 562 #define ISP_FW_ATTR_CLASS2 0x08 563 #define ISP_FW_ATTR_FCTAPE 0x10 564 #define ISP_FW_ATTR_IP 0x20 565 566 /* 567 * Reduced Interrupt Operation Response Queue Entreis 568 */ 569 570 typedef struct { 571 isphdr_t req_header; 572 u_int32_t req_handles[15]; 573 } isp_rio1_t; 574 575 typedef struct { 576 isphdr_t req_header; 577 u_int16_t req_handles[30]; 578 } isp_rio2_t; 579 580 /* 581 * FC (ISP2100) specific data structures 582 */ 583 584 /* 585 * Initialization Control Block 586 * 587 * Version One (prime) format. 588 */ 589 typedef struct isp_icb { 590 u_int8_t icb_version; 591 u_int8_t _reserved0; 592 u_int16_t icb_fwoptions; 593 u_int16_t icb_maxfrmlen; 594 u_int16_t icb_maxalloc; 595 u_int16_t icb_execthrottle; 596 u_int8_t icb_retry_count; 597 u_int8_t icb_retry_delay; 598 u_int8_t icb_portname[8]; 599 u_int16_t icb_hardaddr; 600 u_int8_t icb_iqdevtype; 601 u_int8_t icb_logintime; 602 u_int8_t icb_nodename[8]; 603 u_int16_t icb_rqstout; 604 u_int16_t icb_rspnsin; 605 u_int16_t icb_rqstqlen; 606 u_int16_t icb_rsltqlen; 607 u_int16_t icb_rqstaddr[4]; 608 u_int16_t icb_respaddr[4]; 609 u_int16_t icb_lunenables; 610 u_int8_t icb_ccnt; 611 u_int8_t icb_icnt; 612 u_int16_t icb_lunetimeout; 613 u_int16_t _reserved1; 614 u_int16_t icb_xfwoptions; 615 u_int8_t icb_racctimer; 616 u_int8_t icb_idelaytimer; 617 u_int16_t icb_zfwoptions; 618 u_int16_t _reserved2[13]; 619 } isp_icb_t; 620 #define ICB_VERSION1 1 621 622 #define ICBOPT_HARD_ADDRESS 0x0001 623 #define ICBOPT_FAIRNESS 0x0002 624 #define ICBOPT_FULL_DUPLEX 0x0004 625 #define ICBOPT_FAST_POST 0x0008 626 #define ICBOPT_TGT_ENABLE 0x0010 627 #define ICBOPT_INI_DISABLE 0x0020 628 #define ICBOPT_INI_ADISC 0x0040 629 #define ICBOPT_INI_TGTTYPE 0x0080 630 #define ICBOPT_PDBCHANGE_AE 0x0100 631 #define ICBOPT_NOLIP 0x0200 632 #define ICBOPT_SRCHDOWN 0x0400 633 #define ICBOPT_PREVLOOP 0x0800 634 #define ICBOPT_STOP_ON_QFULL 0x1000 635 #define ICBOPT_FULL_LOGIN 0x2000 636 #define ICBOPT_BOTH_WWNS 0x4000 637 #define ICBOPT_EXTENDED 0x8000 638 639 #define ICBXOPT_CLASS2_ACK0 0x0200 640 #define ICBXOPT_CLASS2 0x0100 641 #define ICBXOPT_LOOP_ONLY (0 << 4) 642 #define ICBXOPT_PTP_ONLY (1 << 4) 643 #define ICBXOPT_LOOP_2_PTP (2 << 4) 644 #define ICBXOPT_PTP_2_LOOP (3 << 4) 645 646 #define ICBXOPT_RIO_OFF 0 647 #define ICBXOPT_RIO_16BIT 1 648 #define ICBXOPT_RIO_32BIT 2 649 #define ICBXOPT_RIO_16BIT_IOCB 3 650 #define ICBXOPT_RIO_32BIT_IOCB 4 651 652 #define ICBZOPT_ENA_RDXFR_RDY 0x01 653 #define ICBZOPT_ENA_OOF (1 << 6) /* out of order frame handling */ 654 /* These 3 only apply to the 2300 */ 655 #define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14) 656 #define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14) 657 #define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14) 658 659 660 #define ICB_MIN_FRMLEN 256 661 #define ICB_MAX_FRMLEN 2112 662 #define ICB_DFLT_FRMLEN 1024 663 #define ICB_DFLT_ALLOC 256 664 #define ICB_DFLT_THROTTLE 16 665 #define ICB_DFLT_RDELAY 5 666 #define ICB_DFLT_RCOUNT 3 667 668 669 #define RQRSP_ADDR0015 0 670 #define RQRSP_ADDR1631 1 671 #define RQRSP_ADDR3247 2 672 #define RQRSP_ADDR4863 3 673 674 675 #define ICB_NNM0 7 676 #define ICB_NNM1 6 677 #define ICB_NNM2 5 678 #define ICB_NNM3 4 679 #define ICB_NNM4 3 680 #define ICB_NNM5 2 681 #define ICB_NNM6 1 682 #define ICB_NNM7 0 683 684 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 685 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ 686 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ 687 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ 688 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ 689 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ 690 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ 691 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ 692 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) 693 694 /* 695 * FC-AL Position Map 696 * 697 * This is an at most 128 byte map that returns either 698 * the LILP or Firmware generated list of ports. 699 * 700 * We deviate a bit from the returned qlogic format to 701 * use an extra bit to say whether this was a LILP or 702 * f/w generated map. 703 */ 704 typedef struct { 705 u_int8_t fwmap : 1, 706 count : 7; 707 u_int8_t map[127]; 708 } fcpos_map_t; 709 710 /* 711 * Port Data Base Element 712 */ 713 714 typedef struct { 715 u_int16_t pdb_options; 716 u_int8_t pdb_mstate; 717 u_int8_t pdb_sstate; 718 #define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2]) 719 u_int8_t pdb_hardaddr_bits[4]; 720 u_int8_t pdb_portid_bits[4]; 721 u_int8_t pdb_nodename[8]; 722 u_int8_t pdb_portname[8]; 723 u_int16_t pdb_execthrottle; 724 u_int16_t pdb_exec_count; 725 u_int8_t pdb_retry_count; 726 u_int8_t pdb_retry_delay; 727 u_int16_t pdb_resalloc; 728 u_int16_t pdb_curalloc; 729 u_int16_t pdb_qhead; 730 u_int16_t pdb_qtail; 731 u_int16_t pdb_tl_next; 732 u_int16_t pdb_tl_last; 733 u_int16_t pdb_features; /* PLOGI, Common Service */ 734 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */ 735 u_int16_t pdb_roi; /* PLOGI, Common Service */ 736 u_int8_t pdb_target; 737 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ 738 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */ 739 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */ 740 u_int16_t pdb_noseq; /* PLOGI, Class 3 */ 741 u_int16_t pdb_labrtflg; 742 u_int16_t pdb_lstopflg; 743 u_int16_t pdb_sqhead; 744 u_int16_t pdb_sqtail; 745 u_int16_t pdb_ptimer; 746 u_int16_t pdb_nxt_seqid; 747 u_int16_t pdb_fcount; 748 u_int16_t pdb_prli_len; 749 u_int16_t pdb_prli_svc0; 750 u_int16_t pdb_prli_svc3; 751 u_int16_t pdb_loopid; 752 u_int16_t pdb_il_ptr; 753 u_int16_t pdb_sl_ptr; 754 } isp_pdb_t; 755 756 #define PDB_OPTIONS_XMITTING (1<<11) 757 #define PDB_OPTIONS_LNKXMIT (1<<10) 758 #define PDB_OPTIONS_ABORTED (1<<9) 759 #define PDB_OPTIONS_ADISC (1<<1) 760 761 #define PDB_STATE_DISCOVERY 0 762 #define PDB_STATE_WDISC_ACK 1 763 #define PDB_STATE_PLOGI 2 764 #define PDB_STATE_PLOGI_ACK 3 765 #define PDB_STATE_PRLI 4 766 #define PDB_STATE_PRLI_ACK 5 767 #define PDB_STATE_LOGGED_IN 6 768 #define PDB_STATE_PORT_UNAVAIL 7 769 #define PDB_STATE_PRLO 8 770 #define PDB_STATE_PRLO_ACK 9 771 #define PDB_STATE_PLOGO 10 772 #define PDB_STATE_PLOG_ACK 11 773 774 #define SVC3_TGT_ROLE 0x10 775 #define SVC3_INI_ROLE 0x20 776 #define SVC3_ROLE_MASK 0x30 777 #define SVC3_ROLE_SHIFT 4 778 779 /* 780 * CT definition 781 * 782 * This is as the QLogic f/w documentations defines it- which is just opposite, 783 * bit wise, from what the specification defines it as. Additionally, the 784 * ct_response and ct_resid (really from FC-GS-2) need to be byte swapped. 785 */ 786 787 typedef struct { 788 u_int8_t ct_revision; 789 u_int8_t ct_portid[3]; 790 u_int8_t ct_fcs_type; 791 u_int8_t ct_fcs_subtype; 792 u_int8_t ct_options; 793 u_int8_t ct_res0; 794 u_int16_t ct_response; 795 u_int16_t ct_resid; 796 u_int8_t ct_res1; 797 u_int8_t ct_reason; 798 u_int8_t ct_explanation; 799 u_int8_t ct_vunique; 800 } ct_hdr_t; 801 #define FS_ACC 0x8002 802 #define FS_RJT 0x8001 803 804 #define FC4_IP 5 /* ISO/EEC 8802-2 LLC/SNAP "Out of Order Delivery" */ 805 #define FC4_SCSI 8 /* SCSI-3 via Fivre Channel Protocol (FCP) */ 806 #define FC4_FC_SVC 0x20 /* Fibre Channel Services */ 807 808 #define SNS_GA_NXT 0x100 809 #define SNS_GPN_ID 0x112 810 #define SNS_GNN_ID 0x113 811 #define SNS_GFF_ID 0x11F 812 #define SNS_GID_FT 0x171 813 #define SNS_RFT_ID 0x217 814 typedef struct { 815 u_int16_t snscb_rblen; /* response buffer length (words) */ 816 u_int16_t snscb_res0; 817 u_int16_t snscb_addr[4]; /* response buffer address */ 818 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 819 u_int16_t snscb_res1; 820 u_int16_t snscb_data[1]; /* variable data */ 821 } sns_screq_t; /* Subcommand Request Structure */ 822 823 typedef struct { 824 u_int16_t snscb_rblen; /* response buffer length (words) */ 825 u_int16_t snscb_res0; 826 u_int16_t snscb_addr[4]; /* response buffer address */ 827 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 828 u_int16_t snscb_res1; 829 u_int16_t snscb_cmd; 830 u_int16_t snscb_res2; 831 u_int32_t snscb_res3; 832 u_int32_t snscb_port; 833 } sns_ga_nxt_req_t; 834 #define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t)) 835 836 typedef struct { 837 u_int16_t snscb_rblen; /* response buffer length (words) */ 838 u_int16_t snscb_res0; 839 u_int16_t snscb_addr[4]; /* response buffer address */ 840 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 841 u_int16_t snscb_res1; 842 u_int16_t snscb_cmd; 843 u_int16_t snscb_res2; 844 u_int32_t snscb_res3; 845 u_int32_t snscb_portid; 846 } sns_gxn_id_req_t; 847 #define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t)) 848 849 typedef struct { 850 u_int16_t snscb_rblen; /* response buffer length (words) */ 851 u_int16_t snscb_res0; 852 u_int16_t snscb_addr[4]; /* response buffer address */ 853 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 854 u_int16_t snscb_res1; 855 u_int16_t snscb_cmd; 856 u_int16_t snscb_mword_div_2; 857 u_int32_t snscb_res3; 858 u_int32_t snscb_fc4_type; 859 } sns_gid_ft_req_t; 860 #define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t)) 861 862 typedef struct { 863 u_int16_t snscb_rblen; /* response buffer length (words) */ 864 u_int16_t snscb_res0; 865 u_int16_t snscb_addr[4]; /* response buffer address */ 866 u_int16_t snscb_sblen; /* subcommand buffer length (words) */ 867 u_int16_t snscb_res1; 868 u_int16_t snscb_cmd; 869 u_int16_t snscb_res2; 870 u_int32_t snscb_res3; 871 u_int32_t snscb_port; 872 u_int32_t snscb_fc4_types[8]; 873 } sns_rft_id_req_t; 874 #define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t)) 875 876 typedef struct { 877 ct_hdr_t snscb_cthdr; 878 u_int8_t snscb_port_type; 879 u_int8_t snscb_port_id[3]; 880 u_int8_t snscb_portname[8]; 881 u_int16_t snscb_data[1]; /* variable data */ 882 } sns_scrsp_t; /* Subcommand Response Structure */ 883 884 typedef struct { 885 ct_hdr_t snscb_cthdr; 886 u_int8_t snscb_port_type; 887 u_int8_t snscb_port_id[3]; 888 u_int8_t snscb_portname[8]; 889 u_int8_t snscb_pnlen; /* symbolic port name length */ 890 u_int8_t snscb_pname[255]; /* symbolic port name */ 891 u_int8_t snscb_nodename[8]; 892 u_int8_t snscb_nnlen; /* symbolic node name length */ 893 u_int8_t snscb_nname[255]; /* symbolic node name */ 894 u_int8_t snscb_ipassoc[8]; 895 u_int8_t snscb_ipaddr[16]; 896 u_int8_t snscb_svc_class[4]; 897 u_int8_t snscb_fc4_types[32]; 898 u_int8_t snscb_fpname[8]; 899 u_int8_t snscb_reserved; 900 u_int8_t snscb_hardaddr[3]; 901 } sns_ga_nxt_rsp_t; /* Subcommand Response Structure */ 902 #define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t)) 903 904 typedef struct { 905 ct_hdr_t snscb_cthdr; 906 u_int8_t snscb_wwn[8]; 907 } sns_gxn_id_rsp_t; 908 #define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t)) 909 910 typedef struct { 911 ct_hdr_t snscb_cthdr; 912 u_int32_t snscb_fc4_features[32]; 913 } sns_gff_id_rsp_t; 914 #define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t)) 915 916 typedef struct { 917 ct_hdr_t snscb_cthdr; 918 struct { 919 u_int8_t control; 920 u_int8_t portid[3]; 921 } snscb_ports[1]; 922 } sns_gid_ft_rsp_t; 923 #define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2)) 924 925 #define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t)) 926 927 #endif /* _ISPMBOX_H */ 928