xref: /freebsd/sys/dev/isp/isp_pci.c (revision fc7284da06408923f7850a0e4e954a903b8ee038)
1 /*-
2  * Copyright (c) 1997-2008 by Matthew Jacob
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice immediately at the beginning of the file, without modification,
10  *    this list of conditions, and the following disclaimer.
11  * 2. The name of the author may not be used to endorse or promote products
12  *    derived from this software without specific prior written permission.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 /*
27  * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
28  * FreeBSD Version.
29  */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/linker.h>
38 #include <sys/firmware.h>
39 #include <sys/bus.h>
40 #include <sys/stdint.h>
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcivar.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <sys/rman.h>
46 #include <sys/malloc.h>
47 #include <sys/uio.h>
48 
49 #ifdef __sparc64__
50 #include <dev/ofw/openfirm.h>
51 #include <machine/ofw_machdep.h>
52 #endif
53 
54 #include <dev/isp/isp_freebsd.h>
55 
56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int);
57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t);
58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int);
59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t);
60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int);
61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t);
62 static uint32_t isp_pci_rd_reg_2600(ispsoftc_t *, int);
63 static void isp_pci_wr_reg_2600(ispsoftc_t *, int, uint32_t);
64 static int isp_pci_rd_isr(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
65 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
66 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
67 static int isp_pci_mbxdma(ispsoftc_t *);
68 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *);
69 
70 
71 static void isp_pci_reset0(ispsoftc_t *);
72 static void isp_pci_reset1(ispsoftc_t *);
73 static void isp_pci_dumpregs(ispsoftc_t *, const char *);
74 
75 static struct ispmdvec mdvec = {
76 	isp_pci_rd_isr,
77 	isp_pci_rd_reg,
78 	isp_pci_wr_reg,
79 	isp_pci_mbxdma,
80 	isp_pci_dmasetup,
81 	isp_common_dmateardown,
82 	isp_pci_reset0,
83 	isp_pci_reset1,
84 	isp_pci_dumpregs,
85 	NULL,
86 	BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
87 };
88 
89 static struct ispmdvec mdvec_1080 = {
90 	isp_pci_rd_isr,
91 	isp_pci_rd_reg_1080,
92 	isp_pci_wr_reg_1080,
93 	isp_pci_mbxdma,
94 	isp_pci_dmasetup,
95 	isp_common_dmateardown,
96 	isp_pci_reset0,
97 	isp_pci_reset1,
98 	isp_pci_dumpregs,
99 	NULL,
100 	BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
101 };
102 
103 static struct ispmdvec mdvec_12160 = {
104 	isp_pci_rd_isr,
105 	isp_pci_rd_reg_1080,
106 	isp_pci_wr_reg_1080,
107 	isp_pci_mbxdma,
108 	isp_pci_dmasetup,
109 	isp_common_dmateardown,
110 	isp_pci_reset0,
111 	isp_pci_reset1,
112 	isp_pci_dumpregs,
113 	NULL,
114 	BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
115 };
116 
117 static struct ispmdvec mdvec_2100 = {
118 	isp_pci_rd_isr,
119 	isp_pci_rd_reg,
120 	isp_pci_wr_reg,
121 	isp_pci_mbxdma,
122 	isp_pci_dmasetup,
123 	isp_common_dmateardown,
124 	isp_pci_reset0,
125 	isp_pci_reset1,
126 	isp_pci_dumpregs
127 };
128 
129 static struct ispmdvec mdvec_2200 = {
130 	isp_pci_rd_isr,
131 	isp_pci_rd_reg,
132 	isp_pci_wr_reg,
133 	isp_pci_mbxdma,
134 	isp_pci_dmasetup,
135 	isp_common_dmateardown,
136 	isp_pci_reset0,
137 	isp_pci_reset1,
138 	isp_pci_dumpregs
139 };
140 
141 static struct ispmdvec mdvec_2300 = {
142 	isp_pci_rd_isr_2300,
143 	isp_pci_rd_reg,
144 	isp_pci_wr_reg,
145 	isp_pci_mbxdma,
146 	isp_pci_dmasetup,
147 	isp_common_dmateardown,
148 	isp_pci_reset0,
149 	isp_pci_reset1,
150 	isp_pci_dumpregs
151 };
152 
153 static struct ispmdvec mdvec_2400 = {
154 	isp_pci_rd_isr_2400,
155 	isp_pci_rd_reg_2400,
156 	isp_pci_wr_reg_2400,
157 	isp_pci_mbxdma,
158 	isp_pci_dmasetup,
159 	isp_common_dmateardown,
160 	isp_pci_reset0,
161 	isp_pci_reset1,
162 	NULL
163 };
164 
165 static struct ispmdvec mdvec_2500 = {
166 	isp_pci_rd_isr_2400,
167 	isp_pci_rd_reg_2400,
168 	isp_pci_wr_reg_2400,
169 	isp_pci_mbxdma,
170 	isp_pci_dmasetup,
171 	isp_common_dmateardown,
172 	isp_pci_reset0,
173 	isp_pci_reset1,
174 	NULL
175 };
176 
177 static struct ispmdvec mdvec_2600 = {
178 	isp_pci_rd_isr_2400,
179 	isp_pci_rd_reg_2600,
180 	isp_pci_wr_reg_2600,
181 	isp_pci_mbxdma,
182 	isp_pci_dmasetup,
183 	isp_common_dmateardown,
184 	isp_pci_reset0,
185 	isp_pci_reset1,
186 	NULL
187 };
188 
189 #ifndef	PCIM_CMD_INVEN
190 #define	PCIM_CMD_INVEN			0x10
191 #endif
192 #ifndef	PCIM_CMD_BUSMASTEREN
193 #define	PCIM_CMD_BUSMASTEREN		0x0004
194 #endif
195 #ifndef	PCIM_CMD_PERRESPEN
196 #define	PCIM_CMD_PERRESPEN		0x0040
197 #endif
198 #ifndef	PCIM_CMD_SEREN
199 #define	PCIM_CMD_SEREN			0x0100
200 #endif
201 #ifndef	PCIM_CMD_INTX_DISABLE
202 #define	PCIM_CMD_INTX_DISABLE		0x0400
203 #endif
204 
205 #ifndef	PCIR_COMMAND
206 #define	PCIR_COMMAND			0x04
207 #endif
208 
209 #ifndef	PCIR_CACHELNSZ
210 #define	PCIR_CACHELNSZ			0x0c
211 #endif
212 
213 #ifndef	PCIR_LATTIMER
214 #define	PCIR_LATTIMER			0x0d
215 #endif
216 
217 #ifndef	PCIR_ROMADDR
218 #define	PCIR_ROMADDR			0x30
219 #endif
220 
221 #ifndef	PCI_VENDOR_QLOGIC
222 #define	PCI_VENDOR_QLOGIC		0x1077
223 #endif
224 
225 #ifndef	PCI_PRODUCT_QLOGIC_ISP1020
226 #define	PCI_PRODUCT_QLOGIC_ISP1020	0x1020
227 #endif
228 
229 #ifndef	PCI_PRODUCT_QLOGIC_ISP1080
230 #define	PCI_PRODUCT_QLOGIC_ISP1080	0x1080
231 #endif
232 
233 #ifndef	PCI_PRODUCT_QLOGIC_ISP10160
234 #define	PCI_PRODUCT_QLOGIC_ISP10160	0x1016
235 #endif
236 
237 #ifndef	PCI_PRODUCT_QLOGIC_ISP12160
238 #define	PCI_PRODUCT_QLOGIC_ISP12160	0x1216
239 #endif
240 
241 #ifndef	PCI_PRODUCT_QLOGIC_ISP1240
242 #define	PCI_PRODUCT_QLOGIC_ISP1240	0x1240
243 #endif
244 
245 #ifndef	PCI_PRODUCT_QLOGIC_ISP1280
246 #define	PCI_PRODUCT_QLOGIC_ISP1280	0x1280
247 #endif
248 
249 #ifndef	PCI_PRODUCT_QLOGIC_ISP2100
250 #define	PCI_PRODUCT_QLOGIC_ISP2100	0x2100
251 #endif
252 
253 #ifndef	PCI_PRODUCT_QLOGIC_ISP2200
254 #define	PCI_PRODUCT_QLOGIC_ISP2200	0x2200
255 #endif
256 
257 #ifndef	PCI_PRODUCT_QLOGIC_ISP2300
258 #define	PCI_PRODUCT_QLOGIC_ISP2300	0x2300
259 #endif
260 
261 #ifndef	PCI_PRODUCT_QLOGIC_ISP2312
262 #define	PCI_PRODUCT_QLOGIC_ISP2312	0x2312
263 #endif
264 
265 #ifndef	PCI_PRODUCT_QLOGIC_ISP2322
266 #define	PCI_PRODUCT_QLOGIC_ISP2322	0x2322
267 #endif
268 
269 #ifndef	PCI_PRODUCT_QLOGIC_ISP2422
270 #define	PCI_PRODUCT_QLOGIC_ISP2422	0x2422
271 #endif
272 
273 #ifndef	PCI_PRODUCT_QLOGIC_ISP2432
274 #define	PCI_PRODUCT_QLOGIC_ISP2432	0x2432
275 #endif
276 
277 #ifndef	PCI_PRODUCT_QLOGIC_ISP2532
278 #define	PCI_PRODUCT_QLOGIC_ISP2532	0x2532
279 #endif
280 
281 #ifndef	PCI_PRODUCT_QLOGIC_ISP6312
282 #define	PCI_PRODUCT_QLOGIC_ISP6312	0x6312
283 #endif
284 
285 #ifndef	PCI_PRODUCT_QLOGIC_ISP6322
286 #define	PCI_PRODUCT_QLOGIC_ISP6322	0x6322
287 #endif
288 
289 #ifndef        PCI_PRODUCT_QLOGIC_ISP5432
290 #define        PCI_PRODUCT_QLOGIC_ISP5432      0x5432
291 #endif
292 
293 #ifndef	PCI_PRODUCT_QLOGIC_ISP2031
294 #define	PCI_PRODUCT_QLOGIC_ISP2031	0x2031
295 #endif
296 
297 #define        PCI_QLOGIC_ISP5432      \
298        ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC)
299 
300 #define	PCI_QLOGIC_ISP1020	\
301 	((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
302 
303 #define	PCI_QLOGIC_ISP1080	\
304 	((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
305 
306 #define	PCI_QLOGIC_ISP10160	\
307 	((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC)
308 
309 #define	PCI_QLOGIC_ISP12160	\
310 	((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
311 
312 #define	PCI_QLOGIC_ISP1240	\
313 	((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
314 
315 #define	PCI_QLOGIC_ISP1280	\
316 	((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
317 
318 #define	PCI_QLOGIC_ISP2100	\
319 	((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
320 
321 #define	PCI_QLOGIC_ISP2200	\
322 	((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
323 
324 #define	PCI_QLOGIC_ISP2300	\
325 	((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
326 
327 #define	PCI_QLOGIC_ISP2312	\
328 	((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
329 
330 #define	PCI_QLOGIC_ISP2322	\
331 	((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC)
332 
333 #define	PCI_QLOGIC_ISP2422	\
334 	((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC)
335 
336 #define	PCI_QLOGIC_ISP2432	\
337 	((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC)
338 
339 #define	PCI_QLOGIC_ISP2532	\
340 	((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC)
341 
342 #define	PCI_QLOGIC_ISP6312	\
343 	((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC)
344 
345 #define	PCI_QLOGIC_ISP6322	\
346 	((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC)
347 
348 #define	PCI_QLOGIC_ISP2031	\
349 	((PCI_PRODUCT_QLOGIC_ISP2031 << 16) | PCI_VENDOR_QLOGIC)
350 
351 /*
352  * Odd case for some AMI raid cards... We need to *not* attach to this.
353  */
354 #define	AMI_RAID_SUBVENDOR_ID	0x101e
355 
356 #define	PCI_DFLT_LTNCY	0x40
357 #define	PCI_DFLT_LNSZ	0x10
358 
359 static int isp_pci_probe (device_t);
360 static int isp_pci_attach (device_t);
361 static int isp_pci_detach (device_t);
362 
363 
364 #define	ISP_PCD(isp)	((struct isp_pcisoftc *)isp)->pci_dev
365 struct isp_pcisoftc {
366 	ispsoftc_t			pci_isp;
367 	device_t			pci_dev;
368 	struct resource *		regs;
369 	struct resource *		regs2;
370 	void *				irq;
371 	int				iqd;
372 	int				rtp;
373 	int				rgd;
374 	int				rtp2;
375 	int				rgd2;
376 	void *				ih;
377 	int16_t				pci_poff[_NREG_BLKS];
378 	bus_dma_tag_t			dmat;
379 	int				msicount;
380 };
381 
382 
383 static device_method_t isp_pci_methods[] = {
384 	/* Device interface */
385 	DEVMETHOD(device_probe,		isp_pci_probe),
386 	DEVMETHOD(device_attach,	isp_pci_attach),
387 	DEVMETHOD(device_detach,	isp_pci_detach),
388 	{ 0, 0 }
389 };
390 
391 static driver_t isp_pci_driver = {
392 	"isp", isp_pci_methods, sizeof (struct isp_pcisoftc)
393 };
394 static devclass_t isp_devclass;
395 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0);
396 MODULE_DEPEND(isp, cam, 1, 1, 1);
397 MODULE_DEPEND(isp, firmware, 1, 1, 1);
398 static int isp_nvports = 0;
399 
400 static int
401 isp_pci_probe(device_t dev)
402 {
403 	switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) {
404 	case PCI_QLOGIC_ISP1020:
405 		device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter");
406 		break;
407 	case PCI_QLOGIC_ISP1080:
408 		device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter");
409 		break;
410 	case PCI_QLOGIC_ISP1240:
411 		device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter");
412 		break;
413 	case PCI_QLOGIC_ISP1280:
414 		device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter");
415 		break;
416 	case PCI_QLOGIC_ISP10160:
417 		device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter");
418 		break;
419 	case PCI_QLOGIC_ISP12160:
420 		if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) {
421 			return (ENXIO);
422 		}
423 		device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter");
424 		break;
425 	case PCI_QLOGIC_ISP2100:
426 		device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter");
427 		break;
428 	case PCI_QLOGIC_ISP2200:
429 		device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter");
430 		break;
431 	case PCI_QLOGIC_ISP2300:
432 		device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter");
433 		break;
434 	case PCI_QLOGIC_ISP2312:
435 		device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter");
436 		break;
437 	case PCI_QLOGIC_ISP2322:
438 		device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter");
439 		break;
440 	case PCI_QLOGIC_ISP2422:
441 		device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter");
442 		break;
443 	case PCI_QLOGIC_ISP2432:
444 		device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter");
445 		break;
446 	case PCI_QLOGIC_ISP2532:
447 		device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter");
448 		break;
449 	case PCI_QLOGIC_ISP5432:
450 		device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter");
451 		break;
452 	case PCI_QLOGIC_ISP6312:
453 		device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter");
454 		break;
455 	case PCI_QLOGIC_ISP6322:
456 		device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter");
457 		break;
458 	case PCI_QLOGIC_ISP2031:
459 		device_set_desc(dev, "Qlogic ISP 2031 PCI FC-AL Adapter");
460 		break;
461 	default:
462 		return (ENXIO);
463 	}
464 	if (isp_announced == 0 && bootverbose) {
465 		printf("Qlogic ISP Driver, FreeBSD Version %d.%d, "
466 		    "Core Version %d.%d\n",
467 		    ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
468 		    ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
469 		isp_announced++;
470 	}
471 	/*
472 	 * XXXX: Here is where we might load the f/w module
473 	 * XXXX: (or increase a reference count to it).
474 	 */
475 	return (BUS_PROBE_DEFAULT);
476 }
477 
478 static void
479 isp_get_generic_options(device_t dev, ispsoftc_t *isp)
480 {
481 	int tval;
482 
483 	tval = 0;
484 	if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) {
485 		isp->isp_confopts |= ISP_CFG_NORELOAD;
486 	}
487 	tval = 0;
488 	if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) {
489 		isp->isp_confopts |= ISP_CFG_NONVRAM;
490 	}
491 	tval = 0;
492 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval);
493 	if (tval) {
494 		isp->isp_dblev = tval;
495 	} else {
496 		isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
497 	}
498 	if (bootverbose) {
499 		isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
500 	}
501 	tval = -1;
502 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval);
503 	if (tval > 0 && tval <= 254) {
504 		isp_nvports = tval;
505 	}
506 	tval = 7;
507 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval);
508 	isp_quickboot_time = tval;
509 }
510 
511 static void
512 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp)
513 {
514 	const char *sptr;
515 	int tval = 0;
516 	char prefix[12], name[16];
517 
518 	if (chan == 0)
519 		prefix[0] = 0;
520 	else
521 		snprintf(prefix, sizeof(prefix), "chan%d.", chan);
522 	snprintf(name, sizeof(name), "%siid", prefix);
523 	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
524 	    name, &tval)) {
525 		if (IS_FC(isp)) {
526 			ISP_FC_PC(isp, chan)->default_id = 109 - chan;
527 		} else {
528 #ifdef __sparc64__
529 			ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev);
530 #else
531 			ISP_SPI_PC(isp, chan)->iid = 7;
532 #endif
533 		}
534 	} else {
535 		if (IS_FC(isp)) {
536 			ISP_FC_PC(isp, chan)->default_id = tval - chan;
537 		} else {
538 			ISP_SPI_PC(isp, chan)->iid = tval;
539 		}
540 		isp->isp_confopts |= ISP_CFG_OWNLOOPID;
541 	}
542 
543 	if (IS_SCSI(isp))
544 		return;
545 
546 	tval = -1;
547 	snprintf(name, sizeof(name), "%srole", prefix);
548 	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
549 	    name, &tval) == 0) {
550 		switch (tval) {
551 		case ISP_ROLE_NONE:
552 		case ISP_ROLE_INITIATOR:
553 		case ISP_ROLE_TARGET:
554 		case ISP_ROLE_BOTH:
555 			device_printf(dev, "Chan %d setting role to 0x%x\n", chan, tval);
556 			break;
557 		default:
558 			tval = -1;
559 			break;
560 		}
561 	}
562 	if (tval == -1) {
563 		tval = ISP_DEFAULT_ROLES;
564 	}
565 	ISP_FC_PC(isp, chan)->def_role = tval;
566 
567 	tval = 0;
568 	snprintf(name, sizeof(name), "%sfullduplex", prefix);
569 	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
570 	    name, &tval) == 0 && tval != 0) {
571 		isp->isp_confopts |= ISP_CFG_FULL_DUPLEX;
572 	}
573 	sptr = 0;
574 	snprintf(name, sizeof(name), "%stopology", prefix);
575 	if (resource_string_value(device_get_name(dev), device_get_unit(dev),
576 	    name, (const char **) &sptr) == 0 && sptr != 0) {
577 		if (strcmp(sptr, "lport") == 0) {
578 			isp->isp_confopts |= ISP_CFG_LPORT;
579 		} else if (strcmp(sptr, "nport") == 0) {
580 			isp->isp_confopts |= ISP_CFG_NPORT;
581 		} else if (strcmp(sptr, "lport-only") == 0) {
582 			isp->isp_confopts |= ISP_CFG_LPORT_ONLY;
583 		} else if (strcmp(sptr, "nport-only") == 0) {
584 			isp->isp_confopts |= ISP_CFG_NPORT_ONLY;
585 		}
586 	}
587 
588 	tval = 0;
589 	snprintf(name, sizeof(name), "%snofctape", prefix);
590 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
591 	    name, &tval);
592 	if (tval) {
593 		isp->isp_confopts |= ISP_CFG_NOFCTAPE;
594 	}
595 
596 	tval = 0;
597 	snprintf(name, sizeof(name), "%sfctape", prefix);
598 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
599 	    name, &tval);
600 	if (tval) {
601 		isp->isp_confopts &= ~ISP_CFG_NOFCTAPE;
602 		isp->isp_confopts |= ISP_CFG_FCTAPE;
603 	}
604 
605 
606 	/*
607 	 * Because the resource_*_value functions can neither return
608 	 * 64 bit integer values, nor can they be directly coerced
609 	 * to interpret the right hand side of the assignment as
610 	 * you want them to interpret it, we have to force WWN
611 	 * hint replacement to specify WWN strings with a leading
612 	 * 'w' (e..g w50000000aaaa0001). Sigh.
613 	 */
614 	sptr = 0;
615 	snprintf(name, sizeof(name), "%sportwwn", prefix);
616 	tval = resource_string_value(device_get_name(dev), device_get_unit(dev),
617 	    name, (const char **) &sptr);
618 	if (tval == 0 && sptr != 0 && *sptr++ == 'w') {
619 		char *eptr = 0;
620 		ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16);
621 		if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) {
622 			device_printf(dev, "mangled portwwn hint '%s'\n", sptr);
623 			ISP_FC_PC(isp, chan)->def_wwpn = 0;
624 		}
625 	}
626 
627 	sptr = 0;
628 	snprintf(name, sizeof(name), "%snodewwn", prefix);
629 	tval = resource_string_value(device_get_name(dev), device_get_unit(dev),
630 	    name, (const char **) &sptr);
631 	if (tval == 0 && sptr != 0 && *sptr++ == 'w') {
632 		char *eptr = 0;
633 		ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16);
634 		if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) {
635 			device_printf(dev, "mangled nodewwn hint '%s'\n", sptr);
636 			ISP_FC_PC(isp, chan)->def_wwnn = 0;
637 		}
638 	}
639 
640 	tval = -1;
641 	snprintf(name, sizeof(name), "%sloop_down_limit", prefix);
642 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
643 	    name, &tval);
644 	if (tval >= 0 && tval < 0xffff) {
645 		ISP_FC_PC(isp, chan)->loop_down_limit = tval;
646 	} else {
647 		ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit;
648 	}
649 
650 	tval = -1;
651 	snprintf(name, sizeof(name), "%sgone_device_time", prefix);
652 	(void) resource_int_value(device_get_name(dev), device_get_unit(dev),
653 	    name, &tval);
654 	if (tval >= 0 && tval < 0xffff) {
655 		ISP_FC_PC(isp, chan)->gone_device_time = tval;
656 	} else {
657 		ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time;
658 	}
659 }
660 
661 static int
662 isp_pci_attach(device_t dev)
663 {
664 	int i, locksetup = 0;
665 	uint32_t data, cmd, linesz, did;
666 	struct isp_pcisoftc *pcs;
667 	ispsoftc_t *isp;
668 	size_t psize, xsize;
669 	char fwname[32];
670 
671 	pcs = device_get_softc(dev);
672 	if (pcs == NULL) {
673 		device_printf(dev, "cannot get softc\n");
674 		return (ENOMEM);
675 	}
676 	memset(pcs, 0, sizeof (*pcs));
677 
678 	pcs->pci_dev = dev;
679 	isp = &pcs->pci_isp;
680 	isp->isp_dev = dev;
681 	isp->isp_nchan = 1;
682 	if (sizeof (bus_addr_t) > 4)
683 		isp->isp_osinfo.sixtyfourbit = 1;
684 
685 	/*
686 	 * Get Generic Options
687 	 */
688 	isp_nvports = 0;
689 	isp_get_generic_options(dev, isp);
690 
691 	linesz = PCI_DFLT_LNSZ;
692 	pcs->irq = pcs->regs = pcs->regs2 = NULL;
693 	pcs->rgd = pcs->rtp = pcs->iqd = 0;
694 
695 	pcs->pci_dev = dev;
696 	pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
697 	pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
698 	pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
699 	pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
700 	pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
701 
702 	switch (pci_get_devid(dev)) {
703 	case PCI_QLOGIC_ISP1020:
704 		did = 0x1040;
705 		isp->isp_mdvec = &mdvec;
706 		isp->isp_type = ISP_HA_SCSI_UNKNOWN;
707 		break;
708 	case PCI_QLOGIC_ISP1080:
709 		did = 0x1080;
710 		isp->isp_mdvec = &mdvec_1080;
711 		isp->isp_type = ISP_HA_SCSI_1080;
712 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
713 		break;
714 	case PCI_QLOGIC_ISP1240:
715 		did = 0x1080;
716 		isp->isp_mdvec = &mdvec_1080;
717 		isp->isp_type = ISP_HA_SCSI_1240;
718 		isp->isp_nchan = 2;
719 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
720 		break;
721 	case PCI_QLOGIC_ISP1280:
722 		did = 0x1080;
723 		isp->isp_mdvec = &mdvec_1080;
724 		isp->isp_type = ISP_HA_SCSI_1280;
725 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
726 		break;
727 	case PCI_QLOGIC_ISP10160:
728 		did = 0x12160;
729 		isp->isp_mdvec = &mdvec_12160;
730 		isp->isp_type = ISP_HA_SCSI_10160;
731 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
732 		break;
733 	case PCI_QLOGIC_ISP12160:
734 		did = 0x12160;
735 		isp->isp_nchan = 2;
736 		isp->isp_mdvec = &mdvec_12160;
737 		isp->isp_type = ISP_HA_SCSI_12160;
738 		pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
739 		break;
740 	case PCI_QLOGIC_ISP2100:
741 		did = 0x2100;
742 		isp->isp_mdvec = &mdvec_2100;
743 		isp->isp_type = ISP_HA_FC_2100;
744 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
745 		if (pci_get_revid(dev) < 3) {
746 			/*
747 			 * XXX: Need to get the actual revision
748 			 * XXX: number of the 2100 FB. At any rate,
749 			 * XXX: lower cache line size for early revision
750 			 * XXX; boards.
751 			 */
752 			linesz = 1;
753 		}
754 		break;
755 	case PCI_QLOGIC_ISP2200:
756 		did = 0x2200;
757 		isp->isp_mdvec = &mdvec_2200;
758 		isp->isp_type = ISP_HA_FC_2200;
759 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
760 		break;
761 	case PCI_QLOGIC_ISP2300:
762 		did = 0x2300;
763 		isp->isp_mdvec = &mdvec_2300;
764 		isp->isp_type = ISP_HA_FC_2300;
765 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
766 		break;
767 	case PCI_QLOGIC_ISP2312:
768 	case PCI_QLOGIC_ISP6312:
769 		did = 0x2300;
770 		isp->isp_mdvec = &mdvec_2300;
771 		isp->isp_type = ISP_HA_FC_2312;
772 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
773 		break;
774 	case PCI_QLOGIC_ISP2322:
775 	case PCI_QLOGIC_ISP6322:
776 		did = 0x2322;
777 		isp->isp_mdvec = &mdvec_2300;
778 		isp->isp_type = ISP_HA_FC_2322;
779 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
780 		break;
781 	case PCI_QLOGIC_ISP2422:
782 	case PCI_QLOGIC_ISP2432:
783 		did = 0x2400;
784 		isp->isp_nchan += isp_nvports;
785 		isp->isp_mdvec = &mdvec_2400;
786 		isp->isp_type = ISP_HA_FC_2400;
787 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
788 		break;
789 	case PCI_QLOGIC_ISP2532:
790 		did = 0x2500;
791 		isp->isp_nchan += isp_nvports;
792 		isp->isp_mdvec = &mdvec_2500;
793 		isp->isp_type = ISP_HA_FC_2500;
794 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
795 		break;
796 	case PCI_QLOGIC_ISP5432:
797 		did = 0x2500;
798 		isp->isp_mdvec = &mdvec_2500;
799 		isp->isp_type = ISP_HA_FC_2500;
800 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
801 		break;
802 	case PCI_QLOGIC_ISP2031:
803 		did = 0x2600;
804 		isp->isp_nchan += isp_nvports;
805 		isp->isp_mdvec = &mdvec_2600;
806 		isp->isp_type = ISP_HA_FC_2600;
807 		pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
808 		break;
809 	default:
810 		device_printf(dev, "unknown device type\n");
811 		goto bad;
812 		break;
813 	}
814 	isp->isp_revision = pci_get_revid(dev);
815 
816 	if (IS_26XX(isp)) {
817 		pcs->rtp = SYS_RES_MEMORY;
818 		pcs->rgd = PCIR_BAR(0);
819 		pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd,
820 		    RF_ACTIVE);
821 		pcs->rtp2 = SYS_RES_MEMORY;
822 		pcs->rgd2 = PCIR_BAR(4);
823 		pcs->regs2 = bus_alloc_resource_any(dev, pcs->rtp2, &pcs->rgd2,
824 		    RF_ACTIVE);
825 	} else {
826 		pcs->rtp = SYS_RES_MEMORY;
827 		pcs->rgd = PCIR_BAR(1);
828 		pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd,
829 		    RF_ACTIVE);
830 		if (pcs->regs == NULL) {
831 			pcs->rtp = SYS_RES_IOPORT;
832 			pcs->rgd = PCIR_BAR(0);
833 			pcs->regs = bus_alloc_resource_any(dev, pcs->rtp,
834 			    &pcs->rgd, RF_ACTIVE);
835 		}
836 	}
837 	if (pcs->regs == NULL) {
838 		device_printf(dev, "Unable to map any ports\n");
839 		goto bad;
840 	}
841 	if (bootverbose) {
842 		device_printf(dev, "Using %s space register mapping\n",
843 		    (pcs->rtp == SYS_RES_IOPORT)? "I/O" : "Memory");
844 	}
845 	isp->isp_regs = pcs->regs;
846 	isp->isp_regs2 = pcs->regs2;
847 
848 	if (IS_FC(isp)) {
849 		psize = sizeof (fcparam);
850 		xsize = sizeof (struct isp_fc);
851 	} else {
852 		psize = sizeof (sdparam);
853 		xsize = sizeof (struct isp_spi);
854 	}
855 	psize *= isp->isp_nchan;
856 	xsize *= isp->isp_nchan;
857 	isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO);
858 	if (isp->isp_param == NULL) {
859 		device_printf(dev, "cannot allocate parameter data\n");
860 		goto bad;
861 	}
862 	isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO);
863 	if (isp->isp_osinfo.pc.ptr == NULL) {
864 		device_printf(dev, "cannot allocate parameter data\n");
865 		goto bad;
866 	}
867 
868 	/*
869 	 * Now that we know who we are (roughly) get/set specific options
870 	 */
871 	for (i = 0; i < isp->isp_nchan; i++) {
872 		isp_get_specific_options(dev, i, isp);
873 	}
874 
875 	isp->isp_osinfo.fw = NULL;
876 	if (isp->isp_osinfo.fw == NULL) {
877 		snprintf(fwname, sizeof (fwname), "isp_%04x", did);
878 		isp->isp_osinfo.fw = firmware_get(fwname);
879 	}
880 	if (isp->isp_osinfo.fw != NULL) {
881 		isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname);
882 		isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data;
883 	}
884 
885 	/*
886 	 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
887 	 */
888 	cmd = pci_read_config(dev, PCIR_COMMAND, 2);
889 	cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN;
890 	if (IS_2300(isp)) {	/* per QLogic errata */
891 		cmd &= ~PCIM_CMD_INVEN;
892 	}
893 	if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) {
894 		cmd &= ~PCIM_CMD_INTX_DISABLE;
895 	}
896 	if (IS_24XX(isp)) {
897 		cmd &= ~PCIM_CMD_INTX_DISABLE;
898 	}
899 	pci_write_config(dev, PCIR_COMMAND, cmd, 2);
900 
901 	/*
902 	 * Make sure the Cache Line Size register is set sensibly.
903 	 */
904 	data = pci_read_config(dev, PCIR_CACHELNSZ, 1);
905 	if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) {
906 		isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data);
907 		data = linesz;
908 		pci_write_config(dev, PCIR_CACHELNSZ, data, 1);
909 	}
910 
911 	/*
912 	 * Make sure the Latency Timer is sane.
913 	 */
914 	data = pci_read_config(dev, PCIR_LATTIMER, 1);
915 	if (data < PCI_DFLT_LTNCY) {
916 		data = PCI_DFLT_LTNCY;
917 		isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data);
918 		pci_write_config(dev, PCIR_LATTIMER, data, 1);
919 	}
920 
921 	/*
922 	 * Make sure we've disabled the ROM.
923 	 */
924 	data = pci_read_config(dev, PCIR_ROMADDR, 4);
925 	data &= ~1;
926 	pci_write_config(dev, PCIR_ROMADDR, data, 4);
927 
928 	/*
929 	 * Do MSI
930 	 *
931 	 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express)
932 	 */
933 	if (IS_24XX(isp) || IS_2322(isp)) {
934 		pcs->msicount = pci_msi_count(dev);
935 		if (pcs->msicount > 1) {
936 			pcs->msicount = 1;
937 		}
938 		if (pci_alloc_msi(dev, &pcs->msicount) == 0) {
939 			pcs->iqd = 1;
940 		} else {
941 			pcs->iqd = 0;
942 		}
943 	}
944 	pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE);
945 	if (pcs->irq == NULL) {
946 		device_printf(dev, "could not allocate interrupt\n");
947 		goto bad;
948 	}
949 
950 	/* Make sure the lock is set up. */
951 	mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF);
952 	locksetup++;
953 
954 	if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) {
955 		device_printf(dev, "could not setup interrupt\n");
956 		goto bad;
957 	}
958 
959 	/*
960 	 * Last minute checks...
961 	 */
962 	if (IS_23XX(isp) || IS_24XX(isp)) {
963 		isp->isp_port = pci_get_function(dev);
964 	}
965 
966 	/*
967 	 * Make sure we're in reset state.
968 	 */
969 	ISP_LOCK(isp);
970 	if (isp_reinit(isp, 1) != 0) {
971 		ISP_UNLOCK(isp);
972 		goto bad;
973 	}
974 	ISP_UNLOCK(isp);
975 	if (isp_attach(isp)) {
976 		ISP_LOCK(isp);
977 		isp_uninit(isp);
978 		ISP_UNLOCK(isp);
979 		goto bad;
980 	}
981 	return (0);
982 
983 bad:
984 	if (pcs->ih) {
985 		(void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
986 	}
987 	if (locksetup) {
988 		mtx_destroy(&isp->isp_osinfo.lock);
989 	}
990 	if (pcs->irq) {
991 		(void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
992 	}
993 	if (pcs->msicount) {
994 		pci_release_msi(dev);
995 	}
996 	if (pcs->regs)
997 		(void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
998 	if (pcs->regs2)
999 		(void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2);
1000 	if (pcs->pci_isp.isp_param) {
1001 		free(pcs->pci_isp.isp_param, M_DEVBUF);
1002 		pcs->pci_isp.isp_param = NULL;
1003 	}
1004 	if (pcs->pci_isp.isp_osinfo.pc.ptr) {
1005 		free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
1006 		pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
1007 	}
1008 	return (ENXIO);
1009 }
1010 
1011 static int
1012 isp_pci_detach(device_t dev)
1013 {
1014 	struct isp_pcisoftc *pcs;
1015 	ispsoftc_t *isp;
1016 	int status;
1017 
1018 	pcs = device_get_softc(dev);
1019 	if (pcs == NULL) {
1020 		return (ENXIO);
1021 	}
1022 	isp = (ispsoftc_t *) pcs;
1023 	status = isp_detach(isp);
1024 	if (status)
1025 		return (status);
1026 	ISP_LOCK(isp);
1027 	isp_uninit(isp);
1028 	if (pcs->ih) {
1029 		(void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
1030 	}
1031 	ISP_UNLOCK(isp);
1032 	mtx_destroy(&isp->isp_osinfo.lock);
1033 	(void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
1034 	if (pcs->msicount) {
1035 		pci_release_msi(dev);
1036 	}
1037 	(void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
1038 	if (pcs->regs2)
1039 		(void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2);
1040 	/*
1041 	 * XXX: THERE IS A LOT OF LEAKAGE HERE
1042 	 */
1043 	if (pcs->pci_isp.isp_param) {
1044 		free(pcs->pci_isp.isp_param, M_DEVBUF);
1045 		pcs->pci_isp.isp_param = NULL;
1046 	}
1047 	if (pcs->pci_isp.isp_osinfo.pc.ptr) {
1048 		free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
1049 		pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
1050 	}
1051 	return (0);
1052 }
1053 
1054 #define	IspVirt2Off(a, x)	\
1055 	(((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
1056 	_BLK_REG_SHFT] + ((x) & 0xfff))
1057 
1058 #define	BXR2(isp, off)		bus_read_2((isp)->isp_regs, (off))
1059 #define	BXW2(isp, off, v)	bus_write_2((isp)->isp_regs, (off), (v))
1060 #define	BXR4(isp, off)		bus_read_4((isp)->isp_regs, (off))
1061 #define	BXW4(isp, off, v)	bus_write_4((isp)->isp_regs, (off), (v))
1062 #define	B2R4(isp, off)		bus_read_4((isp)->isp_regs2, (off))
1063 #define	B2W4(isp, off, v)	bus_write_4((isp)->isp_regs2, (off), (v))
1064 
1065 static ISP_INLINE int
1066 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp)
1067 {
1068 	uint32_t val0, val1;
1069 	int i = 0;
1070 
1071 	do {
1072 		val0 = BXR2(isp, IspVirt2Off(isp, off));
1073 		val1 = BXR2(isp, IspVirt2Off(isp, off));
1074 	} while (val0 != val1 && ++i < 1000);
1075 	if (val0 != val1) {
1076 		return (1);
1077 	}
1078 	*rp = val0;
1079 	return (0);
1080 }
1081 
1082 static int
1083 isp_pci_rd_isr(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1084 {
1085 	uint16_t isr, sema;
1086 
1087 	if (IS_2100(isp)) {
1088 		if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
1089 		    return (0);
1090 		}
1091 		if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
1092 		    return (0);
1093 		}
1094 	} else {
1095 		isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR));
1096 		sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA));
1097 	}
1098 	isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
1099 	isr &= INT_PENDING_MASK(isp);
1100 	sema &= BIU_SEMA_LOCK;
1101 	if (isr == 0 && sema == 0) {
1102 		return (0);
1103 	}
1104 	*isrp = isr;
1105 	if ((*semap = sema) != 0) {
1106 		if (IS_2100(isp)) {
1107 			if (isp_pci_rd_debounced(isp, OUTMAILBOX0, info)) {
1108 				return (0);
1109 			}
1110 		} else {
1111 			*info = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0));
1112 		}
1113 	}
1114 	return (1);
1115 }
1116 
1117 static int
1118 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1119 {
1120 	uint32_t hccr, r2hisr;
1121 
1122 	if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) {
1123 		*isrp = 0;
1124 		return (0);
1125 	}
1126 	r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO));
1127 	isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1128 	if ((r2hisr & BIU_R2HST_INTR) == 0) {
1129 		*isrp = 0;
1130 		return (0);
1131 	}
1132 	switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) {
1133 	case ISPR2HST_ROM_MBX_OK:
1134 	case ISPR2HST_ROM_MBX_FAIL:
1135 	case ISPR2HST_MBX_OK:
1136 	case ISPR2HST_MBX_FAIL:
1137 	case ISPR2HST_ASYNC_EVENT:
1138 		*semap = 1;
1139 		break;
1140 	case ISPR2HST_RIO_16:
1141 		*info = ASYNC_RIO16_1;
1142 		*semap = 1;
1143 		return (1);
1144 	case ISPR2HST_FPOST:
1145 		*info = ASYNC_CMD_CMPLT;
1146 		*semap = 1;
1147 		return (1);
1148 	case ISPR2HST_FPOST_CTIO:
1149 		*info = ASYNC_CTIO_DONE;
1150 		*semap = 1;
1151 		return (1);
1152 	case ISPR2HST_RSPQ_UPDATE:
1153 		*semap = 0;
1154 		break;
1155 	default:
1156 		hccr = ISP_READ(isp, HCCR);
1157 		if (hccr & HCCR_PAUSE) {
1158 			ISP_WRITE(isp, HCCR, HCCR_RESET);
1159 			isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR));
1160 			ISP_WRITE(isp, BIU_ICR, 0);
1161 		} else {
1162 			isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1163 		}
1164 		return (0);
1165 	}
1166 	*info = (r2hisr >> 16);
1167 	return (1);
1168 }
1169 
1170 static int
1171 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1172 {
1173 	uint32_t r2hisr;
1174 
1175 	r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO));
1176 	isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1177 	if ((r2hisr & BIU_R2HST_INTR) == 0) {
1178 		*isrp = 0;
1179 		return (0);
1180 	}
1181 	switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) {
1182 	case ISPR2HST_ROM_MBX_OK:
1183 	case ISPR2HST_ROM_MBX_FAIL:
1184 	case ISPR2HST_MBX_OK:
1185 	case ISPR2HST_MBX_FAIL:
1186 	case ISPR2HST_ASYNC_EVENT:
1187 		*semap = 1;
1188 		break;
1189 	case ISPR2HST_RSPQ_UPDATE:
1190 	case ISPR2HST_RSPQ_UPDATE2:
1191 	case ISPR2HST_ATIO_UPDATE:
1192 	case ISPR2HST_ATIO_RSPQ_UPDATE:
1193 	case ISPR2HST_ATIO_UPDATE2:
1194 		*semap = 0;
1195 		break;
1196 	default:
1197 		ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
1198 		isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1199 		return (0);
1200 	}
1201 	*info = (r2hisr >> 16);
1202 	return (1);
1203 }
1204 
1205 static uint32_t
1206 isp_pci_rd_reg(ispsoftc_t *isp, int regoff)
1207 {
1208 	uint16_t rv;
1209 	int oldconf = 0;
1210 
1211 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1212 		/*
1213 		 * We will assume that someone has paused the RISC processor.
1214 		 */
1215 		oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1216 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP);
1217 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1218 	}
1219 	rv = BXR2(isp, IspVirt2Off(isp, regoff));
1220 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1221 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1222 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1223 	}
1224 	return (rv);
1225 }
1226 
1227 static void
1228 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val)
1229 {
1230 	int oldconf = 0;
1231 
1232 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1233 		/*
1234 		 * We will assume that someone has paused the RISC processor.
1235 		 */
1236 		oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1237 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1238 		    oldconf | BIU_PCI_CONF1_SXP);
1239 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1240 	}
1241 	BXW2(isp, IspVirt2Off(isp, regoff), val);
1242 	MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1243 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1244 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1245 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1246 	}
1247 
1248 }
1249 
1250 static uint32_t
1251 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff)
1252 {
1253 	uint32_t rv, oc = 0;
1254 
1255 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1256 		uint32_t tc;
1257 		/*
1258 		 * We will assume that someone has paused the RISC processor.
1259 		 */
1260 		oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1261 		tc = oc & ~BIU_PCI1080_CONF1_DMA;
1262 		if (regoff & SXP_BANK1_SELECT)
1263 			tc |= BIU_PCI1080_CONF1_SXP1;
1264 		else
1265 			tc |= BIU_PCI1080_CONF1_SXP0;
1266 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1267 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1268 	} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1269 		oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1270 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1271 		    oc | BIU_PCI1080_CONF1_DMA);
1272 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1273 	}
1274 	rv = BXR2(isp, IspVirt2Off(isp, regoff));
1275 	if (oc) {
1276 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1277 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1278 	}
1279 	return (rv);
1280 }
1281 
1282 static void
1283 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val)
1284 {
1285 	int oc = 0;
1286 
1287 	if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1288 		uint32_t tc;
1289 		/*
1290 		 * We will assume that someone has paused the RISC processor.
1291 		 */
1292 		oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1293 		tc = oc & ~BIU_PCI1080_CONF1_DMA;
1294 		if (regoff & SXP_BANK1_SELECT)
1295 			tc |= BIU_PCI1080_CONF1_SXP1;
1296 		else
1297 			tc |= BIU_PCI1080_CONF1_SXP0;
1298 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1299 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1300 	} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1301 		oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1302 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1303 		    oc | BIU_PCI1080_CONF1_DMA);
1304 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1305 	}
1306 	BXW2(isp, IspVirt2Off(isp, regoff), val);
1307 	MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1308 	if (oc) {
1309 		BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1310 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1311 	}
1312 }
1313 
1314 static uint32_t
1315 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
1316 {
1317 	uint32_t rv;
1318 	int block = regoff & _BLK_REG_MASK;
1319 
1320 	switch (block) {
1321 	case BIU_BLOCK:
1322 		break;
1323 	case MBOX_BLOCK:
1324 		return (BXR2(isp, IspVirt2Off(isp, regoff)));
1325 	case SXP_BLOCK:
1326 		isp_prt(isp, ISP_LOGERR, "SXP_BLOCK read at 0x%x", regoff);
1327 		return (0xffffffff);
1328 	case RISC_BLOCK:
1329 		isp_prt(isp, ISP_LOGERR, "RISC_BLOCK read at 0x%x", regoff);
1330 		return (0xffffffff);
1331 	case DMA_BLOCK:
1332 		isp_prt(isp, ISP_LOGERR, "DMA_BLOCK read at 0x%x", regoff);
1333 		return (0xffffffff);
1334 	default:
1335 		isp_prt(isp, ISP_LOGERR, "unknown block read at 0x%x", regoff);
1336 		return (0xffffffff);
1337 	}
1338 
1339 	switch (regoff) {
1340 	case BIU2400_FLASH_ADDR:
1341 	case BIU2400_FLASH_DATA:
1342 	case BIU2400_ICR:
1343 	case BIU2400_ISR:
1344 	case BIU2400_CSR:
1345 	case BIU2400_REQINP:
1346 	case BIU2400_REQOUTP:
1347 	case BIU2400_RSPINP:
1348 	case BIU2400_RSPOUTP:
1349 	case BIU2400_PRI_REQINP:
1350 	case BIU2400_PRI_REQOUTP:
1351 	case BIU2400_ATIO_RSPINP:
1352 	case BIU2400_ATIO_RSPOUTP:
1353 	case BIU2400_HCCR:
1354 	case BIU2400_GPIOD:
1355 	case BIU2400_GPIOE:
1356 	case BIU2400_HSEMA:
1357 		rv = BXR4(isp, IspVirt2Off(isp, regoff));
1358 		break;
1359 	case BIU2400_R2HSTSLO:
1360 		rv = BXR4(isp, IspVirt2Off(isp, regoff));
1361 		break;
1362 	case BIU2400_R2HSTSHI:
1363 		rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16;
1364 		break;
1365 	default:
1366 		isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x",
1367 		    regoff);
1368 		rv = 0xffffffff;
1369 		break;
1370 	}
1371 	return (rv);
1372 }
1373 
1374 static void
1375 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
1376 {
1377 	int block = regoff & _BLK_REG_MASK;
1378 
1379 	switch (block) {
1380 	case BIU_BLOCK:
1381 		break;
1382 	case MBOX_BLOCK:
1383 		BXW2(isp, IspVirt2Off(isp, regoff), val);
1384 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1385 		return;
1386 	case SXP_BLOCK:
1387 		isp_prt(isp, ISP_LOGERR, "SXP_BLOCK write at 0x%x", regoff);
1388 		return;
1389 	case RISC_BLOCK:
1390 		isp_prt(isp, ISP_LOGERR, "RISC_BLOCK write at 0x%x", regoff);
1391 		return;
1392 	case DMA_BLOCK:
1393 		isp_prt(isp, ISP_LOGERR, "DMA_BLOCK write at 0x%x", regoff);
1394 		return;
1395 	default:
1396 		isp_prt(isp, ISP_LOGERR, "unknown block write at 0x%x", regoff);
1397 		break;
1398 	}
1399 
1400 	switch (regoff) {
1401 	case BIU2400_FLASH_ADDR:
1402 	case BIU2400_FLASH_DATA:
1403 	case BIU2400_ICR:
1404 	case BIU2400_ISR:
1405 	case BIU2400_CSR:
1406 	case BIU2400_REQINP:
1407 	case BIU2400_REQOUTP:
1408 	case BIU2400_RSPINP:
1409 	case BIU2400_RSPOUTP:
1410 	case BIU2400_PRI_REQINP:
1411 	case BIU2400_PRI_REQOUTP:
1412 	case BIU2400_ATIO_RSPINP:
1413 	case BIU2400_ATIO_RSPOUTP:
1414 	case BIU2400_HCCR:
1415 	case BIU2400_GPIOD:
1416 	case BIU2400_GPIOE:
1417 	case BIU2400_HSEMA:
1418 		BXW4(isp, IspVirt2Off(isp, regoff), val);
1419 #ifdef MEMORYBARRIERW
1420 		if (regoff == BIU2400_REQINP ||
1421 		    regoff == BIU2400_RSPOUTP ||
1422 		    regoff == BIU2400_PRI_REQINP ||
1423 		    regoff == BIU2400_ATIO_RSPOUTP)
1424 			MEMORYBARRIERW(isp, SYNC_REG,
1425 			    IspVirt2Off(isp, regoff), 4, -1)
1426 		else
1427 #endif
1428 		MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1);
1429 		break;
1430 	default:
1431 		isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x",
1432 		    regoff);
1433 		break;
1434 	}
1435 }
1436 
1437 static uint32_t
1438 isp_pci_rd_reg_2600(ispsoftc_t *isp, int regoff)
1439 {
1440 	uint32_t rv;
1441 
1442 	switch (regoff) {
1443 	case BIU2400_PRI_REQINP:
1444 	case BIU2400_PRI_REQOUTP:
1445 		isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x",
1446 		    regoff);
1447 		rv = 0xffffffff;
1448 		break;
1449 	case BIU2400_REQINP:
1450 		rv = B2R4(isp, 0x00);
1451 		break;
1452 	case BIU2400_REQOUTP:
1453 		rv = B2R4(isp, 0x04);
1454 		break;
1455 	case BIU2400_RSPINP:
1456 		rv = B2R4(isp, 0x08);
1457 		break;
1458 	case BIU2400_RSPOUTP:
1459 		rv = B2R4(isp, 0x0c);
1460 		break;
1461 	case BIU2400_ATIO_RSPINP:
1462 		rv = B2R4(isp, 0x10);
1463 		break;
1464 	case BIU2400_ATIO_RSPOUTP:
1465 		rv = B2R4(isp, 0x14);
1466 		break;
1467 	default:
1468 		rv = isp_pci_rd_reg_2400(isp, regoff);
1469 		break;
1470 	}
1471 	return (rv);
1472 }
1473 
1474 static void
1475 isp_pci_wr_reg_2600(ispsoftc_t *isp, int regoff, uint32_t val)
1476 {
1477 	int off;
1478 
1479 	switch (regoff) {
1480 	case BIU2400_PRI_REQINP:
1481 	case BIU2400_PRI_REQOUTP:
1482 		isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x",
1483 		    regoff);
1484 		return;
1485 	case BIU2400_REQINP:
1486 		off = 0x00;
1487 		break;
1488 	case BIU2400_REQOUTP:
1489 		off = 0x04;
1490 		break;
1491 	case BIU2400_RSPINP:
1492 		off = 0x08;
1493 		break;
1494 	case BIU2400_RSPOUTP:
1495 		off = 0x0c;
1496 		break;
1497 	case BIU2400_ATIO_RSPINP:
1498 		off = 0x10;
1499 		break;
1500 	case BIU2400_ATIO_RSPOUTP:
1501 		off = 0x14;
1502 		break;
1503 	default:
1504 		isp_pci_wr_reg_2400(isp, regoff, val);
1505 		return;
1506 	}
1507 	B2W4(isp, off, val);
1508 }
1509 
1510 
1511 struct imush {
1512 	ispsoftc_t *isp;
1513 	caddr_t vbase;
1514 	int chan;
1515 	int error;
1516 };
1517 
1518 static void imc(void *, bus_dma_segment_t *, int, int);
1519 static void imc1(void *, bus_dma_segment_t *, int, int);
1520 
1521 static void
1522 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1523 {
1524 	struct imush *imushp = (struct imush *) arg;
1525 	isp_ecmd_t *ecmd;
1526 
1527 	if (error) {
1528 		imushp->error = error;
1529 		return;
1530 	}
1531 	if (nseg != 1) {
1532 		imushp->error = EINVAL;
1533 		return;
1534 	}
1535 	isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len);
1536 
1537 	imushp->isp->isp_rquest = imushp->vbase;
1538 	imushp->isp->isp_rquest_dma = segs->ds_addr;
1539 	segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp));
1540 	imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp));
1541 
1542 	imushp->isp->isp_result_dma = segs->ds_addr;
1543 	imushp->isp->isp_result = imushp->vbase;
1544 	segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp));
1545 	imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp));
1546 
1547 	if (imushp->isp->isp_type >= ISP_HA_FC_2200) {
1548         imushp->isp->isp_osinfo.ecmd_dma = segs->ds_addr;
1549         imushp->isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)imushp->vbase;
1550         imushp->isp->isp_osinfo.ecmd_base = imushp->isp->isp_osinfo.ecmd_free;
1551         for (ecmd = imushp->isp->isp_osinfo.ecmd_free; ecmd < &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) {
1552             if (ecmd == &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS - 1]) {
1553                 ecmd->next = NULL;
1554             } else {
1555                 ecmd->next = ecmd + 1;
1556             }
1557         }
1558     }
1559 #ifdef	ISP_TARGET_MODE
1560 	segs->ds_addr += (N_XCMDS * XCMD_SIZE);
1561 	imushp->vbase += (N_XCMDS * XCMD_SIZE);
1562 	if (IS_24XX(imushp->isp)) {
1563 		imushp->isp->isp_atioq_dma = segs->ds_addr;
1564 		imushp->isp->isp_atioq = imushp->vbase;
1565 	}
1566 #endif
1567 }
1568 
1569 static void
1570 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1571 {
1572 	struct imush *imushp = (struct imush *) arg;
1573 	if (error) {
1574 		imushp->error = error;
1575 		return;
1576 	}
1577 	if (nseg != 1) {
1578 		imushp->error = EINVAL;
1579 		return;
1580 	}
1581 	isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len);
1582 	FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr;
1583 	FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase;
1584 }
1585 
1586 static int
1587 isp_pci_mbxdma(ispsoftc_t *isp)
1588 {
1589 	caddr_t base;
1590 	uint32_t len, nsegs;
1591 	int i, error, cmap = 0;
1592 	bus_size_t slim;	/* segment size */
1593 	bus_addr_t llim;	/* low limit of unavailable dma */
1594 	bus_addr_t hlim;	/* high limit of unavailable dma */
1595 	struct imush im;
1596 
1597 	/*
1598 	 * Already been here? If so, leave...
1599 	 */
1600 	if (isp->isp_rquest) {
1601 		return (0);
1602 	}
1603 	ISP_UNLOCK(isp);
1604 
1605 	if (isp->isp_maxcmds == 0) {
1606 		isp_prt(isp, ISP_LOGERR, "maxcmds not set");
1607 		ISP_LOCK(isp);
1608 		return (1);
1609 	}
1610 
1611 	hlim = BUS_SPACE_MAXADDR;
1612 	if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) {
1613 		if (sizeof (bus_size_t) > 4) {
1614 			slim = (bus_size_t) (1ULL << 32);
1615 		} else {
1616 			slim = (bus_size_t) (1UL << 31);
1617 		}
1618 		llim = BUS_SPACE_MAXADDR;
1619 	} else {
1620 		llim = BUS_SPACE_MAXADDR_32BIT;
1621 		slim = (1UL << 24);
1622 	}
1623 
1624 	len = isp->isp_maxcmds * sizeof (struct isp_pcmd);
1625 	isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1626 	if (isp->isp_osinfo.pcmd_pool == NULL) {
1627 		isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds");
1628 		ISP_LOCK(isp);
1629 		return (1);
1630 	}
1631 
1632 	if (isp->isp_osinfo.sixtyfourbit) {
1633 		nsegs = ISP_NSEG64_MAX;
1634 	} else {
1635 		nsegs = ISP_NSEG_MAX;
1636 	}
1637 
1638 	if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, &isp->isp_osinfo.dmat)) {
1639 		free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1640 		ISP_LOCK(isp);
1641 		isp_prt(isp, ISP_LOGERR, "could not create master dma tag");
1642 		return (1);
1643 	}
1644 
1645 	len = sizeof (isp_hdl_t) * isp->isp_maxcmds;
1646 	isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1647 	if (isp->isp_xflist == NULL) {
1648 		free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1649 		ISP_LOCK(isp);
1650 		isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array");
1651 		return (1);
1652 	}
1653 	for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1654 		isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1];
1655 	}
1656 	isp->isp_xffree = isp->isp_xflist;
1657 #ifdef	ISP_TARGET_MODE
1658 	len = sizeof (isp_hdl_t) * isp->isp_maxcmds;
1659 	isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1660 	if (isp->isp_tgtlist == NULL) {
1661 		free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1662 		free(isp->isp_xflist, M_DEVBUF);
1663 		ISP_LOCK(isp);
1664 		isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array");
1665 		return (1);
1666 	}
1667 	for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1668 		isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1];
1669 	}
1670 	isp->isp_tgtfree = isp->isp_tgtlist;
1671 #endif
1672 
1673 	/*
1674 	 * Allocate and map the request and result queues (and ATIO queue
1675 	 * if we're a 2400 supporting target mode), and a region for
1676 	 * external dma addressable command/status structures (23XX and
1677 	 * later).
1678 	 */
1679 	len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1680 	len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1681 #ifdef	ISP_TARGET_MODE
1682 	if (IS_24XX(isp)) {
1683 		len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1684 	}
1685 #endif
1686 	if (isp->isp_type >= ISP_HA_FC_2200) {
1687 		len += (N_XCMDS * XCMD_SIZE);
1688 	}
1689 
1690 	/*
1691 	 * Create a tag for the control spaces. We don't always need this
1692 	 * to be 32 bits, but we do this for simplicity and speed's sake.
1693 	 */
1694 	if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, slim, 0, &isp->isp_osinfo.cdmat)) {
1695 		isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces");
1696 		free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1697 		free(isp->isp_xflist, M_DEVBUF);
1698 #ifdef	ISP_TARGET_MODE
1699 		free(isp->isp_tgtlist, M_DEVBUF);
1700 #endif
1701 		ISP_LOCK(isp);
1702 		return (1);
1703 	}
1704 
1705 	if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) {
1706 		isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len);
1707 		bus_dma_tag_destroy(isp->isp_osinfo.cdmat);
1708 		free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1709 		free(isp->isp_xflist, M_DEVBUF);
1710 #ifdef	ISP_TARGET_MODE
1711 		free(isp->isp_tgtlist, M_DEVBUF);
1712 #endif
1713 		ISP_LOCK(isp);
1714 		return (1);
1715 	}
1716 
1717 	im.isp = isp;
1718 	im.chan = 0;
1719 	im.vbase = base;
1720 	im.error = 0;
1721 
1722 	bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0);
1723 	if (im.error) {
1724 		isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error);
1725 		goto bad;
1726 	}
1727 
1728 	if (IS_FC(isp)) {
1729 		for (cmap = 0; cmap < isp->isp_nchan; cmap++) {
1730 			struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1731 			if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) {
1732 				goto bad;
1733 			}
1734 			if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) {
1735 				bus_dma_tag_destroy(fc->tdmat);
1736 				goto bad;
1737 			}
1738 			im.isp = isp;
1739 			im.chan = cmap;
1740 			im.vbase = base;
1741 			im.error = 0;
1742 			bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0);
1743 			if (im.error) {
1744 				bus_dmamem_free(fc->tdmat, base, fc->tdmap);
1745 				bus_dma_tag_destroy(fc->tdmat);
1746 				goto bad;
1747 			}
1748 			if (!IS_2100(isp)) {
1749 				for (i = 0; i < INITIAL_NEXUS_COUNT; i++) {
1750 					struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO);
1751 					if (n == NULL) {
1752 						while (fc->nexus_free_list) {
1753 							n = fc->nexus_free_list;
1754 							fc->nexus_free_list = n->next;
1755 							free(n, M_DEVBUF);
1756 						}
1757 						goto bad;
1758 					}
1759 					n->next = fc->nexus_free_list;
1760 					fc->nexus_free_list = n;
1761 				}
1762 			}
1763 		}
1764 	}
1765 
1766 	for (i = 0; i < isp->isp_maxcmds; i++) {
1767 		struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i];
1768 		error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap);
1769 		if (error) {
1770 			isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error);
1771 			while (--i >= 0) {
1772 				bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap);
1773 			}
1774 			goto bad;
1775 		}
1776 		callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0);
1777 		if (i == isp->isp_maxcmds-1) {
1778 			pcmd->next = NULL;
1779 		} else {
1780 			pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1];
1781 		}
1782 	}
1783 	isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0];
1784 	ISP_LOCK(isp);
1785 	return (0);
1786 
1787 bad:
1788 	while (--cmap >= 0) {
1789 		struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1790 		bus_dmamap_unload(fc->tdmat, fc->tdmap);
1791 		bus_dmamem_free(fc->tdmat, base, fc->tdmap);
1792 		bus_dma_tag_destroy(fc->tdmat);
1793 		while (fc->nexus_free_list) {
1794 			struct isp_nexus *n = fc->nexus_free_list;
1795 			fc->nexus_free_list = n->next;
1796 			free(n, M_DEVBUF);
1797 		}
1798 	}
1799 	if (isp->isp_rquest_dma != 0)
1800 		bus_dmamap_unload(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap);
1801 	bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap);
1802 	bus_dma_tag_destroy(isp->isp_osinfo.cdmat);
1803 	free(isp->isp_xflist, M_DEVBUF);
1804 #ifdef	ISP_TARGET_MODE
1805 	free(isp->isp_tgtlist, M_DEVBUF);
1806 #endif
1807 	free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1808 	isp->isp_rquest = NULL;
1809 	ISP_LOCK(isp);
1810 	return (1);
1811 }
1812 
1813 typedef struct {
1814 	ispsoftc_t *isp;
1815 	void *cmd_token;
1816 	void *rq;	/* original request */
1817 	int error;
1818 	bus_size_t mapsize;
1819 } mush_t;
1820 
1821 #define	MUSHERR_NOQENTRIES	-2
1822 
1823 #ifdef	ISP_TARGET_MODE
1824 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1825 static void tdma2(void *, bus_dma_segment_t *, int, int);
1826 
1827 static void
1828 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1829 {
1830 	mush_t *mp;
1831 	mp = (mush_t *)arg;
1832 	mp->mapsize = mapsize;
1833 	tdma2(arg, dm_segs, nseg, error);
1834 }
1835 
1836 static void
1837 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1838 {
1839 	mush_t *mp;
1840 	ispsoftc_t *isp;
1841 	struct ccb_scsiio *csio;
1842 	isp_ddir_t ddir;
1843 	ispreq_t *rq;
1844 
1845 	mp = (mush_t *) arg;
1846 	if (error) {
1847 		mp->error = error;
1848 		return;
1849 	}
1850 	csio = mp->cmd_token;
1851 	isp = mp->isp;
1852 	rq = mp->rq;
1853 	if (nseg) {
1854 		if (isp->isp_osinfo.sixtyfourbit) {
1855 			if (nseg >= ISP_NSEG64_MAX) {
1856 				isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1857 				mp->error = EFAULT;
1858 				return;
1859 			}
1860 			if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) {
1861 				rq->req_header.rqs_entry_type = RQSTYPE_CTIO3;
1862 			}
1863 		} else {
1864 			if (nseg >= ISP_NSEG_MAX) {
1865 				isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1866 				mp->error = EFAULT;
1867 				return;
1868 			}
1869 		}
1870 		if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1871 			bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1872 			ddir = ISP_TO_DEVICE;
1873 		} else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1874 			bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1875 			ddir = ISP_FROM_DEVICE;
1876 		} else {
1877 			dm_segs = NULL;
1878 			nseg = 0;
1879 			ddir = ISP_NOXFR;
1880 		}
1881 	} else {
1882 		dm_segs = NULL;
1883 		nseg = 0;
1884 		ddir = ISP_NOXFR;
1885 	}
1886 
1887 	error = isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len);
1888 	switch (error) {
1889 	case CMD_EAGAIN:
1890 		mp->error = MUSHERR_NOQENTRIES;
1891 	case CMD_QUEUED:
1892 		break;
1893 	default:
1894 		mp->error = EIO;
1895 	}
1896 }
1897 #endif
1898 
1899 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1900 static void dma2(void *, bus_dma_segment_t *, int, int);
1901 
1902 static void
1903 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1904 {
1905 	mush_t *mp;
1906 	mp = (mush_t *)arg;
1907 	mp->mapsize = mapsize;
1908 	dma2(arg, dm_segs, nseg, error);
1909 }
1910 
1911 static void
1912 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1913 {
1914 	mush_t *mp;
1915 	ispsoftc_t *isp;
1916 	struct ccb_scsiio *csio;
1917 	isp_ddir_t ddir;
1918 	ispreq_t *rq;
1919 
1920 	mp = (mush_t *) arg;
1921 	if (error) {
1922 		mp->error = error;
1923 		return;
1924 	}
1925 	csio = mp->cmd_token;
1926 	isp = mp->isp;
1927 	rq = mp->rq;
1928 	if (nseg) {
1929 		if (isp->isp_osinfo.sixtyfourbit) {
1930 			if (nseg >= ISP_NSEG64_MAX) {
1931 				isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1932 				mp->error = EFAULT;
1933 				return;
1934 			}
1935 			if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) {
1936 				rq->req_header.rqs_entry_type = RQSTYPE_T3RQS;
1937 			} else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) {
1938 				rq->req_header.rqs_entry_type = RQSTYPE_A64;
1939 			}
1940 		} else {
1941 			if (nseg >= ISP_NSEG_MAX) {
1942 				isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1943 				mp->error = EFAULT;
1944 				return;
1945 			}
1946 		}
1947 		if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1948 			bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1949 			ddir = ISP_FROM_DEVICE;
1950 		} else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1951 			bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1952 			ddir = ISP_TO_DEVICE;
1953 		} else {
1954 			ddir = ISP_NOXFR;
1955 		}
1956 	} else {
1957 		dm_segs = NULL;
1958 		nseg = 0;
1959 		ddir = ISP_NOXFR;
1960 	}
1961 
1962 	error = isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, (ispds64_t *)csio->req_map);
1963 	switch (error) {
1964 	case CMD_EAGAIN:
1965 		mp->error = MUSHERR_NOQENTRIES;
1966 		break;
1967 	case CMD_QUEUED:
1968 		break;
1969 	default:
1970 		mp->error = EIO;
1971 		break;
1972 	}
1973 }
1974 
1975 static int
1976 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff)
1977 {
1978 	mush_t mush, *mp;
1979 	void (*eptr)(void *, bus_dma_segment_t *, int, int);
1980 	void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int);
1981 	int error;
1982 
1983 	mp = &mush;
1984 	mp->isp = isp;
1985 	mp->cmd_token = csio;
1986 	mp->rq = ff;
1987 	mp->error = 0;
1988 	mp->mapsize = 0;
1989 
1990 #ifdef	ISP_TARGET_MODE
1991 	if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) {
1992 		eptr = tdma2;
1993 		eptr2 = tdma2_2;
1994 	} else
1995 #endif
1996 	{
1997 		eptr = dma2;
1998 		eptr2 = dma2_2;
1999 	}
2000 
2001 
2002 	error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap,
2003 	    (union ccb *)csio, eptr, mp, 0);
2004 	if (error == EINPROGRESS) {
2005 		bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap);
2006 		mp->error = EINVAL;
2007 		isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported");
2008 	} else if (error && mp->error == 0) {
2009 #ifdef	DIAGNOSTIC
2010 		isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error);
2011 #endif
2012 		mp->error = error;
2013 	}
2014 	if (mp->error) {
2015 		int retval = CMD_COMPLETE;
2016 		if (mp->error == MUSHERR_NOQENTRIES) {
2017 			retval = CMD_EAGAIN;
2018 		} else if (mp->error == EFBIG) {
2019 			csio->ccb_h.status = CAM_REQ_TOO_BIG;
2020 		} else if (mp->error == EINVAL) {
2021 			csio->ccb_h.status = CAM_REQ_INVALID;
2022 		} else {
2023 			csio->ccb_h.status = CAM_UNREC_HBA_ERROR;
2024 		}
2025 		return (retval);
2026 	}
2027 	return (CMD_QUEUED);
2028 }
2029 
2030 static void
2031 isp_pci_reset0(ispsoftc_t *isp)
2032 {
2033 	ISP_DISABLE_INTS(isp);
2034 }
2035 
2036 static void
2037 isp_pci_reset1(ispsoftc_t *isp)
2038 {
2039 	if (!IS_24XX(isp)) {
2040 		/* Make sure the BIOS is disabled */
2041 		isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
2042 	}
2043 	/* and enable interrupts */
2044 	ISP_ENABLE_INTS(isp);
2045 }
2046 
2047 static void
2048 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg)
2049 {
2050 	struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
2051 	if (msg)
2052 		printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg);
2053 	else
2054 		printf("%s:\n", device_get_nameunit(isp->isp_dev));
2055 	if (IS_SCSI(isp))
2056 		printf("    biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
2057 	else
2058 		printf("    biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
2059 	printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
2060 	    ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
2061 	printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
2062 
2063 
2064 	if (IS_SCSI(isp)) {
2065 		ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
2066 		printf("    cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
2067 			ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
2068 			ISP_READ(isp, CDMA_FIFO_STS));
2069 		printf("    ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
2070 			ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
2071 			ISP_READ(isp, DDMA_FIFO_STS));
2072 		printf("    sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
2073 			ISP_READ(isp, SXP_INTERRUPT),
2074 			ISP_READ(isp, SXP_GROSS_ERR),
2075 			ISP_READ(isp, SXP_PINS_CTRL));
2076 		ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
2077 	}
2078 	printf("    mbox regs: %x %x %x %x %x\n",
2079 	    ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
2080 	    ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
2081 	    ISP_READ(isp, OUTMAILBOX4));
2082 	printf("    PCI Status Command/Status=%x\n",
2083 	    pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1));
2084 }
2085