1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 #include <sys/malloc.h> 47 #include <sys/uio.h> 48 49 #include <dev/isp/isp_freebsd.h> 50 51 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 52 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 53 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 54 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 55 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 56 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 57 static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 58 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 59 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 60 static int isp_pci_mbxdma(ispsoftc_t *); 61 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 62 63 64 static void isp_pci_reset0(ispsoftc_t *); 65 static void isp_pci_reset1(ispsoftc_t *); 66 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 67 68 static struct ispmdvec mdvec = { 69 isp_pci_rd_isr, 70 isp_pci_rd_reg, 71 isp_pci_wr_reg, 72 isp_pci_mbxdma, 73 isp_pci_dmasetup, 74 isp_common_dmateardown, 75 isp_pci_reset0, 76 isp_pci_reset1, 77 isp_pci_dumpregs, 78 NULL, 79 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 80 }; 81 82 static struct ispmdvec mdvec_1080 = { 83 isp_pci_rd_isr, 84 isp_pci_rd_reg_1080, 85 isp_pci_wr_reg_1080, 86 isp_pci_mbxdma, 87 isp_pci_dmasetup, 88 isp_common_dmateardown, 89 isp_pci_reset0, 90 isp_pci_reset1, 91 isp_pci_dumpregs, 92 NULL, 93 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 94 }; 95 96 static struct ispmdvec mdvec_12160 = { 97 isp_pci_rd_isr, 98 isp_pci_rd_reg_1080, 99 isp_pci_wr_reg_1080, 100 isp_pci_mbxdma, 101 isp_pci_dmasetup, 102 isp_common_dmateardown, 103 isp_pci_reset0, 104 isp_pci_reset1, 105 isp_pci_dumpregs, 106 NULL, 107 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 108 }; 109 110 static struct ispmdvec mdvec_2100 = { 111 isp_pci_rd_isr, 112 isp_pci_rd_reg, 113 isp_pci_wr_reg, 114 isp_pci_mbxdma, 115 isp_pci_dmasetup, 116 isp_common_dmateardown, 117 isp_pci_reset0, 118 isp_pci_reset1, 119 isp_pci_dumpregs 120 }; 121 122 static struct ispmdvec mdvec_2200 = { 123 isp_pci_rd_isr, 124 isp_pci_rd_reg, 125 isp_pci_wr_reg, 126 isp_pci_mbxdma, 127 isp_pci_dmasetup, 128 isp_common_dmateardown, 129 isp_pci_reset0, 130 isp_pci_reset1, 131 isp_pci_dumpregs 132 }; 133 134 static struct ispmdvec mdvec_2300 = { 135 isp_pci_rd_isr_2300, 136 isp_pci_rd_reg, 137 isp_pci_wr_reg, 138 isp_pci_mbxdma, 139 isp_pci_dmasetup, 140 isp_common_dmateardown, 141 isp_pci_reset0, 142 isp_pci_reset1, 143 isp_pci_dumpregs 144 }; 145 146 static struct ispmdvec mdvec_2400 = { 147 isp_pci_rd_isr_2400, 148 isp_pci_rd_reg_2400, 149 isp_pci_wr_reg_2400, 150 isp_pci_mbxdma, 151 isp_pci_dmasetup, 152 isp_common_dmateardown, 153 isp_pci_reset0, 154 isp_pci_reset1, 155 NULL 156 }; 157 158 static struct ispmdvec mdvec_2500 = { 159 isp_pci_rd_isr_2400, 160 isp_pci_rd_reg_2400, 161 isp_pci_wr_reg_2400, 162 isp_pci_mbxdma, 163 isp_pci_dmasetup, 164 isp_common_dmateardown, 165 isp_pci_reset0, 166 isp_pci_reset1, 167 NULL 168 }; 169 170 #ifndef PCIM_CMD_INVEN 171 #define PCIM_CMD_INVEN 0x10 172 #endif 173 #ifndef PCIM_CMD_BUSMASTEREN 174 #define PCIM_CMD_BUSMASTEREN 0x0004 175 #endif 176 #ifndef PCIM_CMD_PERRESPEN 177 #define PCIM_CMD_PERRESPEN 0x0040 178 #endif 179 #ifndef PCIM_CMD_SEREN 180 #define PCIM_CMD_SEREN 0x0100 181 #endif 182 #ifndef PCIM_CMD_INTX_DISABLE 183 #define PCIM_CMD_INTX_DISABLE 0x0400 184 #endif 185 186 #ifndef PCIR_COMMAND 187 #define PCIR_COMMAND 0x04 188 #endif 189 190 #ifndef PCIR_CACHELNSZ 191 #define PCIR_CACHELNSZ 0x0c 192 #endif 193 194 #ifndef PCIR_LATTIMER 195 #define PCIR_LATTIMER 0x0d 196 #endif 197 198 #ifndef PCIR_ROMADDR 199 #define PCIR_ROMADDR 0x30 200 #endif 201 202 #ifndef PCI_VENDOR_QLOGIC 203 #define PCI_VENDOR_QLOGIC 0x1077 204 #endif 205 206 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 207 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 208 #endif 209 210 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 211 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 212 #endif 213 214 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 215 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 216 #endif 217 218 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 219 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 220 #endif 221 222 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 223 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 224 #endif 225 226 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 227 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 228 #endif 229 230 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 231 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 232 #endif 233 234 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 235 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 236 #endif 237 238 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 239 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 240 #endif 241 242 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 243 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 244 #endif 245 246 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 247 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 248 #endif 249 250 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 251 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 252 #endif 253 254 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 255 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 256 #endif 257 258 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 259 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 260 #endif 261 262 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 263 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 264 #endif 265 266 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 267 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 268 #endif 269 270 271 #define PCI_QLOGIC_ISP1020 \ 272 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 273 274 #define PCI_QLOGIC_ISP1080 \ 275 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 276 277 #define PCI_QLOGIC_ISP10160 \ 278 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 279 280 #define PCI_QLOGIC_ISP12160 \ 281 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 282 283 #define PCI_QLOGIC_ISP1240 \ 284 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 285 286 #define PCI_QLOGIC_ISP1280 \ 287 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 288 289 #define PCI_QLOGIC_ISP2100 \ 290 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 291 292 #define PCI_QLOGIC_ISP2200 \ 293 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 294 295 #define PCI_QLOGIC_ISP2300 \ 296 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 297 298 #define PCI_QLOGIC_ISP2312 \ 299 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 300 301 #define PCI_QLOGIC_ISP2322 \ 302 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 303 304 #define PCI_QLOGIC_ISP2422 \ 305 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 306 307 #define PCI_QLOGIC_ISP2432 \ 308 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 309 310 #define PCI_QLOGIC_ISP2532 \ 311 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 312 313 #define PCI_QLOGIC_ISP6312 \ 314 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 315 316 #define PCI_QLOGIC_ISP6322 \ 317 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 318 319 /* 320 * Odd case for some AMI raid cards... We need to *not* attach to this. 321 */ 322 #define AMI_RAID_SUBVENDOR_ID 0x101e 323 324 #define IO_MAP_REG 0x10 325 #define MEM_MAP_REG 0x14 326 327 #define PCI_DFLT_LTNCY 0x40 328 #define PCI_DFLT_LNSZ 0x10 329 330 static int isp_pci_probe (device_t); 331 static int isp_pci_attach (device_t); 332 static int isp_pci_detach (device_t); 333 334 335 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 336 struct isp_pcisoftc { 337 ispsoftc_t pci_isp; 338 device_t pci_dev; 339 struct resource * pci_reg; 340 void * ih; 341 int16_t pci_poff[_NREG_BLKS]; 342 bus_dma_tag_t dmat; 343 int msicount; 344 }; 345 346 347 static device_method_t isp_pci_methods[] = { 348 /* Device interface */ 349 DEVMETHOD(device_probe, isp_pci_probe), 350 DEVMETHOD(device_attach, isp_pci_attach), 351 DEVMETHOD(device_detach, isp_pci_detach), 352 { 0, 0 } 353 }; 354 355 static driver_t isp_pci_driver = { 356 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 357 }; 358 static devclass_t isp_devclass; 359 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 360 361 static int 362 isp_pci_probe(device_t dev) 363 { 364 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 365 case PCI_QLOGIC_ISP1020: 366 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 367 break; 368 case PCI_QLOGIC_ISP1080: 369 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 370 break; 371 case PCI_QLOGIC_ISP1240: 372 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 373 break; 374 case PCI_QLOGIC_ISP1280: 375 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 376 break; 377 case PCI_QLOGIC_ISP10160: 378 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 379 break; 380 case PCI_QLOGIC_ISP12160: 381 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 382 return (ENXIO); 383 } 384 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 385 break; 386 case PCI_QLOGIC_ISP2100: 387 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 388 break; 389 case PCI_QLOGIC_ISP2200: 390 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 391 break; 392 case PCI_QLOGIC_ISP2300: 393 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 394 break; 395 case PCI_QLOGIC_ISP2312: 396 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 397 break; 398 case PCI_QLOGIC_ISP2322: 399 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 400 break; 401 case PCI_QLOGIC_ISP2422: 402 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 403 break; 404 case PCI_QLOGIC_ISP2432: 405 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 406 break; 407 case PCI_QLOGIC_ISP2532: 408 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 409 break; 410 case PCI_QLOGIC_ISP6312: 411 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 412 break; 413 case PCI_QLOGIC_ISP6322: 414 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 415 break; 416 default: 417 return (ENXIO); 418 } 419 if (isp_announced == 0 && bootverbose) { 420 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 421 "Core Version %d.%d\n", 422 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 423 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 424 isp_announced++; 425 } 426 /* 427 * XXXX: Here is where we might load the f/w module 428 * XXXX: (or increase a reference count to it). 429 */ 430 return (BUS_PROBE_DEFAULT); 431 } 432 433 static void 434 isp_get_generic_options(device_t dev, ispsoftc_t *isp, int *nvp) 435 { 436 int tval; 437 438 /* 439 * Figure out if we're supposed to skip this one. 440 */ 441 tval = 0; 442 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 443 device_printf(dev, "disabled at user request\n"); 444 isp->isp_osinfo.disabled = 1; 445 return; 446 } 447 448 tval = 0; 449 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 450 isp->isp_confopts |= ISP_CFG_NORELOAD; 451 } 452 tval = 0; 453 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 454 isp->isp_confopts |= ISP_CFG_NONVRAM; 455 } 456 tval = 0; 457 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 458 if (tval) { 459 isp->isp_dblev = tval; 460 } else { 461 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 462 } 463 if (bootverbose) { 464 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 465 } 466 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 467 if (tval > 0 && tval < 127) { 468 *nvp = tval; 469 } else { 470 *nvp = 0; 471 } 472 tval = 1; 473 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 474 isp_autoconfig = tval; 475 tval = 7; 476 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 477 isp_quickboot_time = tval; 478 479 tval = 0; 480 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "forcemulti", &tval) == 0 && tval != 0) { 481 isp->isp_osinfo.forcemulti = 1; 482 } 483 } 484 485 static void 486 isp_get_pci_options(device_t dev, int *m1, int *m2) 487 { 488 int tval; 489 /* 490 * Which we should try first - memory mapping or i/o mapping? 491 * 492 * We used to try memory first followed by i/o on alpha, otherwise 493 * the reverse, but we should just try memory first all the time now. 494 */ 495 *m1 = PCIM_CMD_MEMEN; 496 *m2 = PCIM_CMD_PORTEN; 497 498 tval = 0; 499 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 500 *m1 = PCIM_CMD_PORTEN; 501 *m2 = PCIM_CMD_MEMEN; 502 } 503 tval = 0; 504 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 505 *m1 = PCIM_CMD_MEMEN; 506 *m2 = PCIM_CMD_PORTEN; 507 } 508 } 509 510 static void 511 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 512 { 513 const char *sptr; 514 int tval; 515 516 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 517 if (IS_FC(isp)) { 518 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 519 } else { 520 ISP_SPI_PC(isp, chan)->iid = 7; 521 } 522 } else { 523 if (IS_FC(isp)) { 524 ISP_FC_PC(isp, chan)->default_id = tval - chan; 525 } else { 526 ISP_SPI_PC(isp, chan)->iid = tval; 527 } 528 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 529 } 530 531 tval = -1; 532 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 533 switch (tval) { 534 case ISP_ROLE_NONE: 535 case ISP_ROLE_INITIATOR: 536 case ISP_ROLE_TARGET: 537 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 538 device_printf(dev, "setting role to 0x%x\n", tval); 539 break; 540 default: 541 tval = -1; 542 break; 543 } 544 } 545 if (tval == -1) { 546 tval = ISP_DEFAULT_ROLES; 547 } 548 549 if (IS_SCSI(isp)) { 550 ISP_SPI_PC(isp, chan)->def_role = tval; 551 return; 552 } 553 ISP_FC_PC(isp, chan)->def_role = tval; 554 555 tval = 0; 556 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 557 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 558 } 559 sptr = 0; 560 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", (const char **) &sptr) == 0 && sptr != 0) { 561 if (strcmp(sptr, "lport") == 0) { 562 isp->isp_confopts |= ISP_CFG_LPORT; 563 } else if (strcmp(sptr, "nport") == 0) { 564 isp->isp_confopts |= ISP_CFG_NPORT; 565 } else if (strcmp(sptr, "lport-only") == 0) { 566 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 567 } else if (strcmp(sptr, "nport-only") == 0) { 568 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 569 } 570 } 571 572 /* 573 * Because the resource_*_value functions can neither return 574 * 64 bit integer values, nor can they be directly coerced 575 * to interpret the right hand side of the assignment as 576 * you want them to interpret it, we have to force WWN 577 * hint replacement to specify WWN strings with a leading 578 * 'w' (e..g w50000000aaaa0001). Sigh. 579 */ 580 sptr = 0; 581 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", (const char **) &sptr); 582 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 583 char *eptr = 0; 584 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 585 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 586 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 587 ISP_FC_PC(isp, chan)->def_wwpn = 0; 588 } 589 } 590 591 sptr = 0; 592 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", (const char **) &sptr); 593 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 594 char *eptr = 0; 595 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 596 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 597 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 598 ISP_FC_PC(isp, chan)->def_wwnn = 0; 599 } 600 } 601 602 tval = 0; 603 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 604 if (tval >= 0 && tval < 256) { 605 ISP_FC_PC(isp, chan)->hysteresis = tval; 606 } else { 607 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 608 } 609 610 tval = -1; 611 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 612 if (tval >= 0 && tval < 0xffff) { 613 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 614 } else { 615 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 616 } 617 618 tval = -1; 619 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 620 if (tval >= 0 && tval < 0xffff) { 621 ISP_FC_PC(isp, chan)->gone_device_time = tval; 622 } else { 623 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 624 } 625 } 626 627 static int 628 isp_pci_attach(device_t dev) 629 { 630 struct resource *regs, *irq; 631 int rtp, rgd, iqd, i, m1, m2, locksetup = 0; 632 int isp_nvports = 0; 633 uint32_t data, cmd, linesz, did; 634 struct isp_pcisoftc *pcs; 635 ispsoftc_t *isp = NULL; 636 size_t psize, xsize; 637 char fwname[32]; 638 639 pcs = device_get_softc(dev); 640 if (pcs == NULL) { 641 device_printf(dev, "cannot get softc\n"); 642 return (ENOMEM); 643 } 644 memset(pcs, 0, sizeof (*pcs)); 645 646 pcs->pci_dev = dev; 647 isp = &pcs->pci_isp; 648 isp->isp_dev = dev; 649 isp->isp_nchan = 1; 650 651 /* 652 * Get Generic Options 653 */ 654 isp_get_generic_options(dev, isp, &isp_nvports); 655 656 /* 657 * Check to see if options have us disabled 658 */ 659 if (isp->isp_osinfo.disabled) { 660 /* 661 * But return zero to preserve unit numbering 662 */ 663 return (0); 664 } 665 666 /* 667 * Get PCI options- which in this case are just mapping preferences. 668 */ 669 isp_get_pci_options(dev, &m1, &m2); 670 671 linesz = PCI_DFLT_LNSZ; 672 irq = regs = NULL; 673 rgd = rtp = iqd = 0; 674 675 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 676 if (cmd & m1) { 677 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 678 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 679 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 680 } 681 if (regs == NULL && (cmd & m2)) { 682 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 683 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 684 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 685 } 686 if (regs == NULL) { 687 device_printf(dev, "unable to map any ports\n"); 688 goto bad; 689 } 690 if (bootverbose) { 691 device_printf(dev, "using %s space register mapping\n", (rgd == IO_MAP_REG)? "I/O" : "Memory"); 692 } 693 isp->isp_bus_tag = rman_get_bustag(regs); 694 isp->isp_bus_handle = rman_get_bushandle(regs); 695 696 pcs->pci_dev = dev; 697 pcs->pci_reg = regs; 698 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 699 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 700 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 701 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 702 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 703 704 switch (pci_get_devid(dev)) { 705 case PCI_QLOGIC_ISP1020: 706 did = 0x1040; 707 isp->isp_mdvec = &mdvec; 708 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 709 break; 710 case PCI_QLOGIC_ISP1080: 711 did = 0x1080; 712 isp->isp_mdvec = &mdvec_1080; 713 isp->isp_type = ISP_HA_SCSI_1080; 714 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 715 break; 716 case PCI_QLOGIC_ISP1240: 717 did = 0x1080; 718 isp->isp_mdvec = &mdvec_1080; 719 isp->isp_type = ISP_HA_SCSI_1240; 720 isp->isp_nchan = 2; 721 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 722 break; 723 case PCI_QLOGIC_ISP1280: 724 did = 0x1080; 725 isp->isp_mdvec = &mdvec_1080; 726 isp->isp_type = ISP_HA_SCSI_1280; 727 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 728 break; 729 case PCI_QLOGIC_ISP10160: 730 did = 0x12160; 731 isp->isp_mdvec = &mdvec_12160; 732 isp->isp_type = ISP_HA_SCSI_10160; 733 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 734 break; 735 case PCI_QLOGIC_ISP12160: 736 did = 0x12160; 737 isp->isp_nchan = 2; 738 isp->isp_mdvec = &mdvec_12160; 739 isp->isp_type = ISP_HA_SCSI_12160; 740 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 741 break; 742 case PCI_QLOGIC_ISP2100: 743 did = 0x2100; 744 isp->isp_mdvec = &mdvec_2100; 745 isp->isp_type = ISP_HA_FC_2100; 746 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 747 if (pci_get_revid(dev) < 3) { 748 /* 749 * XXX: Need to get the actual revision 750 * XXX: number of the 2100 FB. At any rate, 751 * XXX: lower cache line size for early revision 752 * XXX; boards. 753 */ 754 linesz = 1; 755 } 756 break; 757 case PCI_QLOGIC_ISP2200: 758 did = 0x2200; 759 isp->isp_mdvec = &mdvec_2200; 760 isp->isp_type = ISP_HA_FC_2200; 761 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 762 break; 763 case PCI_QLOGIC_ISP2300: 764 did = 0x2300; 765 isp->isp_mdvec = &mdvec_2300; 766 isp->isp_type = ISP_HA_FC_2300; 767 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 768 break; 769 case PCI_QLOGIC_ISP2312: 770 case PCI_QLOGIC_ISP6312: 771 did = 0x2300; 772 isp->isp_mdvec = &mdvec_2300; 773 isp->isp_type = ISP_HA_FC_2312; 774 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 775 break; 776 case PCI_QLOGIC_ISP2322: 777 case PCI_QLOGIC_ISP6322: 778 did = 0x2322; 779 isp->isp_mdvec = &mdvec_2300; 780 isp->isp_type = ISP_HA_FC_2322; 781 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 782 break; 783 case PCI_QLOGIC_ISP2422: 784 case PCI_QLOGIC_ISP2432: 785 did = 0x2400; 786 isp->isp_nchan += isp_nvports; 787 isp->isp_mdvec = &mdvec_2400; 788 isp->isp_type = ISP_HA_FC_2400; 789 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 790 break; 791 case PCI_QLOGIC_ISP2532: 792 did = 0x2500; 793 isp->isp_nchan += isp_nvports; 794 isp->isp_mdvec = &mdvec_2500; 795 isp->isp_type = ISP_HA_FC_2500; 796 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 797 break; 798 default: 799 device_printf(dev, "unknown device type\n"); 800 goto bad; 801 break; 802 } 803 isp->isp_revision = pci_get_revid(dev); 804 805 if (IS_FC(isp)) { 806 psize = sizeof (fcparam); 807 xsize = sizeof (struct isp_fc); 808 } else { 809 psize = sizeof (sdparam); 810 xsize = sizeof (struct isp_spi); 811 } 812 psize *= isp->isp_nchan; 813 xsize *= isp->isp_nchan; 814 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 815 if (isp->isp_param == NULL) { 816 device_printf(dev, "cannot allocate parameter data\n"); 817 goto bad; 818 } 819 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 820 if (isp->isp_osinfo.pc.ptr == NULL) { 821 device_printf(dev, "cannot allocate parameter data\n"); 822 goto bad; 823 } 824 825 /* 826 * Now that we know who we are (roughly) get/set specific options 827 */ 828 for (i = 0; i < isp->isp_nchan; i++) { 829 isp_get_specific_options(dev, i, isp); 830 } 831 832 /* 833 * The 'it' suffix really only matters for SCSI cards in target mode. 834 */ 835 isp->isp_osinfo.fw = NULL; 836 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 837 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 838 isp->isp_osinfo.fw = firmware_get(fwname); 839 } else if (IS_24XX(isp) && (isp->isp_nchan > 1 || isp->isp_osinfo.forcemulti)) { 840 snprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 841 isp->isp_osinfo.fw = firmware_get(fwname); 842 } 843 if (isp->isp_osinfo.fw == NULL) { 844 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 845 isp->isp_osinfo.fw = firmware_get(fwname); 846 } 847 if (isp->isp_osinfo.fw != NULL) { 848 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 849 } 850 851 /* 852 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 853 * are set. 854 */ 855 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 856 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 857 858 if (IS_2300(isp)) { /* per QLogic errata */ 859 cmd &= ~PCIM_CMD_INVEN; 860 } 861 862 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 863 cmd &= ~PCIM_CMD_INTX_DISABLE; 864 } 865 866 if (IS_24XX(isp)) { 867 cmd &= ~PCIM_CMD_INTX_DISABLE; 868 } 869 870 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 871 872 /* 873 * Make sure the Cache Line Size register is set sensibly. 874 */ 875 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 876 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 877 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d from %d", linesz, data); 878 data = linesz; 879 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 880 } 881 882 /* 883 * Make sure the Latency Timer is sane. 884 */ 885 data = pci_read_config(dev, PCIR_LATTIMER, 1); 886 if (data < PCI_DFLT_LTNCY) { 887 data = PCI_DFLT_LTNCY; 888 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 889 pci_write_config(dev, PCIR_LATTIMER, data, 1); 890 } 891 892 /* 893 * Make sure we've disabled the ROM. 894 */ 895 data = pci_read_config(dev, PCIR_ROMADDR, 4); 896 data &= ~1; 897 pci_write_config(dev, PCIR_ROMADDR, data, 4); 898 899 /* 900 * Do MSI 901 * 902 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 903 */ 904 if (IS_24XX(isp) || IS_2322(isp)) { 905 pcs->msicount = pci_msi_count(dev); 906 if (pcs->msicount > 1) { 907 pcs->msicount = 1; 908 } 909 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 910 iqd = 1; 911 } else { 912 iqd = 0; 913 } 914 } 915 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd, RF_ACTIVE | RF_SHAREABLE); 916 if (irq == NULL) { 917 device_printf(dev, "could not allocate interrupt\n"); 918 goto bad; 919 } 920 921 /* Make sure the lock is set up. */ 922 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 923 locksetup++; 924 925 if (isp_setup_intr(dev, irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 926 device_printf(dev, "could not setup interrupt\n"); 927 goto bad; 928 } 929 930 /* 931 * Last minute checks... 932 */ 933 if (IS_23XX(isp) || IS_24XX(isp)) { 934 isp->isp_port = pci_get_function(dev); 935 } 936 937 /* 938 * Make sure we're in reset state. 939 */ 940 ISP_LOCK(isp); 941 isp_reset(isp, 1); 942 if (isp->isp_state != ISP_RESETSTATE) { 943 ISP_UNLOCK(isp); 944 goto bad; 945 } 946 isp_init(isp); 947 if (isp->isp_state == ISP_INITSTATE) { 948 isp->isp_state = ISP_RUNSTATE; 949 } 950 ISP_UNLOCK(isp); 951 if (isp_attach(isp)) { 952 ISP_LOCK(isp); 953 isp_uninit(isp); 954 ISP_UNLOCK(isp); 955 goto bad; 956 } 957 return (0); 958 959 bad: 960 if (pcs && pcs->ih) { 961 (void) bus_teardown_intr(dev, irq, pcs->ih); 962 } 963 if (locksetup && isp) { 964 mtx_destroy(&isp->isp_osinfo.lock); 965 } 966 if (irq) { 967 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 968 } 969 if (pcs && pcs->msicount) { 970 pci_release_msi(dev); 971 } 972 if (regs) { 973 (void) bus_release_resource(dev, rtp, rgd, regs); 974 } 975 if (pcs) { 976 if (pcs->pci_isp.isp_param) { 977 free(pcs->pci_isp.isp_param, M_DEVBUF); 978 pcs->pci_isp.isp_param = NULL; 979 } 980 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 981 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 982 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 983 } 984 } 985 return (ENXIO); 986 } 987 988 static int 989 isp_pci_detach(device_t dev) 990 { 991 struct isp_pcisoftc *pcs; 992 ispsoftc_t *isp; 993 994 pcs = device_get_softc(dev); 995 if (pcs == NULL) { 996 return (ENXIO); 997 } 998 isp = (ispsoftc_t *) pcs; 999 ISP_DISABLE_INTS(isp); 1000 mtx_destroy(&isp->isp_osinfo.lock); 1001 return (0); 1002 } 1003 1004 #define IspVirt2Off(a, x) \ 1005 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1006 _BLK_REG_SHFT] + ((x) & 0xfff)) 1007 1008 #define BXR2(isp, off) \ 1009 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1010 #define BXW2(isp, off, v) \ 1011 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1012 #define BXR4(isp, off) \ 1013 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1014 #define BXW4(isp, off, v) \ 1015 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1016 1017 1018 static ISP_INLINE int 1019 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1020 { 1021 uint32_t val0, val1; 1022 int i = 0; 1023 1024 do { 1025 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1026 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1027 } while (val0 != val1 && ++i < 1000); 1028 if (val0 != val1) { 1029 return (1); 1030 } 1031 *rp = val0; 1032 return (0); 1033 } 1034 1035 static int 1036 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1037 { 1038 uint16_t isr, sema; 1039 1040 if (IS_2100(isp)) { 1041 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1042 return (0); 1043 } 1044 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1045 return (0); 1046 } 1047 } else { 1048 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1049 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1050 } 1051 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1052 isr &= INT_PENDING_MASK(isp); 1053 sema &= BIU_SEMA_LOCK; 1054 if (isr == 0 && sema == 0) { 1055 return (0); 1056 } 1057 *isrp = isr; 1058 if ((*semap = sema) != 0) { 1059 if (IS_2100(isp)) { 1060 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1061 return (0); 1062 } 1063 } else { 1064 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1065 } 1066 } 1067 return (1); 1068 } 1069 1070 static int 1071 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1072 { 1073 uint32_t hccr; 1074 uint32_t r2hisr; 1075 1076 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1077 *isrp = 0; 1078 return (0); 1079 } 1080 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1081 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1082 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1083 *isrp = 0; 1084 return (0); 1085 } 1086 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1087 case ISPR2HST_ROM_MBX_OK: 1088 case ISPR2HST_ROM_MBX_FAIL: 1089 case ISPR2HST_MBX_OK: 1090 case ISPR2HST_MBX_FAIL: 1091 case ISPR2HST_ASYNC_EVENT: 1092 *isrp = r2hisr & 0xffff; 1093 *mbox0p = (r2hisr >> 16); 1094 *semap = 1; 1095 return (1); 1096 case ISPR2HST_RIO_16: 1097 *isrp = r2hisr & 0xffff; 1098 *mbox0p = ASYNC_RIO16_1; 1099 *semap = 1; 1100 return (1); 1101 case ISPR2HST_FPOST: 1102 *isrp = r2hisr & 0xffff; 1103 *mbox0p = ASYNC_CMD_CMPLT; 1104 *semap = 1; 1105 return (1); 1106 case ISPR2HST_FPOST_CTIO: 1107 *isrp = r2hisr & 0xffff; 1108 *mbox0p = ASYNC_CTIO_DONE; 1109 *semap = 1; 1110 return (1); 1111 case ISPR2HST_RSPQ_UPDATE: 1112 *isrp = r2hisr & 0xffff; 1113 *mbox0p = 0; 1114 *semap = 0; 1115 return (1); 1116 default: 1117 hccr = ISP_READ(isp, HCCR); 1118 if (hccr & HCCR_PAUSE) { 1119 ISP_WRITE(isp, HCCR, HCCR_RESET); 1120 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1121 ISP_WRITE(isp, BIU_ICR, 0); 1122 } else { 1123 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1124 } 1125 return (0); 1126 } 1127 } 1128 1129 static int 1130 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1131 { 1132 uint32_t r2hisr; 1133 1134 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1135 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1136 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1137 *isrp = 0; 1138 return (0); 1139 } 1140 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1141 case ISP2400R2HST_ROM_MBX_OK: 1142 case ISP2400R2HST_ROM_MBX_FAIL: 1143 case ISP2400R2HST_MBX_OK: 1144 case ISP2400R2HST_MBX_FAIL: 1145 case ISP2400R2HST_ASYNC_EVENT: 1146 *isrp = r2hisr & 0xffff; 1147 *mbox0p = (r2hisr >> 16); 1148 *semap = 1; 1149 return (1); 1150 case ISP2400R2HST_RSPQ_UPDATE: 1151 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1152 case ISP2400R2HST_ATIO_RQST_UPDATE: 1153 *isrp = r2hisr & 0xffff; 1154 *mbox0p = 0; 1155 *semap = 0; 1156 return (1); 1157 default: 1158 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1159 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1160 return (0); 1161 } 1162 } 1163 1164 static uint32_t 1165 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1166 { 1167 uint16_t rv; 1168 int oldconf = 0; 1169 1170 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1171 /* 1172 * We will assume that someone has paused the RISC processor. 1173 */ 1174 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1175 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1176 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1177 } 1178 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1179 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1180 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1181 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1182 } 1183 return (rv); 1184 } 1185 1186 static void 1187 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1188 { 1189 int oldconf = 0; 1190 1191 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1192 /* 1193 * We will assume that someone has paused the RISC processor. 1194 */ 1195 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1196 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1197 oldconf | BIU_PCI_CONF1_SXP); 1198 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1199 } 1200 BXW2(isp, IspVirt2Off(isp, regoff), val); 1201 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1202 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1203 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1204 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1205 } 1206 1207 } 1208 1209 static uint32_t 1210 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1211 { 1212 uint32_t rv, oc = 0; 1213 1214 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1215 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1216 uint32_t tc; 1217 /* 1218 * We will assume that someone has paused the RISC processor. 1219 */ 1220 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1221 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1222 if (regoff & SXP_BANK1_SELECT) 1223 tc |= BIU_PCI1080_CONF1_SXP1; 1224 else 1225 tc |= BIU_PCI1080_CONF1_SXP0; 1226 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1227 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1228 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1229 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1230 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1231 oc | BIU_PCI1080_CONF1_DMA); 1232 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1233 } 1234 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1235 if (oc) { 1236 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1237 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1238 } 1239 return (rv); 1240 } 1241 1242 static void 1243 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1244 { 1245 int oc = 0; 1246 1247 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1248 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1249 uint32_t tc; 1250 /* 1251 * We will assume that someone has paused the RISC processor. 1252 */ 1253 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1254 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1255 if (regoff & SXP_BANK1_SELECT) 1256 tc |= BIU_PCI1080_CONF1_SXP1; 1257 else 1258 tc |= BIU_PCI1080_CONF1_SXP0; 1259 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1260 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1261 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1262 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1263 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1264 oc | BIU_PCI1080_CONF1_DMA); 1265 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1266 } 1267 BXW2(isp, IspVirt2Off(isp, regoff), val); 1268 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1269 if (oc) { 1270 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1271 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1272 } 1273 } 1274 1275 static uint32_t 1276 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1277 { 1278 uint32_t rv; 1279 int block = regoff & _BLK_REG_MASK; 1280 1281 switch (block) { 1282 case BIU_BLOCK: 1283 break; 1284 case MBOX_BLOCK: 1285 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1286 case SXP_BLOCK: 1287 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1288 return (0xffffffff); 1289 case RISC_BLOCK: 1290 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1291 return (0xffffffff); 1292 case DMA_BLOCK: 1293 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1294 return (0xffffffff); 1295 default: 1296 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1297 return (0xffffffff); 1298 } 1299 1300 1301 switch (regoff) { 1302 case BIU2400_FLASH_ADDR: 1303 case BIU2400_FLASH_DATA: 1304 case BIU2400_ICR: 1305 case BIU2400_ISR: 1306 case BIU2400_CSR: 1307 case BIU2400_REQINP: 1308 case BIU2400_REQOUTP: 1309 case BIU2400_RSPINP: 1310 case BIU2400_RSPOUTP: 1311 case BIU2400_PRI_REQINP: 1312 case BIU2400_PRI_REQOUTP: 1313 case BIU2400_ATIO_RSPINP: 1314 case BIU2400_ATIO_RSPOUTP: 1315 case BIU2400_HCCR: 1316 case BIU2400_GPIOD: 1317 case BIU2400_GPIOE: 1318 case BIU2400_HSEMA: 1319 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1320 break; 1321 case BIU2400_R2HSTSLO: 1322 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1323 break; 1324 case BIU2400_R2HSTSHI: 1325 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1326 break; 1327 default: 1328 isp_prt(isp, ISP_LOGERR, 1329 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1330 rv = 0xffffffff; 1331 break; 1332 } 1333 return (rv); 1334 } 1335 1336 static void 1337 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1338 { 1339 int block = regoff & _BLK_REG_MASK; 1340 1341 switch (block) { 1342 case BIU_BLOCK: 1343 break; 1344 case MBOX_BLOCK: 1345 BXW2(isp, IspVirt2Off(isp, regoff), val); 1346 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1347 return; 1348 case SXP_BLOCK: 1349 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1350 return; 1351 case RISC_BLOCK: 1352 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1353 return; 1354 case DMA_BLOCK: 1355 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1356 return; 1357 default: 1358 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1359 regoff); 1360 break; 1361 } 1362 1363 switch (regoff) { 1364 case BIU2400_FLASH_ADDR: 1365 case BIU2400_FLASH_DATA: 1366 case BIU2400_ICR: 1367 case BIU2400_ISR: 1368 case BIU2400_CSR: 1369 case BIU2400_REQINP: 1370 case BIU2400_REQOUTP: 1371 case BIU2400_RSPINP: 1372 case BIU2400_RSPOUTP: 1373 case BIU2400_PRI_REQINP: 1374 case BIU2400_PRI_REQOUTP: 1375 case BIU2400_ATIO_RSPINP: 1376 case BIU2400_ATIO_RSPOUTP: 1377 case BIU2400_HCCR: 1378 case BIU2400_GPIOD: 1379 case BIU2400_GPIOE: 1380 case BIU2400_HSEMA: 1381 BXW4(isp, IspVirt2Off(isp, regoff), val); 1382 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4); 1383 break; 1384 default: 1385 isp_prt(isp, ISP_LOGERR, 1386 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1387 break; 1388 } 1389 } 1390 1391 1392 struct imush { 1393 ispsoftc_t *isp; 1394 caddr_t vbase; 1395 int chan; 1396 int error; 1397 }; 1398 1399 static void imc(void *, bus_dma_segment_t *, int, int); 1400 static void imc1(void *, bus_dma_segment_t *, int, int); 1401 1402 static void 1403 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1404 { 1405 struct imush *imushp = (struct imush *) arg; 1406 1407 if (error) { 1408 imushp->error = error; 1409 return; 1410 } 1411 if (nseg != 1) { 1412 imushp->error = EINVAL; 1413 return; 1414 } 1415 imushp->isp->isp_rquest = imushp->vbase; 1416 imushp->isp->isp_rquest_dma = segs->ds_addr; 1417 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1418 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1419 imushp->isp->isp_result_dma = segs->ds_addr; 1420 imushp->isp->isp_result = imushp->vbase; 1421 1422 #ifdef ISP_TARGET_MODE 1423 if (IS_24XX(imushp->isp)) { 1424 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1425 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1426 imushp->isp->isp_atioq_dma = segs->ds_addr; 1427 imushp->isp->isp_atioq = imushp->vbase; 1428 } 1429 #endif 1430 } 1431 1432 static void 1433 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1434 { 1435 struct imush *imushp = (struct imush *) arg; 1436 if (error) { 1437 imushp->error = error; 1438 return; 1439 } 1440 if (nseg != 1) { 1441 imushp->error = EINVAL; 1442 return; 1443 } 1444 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1445 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1446 } 1447 1448 static int 1449 isp_pci_mbxdma(ispsoftc_t *isp) 1450 { 1451 caddr_t base; 1452 uint32_t len; 1453 int i, error, ns, cmap = 0; 1454 bus_size_t slim; /* segment size */ 1455 bus_addr_t llim; /* low limit of unavailable dma */ 1456 bus_addr_t hlim; /* high limit of unavailable dma */ 1457 struct imush im; 1458 1459 /* 1460 * Already been here? If so, leave... 1461 */ 1462 if (isp->isp_rquest) { 1463 return (0); 1464 } 1465 ISP_UNLOCK(isp); 1466 1467 if (isp->isp_maxcmds == 0) { 1468 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1469 ISP_LOCK(isp); 1470 return (1); 1471 } 1472 1473 hlim = BUS_SPACE_MAXADDR; 1474 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1475 if (sizeof (bus_size_t) > 4) { 1476 slim = (bus_size_t) (1ULL << 32); 1477 } else { 1478 slim = (bus_size_t) (1UL << 31); 1479 } 1480 llim = BUS_SPACE_MAXADDR; 1481 } else { 1482 llim = BUS_SPACE_MAXADDR_32BIT; 1483 slim = (1UL << 24); 1484 } 1485 1486 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1487 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1488 if (isp->isp_osinfo.pcmd_pool == NULL) { 1489 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1490 ISP_LOCK(isp); 1491 return (1); 1492 } 1493 1494 /* 1495 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1496 */ 1497 #ifdef ISP_TARGET_MODE 1498 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1499 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1500 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1501 ISP_LOCK(isp); 1502 return (1); 1503 } 1504 #endif 1505 1506 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) { 1507 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1508 ISP_LOCK(isp); 1509 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1510 return (1); 1511 } 1512 1513 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1514 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1515 if (isp->isp_xflist == NULL) { 1516 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1517 ISP_LOCK(isp); 1518 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1519 return (1); 1520 } 1521 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1522 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1523 } 1524 isp->isp_xffree = isp->isp_xflist; 1525 #ifdef ISP_TARGET_MODE 1526 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1527 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1528 if (isp->isp_tgtlist == NULL) { 1529 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1530 free(isp->isp_xflist, M_DEVBUF); 1531 ISP_LOCK(isp); 1532 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1533 return (1); 1534 } 1535 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1536 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1537 } 1538 isp->isp_tgtfree = isp->isp_tgtlist; 1539 #endif 1540 1541 /* 1542 * Allocate and map the request and result queues (and ATIO queue 1543 * if we're a 2400 supporting target mode). 1544 */ 1545 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1546 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1547 #ifdef ISP_TARGET_MODE 1548 if (IS_24XX(isp)) { 1549 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1550 } 1551 #endif 1552 1553 ns = (len / PAGE_SIZE) + 1; 1554 1555 /* 1556 * Create a tag for the control spaces. We don't always need this 1557 * to be 32 bits, but we do this for simplicity and speed's sake. 1558 */ 1559 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) { 1560 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1561 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1562 free(isp->isp_xflist, M_DEVBUF); 1563 #ifdef ISP_TARGET_MODE 1564 free(isp->isp_tgtlist, M_DEVBUF); 1565 #endif 1566 ISP_LOCK(isp); 1567 return (1); 1568 } 1569 1570 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT, &isp->isp_osinfo.cdmap) != 0) { 1571 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1572 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1573 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1574 free(isp->isp_xflist, M_DEVBUF); 1575 #ifdef ISP_TARGET_MODE 1576 free(isp->isp_tgtlist, M_DEVBUF); 1577 #endif 1578 ISP_LOCK(isp); 1579 return (1); 1580 } 1581 1582 im.isp = isp; 1583 im.chan = 0; 1584 im.vbase = base; 1585 im.error = 0; 1586 1587 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1588 if (im.error) { 1589 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1590 goto bad; 1591 } 1592 1593 if (IS_FC(isp)) { 1594 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1595 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1596 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1597 goto bad; 1598 } 1599 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT, &fc->tdmap) != 0) { 1600 bus_dma_tag_destroy(fc->tdmat); 1601 goto bad; 1602 } 1603 im.isp = isp; 1604 im.chan = cmap; 1605 im.vbase = base; 1606 im.error = 0; 1607 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1608 if (im.error) { 1609 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1610 bus_dma_tag_destroy(fc->tdmat); 1611 goto bad; 1612 } 1613 } 1614 } 1615 1616 for (i = 0; i < isp->isp_maxcmds; i++) { 1617 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1618 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1619 if (error) { 1620 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1621 while (--i >= 0) { 1622 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1623 } 1624 goto bad; 1625 } 1626 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1627 if (i == isp->isp_maxcmds-1) { 1628 pcmd->next = NULL; 1629 } else { 1630 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1631 } 1632 } 1633 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1634 ISP_LOCK(isp); 1635 return (0); 1636 1637 bad: 1638 while (--cmap >= 0) { 1639 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1640 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1641 bus_dma_tag_destroy(fc->tdmat); 1642 } 1643 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1644 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1645 free(isp->isp_xflist, M_DEVBUF); 1646 #ifdef ISP_TARGET_MODE 1647 free(isp->isp_tgtlist, M_DEVBUF); 1648 #endif 1649 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1650 isp->isp_rquest = NULL; 1651 ISP_LOCK(isp); 1652 return (1); 1653 } 1654 1655 typedef struct { 1656 ispsoftc_t *isp; 1657 void *cmd_token; 1658 void *rq; /* original request */ 1659 int error; 1660 bus_size_t mapsize; 1661 } mush_t; 1662 1663 #define MUSHERR_NOQENTRIES -2 1664 1665 #ifdef ISP_TARGET_MODE 1666 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1667 static void tdma2(void *, bus_dma_segment_t *, int, int); 1668 1669 static void 1670 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1671 { 1672 mush_t *mp; 1673 mp = (mush_t *)arg; 1674 mp->mapsize = mapsize; 1675 tdma2(arg, dm_segs, nseg, error); 1676 } 1677 1678 static void 1679 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1680 { 1681 mush_t *mp; 1682 ispsoftc_t *isp; 1683 struct ccb_scsiio *csio; 1684 isp_ddir_t ddir; 1685 ispreq_t *rq; 1686 1687 mp = (mush_t *) arg; 1688 if (error) { 1689 mp->error = error; 1690 return; 1691 } 1692 csio = mp->cmd_token; 1693 isp = mp->isp; 1694 rq = mp->rq; 1695 if (nseg) { 1696 if (sizeof (bus_addr_t) > 4) { 1697 if (nseg >= ISP_NSEG64_MAX) { 1698 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1699 mp->error = EFAULT; 1700 return; 1701 } 1702 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1703 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1704 } 1705 } else { 1706 if (nseg >= ISP_NSEG_MAX) { 1707 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1708 mp->error = EFAULT; 1709 return; 1710 } 1711 } 1712 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1713 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1714 ddir = ISP_TO_DEVICE; 1715 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1716 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1717 ddir = ISP_FROM_DEVICE; 1718 } else { 1719 ddir = ISP_NOXFR; 1720 } 1721 } else { 1722 dm_segs = NULL; 1723 nseg = 0; 1724 ddir = ISP_NOXFR; 1725 } 1726 1727 if (isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len) != CMD_QUEUED) { 1728 mp->error = MUSHERR_NOQENTRIES; 1729 } 1730 } 1731 #endif 1732 1733 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1734 static void dma2(void *, bus_dma_segment_t *, int, int); 1735 1736 static void 1737 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1738 { 1739 mush_t *mp; 1740 mp = (mush_t *)arg; 1741 mp->mapsize = mapsize; 1742 dma2(arg, dm_segs, nseg, error); 1743 } 1744 1745 static void 1746 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1747 { 1748 mush_t *mp; 1749 ispsoftc_t *isp; 1750 struct ccb_scsiio *csio; 1751 isp_ddir_t ddir; 1752 ispreq_t *rq; 1753 1754 mp = (mush_t *) arg; 1755 if (error) { 1756 mp->error = error; 1757 return; 1758 } 1759 csio = mp->cmd_token; 1760 isp = mp->isp; 1761 rq = mp->rq; 1762 if (nseg) { 1763 if (sizeof (bus_addr_t) > 4) { 1764 if (nseg >= ISP_NSEG64_MAX) { 1765 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1766 mp->error = EFAULT; 1767 return; 1768 } 1769 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1770 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1771 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1772 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1773 } 1774 } else { 1775 if (nseg >= ISP_NSEG_MAX) { 1776 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1777 mp->error = EFAULT; 1778 return; 1779 } 1780 } 1781 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1782 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1783 ddir = ISP_FROM_DEVICE; 1784 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1785 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1786 ddir = ISP_TO_DEVICE; 1787 } else { 1788 ddir = ISP_NOXFR; 1789 } 1790 } else { 1791 dm_segs = NULL; 1792 nseg = 0; 1793 ddir = ISP_NOXFR; 1794 } 1795 1796 if (isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir) != CMD_QUEUED) { 1797 mp->error = MUSHERR_NOQENTRIES; 1798 } 1799 } 1800 1801 static int 1802 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1803 { 1804 mush_t mush, *mp; 1805 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1806 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1807 1808 mp = &mush; 1809 mp->isp = isp; 1810 mp->cmd_token = csio; 1811 mp->rq = ff; 1812 mp->error = 0; 1813 mp->mapsize = 0; 1814 1815 #ifdef ISP_TARGET_MODE 1816 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1817 eptr = tdma2; 1818 eptr2 = tdma2_2; 1819 } else 1820 #endif 1821 { 1822 eptr = dma2; 1823 eptr2 = dma2_2; 1824 } 1825 1826 1827 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) { 1828 (*eptr)(mp, NULL, 0, 0); 1829 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1830 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1831 int error; 1832 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1833 #if 0 1834 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error); 1835 #endif 1836 1837 if (error == EINPROGRESS) { 1838 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1839 mp->error = EINVAL; 1840 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1841 } else if (error && mp->error == 0) { 1842 #ifdef DIAGNOSTIC 1843 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1844 #endif 1845 mp->error = error; 1846 } 1847 } else { 1848 /* Pointer to physical buffer */ 1849 struct bus_dma_segment seg; 1850 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 1851 seg.ds_len = csio->dxfer_len; 1852 (*eptr)(mp, &seg, 1, 0); 1853 } 1854 } else { 1855 struct bus_dma_segment *segs; 1856 1857 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1858 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported"); 1859 mp->error = EINVAL; 1860 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1861 struct uio sguio; 1862 int error; 1863 1864 /* 1865 * We're taking advantage of the fact that 1866 * the pointer/length sizes and layout of the iovec 1867 * structure are the same as the bus_dma_segment 1868 * structure. This might be a little dangerous, 1869 * but only if they change the structures, which 1870 * seems unlikely. 1871 */ 1872 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) && 1873 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) && 1874 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed")); 1875 sguio.uio_iov = (struct iovec *)csio->data_ptr; 1876 sguio.uio_iovcnt = csio->sglist_cnt; 1877 sguio.uio_resid = csio->dxfer_len; 1878 sguio.uio_segflg = UIO_SYSSPACE; 1879 1880 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0); 1881 1882 if (error != 0 && mp->error == 0) { 1883 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1884 mp->error = error; 1885 } 1886 } else { 1887 /* Just use the segments provided */ 1888 segs = (struct bus_dma_segment *) csio->data_ptr; 1889 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1890 } 1891 } 1892 if (mp->error) { 1893 int retval = CMD_COMPLETE; 1894 if (mp->error == MUSHERR_NOQENTRIES) { 1895 retval = CMD_EAGAIN; 1896 } else if (mp->error == EFBIG) { 1897 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1898 } else if (mp->error == EINVAL) { 1899 XS_SETERR(csio, CAM_REQ_INVALID); 1900 } else { 1901 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1902 } 1903 return (retval); 1904 } 1905 return (CMD_QUEUED); 1906 } 1907 1908 static void 1909 isp_pci_reset0(ispsoftc_t *isp) 1910 { 1911 ISP_DISABLE_INTS(isp); 1912 } 1913 1914 static void 1915 isp_pci_reset1(ispsoftc_t *isp) 1916 { 1917 if (!IS_24XX(isp)) { 1918 /* Make sure the BIOS is disabled */ 1919 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1920 } 1921 /* and enable interrupts */ 1922 ISP_ENABLE_INTS(isp); 1923 } 1924 1925 static void 1926 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1927 { 1928 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1929 if (msg) 1930 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1931 else 1932 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1933 if (IS_SCSI(isp)) 1934 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1935 else 1936 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1937 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1938 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1939 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1940 1941 1942 if (IS_SCSI(isp)) { 1943 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1944 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1945 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1946 ISP_READ(isp, CDMA_FIFO_STS)); 1947 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1948 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1949 ISP_READ(isp, DDMA_FIFO_STS)); 1950 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1951 ISP_READ(isp, SXP_INTERRUPT), 1952 ISP_READ(isp, SXP_GROSS_ERR), 1953 ISP_READ(isp, SXP_PINS_CTRL)); 1954 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1955 } 1956 printf(" mbox regs: %x %x %x %x %x\n", 1957 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1958 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1959 ISP_READ(isp, OUTMAILBOX4)); 1960 printf(" PCI Status Command/Status=%x\n", 1961 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1962 } 1963