1 /* $FreeBSD$ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * FreeBSD Version. 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000, 2001 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 36 #include <pci/pcireg.h> 37 #include <pci/pcivar.h> 38 39 #include <machine/bus_memio.h> 40 #include <machine/bus_pio.h> 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 46 #include <dev/isp/isp_freebsd.h> 47 48 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int)); 49 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t)); 50 static u_int16_t isp_pci_rd_reg_1080 __P((struct ispsoftc *, int)); 51 static void isp_pci_wr_reg_1080 __P((struct ispsoftc *, int, u_int16_t)); 52 static int isp_pci_mbxdma __P((struct ispsoftc *)); 53 static int isp_pci_dmasetup __P((struct ispsoftc *, XS_T *, 54 ispreq_t *, u_int16_t *, u_int16_t)); 55 static void 56 isp_pci_dmateardown __P((struct ispsoftc *, XS_T *, u_int16_t)); 57 58 static void isp_pci_reset1 __P((struct ispsoftc *)); 59 static void isp_pci_dumpregs __P((struct ispsoftc *, const char *)); 60 61 #ifndef ISP_CODE_ORG 62 #define ISP_CODE_ORG 0x1000 63 #endif 64 65 static struct ispmdvec mdvec = { 66 isp_pci_rd_reg, 67 isp_pci_wr_reg, 68 isp_pci_mbxdma, 69 isp_pci_dmasetup, 70 isp_pci_dmateardown, 71 NULL, 72 isp_pci_reset1, 73 isp_pci_dumpregs, 74 NULL, 75 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 76 }; 77 78 static struct ispmdvec mdvec_1080 = { 79 isp_pci_rd_reg_1080, 80 isp_pci_wr_reg_1080, 81 isp_pci_mbxdma, 82 isp_pci_dmasetup, 83 isp_pci_dmateardown, 84 NULL, 85 isp_pci_reset1, 86 isp_pci_dumpregs, 87 NULL, 88 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 89 }; 90 91 static struct ispmdvec mdvec_12160 = { 92 isp_pci_rd_reg_1080, 93 isp_pci_wr_reg_1080, 94 isp_pci_mbxdma, 95 isp_pci_dmasetup, 96 isp_pci_dmateardown, 97 NULL, 98 isp_pci_reset1, 99 isp_pci_dumpregs, 100 NULL, 101 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 102 }; 103 104 static struct ispmdvec mdvec_2100 = { 105 isp_pci_rd_reg, 106 isp_pci_wr_reg, 107 isp_pci_mbxdma, 108 isp_pci_dmasetup, 109 isp_pci_dmateardown, 110 NULL, 111 isp_pci_reset1, 112 isp_pci_dumpregs 113 }; 114 115 static struct ispmdvec mdvec_2200 = { 116 isp_pci_rd_reg, 117 isp_pci_wr_reg, 118 isp_pci_mbxdma, 119 isp_pci_dmasetup, 120 isp_pci_dmateardown, 121 NULL, 122 isp_pci_reset1, 123 isp_pci_dumpregs 124 }; 125 126 #ifndef PCIM_CMD_INVEN 127 #define PCIM_CMD_INVEN 0x10 128 #endif 129 #ifndef PCIM_CMD_BUSMASTEREN 130 #define PCIM_CMD_BUSMASTEREN 0x0004 131 #endif 132 #ifndef PCIM_CMD_PERRESPEN 133 #define PCIM_CMD_PERRESPEN 0x0040 134 #endif 135 #ifndef PCIM_CMD_SEREN 136 #define PCIM_CMD_SEREN 0x0100 137 #endif 138 139 #ifndef PCIR_COMMAND 140 #define PCIR_COMMAND 0x04 141 #endif 142 143 #ifndef PCIR_CACHELNSZ 144 #define PCIR_CACHELNSZ 0x0c 145 #endif 146 147 #ifndef PCIR_LATTIMER 148 #define PCIR_LATTIMER 0x0d 149 #endif 150 151 #ifndef PCIR_ROMADDR 152 #define PCIR_ROMADDR 0x30 153 #endif 154 155 #ifndef PCI_VENDOR_QLOGIC 156 #define PCI_VENDOR_QLOGIC 0x1077 157 #endif 158 159 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 160 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 161 #endif 162 163 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 164 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 165 #endif 166 167 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 168 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 169 #endif 170 171 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 172 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 173 #endif 174 175 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 176 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 177 #endif 178 179 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 180 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 181 #endif 182 183 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 184 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 185 #endif 186 187 #define PCI_QLOGIC_ISP1020 \ 188 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 189 190 #define PCI_QLOGIC_ISP1080 \ 191 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 192 193 #define PCI_QLOGIC_ISP12160 \ 194 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 195 196 #define PCI_QLOGIC_ISP1240 \ 197 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 198 199 #define PCI_QLOGIC_ISP1280 \ 200 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 201 202 #define PCI_QLOGIC_ISP2100 \ 203 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 204 205 #define PCI_QLOGIC_ISP2200 \ 206 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 207 208 /* 209 * Odd case for some AMI raid cards... We need to *not* attach to this. 210 */ 211 #define AMI_RAID_SUBVENDOR_ID 0x101e 212 213 #define IO_MAP_REG 0x10 214 #define MEM_MAP_REG 0x14 215 216 #define PCI_DFLT_LTNCY 0x40 217 #define PCI_DFLT_LNSZ 0x10 218 219 static int isp_pci_probe (device_t); 220 static int isp_pci_attach (device_t); 221 222 struct isp_pcisoftc { 223 struct ispsoftc pci_isp; 224 device_t pci_dev; 225 struct resource * pci_reg; 226 bus_space_tag_t pci_st; 227 bus_space_handle_t pci_sh; 228 void * ih; 229 int16_t pci_poff[_NREG_BLKS]; 230 bus_dma_tag_t parent_dmat; 231 bus_dma_tag_t cntrol_dmat; 232 bus_dmamap_t cntrol_dmap; 233 bus_dmamap_t *dmaps; 234 }; 235 ispfwfunc *isp_get_firmware_p = NULL; 236 237 static device_method_t isp_pci_methods[] = { 238 /* Device interface */ 239 DEVMETHOD(device_probe, isp_pci_probe), 240 DEVMETHOD(device_attach, isp_pci_attach), 241 { 0, 0 } 242 }; 243 static void isp_pci_intr __P((void *)); 244 245 static driver_t isp_pci_driver = { 246 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 247 }; 248 static devclass_t isp_devclass; 249 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 250 MODULE_VERSION(isp, 1); 251 252 static int 253 isp_pci_probe(device_t dev) 254 { 255 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 256 case PCI_QLOGIC_ISP1020: 257 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 258 break; 259 case PCI_QLOGIC_ISP1080: 260 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 261 break; 262 case PCI_QLOGIC_ISP1240: 263 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 264 break; 265 case PCI_QLOGIC_ISP1280: 266 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 267 break; 268 case PCI_QLOGIC_ISP12160: 269 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 270 return (ENXIO); 271 } 272 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 273 break; 274 case PCI_QLOGIC_ISP2100: 275 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 276 break; 277 case PCI_QLOGIC_ISP2200: 278 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 279 break; 280 default: 281 return (ENXIO); 282 } 283 if (device_get_unit(dev) == 0 && bootverbose) { 284 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 285 "Core Version %d.%d\n", 286 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 287 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 288 } 289 /* 290 * XXXX: Here is where we might load the f/w module 291 * XXXX: (or increase a reference count to it). 292 */ 293 return (0); 294 } 295 296 static int 297 isp_pci_attach(device_t dev) 298 { 299 struct resource *regs, *irq; 300 int tval, rtp, rgd, iqd, m1, m2, isp_debug, role; 301 u_int32_t data, cmd, linesz, psize, basetype; 302 struct isp_pcisoftc *pcs; 303 struct ispsoftc *isp = NULL; 304 struct ispmdvec *mdvp; 305 bus_size_t lim; 306 char *sptr; 307 #ifdef ISP_SMPLOCK 308 int locksetup = 0; 309 #endif 310 311 /* 312 * Figure out if we're supposed to skip this one. 313 * If we are, we actually go to ISP_ROLE_NONE. 314 */ 315 316 tval = 0; 317 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 318 "disable", &tval) == 0 && tval) { 319 device_printf(dev, "device is disabled\n"); 320 /* but return 0 so the !$)$)*!$*) unit isn't reused */ 321 return (0); 322 } 323 324 role = 0; 325 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 326 "role", &role) == 0 && 327 ((role & ~(ISP_ROLE_INITIATOR|ISP_ROLE_TARGET)) == 0)) { 328 device_printf(dev, "setting role to 0x%x\n", role); 329 } else { 330 #ifdef ISP_TARGET_MODE 331 role = ISP_ROLE_INITIATOR|ISP_ROLE_TARGET; 332 #else 333 role = ISP_DEFAULT_ROLES; 334 #endif 335 } 336 337 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT | M_ZERO); 338 if (pcs == NULL) { 339 device_printf(dev, "cannot allocate softc\n"); 340 return (ENOMEM); 341 } 342 343 /* 344 * Figure out which we should try first - memory mapping or i/o mapping? 345 */ 346 #ifdef __alpha__ 347 m1 = PCIM_CMD_MEMEN; 348 m2 = PCIM_CMD_PORTEN; 349 #else 350 m1 = PCIM_CMD_PORTEN; 351 m2 = PCIM_CMD_MEMEN; 352 #endif 353 354 tval = 0; 355 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 356 "prefer_iomap", &tval) == 0 && tval != 0) { 357 m1 = PCIM_CMD_PORTEN; 358 m2 = PCIM_CMD_MEMEN; 359 } 360 tval = 0; 361 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 362 "prefer_memmap", &tval) == 0 && tval != 0) { 363 m1 = PCIM_CMD_MEMEN; 364 m2 = PCIM_CMD_PORTEN; 365 } 366 367 linesz = PCI_DFLT_LNSZ; 368 irq = regs = NULL; 369 rgd = rtp = iqd = 0; 370 371 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 372 if (cmd & m1) { 373 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 374 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 375 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 376 } 377 if (regs == NULL && (cmd & m2)) { 378 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 379 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 380 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 381 } 382 if (regs == NULL) { 383 device_printf(dev, "unable to map any ports\n"); 384 goto bad; 385 } 386 if (bootverbose) 387 device_printf(dev, "using %s space register mapping\n", 388 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 389 pcs->pci_dev = dev; 390 pcs->pci_reg = regs; 391 pcs->pci_st = rman_get_bustag(regs); 392 pcs->pci_sh = rman_get_bushandle(regs); 393 394 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 395 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 396 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 397 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 398 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 399 mdvp = &mdvec; 400 basetype = ISP_HA_SCSI_UNKNOWN; 401 psize = sizeof (sdparam); 402 lim = BUS_SPACE_MAXSIZE_32BIT; 403 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 404 mdvp = &mdvec; 405 basetype = ISP_HA_SCSI_UNKNOWN; 406 psize = sizeof (sdparam); 407 lim = BUS_SPACE_MAXSIZE_24BIT; 408 } 409 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 410 mdvp = &mdvec_1080; 411 basetype = ISP_HA_SCSI_1080; 412 psize = sizeof (sdparam); 413 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 414 ISP1080_DMA_REGS_OFF; 415 } 416 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 417 mdvp = &mdvec_1080; 418 basetype = ISP_HA_SCSI_1240; 419 psize = 2 * sizeof (sdparam); 420 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 421 ISP1080_DMA_REGS_OFF; 422 } 423 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 424 mdvp = &mdvec_1080; 425 basetype = ISP_HA_SCSI_1280; 426 psize = 2 * sizeof (sdparam); 427 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 428 ISP1080_DMA_REGS_OFF; 429 } 430 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 431 mdvp = &mdvec_12160; 432 basetype = ISP_HA_SCSI_12160; 433 psize = 2 * sizeof (sdparam); 434 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 435 ISP1080_DMA_REGS_OFF; 436 } 437 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 438 mdvp = &mdvec_2100; 439 basetype = ISP_HA_FC_2100; 440 psize = sizeof (fcparam); 441 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 442 PCI_MBOX_REGS2100_OFF; 443 if (pci_get_revid(dev) < 3) { 444 /* 445 * XXX: Need to get the actual revision 446 * XXX: number of the 2100 FB. At any rate, 447 * XXX: lower cache line size for early revision 448 * XXX; boards. 449 */ 450 linesz = 1; 451 } 452 } 453 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 454 mdvp = &mdvec_2200; 455 basetype = ISP_HA_FC_2200; 456 psize = sizeof (fcparam); 457 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 458 PCI_MBOX_REGS2100_OFF; 459 } 460 isp = &pcs->pci_isp; 461 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 462 if (isp->isp_param == NULL) { 463 device_printf(dev, "cannot allocate parameter data\n"); 464 goto bad; 465 } 466 isp->isp_mdvec = mdvp; 467 isp->isp_type = basetype; 468 isp->isp_revision = pci_get_revid(dev); 469 isp->isp_role = role; 470 isp->isp_dev = dev; 471 472 /* 473 * Try and find firmware for this device. 474 */ 475 476 if (isp_get_firmware_p) { 477 int device = (int) pci_get_device(dev); 478 #ifdef ISP_TARGET_MODE 479 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 480 #else 481 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 482 #endif 483 } 484 485 /* 486 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 487 * are set. 488 */ 489 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 490 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 491 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 492 493 /* 494 * Make sure the Cache Line Size register is set sensibly. 495 */ 496 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 497 if (data != linesz) { 498 data = PCI_DFLT_LNSZ; 499 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 500 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 501 } 502 503 /* 504 * Make sure the Latency Timer is sane. 505 */ 506 data = pci_read_config(dev, PCIR_LATTIMER, 1); 507 if (data < PCI_DFLT_LTNCY) { 508 data = PCI_DFLT_LTNCY; 509 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 510 pci_write_config(dev, PCIR_LATTIMER, data, 1); 511 } 512 513 /* 514 * Make sure we've disabled the ROM. 515 */ 516 data = pci_read_config(dev, PCIR_ROMADDR, 4); 517 data &= ~1; 518 pci_write_config(dev, PCIR_ROMADDR, data, 4); 519 520 521 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 522 BUS_SPACE_MAXADDR, NULL, NULL, lim + 1, 523 255, lim, 0, &pcs->parent_dmat) != 0) { 524 device_printf(dev, "could not create master dma tag\n"); 525 free(isp->isp_param, M_DEVBUF); 526 free(pcs, M_DEVBUF); 527 return (ENXIO); 528 } 529 530 iqd = 0; 531 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 532 1, RF_ACTIVE | RF_SHAREABLE); 533 if (irq == NULL) { 534 device_printf(dev, "could not allocate interrupt\n"); 535 goto bad; 536 } 537 538 tval = 0; 539 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 540 "fwload_disable", &tval) == 0 && tval != 0) { 541 isp->isp_confopts |= ISP_CFG_NORELOAD; 542 } 543 tval = 0; 544 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 545 "ignore_nvram", &tval) == 0 && tval != 0) { 546 isp->isp_confopts |= ISP_CFG_NONVRAM; 547 } 548 tval = 0; 549 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 550 "fullduplex", &tval) == 0 && tval != 0) { 551 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 552 } 553 554 sptr = 0; 555 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 556 "topology", &sptr) == 0 && sptr != 0) { 557 if (strcmp(sptr, "lport") == 0) { 558 isp->isp_confopts |= ISP_CFG_LPORT; 559 } else if (strcmp(sptr, "nport") == 0) { 560 isp->isp_confopts |= ISP_CFG_NPORT; 561 } else if (strcmp(sptr, "lport-only") == 0) { 562 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 563 } else if (strcmp(sptr, "nport-only") == 0) { 564 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 565 } 566 } 567 568 /* 569 * Because the resource_*_value functions can neither return 570 * 64 bit integer values, nor can they be directly coerced 571 * to interpret the right hand side of the assignment as 572 * you want them to interpret it, we have to force WWN 573 * hint replacement to specify WWN strings with a leading 574 * 'w' (e..g w50000000aaaa0001). Sigh. 575 */ 576 sptr = 0; 577 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 578 "portwwn", &sptr); 579 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 580 char *eptr = 0; 581 isp->isp_osinfo.default_port_wwn = strtouq(sptr, &eptr, 16); 582 if (eptr < sptr + 16 || isp->isp_osinfo.default_port_wwn == 0) { 583 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 584 isp->isp_osinfo.default_port_wwn = 0; 585 } else { 586 isp->isp_confopts |= ISP_CFG_OWNWWN; 587 } 588 } 589 if (isp->isp_osinfo.default_port_wwn == 0) { 590 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 591 } 592 593 sptr = 0; 594 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 595 "nodewwn", &sptr); 596 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 597 char *eptr = 0; 598 isp->isp_osinfo.default_node_wwn = strtouq(sptr, &eptr, 16); 599 if (eptr < sptr + 16 || isp->isp_osinfo.default_node_wwn == 0) { 600 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 601 isp->isp_osinfo.default_node_wwn = 0; 602 } else { 603 isp->isp_confopts |= ISP_CFG_OWNWWN; 604 } 605 } 606 if (isp->isp_osinfo.default_node_wwn == 0) { 607 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 608 } 609 610 isp_debug = 0; 611 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 612 "debug", &isp_debug); 613 614 #ifdef ISP_SMPLOCK 615 /* Make sure the lock is set up. */ 616 mtx_init(&isp->isp_osinfo.lock, "isp", MTX_DEF); 617 locksetup++; 618 619 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM | INTR_MPSAFE | INTR_ENTROPY, 620 isp_pci_intr, isp, &pcs->ih)) { 621 device_printf(dev, "could not setup interrupt\n"); 622 goto bad; 623 } 624 #else 625 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM | INTR_ENTROPY, 626 isp_pci_intr, isp, &pcs->ih)) { 627 device_printf(dev, "could not setup interrupt\n"); 628 goto bad; 629 } 630 #endif 631 632 /* 633 * Set up logging levels. 634 */ 635 if (isp_debug) { 636 isp->isp_dblev = isp_debug; 637 } else { 638 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 639 } 640 if (bootverbose) 641 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 642 643 /* 644 * Make sure we're in reset state. 645 */ 646 ISP_LOCK(isp); 647 isp_reset(isp); 648 if (isp->isp_state != ISP_RESETSTATE) { 649 ISP_UNLOCK(isp); 650 goto bad; 651 } 652 isp_init(isp); 653 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_INITSTATE) { 654 isp_uninit(isp); 655 ISP_UNLOCK(isp); 656 goto bad; 657 } 658 isp_attach(isp); 659 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_RUNSTATE) { 660 isp_uninit(isp); 661 ISP_UNLOCK(isp); 662 goto bad; 663 } 664 /* 665 * XXXX: Here is where we might unload the f/w module 666 * XXXX: (or decrease the reference count to it). 667 */ 668 ISP_UNLOCK(isp); 669 return (0); 670 671 bad: 672 673 if (pcs && pcs->ih) { 674 (void) bus_teardown_intr(dev, irq, pcs->ih); 675 } 676 677 #ifdef ISP_SMPLOCK 678 if (locksetup && isp) { 679 mtx_destroy(&isp->isp_osinfo.lock); 680 } 681 #endif 682 683 if (irq) { 684 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 685 } 686 687 688 if (regs) { 689 (void) bus_release_resource(dev, rtp, rgd, regs); 690 } 691 692 if (pcs) { 693 if (pcs->pci_isp.isp_param) 694 free(pcs->pci_isp.isp_param, M_DEVBUF); 695 free(pcs, M_DEVBUF); 696 } 697 698 /* 699 * XXXX: Here is where we might unload the f/w module 700 * XXXX: (or decrease the reference count to it). 701 */ 702 return (ENXIO); 703 } 704 705 static void 706 isp_pci_intr(void *arg) 707 { 708 struct ispsoftc *isp = arg; 709 ISP_LOCK(isp); 710 (void) isp_intr(isp); 711 ISP_UNLOCK(isp); 712 } 713 714 static u_int16_t 715 isp_pci_rd_reg(isp, regoff) 716 struct ispsoftc *isp; 717 int regoff; 718 { 719 u_int16_t rv; 720 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 721 int offset, oldconf = 0; 722 723 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 724 /* 725 * We will assume that someone has paused the RISC processor. 726 */ 727 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 728 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 729 } 730 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 731 offset += (regoff & 0xff); 732 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 733 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 734 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 735 } 736 return (rv); 737 } 738 739 static void 740 isp_pci_wr_reg(isp, regoff, val) 741 struct ispsoftc *isp; 742 int regoff; 743 u_int16_t val; 744 { 745 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 746 int offset, oldconf = 0; 747 748 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 749 /* 750 * We will assume that someone has paused the RISC processor. 751 */ 752 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 753 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 754 } 755 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 756 offset += (regoff & 0xff); 757 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 758 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 759 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 760 } 761 } 762 763 static u_int16_t 764 isp_pci_rd_reg_1080(isp, regoff) 765 struct ispsoftc *isp; 766 int regoff; 767 { 768 u_int16_t rv, oc = 0; 769 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 770 int offset; 771 772 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 773 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 774 u_int16_t tc; 775 /* 776 * We will assume that someone has paused the RISC processor. 777 */ 778 oc = isp_pci_rd_reg(isp, BIU_CONF1); 779 tc = oc & ~BIU_PCI1080_CONF1_DMA; 780 if (regoff & SXP_BANK1_SELECT) 781 tc |= BIU_PCI1080_CONF1_SXP1; 782 else 783 tc |= BIU_PCI1080_CONF1_SXP0; 784 isp_pci_wr_reg(isp, BIU_CONF1, tc); 785 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 786 oc = isp_pci_rd_reg(isp, BIU_CONF1); 787 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 788 } 789 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 790 offset += (regoff & 0xff); 791 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 792 if (oc) { 793 isp_pci_wr_reg(isp, BIU_CONF1, oc); 794 } 795 return (rv); 796 } 797 798 static void 799 isp_pci_wr_reg_1080(isp, regoff, val) 800 struct ispsoftc *isp; 801 int regoff; 802 u_int16_t val; 803 { 804 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 805 int offset, oc = 0; 806 807 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 808 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 809 u_int16_t tc; 810 /* 811 * We will assume that someone has paused the RISC processor. 812 */ 813 oc = isp_pci_rd_reg(isp, BIU_CONF1); 814 tc = oc & ~BIU_PCI1080_CONF1_DMA; 815 if (regoff & SXP_BANK1_SELECT) 816 tc |= BIU_PCI1080_CONF1_SXP1; 817 else 818 tc |= BIU_PCI1080_CONF1_SXP0; 819 isp_pci_wr_reg(isp, BIU_CONF1, tc); 820 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 821 oc = isp_pci_rd_reg(isp, BIU_CONF1); 822 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 823 } 824 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 825 offset += (regoff & 0xff); 826 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 827 if (oc) { 828 isp_pci_wr_reg(isp, BIU_CONF1, oc); 829 } 830 } 831 832 static void isp_map_rquest __P((void *, bus_dma_segment_t *, int, int)); 833 static void isp_map_result __P((void *, bus_dma_segment_t *, int, int)); 834 static void isp_map_fcscrt __P((void *, bus_dma_segment_t *, int, int)); 835 836 struct imush { 837 struct ispsoftc *isp; 838 int error; 839 }; 840 841 static void 842 isp_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) 843 { 844 struct imush *imushp = (struct imush *) arg; 845 if (error) { 846 imushp->error = error; 847 } else { 848 imushp->isp->isp_rquest_dma = segs->ds_addr; 849 } 850 } 851 852 static void 853 isp_map_result(void *arg, bus_dma_segment_t *segs, int nseg, int error) 854 { 855 struct imush *imushp = (struct imush *) arg; 856 if (error) { 857 imushp->error = error; 858 } else { 859 imushp->isp->isp_result_dma = segs->ds_addr; 860 } 861 } 862 863 static void 864 isp_map_fcscrt(void *arg, bus_dma_segment_t *segs, int nseg, int error) 865 { 866 struct imush *imushp = (struct imush *) arg; 867 if (error) { 868 imushp->error = error; 869 } else { 870 fcparam *fcp = imushp->isp->isp_param; 871 fcp->isp_scdma = segs->ds_addr; 872 } 873 } 874 875 static int 876 isp_pci_mbxdma(struct ispsoftc *isp) 877 { 878 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 879 caddr_t base; 880 u_int32_t len; 881 int i, error; 882 bus_size_t lim; 883 struct imush im; 884 885 886 /* 887 * Already been here? If so, leave... 888 */ 889 if (isp->isp_rquest) { 890 return (0); 891 } 892 893 len = sizeof (XS_T **) * isp->isp_maxcmds; 894 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 895 if (isp->isp_xflist == NULL) { 896 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 897 return (1); 898 } 899 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 900 pci->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 901 if (pci->dmaps == NULL) { 902 isp_prt(isp, ISP_LOGERR, "can't alloc dma maps"); 903 free(isp->isp_xflist, M_DEVBUF); 904 return (1); 905 } 906 907 if (IS_FC(isp) || IS_ULTRA2(isp)) 908 lim = BUS_SPACE_MAXADDR + 1; 909 else 910 lim = BUS_SPACE_MAXADDR_24BIT + 1; 911 912 /* 913 * Allocate and map the request, result queues, plus FC scratch area. 914 */ 915 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 916 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 917 if (IS_FC(isp)) { 918 len += ISP2100_SCRLEN; 919 } 920 if (bus_dma_tag_create(pci->parent_dmat, PAGE_SIZE, lim, 921 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, 922 BUS_SPACE_MAXSIZE_32BIT, 0, &pci->cntrol_dmat) != 0) { 923 isp_prt(isp, ISP_LOGERR, 924 "cannot create a dma tag for control spaces"); 925 free(isp->isp_xflist, M_DEVBUF); 926 free(pci->dmaps, M_DEVBUF); 927 return (1); 928 } 929 if (bus_dmamem_alloc(pci->cntrol_dmat, (void **)&base, 930 BUS_DMA_NOWAIT, &pci->cntrol_dmap) != 0) { 931 isp_prt(isp, ISP_LOGERR, 932 "cannot allocate %d bytes of CCB memory", len); 933 free(isp->isp_xflist, M_DEVBUF); 934 free(pci->dmaps, M_DEVBUF); 935 return (1); 936 } 937 938 isp->isp_rquest = base; 939 im.isp = isp; 940 im.error = 0; 941 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_rquest, 942 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)), isp_map_rquest, &im, 0); 943 if (im.error) { 944 isp_prt(isp, ISP_LOGERR, 945 "error %d loading dma map for DMA request queue", im.error); 946 free(isp->isp_xflist, M_DEVBUF); 947 free(pci->dmaps, M_DEVBUF); 948 isp->isp_rquest = NULL; 949 return (1); 950 } 951 isp->isp_result = base + ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 952 im.error = 0; 953 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_result, 954 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)), isp_map_result, &im, 0); 955 if (im.error) { 956 isp_prt(isp, ISP_LOGERR, 957 "error %d loading dma map for DMA result queue", im.error); 958 free(isp->isp_xflist, M_DEVBUF); 959 free(pci->dmaps, M_DEVBUF); 960 isp->isp_rquest = NULL; 961 return (1); 962 } 963 964 for (i = 0; i < isp->isp_maxcmds; i++) { 965 error = bus_dmamap_create(pci->parent_dmat, 0, &pci->dmaps[i]); 966 if (error) { 967 isp_prt(isp, ISP_LOGERR, 968 "error %d creating per-cmd DMA maps", error); 969 free(isp->isp_xflist, M_DEVBUF); 970 free(pci->dmaps, M_DEVBUF); 971 isp->isp_rquest = NULL; 972 return (1); 973 } 974 } 975 976 if (IS_FC(isp)) { 977 fcparam *fcp = (fcparam *) isp->isp_param; 978 fcp->isp_scratch = base + 979 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)) + 980 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 981 im.error = 0; 982 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, 983 fcp->isp_scratch, ISP2100_SCRLEN, isp_map_fcscrt, &im, 0); 984 if (im.error) { 985 isp_prt(isp, ISP_LOGERR, 986 "error %d loading FC scratch area", im.error); 987 free(isp->isp_xflist, M_DEVBUF); 988 free(pci->dmaps, M_DEVBUF); 989 isp->isp_rquest = NULL; 990 return (1); 991 } 992 } 993 return (0); 994 } 995 996 typedef struct { 997 struct ispsoftc *isp; 998 void *cmd_token; 999 void *rq; 1000 u_int16_t *iptrp; 1001 u_int16_t optr; 1002 u_int error; 1003 } mush_t; 1004 1005 #define MUSHERR_NOQENTRIES -2 1006 1007 #ifdef ISP_TARGET_MODE 1008 /* 1009 * We need to handle DMA for target mode differently from initiator mode. 1010 * 1011 * DMA mapping and construction and submission of CTIO Request Entries 1012 * and rendevous for completion are very tightly coupled because we start 1013 * out by knowing (per platform) how much data we have to move, but we 1014 * don't know, up front, how many DMA mapping segments will have to be used 1015 * cover that data, so we don't know how many CTIO Request Entries we 1016 * will end up using. Further, for performance reasons we may want to 1017 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1018 * 1019 * The standard vector still goes through isp_pci_dmasetup, but the callback 1020 * for the DMA mapping routines comes here instead with the whole transfer 1021 * mapped and a pointer to a partially filled in already allocated request 1022 * queue entry. We finish the job. 1023 */ 1024 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1025 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1026 1027 #define STATUS_WITH_DATA 1 1028 1029 static void 1030 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1031 { 1032 mush_t *mp; 1033 struct ccb_scsiio *csio; 1034 struct isp_pcisoftc *pci; 1035 bus_dmamap_t *dp; 1036 u_int8_t scsi_status; 1037 ct_entry_t *cto; 1038 u_int16_t handle; 1039 u_int32_t totxfr, sflags; 1040 int nctios, send_status; 1041 int32_t resid; 1042 int i, j; 1043 1044 mp = (mush_t *) arg; 1045 if (error) { 1046 mp->error = error; 1047 return; 1048 } 1049 csio = mp->cmd_token; 1050 cto = mp->rq; 1051 1052 cto->ct_xfrlen = 0; 1053 cto->ct_seg_count = 0; 1054 cto->ct_header.rqs_entry_count = 1; 1055 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1056 1057 if (nseg == 0) { 1058 cto->ct_header.rqs_seqno = 1; 1059 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1060 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1061 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1062 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1063 cto->ct_scsi_status, cto->ct_resid); 1064 ISP_TDQE(mp->isp, "tdma_mk[no data]", *mp->iptrp, cto); 1065 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1066 return; 1067 } 1068 1069 nctios = nseg / ISP_RQDSEG; 1070 if (nseg % ISP_RQDSEG) { 1071 nctios++; 1072 } 1073 1074 /* 1075 * Check to see that we don't overflow. 1076 */ 1077 for (i = 0, j = *mp->iptrp; i < nctios; i++) { 1078 j = ISP_NXT_QENTRY(j, RQUEST_QUEUE_LEN(isp)); 1079 if (j == mp->optr) { 1080 isp_prt(mp->isp, ISP_LOGWARN, 1081 "Request Queue Overflow [tdma_mk]"); 1082 mp->error = MUSHERR_NOQENTRIES; 1083 return; 1084 } 1085 } 1086 1087 /* 1088 * Save syshandle, and potentially any SCSI status, which we'll 1089 * reinsert on the last CTIO we're going to send. 1090 */ 1091 handle = cto->ct_syshandle; 1092 cto->ct_syshandle = 0; 1093 cto->ct_header.rqs_seqno = 0; 1094 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1095 1096 if (send_status) { 1097 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1098 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1099 /* 1100 * Preserve residual. 1101 */ 1102 resid = cto->ct_resid; 1103 1104 /* 1105 * Save actual SCSI status. 1106 */ 1107 scsi_status = cto->ct_scsi_status; 1108 1109 #ifndef STATUS_WITH_DATA 1110 sflags |= CT_NO_DATA; 1111 /* 1112 * We can't do a status at the same time as a data CTIO, so 1113 * we need to synthesize an extra CTIO at this level. 1114 */ 1115 nctios++; 1116 #endif 1117 } else { 1118 sflags = scsi_status = resid = 0; 1119 } 1120 1121 totxfr = cto->ct_resid = 0; 1122 cto->ct_scsi_status = 0; 1123 1124 pci = (struct isp_pcisoftc *)mp->isp; 1125 dp = &pci->dmaps[isp_handle_index(handle)]; 1126 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1127 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1128 } else { 1129 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1130 } 1131 1132 1133 while (nctios--) { 1134 int seglim; 1135 1136 seglim = nseg; 1137 if (seglim) { 1138 int seg; 1139 1140 if (seglim > ISP_RQDSEG) 1141 seglim = ISP_RQDSEG; 1142 1143 for (seg = 0; seg < seglim; seg++, nseg--) { 1144 /* 1145 * Unlike normal initiator commands, we don't 1146 * do any swizzling here. 1147 */ 1148 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1149 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1150 cto->ct_xfrlen += dm_segs->ds_len; 1151 totxfr += dm_segs->ds_len; 1152 dm_segs++; 1153 } 1154 cto->ct_seg_count = seg; 1155 } else { 1156 /* 1157 * This case should only happen when we're sending an 1158 * extra CTIO with final status. 1159 */ 1160 if (send_status == 0) { 1161 isp_prt(mp->isp, ISP_LOGWARN, 1162 "tdma_mk ran out of segments"); 1163 mp->error = EINVAL; 1164 return; 1165 } 1166 } 1167 1168 /* 1169 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1170 * ct_tagtype, and ct_timeout have been carried over 1171 * unchanged from what our caller had set. 1172 * 1173 * The dataseg fields and the seg_count fields we just got 1174 * through setting. The data direction we've preserved all 1175 * along and only clear it if we're now sending status. 1176 */ 1177 1178 if (nctios == 0) { 1179 /* 1180 * We're the last in a sequence of CTIOs, so mark 1181 * this CTIO and save the handle to the CCB such that 1182 * when this CTIO completes we can free dma resources 1183 * and do whatever else we need to do to finish the 1184 * rest of the command. We *don't* give this to the 1185 * firmware to work on- the caller will do that. 1186 */ 1187 cto->ct_syshandle = handle; 1188 cto->ct_header.rqs_seqno = 1; 1189 1190 if (send_status) { 1191 cto->ct_scsi_status = scsi_status; 1192 cto->ct_flags |= sflags; 1193 cto->ct_resid = resid; 1194 } 1195 if (send_status) { 1196 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1197 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 1198 "scsi status %x resid %d", 1199 cto->ct_fwhandle, csio->ccb_h.target_lun, 1200 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 1201 cto->ct_scsi_status, cto->ct_resid); 1202 } else { 1203 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1204 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 1205 cto->ct_fwhandle, csio->ccb_h.target_lun, 1206 cto->ct_iid, cto->ct_tag_val, 1207 cto->ct_flags); 1208 } 1209 ISP_TDQE(mp->isp, "last tdma_mk", *mp->iptrp, cto); 1210 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1211 } else { 1212 ct_entry_t *octo = cto; 1213 1214 /* 1215 * Make sure syshandle fields are clean 1216 */ 1217 cto->ct_syshandle = 0; 1218 cto->ct_header.rqs_seqno = 0; 1219 1220 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1221 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 1222 cto->ct_fwhandle, csio->ccb_h.target_lun, 1223 cto->ct_iid, cto->ct_flags); 1224 ISP_TDQE(mp->isp, "tdma_mk", *mp->iptrp, cto); 1225 1226 /* 1227 * Get a new CTIO 1228 */ 1229 cto = (ct_entry_t *) 1230 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1231 j = *mp->iptrp; 1232 *mp->iptrp = 1233 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1234 if (*mp->iptrp == mp->optr) { 1235 isp_prt(mp->isp, ISP_LOGTDEBUG0, 1236 "Queue Overflow in tdma_mk"); 1237 mp->error = MUSHERR_NOQENTRIES; 1238 return; 1239 } 1240 /* 1241 * Fill in the new CTIO with info from the old one. 1242 */ 1243 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1244 cto->ct_header.rqs_entry_count = 1; 1245 cto->ct_fwhandle = octo->ct_fwhandle; 1246 cto->ct_header.rqs_flags = 0; 1247 cto->ct_lun = octo->ct_lun; 1248 cto->ct_iid = octo->ct_iid; 1249 cto->ct_reserved2 = octo->ct_reserved2; 1250 cto->ct_tgt = octo->ct_tgt; 1251 cto->ct_flags = octo->ct_flags; 1252 cto->ct_status = 0; 1253 cto->ct_scsi_status = 0; 1254 cto->ct_tag_val = octo->ct_tag_val; 1255 cto->ct_tag_type = octo->ct_tag_type; 1256 cto->ct_xfrlen = 0; 1257 cto->ct_resid = 0; 1258 cto->ct_timeout = octo->ct_timeout; 1259 cto->ct_seg_count = 0; 1260 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1261 /* 1262 * Now swizzle the old one for the consumption 1263 * of the chip and give it to the firmware to 1264 * work on while we do the next. 1265 */ 1266 ISP_SWIZ_CTIO(mp->isp, octo, octo); 1267 ISP_ADD_REQUEST(mp->isp, j); 1268 } 1269 } 1270 } 1271 1272 static void 1273 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1274 { 1275 mush_t *mp; 1276 struct ccb_scsiio *csio; 1277 struct isp_pcisoftc *pci; 1278 bus_dmamap_t *dp; 1279 ct2_entry_t *cto; 1280 u_int16_t scsi_status, send_status, send_sense, handle; 1281 u_int32_t totxfr, datalen; 1282 u_int8_t sense[QLTM_SENSELEN]; 1283 int nctios; 1284 1285 mp = (mush_t *) arg; 1286 if (error) { 1287 mp->error = error; 1288 return; 1289 } 1290 1291 csio = mp->cmd_token; 1292 cto = mp->rq; 1293 1294 if (nseg == 0) { 1295 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1296 isp_prt(mp->isp, ISP_LOGWARN, 1297 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1298 "set (0x%x)", cto->ct_flags); 1299 mp->error = EINVAL; 1300 return; 1301 } 1302 cto->ct_header.rqs_entry_count = 1; 1303 cto->ct_header.rqs_seqno = 1; 1304 /* ct_syshandle contains the handle set by caller */ 1305 /* 1306 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1307 * flags to NO DATA and clear relative offset flags. 1308 * We preserve the ct_resid and the response area. 1309 */ 1310 cto->ct_flags |= CT2_NO_DATA; 1311 if (cto->ct_resid > 0) 1312 cto->ct_flags |= CT2_DATA_UNDER; 1313 else if (cto->ct_resid < 0) 1314 cto->ct_flags |= CT2_DATA_OVER; 1315 cto->ct_seg_count = 0; 1316 cto->ct_reloff = 0; 1317 ISP_TDQE(mp->isp, "dma2_tgt_fc[no data]", *mp->iptrp, cto); 1318 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1319 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1320 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1321 cto->ct_iid, cto->ct_flags, cto->ct_status, 1322 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1323 ISP_SWIZ_CTIO2(isp, cto, cto); 1324 return; 1325 } 1326 1327 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1328 isp_prt(mp->isp, ISP_LOGWARN, 1329 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1330 "(0x%x)", cto->ct_flags); 1331 mp->error = EINVAL; 1332 return; 1333 } 1334 1335 1336 nctios = nseg / ISP_RQDSEG_T2; 1337 if (nseg % ISP_RQDSEG_T2) { 1338 nctios++; 1339 } 1340 1341 /* 1342 * Save the handle, status, reloff, and residual. We'll reinsert the 1343 * handle into the last CTIO2 we're going to send, and reinsert status 1344 * and residual (and possibly sense data) if that's to be sent as well. 1345 * 1346 * We preserve ct_reloff and adjust it for each data CTIO2 we send past 1347 * the first one. This is needed so that the FCP DATA IUs being sent 1348 * out have the correct offset (they can arrive at the other end out 1349 * of order). 1350 */ 1351 1352 handle = cto->ct_syshandle; 1353 cto->ct_syshandle = 0; 1354 1355 if ((send_status = (cto->ct_flags & CT2_SENDSTATUS)) != 0) { 1356 cto->ct_flags &= ~CT2_SENDSTATUS; 1357 1358 /* 1359 * Preserve residual, which is actually the total count. 1360 */ 1361 datalen = cto->ct_resid; 1362 1363 /* 1364 * Save actual SCSI status. We'll reinsert the 1365 * CT2_SNSLEN_VALID later if appropriate. 1366 */ 1367 scsi_status = cto->rsp.m0.ct_scsi_status & 0xff; 1368 send_sense = cto->rsp.m0.ct_scsi_status & CT2_SNSLEN_VALID; 1369 1370 /* 1371 * If we're sending status and have a CHECK CONDTION and 1372 * have sense data, we send one more CTIO2 with just the 1373 * status and sense data. The upper layers have stashed 1374 * the sense data in the dataseg structure for us. 1375 */ 1376 1377 if ((scsi_status & 0xf) == SCSI_STATUS_CHECK_COND && 1378 send_sense) { 1379 bcopy(cto->rsp.m0.ct_dataseg, sense, QLTM_SENSELEN); 1380 nctios++; 1381 } 1382 } else { 1383 scsi_status = send_sense = datalen = 0; 1384 } 1385 1386 totxfr = cto->ct_resid = 0; 1387 cto->rsp.m0.ct_scsi_status = 0; 1388 bzero(&cto->rsp, sizeof (cto->rsp)); 1389 1390 pci = (struct isp_pcisoftc *)mp->isp; 1391 dp = &pci->dmaps[isp_handle_index(handle)]; 1392 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1393 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1394 } else { 1395 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1396 } 1397 1398 while (nctios--) { 1399 int seg, seglim; 1400 1401 seglim = nseg; 1402 if (seglim) { 1403 if (seglim > ISP_RQDSEG_T2) 1404 seglim = ISP_RQDSEG_T2; 1405 1406 for (seg = 0; seg < seglim; seg++) { 1407 cto->rsp.m0.ct_dataseg[seg].ds_base = 1408 dm_segs->ds_addr; 1409 cto->rsp.m0.ct_dataseg[seg].ds_count = 1410 dm_segs->ds_len; 1411 cto->rsp.m0.ct_xfrlen += dm_segs->ds_len; 1412 totxfr += dm_segs->ds_len; 1413 dm_segs++; 1414 } 1415 cto->ct_seg_count = seg; 1416 } else { 1417 /* 1418 * This case should only happen when we're sending a 1419 * synthesized MODE1 final status with sense data. 1420 */ 1421 if (send_sense == 0) { 1422 isp_prt(mp->isp, ISP_LOGWARN, 1423 "dma2_tgt_fc ran out of segments, " 1424 "no SENSE DATA"); 1425 mp->error = EINVAL; 1426 return; 1427 } 1428 } 1429 1430 /* 1431 * At this point, the fields ct_lun, ct_iid, ct_rxid, 1432 * ct_timeout have been carried over unchanged from what 1433 * our caller had set. 1434 * 1435 * The field ct_reloff is either what the caller set, or 1436 * what we've added to below. 1437 * 1438 * The dataseg fields and the seg_count fields we just got 1439 * through setting. The data direction we've preserved all 1440 * along and only clear it if we're sending a MODE1 status 1441 * as the last CTIO. 1442 * 1443 */ 1444 1445 if (nctios == 0) { 1446 1447 /* 1448 * We're the last in a sequence of CTIO2s, so mark this 1449 * CTIO2 and save the handle to the CCB such that when 1450 * this CTIO2 completes we can free dma resources and 1451 * do whatever else we need to do to finish the rest 1452 * of the command. 1453 */ 1454 1455 cto->ct_syshandle = handle; 1456 cto->ct_header.rqs_seqno = 1; 1457 1458 if (send_status) { 1459 if (send_sense) { 1460 bcopy(sense, cto->rsp.m1.ct_resp, 1461 QLTM_SENSELEN); 1462 cto->rsp.m1.ct_senselen = 1463 QLTM_SENSELEN; 1464 scsi_status |= CT2_SNSLEN_VALID; 1465 cto->rsp.m1.ct_scsi_status = 1466 scsi_status; 1467 cto->ct_flags &= CT2_FLAG_MMASK; 1468 cto->ct_flags |= CT2_FLAG_MODE1 | 1469 CT2_NO_DATA| CT2_SENDSTATUS; 1470 } else { 1471 cto->rsp.m0.ct_scsi_status = 1472 scsi_status; 1473 cto->ct_flags |= CT2_SENDSTATUS; 1474 } 1475 /* 1476 * Get 'real' residual and set flags based 1477 * on it. 1478 */ 1479 cto->ct_resid = datalen - totxfr; 1480 if (cto->ct_resid > 0) 1481 cto->ct_flags |= CT2_DATA_UNDER; 1482 else if (cto->ct_resid < 0) 1483 cto->ct_flags |= CT2_DATA_OVER; 1484 } 1485 ISP_TDQE(mp->isp, "last dma2_tgt_fc", *mp->iptrp, cto); 1486 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1487 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x" 1488 " ssts 0x%x res %d", cto->ct_rxid, 1489 csio->ccb_h.target_lun, (int) cto->ct_iid, 1490 cto->ct_flags, cto->ct_status, 1491 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1492 ISP_SWIZ_CTIO2(isp, cto, cto); 1493 } else { 1494 ct2_entry_t *octo = cto; 1495 1496 /* 1497 * Make sure handle fields are clean 1498 */ 1499 cto->ct_syshandle = 0; 1500 cto->ct_header.rqs_seqno = 0; 1501 1502 ISP_TDQE(mp->isp, "dma2_tgt_fc", *mp->iptrp, cto); 1503 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1504 "CTIO2[%x] lun %d->iid%d flgs 0x%x", 1505 cto->ct_rxid, csio->ccb_h.target_lun, 1506 (int) cto->ct_iid, cto->ct_flags); 1507 /* 1508 * Get a new CTIO2 1509 */ 1510 cto = (ct2_entry_t *) 1511 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1512 *mp->iptrp = 1513 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1514 if (*mp->iptrp == mp->optr) { 1515 isp_prt(mp->isp, ISP_LOGWARN, 1516 "Queue Overflow in dma2_tgt_fc"); 1517 mp->error = MUSHERR_NOQENTRIES; 1518 return; 1519 } 1520 1521 /* 1522 * Fill in the new CTIO2 with info from the old one. 1523 */ 1524 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO2; 1525 cto->ct_header.rqs_entry_count = 1; 1526 cto->ct_header.rqs_flags = 0; 1527 /* ct_header.rqs_seqno && ct_syshandle done later */ 1528 cto->ct_fwhandle = octo->ct_fwhandle; 1529 cto->ct_lun = octo->ct_lun; 1530 cto->ct_iid = octo->ct_iid; 1531 cto->ct_rxid = octo->ct_rxid; 1532 cto->ct_flags = octo->ct_flags; 1533 cto->ct_status = 0; 1534 cto->ct_resid = 0; 1535 cto->ct_timeout = octo->ct_timeout; 1536 cto->ct_seg_count = 0; 1537 /* 1538 * Adjust the new relative offset by the amount which 1539 * is recorded in the data segment of the old CTIO2 we 1540 * just finished filling out. 1541 */ 1542 cto->ct_reloff += octo->rsp.m0.ct_xfrlen; 1543 bzero(&cto->rsp, sizeof (cto->rsp)); 1544 ISP_SWIZ_CTIO2(isp, cto, cto); 1545 } 1546 } 1547 } 1548 #endif 1549 1550 static void dma2 __P((void *, bus_dma_segment_t *, int, int)); 1551 1552 static void 1553 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1554 { 1555 mush_t *mp; 1556 struct ccb_scsiio *csio; 1557 struct isp_pcisoftc *pci; 1558 bus_dmamap_t *dp; 1559 bus_dma_segment_t *eseg; 1560 ispreq_t *rq; 1561 ispcontreq_t *crq; 1562 int seglim, datalen; 1563 1564 mp = (mush_t *) arg; 1565 if (error) { 1566 mp->error = error; 1567 return; 1568 } 1569 1570 if (nseg < 1) { 1571 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1572 mp->error = EFAULT; 1573 return; 1574 } 1575 csio = mp->cmd_token; 1576 rq = mp->rq; 1577 pci = (struct isp_pcisoftc *)mp->isp; 1578 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1579 1580 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1581 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1582 } else { 1583 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1584 } 1585 1586 datalen = XS_XFRLEN(csio); 1587 1588 /* 1589 * We're passed an initial partially filled in entry that 1590 * has most fields filled in except for data transfer 1591 * related values. 1592 * 1593 * Our job is to fill in the initial request queue entry and 1594 * then to start allocating and filling in continuation entries 1595 * until we've covered the entire transfer. 1596 */ 1597 1598 if (IS_FC(mp->isp)) { 1599 seglim = ISP_RQDSEG_T2; 1600 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1601 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1602 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1603 } else { 1604 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1605 } 1606 } else { 1607 if (csio->cdb_len > 12) { 1608 seglim = 0; 1609 } else { 1610 seglim = ISP_RQDSEG; 1611 } 1612 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1613 rq->req_flags |= REQFLAG_DATA_IN; 1614 } else { 1615 rq->req_flags |= REQFLAG_DATA_OUT; 1616 } 1617 } 1618 1619 eseg = dm_segs + nseg; 1620 1621 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1622 if (IS_FC(mp->isp)) { 1623 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1624 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1625 dm_segs->ds_addr; 1626 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1627 dm_segs->ds_len; 1628 } else { 1629 rq->req_dataseg[rq->req_seg_count].ds_base = 1630 dm_segs->ds_addr; 1631 rq->req_dataseg[rq->req_seg_count].ds_count = 1632 dm_segs->ds_len; 1633 } 1634 datalen -= dm_segs->ds_len; 1635 #if 0 1636 if (IS_FC(mp->isp)) { 1637 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1638 device_printf(mp->isp->isp_dev, 1639 "seg0[%d] cnt 0x%x paddr 0x%08x\n", 1640 rq->req_seg_count, 1641 rq2->req_dataseg[rq2->req_seg_count].ds_count, 1642 rq2->req_dataseg[rq2->req_seg_count].ds_base); 1643 } else { 1644 device_printf(mp->isp->isp_dev, 1645 "seg0[%d] cnt 0x%x paddr 0x%08x\n", 1646 rq->req_seg_count, 1647 rq->req_dataseg[rq->req_seg_count].ds_count, 1648 rq->req_dataseg[rq->req_seg_count].ds_base); 1649 } 1650 #endif 1651 rq->req_seg_count++; 1652 dm_segs++; 1653 } 1654 1655 while (datalen > 0 && dm_segs != eseg) { 1656 crq = (ispcontreq_t *) 1657 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1658 *mp->iptrp = ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1659 if (*mp->iptrp == mp->optr) { 1660 isp_prt(mp->isp, 1661 ISP_LOGDEBUG0, "Request Queue Overflow++"); 1662 mp->error = MUSHERR_NOQENTRIES; 1663 return; 1664 } 1665 rq->req_header.rqs_entry_count++; 1666 bzero((void *)crq, sizeof (*crq)); 1667 crq->req_header.rqs_entry_count = 1; 1668 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1669 1670 seglim = 0; 1671 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1672 crq->req_dataseg[seglim].ds_base = 1673 dm_segs->ds_addr; 1674 crq->req_dataseg[seglim].ds_count = 1675 dm_segs->ds_len; 1676 #if 0 1677 device_printf(mp->isp->isp_dev, 1678 "seg%d[%d] cnt 0x%x paddr 0x%08x\n", 1679 rq->req_header.rqs_entry_count-1, 1680 seglim, crq->req_dataseg[seglim].ds_count, 1681 crq->req_dataseg[seglim].ds_base); 1682 #endif 1683 rq->req_seg_count++; 1684 dm_segs++; 1685 seglim++; 1686 datalen -= dm_segs->ds_len; 1687 } 1688 } 1689 } 1690 1691 static int 1692 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1693 u_int16_t *iptrp, u_int16_t optr) 1694 { 1695 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1696 bus_dmamap_t *dp = NULL; 1697 mush_t mush, *mp; 1698 void (*eptr) __P((void *, bus_dma_segment_t *, int, int)); 1699 1700 #ifdef ISP_TARGET_MODE 1701 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1702 if (IS_FC(isp)) { 1703 eptr = tdma_mkfc; 1704 } else { 1705 eptr = tdma_mk; 1706 } 1707 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1708 (csio->dxfer_len == 0)) { 1709 mp = &mush; 1710 mp->isp = isp; 1711 mp->cmd_token = csio; 1712 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 1713 mp->iptrp = iptrp; 1714 mp->optr = optr; 1715 mp->error = 0; 1716 (*eptr)(mp, NULL, 0, 0); 1717 goto exit; 1718 } 1719 } else 1720 #endif 1721 eptr = dma2; 1722 1723 /* 1724 * NB: if we need to do request queue entry swizzling, 1725 * NB: this is where it would need to be done for cmds 1726 * NB: that move no data. For commands that move data, 1727 * NB: swizzling would take place in those functions. 1728 */ 1729 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1730 (csio->dxfer_len == 0)) { 1731 rq->req_seg_count = 1; 1732 return (CMD_QUEUED); 1733 } 1734 1735 /* 1736 * Do a virtual grapevine step to collect info for 1737 * the callback dma allocation that we have to use... 1738 */ 1739 mp = &mush; 1740 mp->isp = isp; 1741 mp->cmd_token = csio; 1742 mp->rq = rq; 1743 mp->iptrp = iptrp; 1744 mp->optr = optr; 1745 mp->error = 0; 1746 1747 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1748 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1749 int error, s; 1750 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1751 s = splsoftvm(); 1752 error = bus_dmamap_load(pci->parent_dmat, *dp, 1753 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1754 if (error == EINPROGRESS) { 1755 bus_dmamap_unload(pci->parent_dmat, *dp); 1756 mp->error = EINVAL; 1757 isp_prt(isp, ISP_LOGERR, 1758 "deferred dma allocation not supported"); 1759 } else if (error && mp->error == 0) { 1760 #ifdef DIAGNOSTIC 1761 isp_prt(isp, ISP_LOGERR, 1762 "error %d in dma mapping code", error); 1763 #endif 1764 mp->error = error; 1765 } 1766 splx(s); 1767 } else { 1768 /* Pointer to physical buffer */ 1769 struct bus_dma_segment seg; 1770 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1771 seg.ds_len = csio->dxfer_len; 1772 (*eptr)(mp, &seg, 1, 0); 1773 } 1774 } else { 1775 struct bus_dma_segment *segs; 1776 1777 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1778 isp_prt(isp, ISP_LOGERR, 1779 "Physical segment pointers unsupported"); 1780 mp->error = EINVAL; 1781 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1782 isp_prt(isp, ISP_LOGERR, 1783 "Virtual segment addresses unsupported"); 1784 mp->error = EINVAL; 1785 } else { 1786 /* Just use the segments provided */ 1787 segs = (struct bus_dma_segment *) csio->data_ptr; 1788 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1789 } 1790 } 1791 #ifdef ISP_TARGET_MODE 1792 exit: 1793 #endif 1794 if (mp->error) { 1795 int retval = CMD_COMPLETE; 1796 if (mp->error == MUSHERR_NOQENTRIES) { 1797 retval = CMD_EAGAIN; 1798 } else if (mp->error == EFBIG) { 1799 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1800 } else if (mp->error == EINVAL) { 1801 XS_SETERR(csio, CAM_REQ_INVALID); 1802 } else { 1803 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1804 } 1805 return (retval); 1806 } else { 1807 /* 1808 * Check to see if we weren't cancelled while sleeping on 1809 * getting DMA resources... 1810 */ 1811 if ((csio->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 1812 if (dp) { 1813 bus_dmamap_unload(pci->parent_dmat, *dp); 1814 } 1815 return (CMD_COMPLETE); 1816 } 1817 return (CMD_QUEUED); 1818 } 1819 } 1820 1821 static void 1822 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1823 { 1824 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1825 bus_dmamap_t *dp = &pci->dmaps[isp_handle_index(handle)]; 1826 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1827 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTREAD); 1828 } else { 1829 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTWRITE); 1830 } 1831 bus_dmamap_unload(pci->parent_dmat, *dp); 1832 } 1833 1834 1835 static void 1836 isp_pci_reset1(struct ispsoftc *isp) 1837 { 1838 /* Make sure the BIOS is disabled */ 1839 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1840 /* and enable interrupts */ 1841 ENABLE_INTS(isp); 1842 } 1843 1844 static void 1845 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1846 { 1847 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1848 if (msg) 1849 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1850 else 1851 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1852 if (IS_SCSI(isp)) 1853 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1854 else 1855 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1856 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1857 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1858 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1859 1860 1861 if (IS_SCSI(isp)) { 1862 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1863 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1864 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1865 ISP_READ(isp, CDMA_FIFO_STS)); 1866 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1867 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1868 ISP_READ(isp, DDMA_FIFO_STS)); 1869 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1870 ISP_READ(isp, SXP_INTERRUPT), 1871 ISP_READ(isp, SXP_GROSS_ERR), 1872 ISP_READ(isp, SXP_PINS_CTRL)); 1873 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1874 } 1875 printf(" mbox regs: %x %x %x %x %x\n", 1876 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1877 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1878 ISP_READ(isp, OUTMAILBOX4)); 1879 printf(" PCI Status Command/Status=%x\n", 1880 pci_read_config(pci->pci_dev, PCIR_COMMAND, 1)); 1881 } 1882