1 /* $FreeBSD$ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * FreeBSD Version. 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 36 #include <pci/pcireg.h> 37 #include <pci/pcivar.h> 38 39 #include <machine/bus_memio.h> 40 #include <machine/bus_pio.h> 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 46 #include <dev/isp/isp_freebsd.h> 47 48 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int)); 49 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t)); 50 static u_int16_t isp_pci_rd_reg_1080 __P((struct ispsoftc *, int)); 51 static void isp_pci_wr_reg_1080 __P((struct ispsoftc *, int, u_int16_t)); 52 static int isp_pci_mbxdma __P((struct ispsoftc *)); 53 static int isp_pci_dmasetup __P((struct ispsoftc *, XS_T *, 54 ispreq_t *, u_int16_t *, u_int16_t)); 55 static void 56 isp_pci_dmateardown __P((struct ispsoftc *, XS_T *, u_int32_t)); 57 58 static void isp_pci_reset1 __P((struct ispsoftc *)); 59 static void isp_pci_dumpregs __P((struct ispsoftc *, const char *)); 60 61 #ifndef ISP_CODE_ORG 62 #define ISP_CODE_ORG 0x1000 63 #endif 64 65 static struct ispmdvec mdvec = { 66 isp_pci_rd_reg, 67 isp_pci_wr_reg, 68 isp_pci_mbxdma, 69 isp_pci_dmasetup, 70 isp_pci_dmateardown, 71 NULL, 72 isp_pci_reset1, 73 isp_pci_dumpregs, 74 NULL, 75 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 76 }; 77 78 static struct ispmdvec mdvec_1080 = { 79 isp_pci_rd_reg_1080, 80 isp_pci_wr_reg_1080, 81 isp_pci_mbxdma, 82 isp_pci_dmasetup, 83 isp_pci_dmateardown, 84 NULL, 85 isp_pci_reset1, 86 isp_pci_dumpregs, 87 NULL, 88 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 89 }; 90 91 static struct ispmdvec mdvec_12160 = { 92 isp_pci_rd_reg_1080, 93 isp_pci_wr_reg_1080, 94 isp_pci_mbxdma, 95 isp_pci_dmasetup, 96 isp_pci_dmateardown, 97 NULL, 98 isp_pci_reset1, 99 isp_pci_dumpregs, 100 NULL, 101 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 102 }; 103 104 static struct ispmdvec mdvec_2100 = { 105 isp_pci_rd_reg, 106 isp_pci_wr_reg, 107 isp_pci_mbxdma, 108 isp_pci_dmasetup, 109 isp_pci_dmateardown, 110 NULL, 111 isp_pci_reset1, 112 isp_pci_dumpregs 113 }; 114 115 static struct ispmdvec mdvec_2200 = { 116 isp_pci_rd_reg, 117 isp_pci_wr_reg, 118 isp_pci_mbxdma, 119 isp_pci_dmasetup, 120 isp_pci_dmateardown, 121 NULL, 122 isp_pci_reset1, 123 isp_pci_dumpregs 124 }; 125 126 #ifndef PCIM_CMD_INVEN 127 #define PCIM_CMD_INVEN 0x10 128 #endif 129 #ifndef PCIM_CMD_BUSMASTEREN 130 #define PCIM_CMD_BUSMASTEREN 0x0004 131 #endif 132 #ifndef PCIM_CMD_PERRESPEN 133 #define PCIM_CMD_PERRESPEN 0x0040 134 #endif 135 #ifndef PCIM_CMD_SEREN 136 #define PCIM_CMD_SEREN 0x0100 137 #endif 138 139 #ifndef PCIR_COMMAND 140 #define PCIR_COMMAND 0x04 141 #endif 142 143 #ifndef PCIR_CACHELNSZ 144 #define PCIR_CACHELNSZ 0x0c 145 #endif 146 147 #ifndef PCIR_LATTIMER 148 #define PCIR_LATTIMER 0x0d 149 #endif 150 151 #ifndef PCIR_ROMADDR 152 #define PCIR_ROMADDR 0x30 153 #endif 154 155 #ifndef PCI_VENDOR_QLOGIC 156 #define PCI_VENDOR_QLOGIC 0x1077 157 #endif 158 159 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 160 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 161 #endif 162 163 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 164 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 165 #endif 166 167 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 168 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 169 #endif 170 171 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 172 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 173 #endif 174 175 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 176 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 177 #endif 178 179 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 180 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 181 #endif 182 183 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 184 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 185 #endif 186 187 #define PCI_QLOGIC_ISP1020 \ 188 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 189 190 #define PCI_QLOGIC_ISP1080 \ 191 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 192 193 #define PCI_QLOGIC_ISP12160 \ 194 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 195 196 #define PCI_QLOGIC_ISP1240 \ 197 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 198 199 #define PCI_QLOGIC_ISP1280 \ 200 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 201 202 #define PCI_QLOGIC_ISP2100 \ 203 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 204 205 #define PCI_QLOGIC_ISP2200 \ 206 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 207 208 /* 209 * Odd case for some AMI raid cards... We need to *not* attach to this. 210 */ 211 #define AMI_RAID_SUBVENDOR_ID 0x101e 212 213 #define IO_MAP_REG 0x10 214 #define MEM_MAP_REG 0x14 215 216 #define PCI_DFLT_LTNCY 0x40 217 #define PCI_DFLT_LNSZ 0x10 218 219 static int isp_pci_probe (device_t); 220 static int isp_pci_attach (device_t); 221 222 struct isp_pcisoftc { 223 struct ispsoftc pci_isp; 224 device_t pci_dev; 225 struct resource * pci_reg; 226 bus_space_tag_t pci_st; 227 bus_space_handle_t pci_sh; 228 void * ih; 229 int16_t pci_poff[_NREG_BLKS]; 230 bus_dma_tag_t parent_dmat; 231 bus_dma_tag_t cntrol_dmat; 232 bus_dmamap_t cntrol_dmap; 233 bus_dmamap_t *dmaps; 234 }; 235 ispfwfunc *isp_get_firmware_p = NULL; 236 237 static device_method_t isp_pci_methods[] = { 238 /* Device interface */ 239 DEVMETHOD(device_probe, isp_pci_probe), 240 DEVMETHOD(device_attach, isp_pci_attach), 241 { 0, 0 } 242 }; 243 static void isp_pci_intr __P((void *)); 244 245 static driver_t isp_pci_driver = { 246 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 247 }; 248 static devclass_t isp_devclass; 249 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 250 MODULE_VERSION(isp, 1); 251 252 static int 253 isp_pci_probe(device_t dev) 254 { 255 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 256 case PCI_QLOGIC_ISP1020: 257 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 258 break; 259 case PCI_QLOGIC_ISP1080: 260 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 261 break; 262 case PCI_QLOGIC_ISP1240: 263 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 264 break; 265 case PCI_QLOGIC_ISP1280: 266 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 267 break; 268 case PCI_QLOGIC_ISP12160: 269 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 270 return (ENXIO); 271 } 272 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 273 break; 274 case PCI_QLOGIC_ISP2100: 275 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 276 break; 277 case PCI_QLOGIC_ISP2200: 278 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 279 break; 280 default: 281 return (ENXIO); 282 } 283 if (device_get_unit(dev) == 0 && bootverbose) { 284 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 285 "Core Version %d.%d\n", 286 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 287 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 288 } 289 /* 290 * XXXX: Here is where we might load the f/w module 291 * XXXX: (or increase a reference count to it). 292 */ 293 return (0); 294 } 295 296 static int 297 isp_pci_attach(device_t dev) 298 { 299 struct resource *regs, *irq; 300 int unit, bitmap, rtp, rgd, iqd, m1, m2, isp_debug; 301 u_int32_t data, cmd, linesz, psize, basetype; 302 struct isp_pcisoftc *pcs; 303 struct ispsoftc *isp = NULL; 304 struct ispmdvec *mdvp; 305 bus_size_t lim; 306 #ifdef ISP_SMPLOCK 307 int locksetup = 0; 308 #endif 309 310 /* 311 * Figure out if we're supposed to skip this one. 312 */ 313 unit = device_get_unit(dev); 314 if (getenv_int("isp_disable", &bitmap)) { 315 if (bitmap & (1 << unit)) { 316 device_printf(dev, "not configuring\n"); 317 return (ENODEV); 318 } 319 } 320 321 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT | M_ZERO); 322 if (pcs == NULL) { 323 device_printf(dev, "cannot allocate softc\n"); 324 return (ENOMEM); 325 } 326 327 /* 328 * Figure out which we should try first - memory mapping or i/o mapping? 329 */ 330 #ifdef __alpha__ 331 m1 = PCIM_CMD_MEMEN; 332 m2 = PCIM_CMD_PORTEN; 333 #else 334 m1 = PCIM_CMD_PORTEN; 335 m2 = PCIM_CMD_MEMEN; 336 #endif 337 bitmap = 0; 338 if (getenv_int("isp_mem_map", &bitmap)) { 339 if (bitmap & (1 << unit)) { 340 m1 = PCIM_CMD_MEMEN; 341 m2 = PCIM_CMD_PORTEN; 342 } 343 } 344 bitmap = 0; 345 if (getenv_int("isp_io_map", &bitmap)) { 346 if (bitmap & (1 << unit)) { 347 m1 = PCIM_CMD_PORTEN; 348 m2 = PCIM_CMD_MEMEN; 349 } 350 } 351 352 linesz = PCI_DFLT_LNSZ; 353 irq = regs = NULL; 354 rgd = rtp = iqd = 0; 355 356 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 357 if (cmd & m1) { 358 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 359 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 360 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 361 } 362 if (regs == NULL && (cmd & m2)) { 363 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 364 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 365 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 366 } 367 if (regs == NULL) { 368 device_printf(dev, "unable to map any ports\n"); 369 goto bad; 370 } 371 if (bootverbose) 372 device_printf(dev, "using %s space register mapping\n", 373 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 374 pcs->pci_dev = dev; 375 pcs->pci_reg = regs; 376 pcs->pci_st = rman_get_bustag(regs); 377 pcs->pci_sh = rman_get_bushandle(regs); 378 379 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 380 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 381 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 382 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 383 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 384 mdvp = &mdvec; 385 basetype = ISP_HA_SCSI_UNKNOWN; 386 psize = sizeof (sdparam); 387 lim = BUS_SPACE_MAXSIZE_32BIT; 388 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 389 mdvp = &mdvec; 390 basetype = ISP_HA_SCSI_UNKNOWN; 391 psize = sizeof (sdparam); 392 lim = BUS_SPACE_MAXSIZE_24BIT; 393 } 394 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 395 mdvp = &mdvec_1080; 396 basetype = ISP_HA_SCSI_1080; 397 psize = sizeof (sdparam); 398 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 399 ISP1080_DMA_REGS_OFF; 400 } 401 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 402 mdvp = &mdvec_1080; 403 basetype = ISP_HA_SCSI_1240; 404 psize = 2 * sizeof (sdparam); 405 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 406 ISP1080_DMA_REGS_OFF; 407 } 408 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 409 mdvp = &mdvec_1080; 410 basetype = ISP_HA_SCSI_1280; 411 psize = 2 * sizeof (sdparam); 412 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 413 ISP1080_DMA_REGS_OFF; 414 } 415 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 416 mdvp = &mdvec_12160; 417 basetype = ISP_HA_SCSI_12160; 418 psize = 2 * sizeof (sdparam); 419 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 420 ISP1080_DMA_REGS_OFF; 421 } 422 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 423 mdvp = &mdvec_2100; 424 basetype = ISP_HA_FC_2100; 425 psize = sizeof (fcparam); 426 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 427 PCI_MBOX_REGS2100_OFF; 428 if (pci_get_revid(dev) < 3) { 429 /* 430 * XXX: Need to get the actual revision 431 * XXX: number of the 2100 FB. At any rate, 432 * XXX: lower cache line size for early revision 433 * XXX; boards. 434 */ 435 linesz = 1; 436 } 437 } 438 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 439 mdvp = &mdvec_2200; 440 basetype = ISP_HA_FC_2200; 441 psize = sizeof (fcparam); 442 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 443 PCI_MBOX_REGS2100_OFF; 444 } 445 isp = &pcs->pci_isp; 446 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 447 if (isp->isp_param == NULL) { 448 device_printf(dev, "cannot allocate parameter data\n"); 449 goto bad; 450 } 451 isp->isp_mdvec = mdvp; 452 isp->isp_type = basetype; 453 isp->isp_revision = pci_get_revid(dev); 454 (void) snprintf(isp->isp_name, sizeof (isp->isp_name), "isp%d", unit); 455 isp->isp_osinfo.unit = unit; 456 457 /* 458 * Try and find firmware for this device. 459 */ 460 461 if (isp_get_firmware_p) { 462 int device = (int) pci_get_device(dev); 463 #ifdef ISP_TARGET_MODE 464 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 465 #else 466 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 467 #endif 468 } 469 470 /* 471 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 472 * are set. 473 */ 474 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 475 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 476 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 477 478 /* 479 * Make sure the Cache Line Size register is set sensibly. 480 */ 481 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 482 if (data != linesz) { 483 data = PCI_DFLT_LNSZ; 484 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 485 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 486 } 487 488 /* 489 * Make sure the Latency Timer is sane. 490 */ 491 data = pci_read_config(dev, PCIR_LATTIMER, 1); 492 if (data < PCI_DFLT_LTNCY) { 493 data = PCI_DFLT_LTNCY; 494 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 495 pci_write_config(dev, PCIR_LATTIMER, data, 1); 496 } 497 498 /* 499 * Make sure we've disabled the ROM. 500 */ 501 data = pci_read_config(dev, PCIR_ROMADDR, 4); 502 data &= ~1; 503 pci_write_config(dev, PCIR_ROMADDR, data, 4); 504 505 506 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 507 BUS_SPACE_MAXADDR, NULL, NULL, lim + 1, 508 255, lim, 0, &pcs->parent_dmat) != 0) { 509 device_printf(dev, "could not create master dma tag\n"); 510 free(isp->isp_param, M_DEVBUF); 511 free(pcs, M_DEVBUF); 512 return (ENXIO); 513 } 514 515 iqd = 0; 516 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 517 1, RF_ACTIVE | RF_SHAREABLE); 518 if (irq == NULL) { 519 device_printf(dev, "could not allocate interrupt\n"); 520 goto bad; 521 } 522 523 if (getenv_int("isp_no_fwload", &bitmap)) { 524 if (bitmap & (1 << unit)) 525 isp->isp_confopts |= ISP_CFG_NORELOAD; 526 } 527 if (getenv_int("isp_fwload", &bitmap)) { 528 if (bitmap & (1 << unit)) 529 isp->isp_confopts &= ~ISP_CFG_NORELOAD; 530 } 531 if (getenv_int("isp_no_nvram", &bitmap)) { 532 if (bitmap & (1 << unit)) 533 isp->isp_confopts |= ISP_CFG_NONVRAM; 534 } 535 if (getenv_int("isp_nvram", &bitmap)) { 536 if (bitmap & (1 << unit)) 537 isp->isp_confopts &= ~ISP_CFG_NONVRAM; 538 } 539 if (getenv_int("isp_fcduplex", &bitmap)) { 540 if (bitmap & (1 << unit)) 541 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 542 } 543 if (getenv_int("isp_no_fcduplex", &bitmap)) { 544 if (bitmap & (1 << unit)) 545 isp->isp_confopts &= ~ISP_CFG_FULL_DUPLEX; 546 } 547 if (getenv_int("isp_nport", &bitmap)) { 548 if (bitmap & (1 << unit)) 549 isp->isp_confopts |= ISP_CFG_NPORT; 550 } 551 /* 552 * Look for overriding WWN. This is a Node WWN so it binds to 553 * all FC instances. A Port WWN will be constructed from it 554 * as appropriate. 555 */ 556 if (!getenv_quad("isp_wwn", (quad_t *) &isp->isp_osinfo.default_wwn)) { 557 int i; 558 u_int64_t seed = (u_int64_t) (intptr_t) isp; 559 560 seed <<= 16; 561 seed &= ((1LL << 48) - 1LL); 562 /* 563 * This isn't very random, but it's the best we can do for 564 * the real edge case of cards that don't have WWNs. If 565 * you recompile a new vers.c, you'll get a different WWN. 566 */ 567 for (i = 0; version[i] != 0; i++) { 568 seed += version[i]; 569 } 570 /* 571 * Make sure the top nibble has something vaguely sensible 572 * (NAA == Locally Administered) 573 */ 574 isp->isp_osinfo.default_wwn |= (3LL << 60) | seed; 575 } else { 576 isp->isp_confopts |= ISP_CFG_OWNWWN; 577 } 578 isp_debug = 0; 579 (void) getenv_int("isp_debug", &isp_debug); 580 581 #ifdef ISP_SMPLOCK 582 /* Make sure the lock is set up. */ 583 mtx_init(&isp->isp_osinfo.lock, "isp", MTX_DEF); 584 locksetup++; 585 #endif 586 587 #ifdef ISP_SMPLOCK 588 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM | INTR_MPSAFE, 589 isp_pci_intr, isp, &pcs->ih)) { 590 device_printf(dev, "could not setup interrupt\n"); 591 goto bad; 592 } 593 #else 594 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM, 595 isp_pci_intr, isp, &pcs->ih)) { 596 device_printf(dev, "could not setup interrupt\n"); 597 goto bad; 598 } 599 #endif 600 601 /* 602 * Set up logging levels. 603 */ 604 if (isp_debug) { 605 isp->isp_dblev = isp_debug; 606 } else { 607 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 608 } 609 if (bootverbose) 610 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 611 612 /* 613 * Make sure we're in reset state. 614 */ 615 ISP_LOCK(isp); 616 isp_reset(isp); 617 618 if (isp->isp_state != ISP_RESETSTATE) { 619 ISP_UNLOCK(isp); 620 goto bad; 621 } 622 isp_init(isp); 623 if (isp->isp_state != ISP_INITSTATE) { 624 /* If we're a Fibre Channel Card, we allow deferred attach */ 625 if (IS_SCSI(isp)) { 626 isp_uninit(isp); 627 ISP_UNLOCK(isp); 628 goto bad; 629 } 630 } 631 isp_attach(isp); 632 if (isp->isp_state != ISP_RUNSTATE) { 633 /* If we're a Fibre Channel Card, we allow deferred attach */ 634 if (IS_SCSI(isp)) { 635 isp_uninit(isp); 636 ISP_UNLOCK(isp); 637 goto bad; 638 } 639 } 640 /* 641 * XXXX: Here is where we might unload the f/w module 642 * XXXX: (or decrease the reference count to it). 643 */ 644 ISP_UNLOCK(isp); 645 return (0); 646 647 bad: 648 649 if (pcs && pcs->ih) { 650 (void) bus_teardown_intr(dev, irq, pcs->ih); 651 } 652 653 #ifdef ISP_SMPLOCK 654 if (locksetup && isp) { 655 mtx_destroy(&isp->isp_osinfo.lock); 656 } 657 #endif 658 659 if (irq) { 660 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 661 } 662 663 664 if (regs) { 665 (void) bus_release_resource(dev, rtp, rgd, regs); 666 } 667 668 if (pcs) { 669 if (pcs->pci_isp.isp_param) 670 free(pcs->pci_isp.isp_param, M_DEVBUF); 671 free(pcs, M_DEVBUF); 672 } 673 674 /* 675 * XXXX: Here is where we might unload the f/w module 676 * XXXX: (or decrease the reference count to it). 677 */ 678 return (ENXIO); 679 } 680 681 static void 682 isp_pci_intr(void *arg) 683 { 684 struct ispsoftc *isp = arg; 685 ISP_LOCK(isp); 686 (void) isp_intr(isp); 687 ISP_UNLOCK(isp); 688 } 689 690 static u_int16_t 691 isp_pci_rd_reg(isp, regoff) 692 struct ispsoftc *isp; 693 int regoff; 694 { 695 u_int16_t rv; 696 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 697 int offset, oldconf = 0; 698 699 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 700 /* 701 * We will assume that someone has paused the RISC processor. 702 */ 703 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 704 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 705 } 706 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 707 offset += (regoff & 0xff); 708 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 709 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 710 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 711 } 712 return (rv); 713 } 714 715 static void 716 isp_pci_wr_reg(isp, regoff, val) 717 struct ispsoftc *isp; 718 int regoff; 719 u_int16_t val; 720 { 721 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 722 int offset, oldconf = 0; 723 724 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 725 /* 726 * We will assume that someone has paused the RISC processor. 727 */ 728 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 729 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 730 } 731 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 732 offset += (regoff & 0xff); 733 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 734 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 735 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 736 } 737 } 738 739 static u_int16_t 740 isp_pci_rd_reg_1080(isp, regoff) 741 struct ispsoftc *isp; 742 int regoff; 743 { 744 u_int16_t rv, oc = 0; 745 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 746 int offset; 747 748 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 749 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 750 u_int16_t tc; 751 /* 752 * We will assume that someone has paused the RISC processor. 753 */ 754 oc = isp_pci_rd_reg(isp, BIU_CONF1); 755 tc = oc & ~BIU_PCI1080_CONF1_DMA; 756 if (regoff & SXP_BANK1_SELECT) 757 tc |= BIU_PCI1080_CONF1_SXP1; 758 else 759 tc |= BIU_PCI1080_CONF1_SXP0; 760 isp_pci_wr_reg(isp, BIU_CONF1, tc); 761 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 762 oc = isp_pci_rd_reg(isp, BIU_CONF1); 763 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 764 } 765 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 766 offset += (regoff & 0xff); 767 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 768 if (oc) { 769 isp_pci_wr_reg(isp, BIU_CONF1, oc); 770 } 771 return (rv); 772 } 773 774 static void 775 isp_pci_wr_reg_1080(isp, regoff, val) 776 struct ispsoftc *isp; 777 int regoff; 778 u_int16_t val; 779 { 780 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 781 int offset, oc = 0; 782 783 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 784 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 785 u_int16_t tc; 786 /* 787 * We will assume that someone has paused the RISC processor. 788 */ 789 oc = isp_pci_rd_reg(isp, BIU_CONF1); 790 tc = oc & ~BIU_PCI1080_CONF1_DMA; 791 if (regoff & SXP_BANK1_SELECT) 792 tc |= BIU_PCI1080_CONF1_SXP1; 793 else 794 tc |= BIU_PCI1080_CONF1_SXP0; 795 isp_pci_wr_reg(isp, BIU_CONF1, tc); 796 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 797 oc = isp_pci_rd_reg(isp, BIU_CONF1); 798 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 799 } 800 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 801 offset += (regoff & 0xff); 802 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 803 if (oc) { 804 isp_pci_wr_reg(isp, BIU_CONF1, oc); 805 } 806 } 807 808 static void isp_map_rquest __P((void *, bus_dma_segment_t *, int, int)); 809 static void isp_map_result __P((void *, bus_dma_segment_t *, int, int)); 810 static void isp_map_fcscrt __P((void *, bus_dma_segment_t *, int, int)); 811 812 struct imush { 813 struct ispsoftc *isp; 814 int error; 815 }; 816 817 static void 818 isp_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) 819 { 820 struct imush *imushp = (struct imush *) arg; 821 if (error) { 822 imushp->error = error; 823 } else { 824 imushp->isp->isp_rquest_dma = segs->ds_addr; 825 } 826 } 827 828 static void 829 isp_map_result(void *arg, bus_dma_segment_t *segs, int nseg, int error) 830 { 831 struct imush *imushp = (struct imush *) arg; 832 if (error) { 833 imushp->error = error; 834 } else { 835 imushp->isp->isp_result_dma = segs->ds_addr; 836 } 837 } 838 839 static void 840 isp_map_fcscrt(void *arg, bus_dma_segment_t *segs, int nseg, int error) 841 { 842 struct imush *imushp = (struct imush *) arg; 843 if (error) { 844 imushp->error = error; 845 } else { 846 fcparam *fcp = imushp->isp->isp_param; 847 fcp->isp_scdma = segs->ds_addr; 848 } 849 } 850 851 static int 852 isp_pci_mbxdma(struct ispsoftc *isp) 853 { 854 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 855 caddr_t base; 856 u_int32_t len; 857 int i, error; 858 bus_size_t lim; 859 struct imush im; 860 861 862 /* 863 * Already been here? If so, leave... 864 */ 865 if (isp->isp_rquest) { 866 return (0); 867 } 868 869 len = sizeof (XS_T **) * isp->isp_maxcmds; 870 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 871 if (isp->isp_xflist == NULL) { 872 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 873 return (1); 874 } 875 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 876 pci->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 877 if (pci->dmaps == NULL) { 878 isp_prt(isp, ISP_LOGERR, "can't alloc dma maps"); 879 free(isp->isp_xflist, M_DEVBUF); 880 return (1); 881 } 882 883 if (IS_FC(isp) || IS_ULTRA2(isp)) 884 lim = BUS_SPACE_MAXADDR + 1; 885 else 886 lim = BUS_SPACE_MAXADDR_24BIT + 1; 887 888 /* 889 * Allocate and map the request, result queues, plus FC scratch area. 890 */ 891 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 892 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 893 if (IS_FC(isp)) { 894 len += ISP2100_SCRLEN; 895 } 896 if (bus_dma_tag_create(pci->parent_dmat, PAGE_SIZE, lim, 897 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, 898 BUS_SPACE_MAXSIZE_32BIT, 0, &pci->cntrol_dmat) != 0) { 899 isp_prt(isp, ISP_LOGERR, 900 "cannot create a dma tag for control spaces"); 901 free(isp->isp_xflist, M_DEVBUF); 902 free(pci->dmaps, M_DEVBUF); 903 return (1); 904 } 905 if (bus_dmamem_alloc(pci->cntrol_dmat, (void **)&base, 906 BUS_DMA_NOWAIT, &pci->cntrol_dmap) != 0) { 907 isp_prt(isp, ISP_LOGERR, 908 "cannot allocate %d bytes of CCB memory"); 909 free(isp->isp_xflist, M_DEVBUF); 910 free(pci->dmaps, M_DEVBUF); 911 return (1); 912 } 913 914 isp->isp_rquest = base; 915 im.isp = isp; 916 im.error = 0; 917 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_rquest, 918 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)), isp_map_rquest, &im, 0); 919 if (im.error) { 920 isp_prt(isp, ISP_LOGERR, 921 "error %d loading dma map for DMA request queue", im.error); 922 free(isp->isp_xflist, M_DEVBUF); 923 free(pci->dmaps, M_DEVBUF); 924 isp->isp_rquest = NULL; 925 return (1); 926 } 927 isp->isp_result = base + ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 928 im.error = 0; 929 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_result, 930 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)), isp_map_result, &im, 0); 931 if (im.error) { 932 isp_prt(isp, ISP_LOGERR, 933 "error %d loading dma map for DMA result queue", im.error); 934 free(isp->isp_xflist, M_DEVBUF); 935 free(pci->dmaps, M_DEVBUF); 936 isp->isp_rquest = NULL; 937 return (1); 938 } 939 940 for (i = 0; i < isp->isp_maxcmds; i++) { 941 error = bus_dmamap_create(pci->parent_dmat, 0, &pci->dmaps[i]); 942 if (error) { 943 isp_prt(isp, ISP_LOGERR, 944 "error %d creating per-cmd DMA maps", error); 945 free(isp->isp_xflist, M_DEVBUF); 946 free(pci->dmaps, M_DEVBUF); 947 isp->isp_rquest = NULL; 948 return (1); 949 } 950 } 951 952 if (IS_FC(isp)) { 953 fcparam *fcp = (fcparam *) isp->isp_param; 954 fcp->isp_scratch = base + 955 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)) + 956 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 957 im.error = 0; 958 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, 959 fcp->isp_scratch, ISP2100_SCRLEN, isp_map_fcscrt, &im, 0); 960 if (im.error) { 961 isp_prt(isp, ISP_LOGERR, 962 "error %d loading FC scratch area", im.error); 963 free(isp->isp_xflist, M_DEVBUF); 964 free(pci->dmaps, M_DEVBUF); 965 isp->isp_rquest = NULL; 966 return (1); 967 } 968 } 969 return (0); 970 } 971 972 typedef struct { 973 struct ispsoftc *isp; 974 void *cmd_token; 975 void *rq; 976 u_int16_t *iptrp; 977 u_int16_t optr; 978 u_int error; 979 } mush_t; 980 981 #define MUSHERR_NOQENTRIES -2 982 983 #ifdef ISP_TARGET_MODE 984 /* 985 * We need to handle DMA for target mode differently from initiator mode. 986 * 987 * DMA mapping and construction and submission of CTIO Request Entries 988 * and rendevous for completion are very tightly coupled because we start 989 * out by knowing (per platform) how much data we have to move, but we 990 * don't know, up front, how many DMA mapping segments will have to be used 991 * cover that data, so we don't know how many CTIO Request Entries we 992 * will end up using. Further, for performance reasons we may want to 993 * (on the last CTIO for Fibre Channel), send status too (if all went well). 994 * 995 * The standard vector still goes through isp_pci_dmasetup, but the callback 996 * for the DMA mapping routines comes here instead with the whole transfer 997 * mapped and a pointer to a partially filled in already allocated request 998 * queue entry. We finish the job. 999 */ 1000 static void tdma_mk __P((void *, bus_dma_segment_t *, int, int)); 1001 static void tdma_mkfc __P((void *, bus_dma_segment_t *, int, int)); 1002 1003 static void 1004 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1005 { 1006 mush_t *mp; 1007 struct ccb_scsiio *csio; 1008 struct isp_pcisoftc *pci; 1009 bus_dmamap_t *dp; 1010 u_int8_t scsi_status; 1011 ct_entry_t *cto; 1012 u_int32_t handle, totxfr, sflags; 1013 int nctios, send_status; 1014 int32_t resid; 1015 1016 mp = (mush_t *) arg; 1017 if (error) { 1018 mp->error = error; 1019 return; 1020 } 1021 csio = mp->cmd_token; 1022 cto = mp->rq; 1023 1024 cto->ct_xfrlen = 0; 1025 cto->ct_seg_count = 0; 1026 cto->ct_header.rqs_entry_count = 1; 1027 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1028 1029 if (nseg == 0) { 1030 cto->ct_header.rqs_seqno = 1; 1031 ISP_TDQE(mp->isp, "tdma_mk[no data]", *mp->iptrp, cto); 1032 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1033 "CTIO lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x res %d", 1034 csio->ccb_h.target_lun, cto->ct_iid, cto->ct_flags, 1035 cto->ct_status, cto->ct_scsi_status, cto->ct_resid); 1036 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1037 return; 1038 } 1039 1040 nctios = nseg / ISP_RQDSEG; 1041 if (nseg % ISP_RQDSEG) { 1042 nctios++; 1043 } 1044 1045 /* 1046 * Save handle, and potentially any SCSI status, which we'll reinsert 1047 * on the last CTIO we're going to send. 1048 */ 1049 handle = cto->ct_reserved; 1050 cto->ct_reserved = 0; 1051 cto->ct_header.rqs_seqno = 0; 1052 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1053 1054 if (send_status) { 1055 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1056 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1057 /* 1058 * Preserve residual. 1059 */ 1060 resid = cto->ct_resid; 1061 1062 /* 1063 * Save actual SCSI status. 1064 */ 1065 scsi_status = cto->ct_scsi_status; 1066 1067 /* 1068 * We can't do a status at the same time as a data CTIO, so 1069 * we need to synthesize an extra CTIO at this level. 1070 */ 1071 nctios++; 1072 } else { 1073 sflags = scsi_status = resid = 0; 1074 } 1075 1076 totxfr = cto->ct_resid = 0; 1077 cto->ct_scsi_status = 0; 1078 1079 pci = (struct isp_pcisoftc *)mp->isp; 1080 dp = &pci->dmaps[isp_handle_index(handle)]; 1081 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1082 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1083 } else { 1084 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1085 } 1086 1087 1088 while (nctios--) { 1089 int seglim; 1090 1091 seglim = nseg; 1092 if (seglim) { 1093 int seg; 1094 1095 if (seglim > ISP_RQDSEG) 1096 seglim = ISP_RQDSEG; 1097 1098 for (seg = 0; seg < seglim; seg++, nseg--) { 1099 /* 1100 * Unlike normal initiator commands, we don't 1101 * do any swizzling here. 1102 */ 1103 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1104 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1105 cto->ct_xfrlen += dm_segs->ds_len; 1106 totxfr += dm_segs->ds_len; 1107 dm_segs++; 1108 } 1109 cto->ct_seg_count = seg; 1110 } else { 1111 /* 1112 * This case should only happen when we're sending an 1113 * extra CTIO with final status. 1114 */ 1115 if (send_status == 0) { 1116 isp_prt(mp->isp, ISP_LOGWARN, 1117 "tdma_mk ran out of segments"); 1118 mp->error = EINVAL; 1119 return; 1120 } 1121 } 1122 1123 /* 1124 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1125 * ct_tagtype, and ct_timeout have been carried over 1126 * unchanged from what our caller had set. 1127 * 1128 * The dataseg fields and the seg_count fields we just got 1129 * through setting. The data direction we've preserved all 1130 * along and only clear it if we're now sending status. 1131 */ 1132 1133 if (nctios == 0) { 1134 /* 1135 * We're the last in a sequence of CTIOs, so mark 1136 * this CTIO and save the handle to the CCB such that 1137 * when this CTIO completes we can free dma resources 1138 * and do whatever else we need to do to finish the 1139 * rest of the command. 1140 */ 1141 cto->ct_reserved = handle; 1142 cto->ct_header.rqs_seqno = 1; 1143 1144 if (send_status) { 1145 cto->ct_scsi_status = scsi_status; 1146 cto->ct_flags |= sflags | CT_NO_DATA;; 1147 cto->ct_resid = resid; 1148 } 1149 if (send_status) { 1150 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1151 "CTIO lun%d for ID %d ct_flags 0x%x scsi " 1152 "status %x resid %d", 1153 csio->ccb_h.target_lun, 1154 cto->ct_iid, cto->ct_flags, 1155 cto->ct_scsi_status, cto->ct_resid); 1156 } else { 1157 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1158 "CTIO lun%d for ID%d ct_flags 0x%x", 1159 csio->ccb_h.target_lun, 1160 cto->ct_iid, cto->ct_flags); 1161 } 1162 ISP_TDQE(mp->isp, "last tdma_mk", *mp->iptrp, cto); 1163 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1164 } else { 1165 ct_entry_t *octo = cto; 1166 1167 /* 1168 * Make sure handle fields are clean 1169 */ 1170 cto->ct_reserved = 0; 1171 cto->ct_header.rqs_seqno = 0; 1172 1173 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1174 "CTIO lun%d for ID%d ct_flags 0x%x", 1175 csio->ccb_h.target_lun, cto->ct_iid, cto->ct_flags); 1176 ISP_TDQE(mp->isp, "tdma_mk", *mp->iptrp, cto); 1177 1178 /* 1179 * Get a new CTIO 1180 */ 1181 cto = (ct_entry_t *) 1182 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1183 *mp->iptrp = 1184 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1185 if (*mp->iptrp == mp->optr) { 1186 isp_prt(mp->isp, ISP_LOGWARN, 1187 "Queue Overflow in tdma_mk"); 1188 mp->error = MUSHERR_NOQENTRIES; 1189 return; 1190 } 1191 /* 1192 * Fill in the new CTIO with info from the old one. 1193 */ 1194 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1195 cto->ct_header.rqs_entry_count = 1; 1196 cto->ct_header.rqs_flags = 0; 1197 cto->ct_lun = octo->ct_lun; 1198 cto->ct_iid = octo->ct_iid; 1199 cto->ct_reserved2 = octo->ct_reserved2; 1200 cto->ct_tgt = octo->ct_tgt; 1201 cto->ct_flags = octo->ct_flags; 1202 cto->ct_status = 0; 1203 cto->ct_scsi_status = 0; 1204 cto->ct_tag_val = octo->ct_tag_val; 1205 cto->ct_tag_type = octo->ct_tag_type; 1206 cto->ct_xfrlen = 0; 1207 cto->ct_resid = 0; 1208 cto->ct_timeout = octo->ct_timeout; 1209 cto->ct_seg_count = 0; 1210 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1211 /* 1212 * Now swizzle the old one for the consumption of the 1213 * chip. 1214 */ 1215 ISP_SWIZ_CTIO(mp->isp, octo, octo); 1216 } 1217 } 1218 } 1219 1220 static void 1221 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1222 { 1223 mush_t *mp; 1224 struct ccb_scsiio *csio; 1225 struct isp_pcisoftc *pci; 1226 bus_dmamap_t *dp; 1227 ct2_entry_t *cto; 1228 u_int16_t scsi_status, send_status, send_sense; 1229 u_int32_t handle, totxfr, datalen; 1230 u_int8_t sense[QLTM_SENSELEN]; 1231 int nctios; 1232 1233 mp = (mush_t *) arg; 1234 if (error) { 1235 mp->error = error; 1236 return; 1237 } 1238 1239 csio = mp->cmd_token; 1240 cto = mp->rq; 1241 1242 if (nseg == 0) { 1243 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1244 isp_prt(mp->isp, ISP_LOGWARN, 1245 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1246 "set (0x%x)", cto->ct_flags); 1247 mp->error = EINVAL; 1248 return; 1249 } 1250 cto->ct_header.rqs_entry_count = 1; 1251 cto->ct_header.rqs_seqno = 1; 1252 /* ct_reserved contains the handle set by caller */ 1253 /* 1254 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1255 * flags to NO DATA and clear relative offset flags. 1256 * We preserve the ct_resid and the response area. 1257 */ 1258 cto->ct_flags |= CT2_NO_DATA; 1259 if (cto->ct_resid > 0) 1260 cto->ct_flags |= CT2_DATA_UNDER; 1261 else if (cto->ct_resid < 0) 1262 cto->ct_flags |= CT2_DATA_OVER; 1263 cto->ct_seg_count = 0; 1264 cto->ct_reloff = 0; 1265 ISP_TDQE(mp->isp, "dma2_tgt_fc[no data]", *mp->iptrp, cto); 1266 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1267 "CTIO2 RX_ID 0x%x lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1268 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1269 cto->ct_iid, cto->ct_flags, cto->ct_status, 1270 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1271 ISP_SWIZ_CTIO2(isp, cto, cto); 1272 return; 1273 } 1274 1275 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1276 isp_prt(mp->isp, ISP_LOGWARN, 1277 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1278 "(0x%x)", cto->ct_flags); 1279 mp->error = EINVAL; 1280 return; 1281 } 1282 1283 1284 nctios = nseg / ISP_RQDSEG_T2; 1285 if (nseg % ISP_RQDSEG_T2) { 1286 nctios++; 1287 } 1288 1289 /* 1290 * Save the handle, status, reloff, and residual. We'll reinsert the 1291 * handle into the last CTIO2 we're going to send, and reinsert status 1292 * and residual (and possibly sense data) if that's to be sent as well. 1293 * 1294 * We preserve ct_reloff and adjust it for each data CTIO2 we send past 1295 * the first one. This is needed so that the FCP DATA IUs being sent 1296 * out have the correct offset (they can arrive at the other end out 1297 * of order). 1298 */ 1299 1300 handle = cto->ct_reserved; 1301 cto->ct_reserved = 0; 1302 1303 if ((send_status = (cto->ct_flags & CT2_SENDSTATUS)) != 0) { 1304 cto->ct_flags &= ~CT2_SENDSTATUS; 1305 1306 /* 1307 * Preserve residual, which is actually the total count. 1308 */ 1309 datalen = cto->ct_resid; 1310 1311 /* 1312 * Save actual SCSI status. We'll reinsert the 1313 * CT2_SNSLEN_VALID later if appropriate. 1314 */ 1315 scsi_status = cto->rsp.m0.ct_scsi_status & 0xff; 1316 send_sense = cto->rsp.m0.ct_scsi_status & CT2_SNSLEN_VALID; 1317 1318 /* 1319 * If we're sending status and have a CHECK CONDTION and 1320 * have sense data, we send one more CTIO2 with just the 1321 * status and sense data. The upper layers have stashed 1322 * the sense data in the dataseg structure for us. 1323 */ 1324 1325 if ((scsi_status & 0xf) == SCSI_STATUS_CHECK_COND && 1326 send_sense) { 1327 bcopy(cto->rsp.m0.ct_dataseg, sense, QLTM_SENSELEN); 1328 nctios++; 1329 } 1330 } else { 1331 scsi_status = send_sense = datalen = 0; 1332 } 1333 1334 totxfr = cto->ct_resid = 0; 1335 cto->rsp.m0.ct_scsi_status = 0; 1336 bzero(&cto->rsp, sizeof (cto->rsp)); 1337 1338 pci = (struct isp_pcisoftc *)mp->isp; 1339 dp = &pci->dmaps[isp_handle_index(handle)]; 1340 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1341 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1342 } else { 1343 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1344 } 1345 1346 while (nctios--) { 1347 int seg, seglim; 1348 1349 seglim = nseg; 1350 if (seglim) { 1351 if (seglim > ISP_RQDSEG_T2) 1352 seglim = ISP_RQDSEG_T2; 1353 1354 for (seg = 0; seg < seglim; seg++) { 1355 cto->rsp.m0.ct_dataseg[seg].ds_base = 1356 dm_segs->ds_addr; 1357 cto->rsp.m0.ct_dataseg[seg].ds_count = 1358 dm_segs->ds_len; 1359 cto->rsp.m0.ct_xfrlen += dm_segs->ds_len; 1360 totxfr += dm_segs->ds_len; 1361 dm_segs++; 1362 } 1363 cto->ct_seg_count = seg; 1364 } else { 1365 /* 1366 * This case should only happen when we're sending a 1367 * synthesized MODE1 final status with sense data. 1368 */ 1369 if (send_sense == 0) { 1370 isp_prt(mp->isp, ISP_LOGWARN, 1371 "dma2_tgt_fc ran out of segments, " 1372 "no SENSE DATA"); 1373 mp->error = EINVAL; 1374 return; 1375 } 1376 } 1377 1378 /* 1379 * At this point, the fields ct_lun, ct_iid, ct_rxid, 1380 * ct_timeout have been carried over unchanged from what 1381 * our caller had set. 1382 * 1383 * The field ct_reloff is either what the caller set, or 1384 * what we've added to below. 1385 * 1386 * The dataseg fields and the seg_count fields we just got 1387 * through setting. The data direction we've preserved all 1388 * along and only clear it if we're sending a MODE1 status 1389 * as the last CTIO. 1390 * 1391 */ 1392 1393 if (nctios == 0) { 1394 1395 /* 1396 * We're the last in a sequence of CTIO2s, so mark this 1397 * CTIO2 and save the handle to the CCB such that when 1398 * this CTIO2 completes we can free dma resources and 1399 * do whatever else we need to do to finish the rest 1400 * of the command. 1401 */ 1402 1403 cto->ct_reserved = handle; 1404 cto->ct_header.rqs_seqno = 1; 1405 1406 if (send_status) { 1407 if (send_sense) { 1408 bcopy(sense, cto->rsp.m1.ct_resp, 1409 QLTM_SENSELEN); 1410 cto->rsp.m1.ct_senselen = 1411 QLTM_SENSELEN; 1412 scsi_status |= CT2_SNSLEN_VALID; 1413 cto->rsp.m1.ct_scsi_status = 1414 scsi_status; 1415 cto->ct_flags &= CT2_FLAG_MMASK; 1416 cto->ct_flags |= CT2_FLAG_MODE1 | 1417 CT2_NO_DATA| CT2_SENDSTATUS; 1418 } else { 1419 cto->rsp.m0.ct_scsi_status = 1420 scsi_status; 1421 cto->ct_flags |= CT2_SENDSTATUS; 1422 } 1423 /* 1424 * Get 'real' residual and set flags based 1425 * on it. 1426 */ 1427 cto->ct_resid = datalen - totxfr; 1428 if (cto->ct_resid > 0) 1429 cto->ct_flags |= CT2_DATA_UNDER; 1430 else if (cto->ct_resid < 0) 1431 cto->ct_flags |= CT2_DATA_OVER; 1432 } 1433 ISP_TDQE(mp->isp, "last dma2_tgt_fc", *mp->iptrp, cto); 1434 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1435 "CTIO2 RX_ID 0x%x lun %d->iid%d flgs 0x%x sts 0x%x" 1436 " ssts 0x%x res %d", cto->ct_rxid, 1437 csio->ccb_h.target_lun, (int) cto->ct_iid, 1438 cto->ct_flags, cto->ct_status, 1439 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1440 ISP_SWIZ_CTIO2(isp, cto, cto); 1441 } else { 1442 ct2_entry_t *octo = cto; 1443 1444 /* 1445 * Make sure handle fields are clean 1446 */ 1447 cto->ct_reserved = 0; 1448 cto->ct_header.rqs_seqno = 0; 1449 1450 ISP_TDQE(mp->isp, "dma2_tgt_fc", *mp->iptrp, cto); 1451 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1452 "CTIO2 RX_ID 0x%x lun %d->iid%d flgs 0x%x", 1453 cto->ct_rxid, csio->ccb_h.target_lun, 1454 (int) cto->ct_iid, cto->ct_flags); 1455 /* 1456 * Get a new CTIO2 1457 */ 1458 cto = (ct2_entry_t *) 1459 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1460 *mp->iptrp = 1461 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1462 if (*mp->iptrp == mp->optr) { 1463 isp_prt(mp->isp, ISP_LOGWARN, 1464 "Queue Overflow in dma2_tgt_fc"); 1465 mp->error = MUSHERR_NOQENTRIES; 1466 return; 1467 } 1468 1469 /* 1470 * Fill in the new CTIO2 with info from the old one. 1471 */ 1472 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO2; 1473 cto->ct_header.rqs_entry_count = 1; 1474 cto->ct_header.rqs_flags = 0; 1475 /* ct_header.rqs_seqno && ct_reserved done later */ 1476 cto->ct_lun = octo->ct_lun; 1477 cto->ct_iid = octo->ct_iid; 1478 cto->ct_rxid = octo->ct_rxid; 1479 cto->ct_flags = octo->ct_flags; 1480 cto->ct_status = 0; 1481 cto->ct_resid = 0; 1482 cto->ct_timeout = octo->ct_timeout; 1483 cto->ct_seg_count = 0; 1484 /* 1485 * Adjust the new relative offset by the amount which 1486 * is recorded in the data segment of the old CTIO2 we 1487 * just finished filling out. 1488 */ 1489 cto->ct_reloff += octo->rsp.m0.ct_xfrlen; 1490 bzero(&cto->rsp, sizeof (cto->rsp)); 1491 ISP_SWIZ_CTIO2(isp, cto, cto); 1492 } 1493 } 1494 } 1495 #endif 1496 1497 static void dma2 __P((void *, bus_dma_segment_t *, int, int)); 1498 1499 static void 1500 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1501 { 1502 mush_t *mp; 1503 struct ccb_scsiio *csio; 1504 struct isp_pcisoftc *pci; 1505 bus_dmamap_t *dp; 1506 bus_dma_segment_t *eseg; 1507 ispreq_t *rq; 1508 ispcontreq_t *crq; 1509 int seglim, datalen; 1510 1511 mp = (mush_t *) arg; 1512 if (error) { 1513 mp->error = error; 1514 return; 1515 } 1516 1517 if (nseg < 1) { 1518 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1519 mp->error = EFAULT; 1520 return; 1521 } 1522 csio = mp->cmd_token; 1523 rq = mp->rq; 1524 pci = (struct isp_pcisoftc *)mp->isp; 1525 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1526 1527 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1528 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1529 } else { 1530 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1531 } 1532 1533 datalen = XS_XFRLEN(csio); 1534 1535 /* 1536 * We're passed an initial partially filled in entry that 1537 * has most fields filled in except for data transfer 1538 * related values. 1539 * 1540 * Our job is to fill in the initial request queue entry and 1541 * then to start allocating and filling in continuation entries 1542 * until we've covered the entire transfer. 1543 */ 1544 1545 if (IS_FC(mp->isp)) { 1546 seglim = ISP_RQDSEG_T2; 1547 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1548 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1549 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1550 } else { 1551 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1552 } 1553 } else { 1554 if (csio->cdb_len > 12) { 1555 seglim = 0; 1556 } else { 1557 seglim = ISP_RQDSEG; 1558 } 1559 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1560 rq->req_flags |= REQFLAG_DATA_IN; 1561 } else { 1562 rq->req_flags |= REQFLAG_DATA_OUT; 1563 } 1564 } 1565 1566 eseg = dm_segs + nseg; 1567 1568 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1569 if (IS_FC(mp->isp)) { 1570 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1571 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1572 dm_segs->ds_addr; 1573 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1574 dm_segs->ds_len; 1575 } else { 1576 rq->req_dataseg[rq->req_seg_count].ds_base = 1577 dm_segs->ds_addr; 1578 rq->req_dataseg[rq->req_seg_count].ds_count = 1579 dm_segs->ds_len; 1580 } 1581 datalen -= dm_segs->ds_len; 1582 #if 0 1583 if (IS_FC(mp->isp)) { 1584 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1585 printf("%s: seg0[%d] cnt 0x%x paddr 0x%08x\n", 1586 mp->isp->isp_name, rq->req_seg_count, 1587 rq2->req_dataseg[rq2->req_seg_count].ds_count, 1588 rq2->req_dataseg[rq2->req_seg_count].ds_base); 1589 } else { 1590 printf("%s: seg0[%d] cnt 0x%x paddr 0x%08x\n", 1591 mp->isp->isp_name, rq->req_seg_count, 1592 rq->req_dataseg[rq->req_seg_count].ds_count, 1593 rq->req_dataseg[rq->req_seg_count].ds_base); 1594 } 1595 #endif 1596 rq->req_seg_count++; 1597 dm_segs++; 1598 } 1599 1600 while (datalen > 0 && dm_segs != eseg) { 1601 crq = (ispcontreq_t *) 1602 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1603 *mp->iptrp = ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1604 if (*mp->iptrp == mp->optr) { 1605 #if 0 1606 printf("%s: Request Queue Overflow++\n", 1607 mp->isp->isp_name); 1608 #endif 1609 mp->error = MUSHERR_NOQENTRIES; 1610 return; 1611 } 1612 rq->req_header.rqs_entry_count++; 1613 bzero((void *)crq, sizeof (*crq)); 1614 crq->req_header.rqs_entry_count = 1; 1615 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1616 1617 seglim = 0; 1618 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1619 crq->req_dataseg[seglim].ds_base = 1620 dm_segs->ds_addr; 1621 crq->req_dataseg[seglim].ds_count = 1622 dm_segs->ds_len; 1623 #if 0 1624 printf("%s: seg%d[%d] cnt 0x%x paddr 0x%08x\n", 1625 mp->isp->isp_name, rq->req_header.rqs_entry_count-1, 1626 seglim, crq->req_dataseg[seglim].ds_count, 1627 crq->req_dataseg[seglim].ds_base); 1628 #endif 1629 rq->req_seg_count++; 1630 dm_segs++; 1631 seglim++; 1632 datalen -= dm_segs->ds_len; 1633 } 1634 } 1635 } 1636 1637 static int 1638 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1639 u_int16_t *iptrp, u_int16_t optr) 1640 { 1641 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1642 bus_dmamap_t *dp = NULL; 1643 mush_t mush, *mp; 1644 void (*eptr) __P((void *, bus_dma_segment_t *, int, int)); 1645 1646 #ifdef ISP_TARGET_MODE 1647 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1648 if (IS_FC(isp)) { 1649 eptr = tdma_mkfc; 1650 } else { 1651 eptr = tdma_mk; 1652 } 1653 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1654 (csio->dxfer_len == 0)) { 1655 rq->req_seg_count = 1; 1656 mp = &mush; 1657 mp->isp = isp; 1658 mp->cmd_token = csio; 1659 mp->rq = rq; 1660 mp->iptrp = iptrp; 1661 mp->optr = optr; 1662 mp->error = 0; 1663 (*eptr)(mp, NULL, 0, 0); 1664 goto exit; 1665 } 1666 } else 1667 #endif 1668 eptr = dma2; 1669 1670 /* 1671 * NB: if we need to do request queue entry swizzling, 1672 * NB: this is where it would need to be done for cmds 1673 * NB: that move no data. For commands that move data, 1674 * NB: swizzling would take place in those functions. 1675 */ 1676 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1677 (csio->dxfer_len == 0)) { 1678 rq->req_seg_count = 1; 1679 return (CMD_QUEUED); 1680 } 1681 1682 /* 1683 * Do a virtual grapevine step to collect info for 1684 * the callback dma allocation that we have to use... 1685 */ 1686 mp = &mush; 1687 mp->isp = isp; 1688 mp->cmd_token = csio; 1689 mp->rq = rq; 1690 mp->iptrp = iptrp; 1691 mp->optr = optr; 1692 mp->error = 0; 1693 1694 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1695 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1696 int error, s; 1697 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1698 s = splsoftvm(); 1699 error = bus_dmamap_load(pci->parent_dmat, *dp, 1700 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1701 if (error == EINPROGRESS) { 1702 bus_dmamap_unload(pci->parent_dmat, *dp); 1703 mp->error = EINVAL; 1704 isp_prt(isp, ISP_LOGERR, 1705 "deferred dma allocation not supported"); 1706 } else if (error && mp->error == 0) { 1707 #ifdef DIAGNOSTIC 1708 printf("%s: error %d in dma mapping code\n", 1709 isp->isp_name, error); 1710 #endif 1711 mp->error = error; 1712 } 1713 splx(s); 1714 } else { 1715 /* Pointer to physical buffer */ 1716 struct bus_dma_segment seg; 1717 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1718 seg.ds_len = csio->dxfer_len; 1719 (*eptr)(mp, &seg, 1, 0); 1720 } 1721 } else { 1722 struct bus_dma_segment *segs; 1723 1724 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1725 isp_prt(isp, ISP_LOGERR, 1726 "Physical segment pointers unsupported"); 1727 mp->error = EINVAL; 1728 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1729 isp_prt(isp, ISP_LOGERR, 1730 "Virtual segment addresses unsupported"); 1731 mp->error = EINVAL; 1732 } else { 1733 /* Just use the segments provided */ 1734 segs = (struct bus_dma_segment *) csio->data_ptr; 1735 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1736 } 1737 } 1738 #ifdef ISP_TARGET_MODE 1739 exit: 1740 #endif 1741 if (mp->error) { 1742 int retval = CMD_COMPLETE; 1743 if (mp->error == MUSHERR_NOQENTRIES) { 1744 retval = CMD_EAGAIN; 1745 } else if (mp->error == EFBIG) { 1746 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1747 } else if (mp->error == EINVAL) { 1748 XS_SETERR(csio, CAM_REQ_INVALID); 1749 } else { 1750 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1751 } 1752 return (retval); 1753 } else { 1754 /* 1755 * Check to see if we weren't cancelled while sleeping on 1756 * getting DMA resources... 1757 */ 1758 if ((csio->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 1759 if (dp) { 1760 bus_dmamap_unload(pci->parent_dmat, *dp); 1761 } 1762 return (CMD_COMPLETE); 1763 } 1764 return (CMD_QUEUED); 1765 } 1766 } 1767 1768 static void 1769 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int32_t handle) 1770 { 1771 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1772 bus_dmamap_t *dp = &pci->dmaps[isp_handle_index(handle)]; 1773 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1774 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTREAD); 1775 } else { 1776 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTWRITE); 1777 } 1778 bus_dmamap_unload(pci->parent_dmat, *dp); 1779 } 1780 1781 1782 static void 1783 isp_pci_reset1(struct ispsoftc *isp) 1784 { 1785 /* Make sure the BIOS is disabled */ 1786 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1787 /* and enable interrupts */ 1788 ENABLE_INTS(isp); 1789 } 1790 1791 static void 1792 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1793 { 1794 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1795 if (msg) 1796 printf("%s: %s\n", isp->isp_name, msg); 1797 if (IS_SCSI(isp)) 1798 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1799 else 1800 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1801 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1802 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1803 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1804 1805 1806 if (IS_SCSI(isp)) { 1807 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1808 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1809 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1810 ISP_READ(isp, CDMA_FIFO_STS)); 1811 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1812 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1813 ISP_READ(isp, DDMA_FIFO_STS)); 1814 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1815 ISP_READ(isp, SXP_INTERRUPT), 1816 ISP_READ(isp, SXP_GROSS_ERR), 1817 ISP_READ(isp, SXP_PINS_CTRL)); 1818 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1819 } 1820 printf(" mbox regs: %x %x %x %x %x\n", 1821 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1822 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1823 ISP_READ(isp, OUTMAILBOX4)); 1824 printf(" PCI Status Command/Status=%x\n", 1825 pci_read_config(pci->pci_dev, PCIR_COMMAND, 1)); 1826 } 1827