1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 #include <sys/malloc.h> 47 #include <sys/uio.h> 48 49 #ifdef __sparc64__ 50 #include <dev/ofw/openfirm.h> 51 #include <machine/ofw_machdep.h> 52 #endif 53 54 #include <dev/isp/isp_freebsd.h> 55 56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 62 static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 63 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 64 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 65 static int isp_pci_mbxdma(ispsoftc_t *); 66 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 67 68 69 static void isp_pci_reset0(ispsoftc_t *); 70 static void isp_pci_reset1(ispsoftc_t *); 71 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 72 73 static struct ispmdvec mdvec = { 74 isp_pci_rd_isr, 75 isp_pci_rd_reg, 76 isp_pci_wr_reg, 77 isp_pci_mbxdma, 78 isp_pci_dmasetup, 79 isp_common_dmateardown, 80 isp_pci_reset0, 81 isp_pci_reset1, 82 isp_pci_dumpregs, 83 NULL, 84 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 85 }; 86 87 static struct ispmdvec mdvec_1080 = { 88 isp_pci_rd_isr, 89 isp_pci_rd_reg_1080, 90 isp_pci_wr_reg_1080, 91 isp_pci_mbxdma, 92 isp_pci_dmasetup, 93 isp_common_dmateardown, 94 isp_pci_reset0, 95 isp_pci_reset1, 96 isp_pci_dumpregs, 97 NULL, 98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 99 }; 100 101 static struct ispmdvec mdvec_12160 = { 102 isp_pci_rd_isr, 103 isp_pci_rd_reg_1080, 104 isp_pci_wr_reg_1080, 105 isp_pci_mbxdma, 106 isp_pci_dmasetup, 107 isp_common_dmateardown, 108 isp_pci_reset0, 109 isp_pci_reset1, 110 isp_pci_dumpregs, 111 NULL, 112 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 113 }; 114 115 static struct ispmdvec mdvec_2100 = { 116 isp_pci_rd_isr, 117 isp_pci_rd_reg, 118 isp_pci_wr_reg, 119 isp_pci_mbxdma, 120 isp_pci_dmasetup, 121 isp_common_dmateardown, 122 isp_pci_reset0, 123 isp_pci_reset1, 124 isp_pci_dumpregs 125 }; 126 127 static struct ispmdvec mdvec_2200 = { 128 isp_pci_rd_isr, 129 isp_pci_rd_reg, 130 isp_pci_wr_reg, 131 isp_pci_mbxdma, 132 isp_pci_dmasetup, 133 isp_common_dmateardown, 134 isp_pci_reset0, 135 isp_pci_reset1, 136 isp_pci_dumpregs 137 }; 138 139 static struct ispmdvec mdvec_2300 = { 140 isp_pci_rd_isr_2300, 141 isp_pci_rd_reg, 142 isp_pci_wr_reg, 143 isp_pci_mbxdma, 144 isp_pci_dmasetup, 145 isp_common_dmateardown, 146 isp_pci_reset0, 147 isp_pci_reset1, 148 isp_pci_dumpregs 149 }; 150 151 static struct ispmdvec mdvec_2400 = { 152 isp_pci_rd_isr_2400, 153 isp_pci_rd_reg_2400, 154 isp_pci_wr_reg_2400, 155 isp_pci_mbxdma, 156 isp_pci_dmasetup, 157 isp_common_dmateardown, 158 isp_pci_reset0, 159 isp_pci_reset1, 160 NULL 161 }; 162 163 static struct ispmdvec mdvec_2500 = { 164 isp_pci_rd_isr_2400, 165 isp_pci_rd_reg_2400, 166 isp_pci_wr_reg_2400, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_common_dmateardown, 170 isp_pci_reset0, 171 isp_pci_reset1, 172 NULL 173 }; 174 175 #ifndef PCIM_CMD_INVEN 176 #define PCIM_CMD_INVEN 0x10 177 #endif 178 #ifndef PCIM_CMD_BUSMASTEREN 179 #define PCIM_CMD_BUSMASTEREN 0x0004 180 #endif 181 #ifndef PCIM_CMD_PERRESPEN 182 #define PCIM_CMD_PERRESPEN 0x0040 183 #endif 184 #ifndef PCIM_CMD_SEREN 185 #define PCIM_CMD_SEREN 0x0100 186 #endif 187 #ifndef PCIM_CMD_INTX_DISABLE 188 #define PCIM_CMD_INTX_DISABLE 0x0400 189 #endif 190 191 #ifndef PCIR_COMMAND 192 #define PCIR_COMMAND 0x04 193 #endif 194 195 #ifndef PCIR_CACHELNSZ 196 #define PCIR_CACHELNSZ 0x0c 197 #endif 198 199 #ifndef PCIR_LATTIMER 200 #define PCIR_LATTIMER 0x0d 201 #endif 202 203 #ifndef PCIR_ROMADDR 204 #define PCIR_ROMADDR 0x30 205 #endif 206 207 #ifndef PCI_VENDOR_QLOGIC 208 #define PCI_VENDOR_QLOGIC 0x1077 209 #endif 210 211 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 212 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 213 #endif 214 215 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 216 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 217 #endif 218 219 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 220 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 221 #endif 222 223 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 224 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 225 #endif 226 227 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 228 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 229 #endif 230 231 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 232 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 233 #endif 234 235 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 236 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 237 #endif 238 239 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 240 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 241 #endif 242 243 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 244 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 245 #endif 246 247 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 248 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 249 #endif 250 251 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 252 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 253 #endif 254 255 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 256 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 257 #endif 258 259 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 260 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 261 #endif 262 263 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 264 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 265 #endif 266 267 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 268 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 269 #endif 270 271 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 272 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 273 #endif 274 275 #ifndef PCI_PRODUCT_QLOGIC_ISP5432 276 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 277 #endif 278 279 #define PCI_QLOGIC_ISP5432 \ 280 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP1020 \ 283 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP1080 \ 286 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define PCI_QLOGIC_ISP10160 \ 289 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 290 291 #define PCI_QLOGIC_ISP12160 \ 292 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 293 294 #define PCI_QLOGIC_ISP1240 \ 295 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 296 297 #define PCI_QLOGIC_ISP1280 \ 298 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 299 300 #define PCI_QLOGIC_ISP2100 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 302 303 #define PCI_QLOGIC_ISP2200 \ 304 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 305 306 #define PCI_QLOGIC_ISP2300 \ 307 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 308 309 #define PCI_QLOGIC_ISP2312 \ 310 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 311 312 #define PCI_QLOGIC_ISP2322 \ 313 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 314 315 #define PCI_QLOGIC_ISP2422 \ 316 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 317 318 #define PCI_QLOGIC_ISP2432 \ 319 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 320 321 #define PCI_QLOGIC_ISP2532 \ 322 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 323 324 #define PCI_QLOGIC_ISP6312 \ 325 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 326 327 #define PCI_QLOGIC_ISP6322 \ 328 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 329 330 /* 331 * Odd case for some AMI raid cards... We need to *not* attach to this. 332 */ 333 #define AMI_RAID_SUBVENDOR_ID 0x101e 334 335 #define IO_MAP_REG 0x10 336 #define MEM_MAP_REG 0x14 337 338 #define PCI_DFLT_LTNCY 0x40 339 #define PCI_DFLT_LNSZ 0x10 340 341 static int isp_pci_probe (device_t); 342 static int isp_pci_attach (device_t); 343 static int isp_pci_detach (device_t); 344 345 346 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 347 struct isp_pcisoftc { 348 ispsoftc_t pci_isp; 349 device_t pci_dev; 350 struct resource * regs; 351 void * irq; 352 int iqd; 353 int rtp; 354 int rgd; 355 void * ih; 356 int16_t pci_poff[_NREG_BLKS]; 357 bus_dma_tag_t dmat; 358 int msicount; 359 }; 360 361 362 static device_method_t isp_pci_methods[] = { 363 /* Device interface */ 364 DEVMETHOD(device_probe, isp_pci_probe), 365 DEVMETHOD(device_attach, isp_pci_attach), 366 DEVMETHOD(device_detach, isp_pci_detach), 367 { 0, 0 } 368 }; 369 370 static driver_t isp_pci_driver = { 371 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 372 }; 373 static devclass_t isp_devclass; 374 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 375 MODULE_DEPEND(isp, cam, 1, 1, 1); 376 MODULE_DEPEND(isp, firmware, 1, 1, 1); 377 static int isp_nvports = 0; 378 379 static int 380 isp_pci_probe(device_t dev) 381 { 382 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 383 case PCI_QLOGIC_ISP1020: 384 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 385 break; 386 case PCI_QLOGIC_ISP1080: 387 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 388 break; 389 case PCI_QLOGIC_ISP1240: 390 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 391 break; 392 case PCI_QLOGIC_ISP1280: 393 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 394 break; 395 case PCI_QLOGIC_ISP10160: 396 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 397 break; 398 case PCI_QLOGIC_ISP12160: 399 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 400 return (ENXIO); 401 } 402 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 403 break; 404 case PCI_QLOGIC_ISP2100: 405 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 406 break; 407 case PCI_QLOGIC_ISP2200: 408 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 409 break; 410 case PCI_QLOGIC_ISP2300: 411 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 412 break; 413 case PCI_QLOGIC_ISP2312: 414 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 415 break; 416 case PCI_QLOGIC_ISP2322: 417 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 418 break; 419 case PCI_QLOGIC_ISP2422: 420 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 421 break; 422 case PCI_QLOGIC_ISP2432: 423 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 424 break; 425 case PCI_QLOGIC_ISP2532: 426 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 427 break; 428 case PCI_QLOGIC_ISP5432: 429 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 430 break; 431 case PCI_QLOGIC_ISP6312: 432 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 433 break; 434 case PCI_QLOGIC_ISP6322: 435 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 436 break; 437 default: 438 return (ENXIO); 439 } 440 if (isp_announced == 0 && bootverbose) { 441 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 442 "Core Version %d.%d\n", 443 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 444 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 445 isp_announced++; 446 } 447 /* 448 * XXXX: Here is where we might load the f/w module 449 * XXXX: (or increase a reference count to it). 450 */ 451 return (BUS_PROBE_DEFAULT); 452 } 453 454 static void 455 isp_get_generic_options(device_t dev, ispsoftc_t *isp) 456 { 457 int tval; 458 459 /* 460 * Figure out if we're supposed to skip this one. 461 */ 462 tval = 0; 463 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 464 device_printf(dev, "disabled at user request\n"); 465 isp->isp_osinfo.disabled = 1; 466 return; 467 } 468 469 tval = 0; 470 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 471 isp->isp_confopts |= ISP_CFG_NORELOAD; 472 } 473 tval = 0; 474 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 475 isp->isp_confopts |= ISP_CFG_NONVRAM; 476 } 477 tval = 0; 478 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 479 if (tval) { 480 isp->isp_dblev = tval; 481 } else { 482 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 483 } 484 if (bootverbose) { 485 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 486 } 487 tval = -1; 488 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 489 if (tval > 0 && tval < 127) { 490 isp_nvports = tval; 491 } 492 tval = 1; 493 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 494 isp_autoconfig = tval; 495 tval = 7; 496 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 497 isp_quickboot_time = tval; 498 } 499 500 static void 501 isp_get_pci_options(device_t dev, int *m1, int *m2) 502 { 503 int tval; 504 /* 505 * Which we should try first - memory mapping or i/o mapping? 506 * 507 * We used to try memory first followed by i/o on alpha, otherwise 508 * the reverse, but we should just try memory first all the time now. 509 */ 510 *m1 = PCIM_CMD_MEMEN; 511 *m2 = PCIM_CMD_PORTEN; 512 513 tval = 0; 514 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 515 *m1 = PCIM_CMD_PORTEN; 516 *m2 = PCIM_CMD_MEMEN; 517 } 518 tval = 0; 519 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 520 *m1 = PCIM_CMD_MEMEN; 521 *m2 = PCIM_CMD_PORTEN; 522 } 523 } 524 525 static void 526 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 527 { 528 const char *sptr; 529 int tval = 0; 530 531 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 532 if (IS_FC(isp)) { 533 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 534 } else { 535 #ifdef __sparc64__ 536 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 537 #else 538 ISP_SPI_PC(isp, chan)->iid = 7; 539 #endif 540 } 541 } else { 542 if (IS_FC(isp)) { 543 ISP_FC_PC(isp, chan)->default_id = tval - chan; 544 } else { 545 ISP_SPI_PC(isp, chan)->iid = tval; 546 } 547 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 548 } 549 550 tval = -1; 551 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 552 switch (tval) { 553 case ISP_ROLE_NONE: 554 case ISP_ROLE_INITIATOR: 555 case ISP_ROLE_TARGET: 556 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 557 device_printf(dev, "setting role to 0x%x\n", tval); 558 break; 559 default: 560 tval = -1; 561 break; 562 } 563 } 564 if (tval == -1) { 565 tval = ISP_DEFAULT_ROLES; 566 } 567 568 if (IS_SCSI(isp)) { 569 ISP_SPI_PC(isp, chan)->def_role = tval; 570 return; 571 } 572 ISP_FC_PC(isp, chan)->def_role = tval; 573 574 tval = 0; 575 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 576 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 577 } 578 sptr = 0; 579 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", (const char **) &sptr) == 0 && sptr != 0) { 580 if (strcmp(sptr, "lport") == 0) { 581 isp->isp_confopts |= ISP_CFG_LPORT; 582 } else if (strcmp(sptr, "nport") == 0) { 583 isp->isp_confopts |= ISP_CFG_NPORT; 584 } else if (strcmp(sptr, "lport-only") == 0) { 585 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 586 } else if (strcmp(sptr, "nport-only") == 0) { 587 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 588 } 589 } 590 591 /* 592 * Because the resource_*_value functions can neither return 593 * 64 bit integer values, nor can they be directly coerced 594 * to interpret the right hand side of the assignment as 595 * you want them to interpret it, we have to force WWN 596 * hint replacement to specify WWN strings with a leading 597 * 'w' (e..g w50000000aaaa0001). Sigh. 598 */ 599 sptr = 0; 600 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", (const char **) &sptr); 601 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 602 char *eptr = 0; 603 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 604 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 605 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 606 ISP_FC_PC(isp, chan)->def_wwpn = 0; 607 } 608 } 609 610 sptr = 0; 611 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", (const char **) &sptr); 612 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 613 char *eptr = 0; 614 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 615 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 616 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 617 ISP_FC_PC(isp, chan)->def_wwnn = 0; 618 } 619 } 620 621 tval = 0; 622 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 623 if (tval >= 0 && tval < 256) { 624 ISP_FC_PC(isp, chan)->hysteresis = tval; 625 } else { 626 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 627 } 628 629 tval = -1; 630 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 631 if (tval >= 0 && tval < 0xffff) { 632 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 633 } else { 634 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 635 } 636 637 tval = -1; 638 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 639 if (tval >= 0 && tval < 0xffff) { 640 ISP_FC_PC(isp, chan)->gone_device_time = tval; 641 } else { 642 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 643 } 644 } 645 646 static int 647 isp_pci_attach(device_t dev) 648 { 649 int i, m1, m2, locksetup = 0; 650 uint32_t data, cmd, linesz, did; 651 struct isp_pcisoftc *pcs; 652 ispsoftc_t *isp; 653 size_t psize, xsize; 654 char fwname[32]; 655 656 pcs = device_get_softc(dev); 657 if (pcs == NULL) { 658 device_printf(dev, "cannot get softc\n"); 659 return (ENOMEM); 660 } 661 memset(pcs, 0, sizeof (*pcs)); 662 663 pcs->pci_dev = dev; 664 isp = &pcs->pci_isp; 665 isp->isp_dev = dev; 666 isp->isp_nchan = 1; 667 668 /* 669 * Get Generic Options 670 */ 671 isp_nvports = 0; 672 isp_get_generic_options(dev, isp); 673 674 /* 675 * Check to see if options have us disabled 676 */ 677 if (isp->isp_osinfo.disabled) { 678 /* 679 * But return zero to preserve unit numbering 680 */ 681 return (0); 682 } 683 684 /* 685 * Get PCI options- which in this case are just mapping preferences. 686 */ 687 isp_get_pci_options(dev, &m1, &m2); 688 689 linesz = PCI_DFLT_LNSZ; 690 pcs->irq = pcs->regs = NULL; 691 pcs->rgd = pcs->rtp = pcs->iqd = 0; 692 693 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 694 if (cmd & m1) { 695 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 696 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 697 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 698 } 699 if (pcs->regs == NULL && (cmd & m2)) { 700 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 701 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 702 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 703 } 704 if (pcs->regs == NULL) { 705 device_printf(dev, "unable to map any ports\n"); 706 goto bad; 707 } 708 if (bootverbose) { 709 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 710 } 711 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 712 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 713 714 pcs->pci_dev = dev; 715 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 716 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 717 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 718 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 719 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 720 721 switch (pci_get_devid(dev)) { 722 case PCI_QLOGIC_ISP1020: 723 did = 0x1040; 724 isp->isp_mdvec = &mdvec; 725 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 726 break; 727 case PCI_QLOGIC_ISP1080: 728 did = 0x1080; 729 isp->isp_mdvec = &mdvec_1080; 730 isp->isp_type = ISP_HA_SCSI_1080; 731 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 732 break; 733 case PCI_QLOGIC_ISP1240: 734 did = 0x1080; 735 isp->isp_mdvec = &mdvec_1080; 736 isp->isp_type = ISP_HA_SCSI_1240; 737 isp->isp_nchan = 2; 738 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 739 break; 740 case PCI_QLOGIC_ISP1280: 741 did = 0x1080; 742 isp->isp_mdvec = &mdvec_1080; 743 isp->isp_type = ISP_HA_SCSI_1280; 744 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 745 break; 746 case PCI_QLOGIC_ISP10160: 747 did = 0x12160; 748 isp->isp_mdvec = &mdvec_12160; 749 isp->isp_type = ISP_HA_SCSI_10160; 750 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 751 break; 752 case PCI_QLOGIC_ISP12160: 753 did = 0x12160; 754 isp->isp_nchan = 2; 755 isp->isp_mdvec = &mdvec_12160; 756 isp->isp_type = ISP_HA_SCSI_12160; 757 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 758 break; 759 case PCI_QLOGIC_ISP2100: 760 did = 0x2100; 761 isp->isp_mdvec = &mdvec_2100; 762 isp->isp_type = ISP_HA_FC_2100; 763 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 764 if (pci_get_revid(dev) < 3) { 765 /* 766 * XXX: Need to get the actual revision 767 * XXX: number of the 2100 FB. At any rate, 768 * XXX: lower cache line size for early revision 769 * XXX; boards. 770 */ 771 linesz = 1; 772 } 773 break; 774 case PCI_QLOGIC_ISP2200: 775 did = 0x2200; 776 isp->isp_mdvec = &mdvec_2200; 777 isp->isp_type = ISP_HA_FC_2200; 778 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 779 break; 780 case PCI_QLOGIC_ISP2300: 781 did = 0x2300; 782 isp->isp_mdvec = &mdvec_2300; 783 isp->isp_type = ISP_HA_FC_2300; 784 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 785 break; 786 case PCI_QLOGIC_ISP2312: 787 case PCI_QLOGIC_ISP6312: 788 did = 0x2300; 789 isp->isp_mdvec = &mdvec_2300; 790 isp->isp_type = ISP_HA_FC_2312; 791 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 792 break; 793 case PCI_QLOGIC_ISP2322: 794 case PCI_QLOGIC_ISP6322: 795 did = 0x2322; 796 isp->isp_mdvec = &mdvec_2300; 797 isp->isp_type = ISP_HA_FC_2322; 798 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 799 break; 800 case PCI_QLOGIC_ISP2422: 801 case PCI_QLOGIC_ISP2432: 802 did = 0x2400; 803 isp->isp_nchan += isp_nvports; 804 isp->isp_mdvec = &mdvec_2400; 805 isp->isp_type = ISP_HA_FC_2400; 806 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 807 break; 808 case PCI_QLOGIC_ISP2532: 809 did = 0x2500; 810 isp->isp_nchan += isp_nvports; 811 isp->isp_mdvec = &mdvec_2500; 812 isp->isp_type = ISP_HA_FC_2500; 813 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 814 break; 815 case PCI_QLOGIC_ISP5432: 816 did = 0x2500; 817 isp->isp_mdvec = &mdvec_2500; 818 isp->isp_type = ISP_HA_FC_2500; 819 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 820 break; 821 default: 822 device_printf(dev, "unknown device type\n"); 823 goto bad; 824 break; 825 } 826 isp->isp_revision = pci_get_revid(dev); 827 828 if (IS_FC(isp)) { 829 psize = sizeof (fcparam); 830 xsize = sizeof (struct isp_fc); 831 } else { 832 psize = sizeof (sdparam); 833 xsize = sizeof (struct isp_spi); 834 } 835 psize *= isp->isp_nchan; 836 xsize *= isp->isp_nchan; 837 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 838 if (isp->isp_param == NULL) { 839 device_printf(dev, "cannot allocate parameter data\n"); 840 goto bad; 841 } 842 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 843 if (isp->isp_osinfo.pc.ptr == NULL) { 844 device_printf(dev, "cannot allocate parameter data\n"); 845 goto bad; 846 } 847 848 /* 849 * Now that we know who we are (roughly) get/set specific options 850 */ 851 for (i = 0; i < isp->isp_nchan; i++) { 852 isp_get_specific_options(dev, i, isp); 853 } 854 855 /* 856 * The 'it' suffix really only matters for SCSI cards in target mode. 857 */ 858 isp->isp_osinfo.fw = NULL; 859 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 860 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 861 isp->isp_osinfo.fw = firmware_get(fwname); 862 } else if (IS_24XX(isp)) { 863 snprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 864 isp->isp_osinfo.fw = firmware_get(fwname); 865 } 866 if (isp->isp_osinfo.fw == NULL) { 867 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 868 isp->isp_osinfo.fw = firmware_get(fwname); 869 } 870 if (isp->isp_osinfo.fw != NULL) { 871 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname); 872 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 873 } 874 875 /* 876 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 877 */ 878 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 879 if (IS_2300(isp)) { /* per QLogic errata */ 880 cmd &= ~PCIM_CMD_INVEN; 881 } 882 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 883 cmd &= ~PCIM_CMD_INTX_DISABLE; 884 } 885 if (IS_24XX(isp)) { 886 cmd &= ~PCIM_CMD_INTX_DISABLE; 887 } 888 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 889 890 /* 891 * Make sure the Cache Line Size register is set sensibly. 892 */ 893 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 894 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 895 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data); 896 data = linesz; 897 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 898 } 899 900 /* 901 * Make sure the Latency Timer is sane. 902 */ 903 data = pci_read_config(dev, PCIR_LATTIMER, 1); 904 if (data < PCI_DFLT_LTNCY) { 905 data = PCI_DFLT_LTNCY; 906 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data); 907 pci_write_config(dev, PCIR_LATTIMER, data, 1); 908 } 909 910 /* 911 * Make sure we've disabled the ROM. 912 */ 913 data = pci_read_config(dev, PCIR_ROMADDR, 4); 914 data &= ~1; 915 pci_write_config(dev, PCIR_ROMADDR, data, 4); 916 917 /* 918 * Do MSI 919 * 920 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 921 */ 922 if (IS_24XX(isp) || IS_2322(isp)) { 923 pcs->msicount = pci_msi_count(dev); 924 if (pcs->msicount > 1) { 925 pcs->msicount = 1; 926 } 927 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 928 pcs->iqd = 1; 929 } else { 930 pcs->iqd = 0; 931 } 932 } 933 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE); 934 if (pcs->irq == NULL) { 935 device_printf(dev, "could not allocate interrupt\n"); 936 goto bad; 937 } 938 939 /* Make sure the lock is set up. */ 940 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 941 locksetup++; 942 943 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 944 device_printf(dev, "could not setup interrupt\n"); 945 goto bad; 946 } 947 948 /* 949 * Last minute checks... 950 */ 951 if (IS_23XX(isp) || IS_24XX(isp)) { 952 isp->isp_port = pci_get_function(dev); 953 } 954 955 /* 956 * Make sure we're in reset state. 957 */ 958 ISP_LOCK(isp); 959 isp_reset(isp, 1); 960 if (isp->isp_state != ISP_RESETSTATE) { 961 ISP_UNLOCK(isp); 962 goto bad; 963 } 964 isp_init(isp); 965 if (isp->isp_state == ISP_INITSTATE) { 966 isp->isp_state = ISP_RUNSTATE; 967 } 968 ISP_UNLOCK(isp); 969 if (isp_attach(isp)) { 970 ISP_LOCK(isp); 971 isp_uninit(isp); 972 ISP_UNLOCK(isp); 973 goto bad; 974 } 975 return (0); 976 977 bad: 978 if (pcs->ih) { 979 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 980 } 981 if (locksetup) { 982 mtx_destroy(&isp->isp_osinfo.lock); 983 } 984 if (pcs->irq) { 985 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 986 } 987 if (pcs->msicount) { 988 pci_release_msi(dev); 989 } 990 if (pcs->regs) { 991 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 992 } 993 if (pcs->pci_isp.isp_param) { 994 free(pcs->pci_isp.isp_param, M_DEVBUF); 995 pcs->pci_isp.isp_param = NULL; 996 } 997 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 998 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 999 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1000 } 1001 return (ENXIO); 1002 } 1003 1004 static int 1005 isp_pci_detach(device_t dev) 1006 { 1007 struct isp_pcisoftc *pcs; 1008 ispsoftc_t *isp; 1009 int status; 1010 1011 pcs = device_get_softc(dev); 1012 if (pcs == NULL) { 1013 return (ENXIO); 1014 } 1015 isp = (ispsoftc_t *) pcs; 1016 status = isp_detach(isp); 1017 if (status) 1018 return (status); 1019 ISP_LOCK(isp); 1020 isp_uninit(isp); 1021 if (pcs->ih) { 1022 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1023 } 1024 ISP_UNLOCK(isp); 1025 mtx_destroy(&isp->isp_osinfo.lock); 1026 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1027 if (pcs->msicount) { 1028 pci_release_msi(dev); 1029 } 1030 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1031 if (pcs->pci_isp.isp_param) { 1032 free(pcs->pci_isp.isp_param, M_DEVBUF); 1033 pcs->pci_isp.isp_param = NULL; 1034 } 1035 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1036 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1037 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1038 } 1039 return (0); 1040 } 1041 1042 #define IspVirt2Off(a, x) \ 1043 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1044 _BLK_REG_SHFT] + ((x) & 0xfff)) 1045 1046 #define BXR2(isp, off) \ 1047 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1048 #define BXW2(isp, off, v) \ 1049 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1050 #define BXR4(isp, off) \ 1051 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1052 #define BXW4(isp, off, v) \ 1053 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1054 1055 1056 static ISP_INLINE int 1057 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1058 { 1059 uint32_t val0, val1; 1060 int i = 0; 1061 1062 do { 1063 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1064 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1065 } while (val0 != val1 && ++i < 1000); 1066 if (val0 != val1) { 1067 return (1); 1068 } 1069 *rp = val0; 1070 return (0); 1071 } 1072 1073 static int 1074 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1075 { 1076 uint16_t isr, sema; 1077 1078 if (IS_2100(isp)) { 1079 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1080 return (0); 1081 } 1082 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1083 return (0); 1084 } 1085 } else { 1086 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1087 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1088 } 1089 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1090 isr &= INT_PENDING_MASK(isp); 1091 sema &= BIU_SEMA_LOCK; 1092 if (isr == 0 && sema == 0) { 1093 return (0); 1094 } 1095 *isrp = isr; 1096 if ((*semap = sema) != 0) { 1097 if (IS_2100(isp)) { 1098 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1099 return (0); 1100 } 1101 } else { 1102 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1103 } 1104 } 1105 return (1); 1106 } 1107 1108 static int 1109 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1110 { 1111 uint32_t hccr; 1112 uint32_t r2hisr; 1113 1114 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1115 *isrp = 0; 1116 return (0); 1117 } 1118 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1119 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1120 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1121 *isrp = 0; 1122 return (0); 1123 } 1124 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1125 case ISPR2HST_ROM_MBX_OK: 1126 case ISPR2HST_ROM_MBX_FAIL: 1127 case ISPR2HST_MBX_OK: 1128 case ISPR2HST_MBX_FAIL: 1129 case ISPR2HST_ASYNC_EVENT: 1130 *isrp = r2hisr & 0xffff; 1131 *mbox0p = (r2hisr >> 16); 1132 *semap = 1; 1133 return (1); 1134 case ISPR2HST_RIO_16: 1135 *isrp = r2hisr & 0xffff; 1136 *mbox0p = ASYNC_RIO16_1; 1137 *semap = 1; 1138 return (1); 1139 case ISPR2HST_FPOST: 1140 *isrp = r2hisr & 0xffff; 1141 *mbox0p = ASYNC_CMD_CMPLT; 1142 *semap = 1; 1143 return (1); 1144 case ISPR2HST_FPOST_CTIO: 1145 *isrp = r2hisr & 0xffff; 1146 *mbox0p = ASYNC_CTIO_DONE; 1147 *semap = 1; 1148 return (1); 1149 case ISPR2HST_RSPQ_UPDATE: 1150 *isrp = r2hisr & 0xffff; 1151 *mbox0p = 0; 1152 *semap = 0; 1153 return (1); 1154 default: 1155 hccr = ISP_READ(isp, HCCR); 1156 if (hccr & HCCR_PAUSE) { 1157 ISP_WRITE(isp, HCCR, HCCR_RESET); 1158 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1159 ISP_WRITE(isp, BIU_ICR, 0); 1160 } else { 1161 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1162 } 1163 return (0); 1164 } 1165 } 1166 1167 static int 1168 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1169 { 1170 uint32_t r2hisr; 1171 1172 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1173 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1174 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1175 *isrp = 0; 1176 return (0); 1177 } 1178 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1179 case ISP2400R2HST_ROM_MBX_OK: 1180 case ISP2400R2HST_ROM_MBX_FAIL: 1181 case ISP2400R2HST_MBX_OK: 1182 case ISP2400R2HST_MBX_FAIL: 1183 case ISP2400R2HST_ASYNC_EVENT: 1184 *isrp = r2hisr & 0xffff; 1185 *mbox0p = (r2hisr >> 16); 1186 *semap = 1; 1187 return (1); 1188 case ISP2400R2HST_RSPQ_UPDATE: 1189 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1190 case ISP2400R2HST_ATIO_RQST_UPDATE: 1191 *isrp = r2hisr & 0xffff; 1192 *mbox0p = 0; 1193 *semap = 0; 1194 return (1); 1195 default: 1196 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1197 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1198 return (0); 1199 } 1200 } 1201 1202 static uint32_t 1203 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1204 { 1205 uint16_t rv; 1206 int oldconf = 0; 1207 1208 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1209 /* 1210 * We will assume that someone has paused the RISC processor. 1211 */ 1212 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1213 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1214 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1215 } 1216 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1217 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1218 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1219 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1220 } 1221 return (rv); 1222 } 1223 1224 static void 1225 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1226 { 1227 int oldconf = 0; 1228 1229 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1230 /* 1231 * We will assume that someone has paused the RISC processor. 1232 */ 1233 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1234 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1235 oldconf | BIU_PCI_CONF1_SXP); 1236 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1237 } 1238 BXW2(isp, IspVirt2Off(isp, regoff), val); 1239 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1240 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1241 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1242 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1243 } 1244 1245 } 1246 1247 static uint32_t 1248 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1249 { 1250 uint32_t rv, oc = 0; 1251 1252 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1253 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1254 uint32_t tc; 1255 /* 1256 * We will assume that someone has paused the RISC processor. 1257 */ 1258 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1259 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1260 if (regoff & SXP_BANK1_SELECT) 1261 tc |= BIU_PCI1080_CONF1_SXP1; 1262 else 1263 tc |= BIU_PCI1080_CONF1_SXP0; 1264 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1265 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1266 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1267 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1268 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1269 oc | BIU_PCI1080_CONF1_DMA); 1270 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1271 } 1272 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1273 if (oc) { 1274 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1275 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1276 } 1277 return (rv); 1278 } 1279 1280 static void 1281 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1282 { 1283 int oc = 0; 1284 1285 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1286 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1287 uint32_t tc; 1288 /* 1289 * We will assume that someone has paused the RISC processor. 1290 */ 1291 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1292 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1293 if (regoff & SXP_BANK1_SELECT) 1294 tc |= BIU_PCI1080_CONF1_SXP1; 1295 else 1296 tc |= BIU_PCI1080_CONF1_SXP0; 1297 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1298 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1299 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1300 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1301 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1302 oc | BIU_PCI1080_CONF1_DMA); 1303 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1304 } 1305 BXW2(isp, IspVirt2Off(isp, regoff), val); 1306 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1307 if (oc) { 1308 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1309 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1310 } 1311 } 1312 1313 static uint32_t 1314 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1315 { 1316 uint32_t rv; 1317 int block = regoff & _BLK_REG_MASK; 1318 1319 switch (block) { 1320 case BIU_BLOCK: 1321 break; 1322 case MBOX_BLOCK: 1323 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1324 case SXP_BLOCK: 1325 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1326 return (0xffffffff); 1327 case RISC_BLOCK: 1328 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1329 return (0xffffffff); 1330 case DMA_BLOCK: 1331 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1332 return (0xffffffff); 1333 default: 1334 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1335 return (0xffffffff); 1336 } 1337 1338 1339 switch (regoff) { 1340 case BIU2400_FLASH_ADDR: 1341 case BIU2400_FLASH_DATA: 1342 case BIU2400_ICR: 1343 case BIU2400_ISR: 1344 case BIU2400_CSR: 1345 case BIU2400_REQINP: 1346 case BIU2400_REQOUTP: 1347 case BIU2400_RSPINP: 1348 case BIU2400_RSPOUTP: 1349 case BIU2400_PRI_REQINP: 1350 case BIU2400_PRI_REQOUTP: 1351 case BIU2400_ATIO_RSPINP: 1352 case BIU2400_ATIO_RSPOUTP: 1353 case BIU2400_HCCR: 1354 case BIU2400_GPIOD: 1355 case BIU2400_GPIOE: 1356 case BIU2400_HSEMA: 1357 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1358 break; 1359 case BIU2400_R2HSTSLO: 1360 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1361 break; 1362 case BIU2400_R2HSTSHI: 1363 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1364 break; 1365 default: 1366 isp_prt(isp, ISP_LOGERR, 1367 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1368 rv = 0xffffffff; 1369 break; 1370 } 1371 return (rv); 1372 } 1373 1374 static void 1375 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1376 { 1377 int block = regoff & _BLK_REG_MASK; 1378 1379 switch (block) { 1380 case BIU_BLOCK: 1381 break; 1382 case MBOX_BLOCK: 1383 BXW2(isp, IspVirt2Off(isp, regoff), val); 1384 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1385 return; 1386 case SXP_BLOCK: 1387 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1388 return; 1389 case RISC_BLOCK: 1390 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1391 return; 1392 case DMA_BLOCK: 1393 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1394 return; 1395 default: 1396 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1397 regoff); 1398 break; 1399 } 1400 1401 switch (regoff) { 1402 case BIU2400_FLASH_ADDR: 1403 case BIU2400_FLASH_DATA: 1404 case BIU2400_ICR: 1405 case BIU2400_ISR: 1406 case BIU2400_CSR: 1407 case BIU2400_REQINP: 1408 case BIU2400_REQOUTP: 1409 case BIU2400_RSPINP: 1410 case BIU2400_RSPOUTP: 1411 case BIU2400_PRI_REQINP: 1412 case BIU2400_PRI_REQOUTP: 1413 case BIU2400_ATIO_RSPINP: 1414 case BIU2400_ATIO_RSPOUTP: 1415 case BIU2400_HCCR: 1416 case BIU2400_GPIOD: 1417 case BIU2400_GPIOE: 1418 case BIU2400_HSEMA: 1419 BXW4(isp, IspVirt2Off(isp, regoff), val); 1420 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1421 break; 1422 default: 1423 isp_prt(isp, ISP_LOGERR, 1424 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1425 break; 1426 } 1427 } 1428 1429 1430 struct imush { 1431 ispsoftc_t *isp; 1432 caddr_t vbase; 1433 int chan; 1434 int error; 1435 }; 1436 1437 static void imc(void *, bus_dma_segment_t *, int, int); 1438 static void imc1(void *, bus_dma_segment_t *, int, int); 1439 1440 static void 1441 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1442 { 1443 struct imush *imushp = (struct imush *) arg; 1444 1445 if (error) { 1446 imushp->error = error; 1447 return; 1448 } 1449 if (nseg != 1) { 1450 imushp->error = EINVAL; 1451 return; 1452 } 1453 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1454 imushp->isp->isp_rquest = imushp->vbase; 1455 imushp->isp->isp_rquest_dma = segs->ds_addr; 1456 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1457 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1458 imushp->isp->isp_result_dma = segs->ds_addr; 1459 imushp->isp->isp_result = imushp->vbase; 1460 1461 #ifdef ISP_TARGET_MODE 1462 if (IS_24XX(imushp->isp)) { 1463 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1464 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1465 imushp->isp->isp_atioq_dma = segs->ds_addr; 1466 imushp->isp->isp_atioq = imushp->vbase; 1467 } 1468 #endif 1469 } 1470 1471 static void 1472 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1473 { 1474 struct imush *imushp = (struct imush *) arg; 1475 if (error) { 1476 imushp->error = error; 1477 return; 1478 } 1479 if (nseg != 1) { 1480 imushp->error = EINVAL; 1481 return; 1482 } 1483 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1484 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1485 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1486 } 1487 1488 static int 1489 isp_pci_mbxdma(ispsoftc_t *isp) 1490 { 1491 caddr_t base; 1492 uint32_t len; 1493 int i, error, ns, cmap = 0; 1494 bus_size_t slim; /* segment size */ 1495 bus_addr_t llim; /* low limit of unavailable dma */ 1496 bus_addr_t hlim; /* high limit of unavailable dma */ 1497 struct imush im; 1498 1499 /* 1500 * Already been here? If so, leave... 1501 */ 1502 if (isp->isp_rquest) { 1503 return (0); 1504 } 1505 ISP_UNLOCK(isp); 1506 1507 if (isp->isp_maxcmds == 0) { 1508 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1509 ISP_LOCK(isp); 1510 return (1); 1511 } 1512 1513 hlim = BUS_SPACE_MAXADDR; 1514 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1515 if (sizeof (bus_size_t) > 4) { 1516 slim = (bus_size_t) (1ULL << 32); 1517 } else { 1518 slim = (bus_size_t) (1UL << 31); 1519 } 1520 llim = BUS_SPACE_MAXADDR; 1521 } else { 1522 llim = BUS_SPACE_MAXADDR_32BIT; 1523 slim = (1UL << 24); 1524 } 1525 1526 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1527 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1528 if (isp->isp_osinfo.pcmd_pool == NULL) { 1529 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1530 ISP_LOCK(isp); 1531 return (1); 1532 } 1533 1534 /* 1535 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1536 */ 1537 #ifdef ISP_TARGET_MODE 1538 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1539 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1540 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1541 ISP_LOCK(isp); 1542 return (1); 1543 } 1544 #endif 1545 1546 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) { 1547 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1548 ISP_LOCK(isp); 1549 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1550 return (1); 1551 } 1552 1553 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1554 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1555 if (isp->isp_xflist == NULL) { 1556 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1557 ISP_LOCK(isp); 1558 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1559 return (1); 1560 } 1561 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1562 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1563 } 1564 isp->isp_xffree = isp->isp_xflist; 1565 #ifdef ISP_TARGET_MODE 1566 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1567 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1568 if (isp->isp_tgtlist == NULL) { 1569 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1570 free(isp->isp_xflist, M_DEVBUF); 1571 ISP_LOCK(isp); 1572 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1573 return (1); 1574 } 1575 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1576 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1577 } 1578 isp->isp_tgtfree = isp->isp_tgtlist; 1579 #endif 1580 1581 /* 1582 * Allocate and map the request and result queues (and ATIO queue 1583 * if we're a 2400 supporting target mode). 1584 */ 1585 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1586 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1587 #ifdef ISP_TARGET_MODE 1588 if (IS_24XX(isp)) { 1589 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1590 } 1591 #endif 1592 1593 ns = (len / PAGE_SIZE) + 1; 1594 1595 /* 1596 * Create a tag for the control spaces. We don't always need this 1597 * to be 32 bits, but we do this for simplicity and speed's sake. 1598 */ 1599 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) { 1600 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1601 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1602 free(isp->isp_xflist, M_DEVBUF); 1603 #ifdef ISP_TARGET_MODE 1604 free(isp->isp_tgtlist, M_DEVBUF); 1605 #endif 1606 ISP_LOCK(isp); 1607 return (1); 1608 } 1609 1610 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1611 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1612 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1613 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1614 free(isp->isp_xflist, M_DEVBUF); 1615 #ifdef ISP_TARGET_MODE 1616 free(isp->isp_tgtlist, M_DEVBUF); 1617 #endif 1618 ISP_LOCK(isp); 1619 return (1); 1620 } 1621 1622 im.isp = isp; 1623 im.chan = 0; 1624 im.vbase = base; 1625 im.error = 0; 1626 1627 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1628 if (im.error) { 1629 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1630 goto bad; 1631 } 1632 1633 if (IS_FC(isp)) { 1634 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1635 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1636 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1637 goto bad; 1638 } 1639 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1640 bus_dma_tag_destroy(fc->tdmat); 1641 goto bad; 1642 } 1643 im.isp = isp; 1644 im.chan = cmap; 1645 im.vbase = base; 1646 im.error = 0; 1647 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1648 if (im.error) { 1649 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1650 bus_dma_tag_destroy(fc->tdmat); 1651 goto bad; 1652 } 1653 } 1654 } 1655 1656 for (i = 0; i < isp->isp_maxcmds; i++) { 1657 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1658 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1659 if (error) { 1660 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1661 while (--i >= 0) { 1662 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1663 } 1664 goto bad; 1665 } 1666 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1667 if (i == isp->isp_maxcmds-1) { 1668 pcmd->next = NULL; 1669 } else { 1670 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1671 } 1672 } 1673 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1674 ISP_LOCK(isp); 1675 return (0); 1676 1677 bad: 1678 while (--cmap >= 0) { 1679 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1680 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1681 bus_dma_tag_destroy(fc->tdmat); 1682 } 1683 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1684 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1685 free(isp->isp_xflist, M_DEVBUF); 1686 #ifdef ISP_TARGET_MODE 1687 free(isp->isp_tgtlist, M_DEVBUF); 1688 #endif 1689 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1690 isp->isp_rquest = NULL; 1691 ISP_LOCK(isp); 1692 return (1); 1693 } 1694 1695 typedef struct { 1696 ispsoftc_t *isp; 1697 void *cmd_token; 1698 void *rq; /* original request */ 1699 int error; 1700 bus_size_t mapsize; 1701 } mush_t; 1702 1703 #define MUSHERR_NOQENTRIES -2 1704 1705 #ifdef ISP_TARGET_MODE 1706 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1707 static void tdma2(void *, bus_dma_segment_t *, int, int); 1708 1709 static void 1710 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1711 { 1712 mush_t *mp; 1713 mp = (mush_t *)arg; 1714 mp->mapsize = mapsize; 1715 tdma2(arg, dm_segs, nseg, error); 1716 } 1717 1718 static void 1719 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1720 { 1721 mush_t *mp; 1722 ispsoftc_t *isp; 1723 struct ccb_scsiio *csio; 1724 isp_ddir_t ddir; 1725 ispreq_t *rq; 1726 1727 mp = (mush_t *) arg; 1728 if (error) { 1729 mp->error = error; 1730 return; 1731 } 1732 csio = mp->cmd_token; 1733 isp = mp->isp; 1734 rq = mp->rq; 1735 if (nseg) { 1736 if (sizeof (bus_addr_t) > 4) { 1737 if (nseg >= ISP_NSEG64_MAX) { 1738 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1739 mp->error = EFAULT; 1740 return; 1741 } 1742 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1743 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1744 } 1745 } else { 1746 if (nseg >= ISP_NSEG_MAX) { 1747 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1748 mp->error = EFAULT; 1749 return; 1750 } 1751 } 1752 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1753 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1754 ddir = ISP_TO_DEVICE; 1755 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1756 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1757 ddir = ISP_FROM_DEVICE; 1758 } else { 1759 dm_segs = NULL; 1760 nseg = 0; 1761 ddir = ISP_NOXFR; 1762 } 1763 } else { 1764 dm_segs = NULL; 1765 nseg = 0; 1766 ddir = ISP_NOXFR; 1767 } 1768 1769 if (isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len) != CMD_QUEUED) { 1770 mp->error = MUSHERR_NOQENTRIES; 1771 } 1772 } 1773 #endif 1774 1775 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1776 static void dma2(void *, bus_dma_segment_t *, int, int); 1777 1778 static void 1779 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1780 { 1781 mush_t *mp; 1782 mp = (mush_t *)arg; 1783 mp->mapsize = mapsize; 1784 dma2(arg, dm_segs, nseg, error); 1785 } 1786 1787 static void 1788 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1789 { 1790 mush_t *mp; 1791 ispsoftc_t *isp; 1792 struct ccb_scsiio *csio; 1793 isp_ddir_t ddir; 1794 ispreq_t *rq; 1795 1796 mp = (mush_t *) arg; 1797 if (error) { 1798 mp->error = error; 1799 return; 1800 } 1801 csio = mp->cmd_token; 1802 isp = mp->isp; 1803 rq = mp->rq; 1804 if (nseg) { 1805 if (sizeof (bus_addr_t) > 4) { 1806 if (nseg >= ISP_NSEG64_MAX) { 1807 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1808 mp->error = EFAULT; 1809 return; 1810 } 1811 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1812 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1813 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1814 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1815 } 1816 } else { 1817 if (nseg >= ISP_NSEG_MAX) { 1818 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1819 mp->error = EFAULT; 1820 return; 1821 } 1822 } 1823 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1824 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1825 ddir = ISP_FROM_DEVICE; 1826 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1827 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1828 ddir = ISP_TO_DEVICE; 1829 } else { 1830 ddir = ISP_NOXFR; 1831 } 1832 } else { 1833 dm_segs = NULL; 1834 nseg = 0; 1835 ddir = ISP_NOXFR; 1836 } 1837 1838 if (isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir) != CMD_QUEUED) { 1839 mp->error = MUSHERR_NOQENTRIES; 1840 } 1841 } 1842 1843 static int 1844 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1845 { 1846 mush_t mush, *mp; 1847 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1848 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1849 1850 mp = &mush; 1851 mp->isp = isp; 1852 mp->cmd_token = csio; 1853 mp->rq = ff; 1854 mp->error = 0; 1855 mp->mapsize = 0; 1856 1857 #ifdef ISP_TARGET_MODE 1858 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1859 eptr = tdma2; 1860 eptr2 = tdma2_2; 1861 } else 1862 #endif 1863 { 1864 eptr = dma2; 1865 eptr2 = dma2_2; 1866 } 1867 1868 1869 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) { 1870 (*eptr)(mp, NULL, 0, 0); 1871 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1872 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1873 int error; 1874 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1875 #if 0 1876 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error); 1877 #endif 1878 1879 if (error == EINPROGRESS) { 1880 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1881 mp->error = EINVAL; 1882 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1883 } else if (error && mp->error == 0) { 1884 #ifdef DIAGNOSTIC 1885 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1886 #endif 1887 mp->error = error; 1888 } 1889 } else { 1890 /* Pointer to physical buffer */ 1891 struct bus_dma_segment seg; 1892 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 1893 seg.ds_len = csio->dxfer_len; 1894 (*eptr)(mp, &seg, 1, 0); 1895 } 1896 } else { 1897 struct bus_dma_segment *segs; 1898 1899 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1900 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported"); 1901 mp->error = EINVAL; 1902 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1903 struct uio sguio; 1904 int error; 1905 1906 /* 1907 * We're taking advantage of the fact that 1908 * the pointer/length sizes and layout of the iovec 1909 * structure are the same as the bus_dma_segment 1910 * structure. This might be a little dangerous, 1911 * but only if they change the structures, which 1912 * seems unlikely. 1913 */ 1914 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) && 1915 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) && 1916 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed")); 1917 sguio.uio_iov = (struct iovec *)csio->data_ptr; 1918 sguio.uio_iovcnt = csio->sglist_cnt; 1919 sguio.uio_resid = csio->dxfer_len; 1920 sguio.uio_segflg = UIO_SYSSPACE; 1921 1922 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0); 1923 1924 if (error != 0 && mp->error == 0) { 1925 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1926 mp->error = error; 1927 } 1928 } else { 1929 /* Just use the segments provided */ 1930 segs = (struct bus_dma_segment *) csio->data_ptr; 1931 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1932 } 1933 } 1934 if (mp->error) { 1935 int retval = CMD_COMPLETE; 1936 if (mp->error == MUSHERR_NOQENTRIES) { 1937 retval = CMD_EAGAIN; 1938 } else if (mp->error == EFBIG) { 1939 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1940 } else if (mp->error == EINVAL) { 1941 XS_SETERR(csio, CAM_REQ_INVALID); 1942 } else { 1943 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1944 } 1945 return (retval); 1946 } 1947 return (CMD_QUEUED); 1948 } 1949 1950 static void 1951 isp_pci_reset0(ispsoftc_t *isp) 1952 { 1953 ISP_DISABLE_INTS(isp); 1954 } 1955 1956 static void 1957 isp_pci_reset1(ispsoftc_t *isp) 1958 { 1959 if (!IS_24XX(isp)) { 1960 /* Make sure the BIOS is disabled */ 1961 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1962 } 1963 /* and enable interrupts */ 1964 ISP_ENABLE_INTS(isp); 1965 } 1966 1967 static void 1968 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1969 { 1970 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1971 if (msg) 1972 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1973 else 1974 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1975 if (IS_SCSI(isp)) 1976 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1977 else 1978 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1979 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1980 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1981 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1982 1983 1984 if (IS_SCSI(isp)) { 1985 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1986 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1987 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1988 ISP_READ(isp, CDMA_FIFO_STS)); 1989 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1990 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1991 ISP_READ(isp, DDMA_FIFO_STS)); 1992 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1993 ISP_READ(isp, SXP_INTERRUPT), 1994 ISP_READ(isp, SXP_GROSS_ERR), 1995 ISP_READ(isp, SXP_PINS_CTRL)); 1996 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1997 } 1998 printf(" mbox regs: %x %x %x %x %x\n", 1999 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2000 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2001 ISP_READ(isp, OUTMAILBOX4)); 2002 printf(" PCI Status Command/Status=%x\n", 2003 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2004 } 2005