1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2018 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 1997-2008 by Matthew Jacob 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 /* 30 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 31 * FreeBSD Version. 32 */ 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/linker.h> 41 #include <sys/firmware.h> 42 #include <sys/bus.h> 43 #include <sys/stdint.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <sys/rman.h> 49 #include <sys/malloc.h> 50 #include <sys/uio.h> 51 #include <dev/isp/isp_freebsd.h> 52 53 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 54 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 55 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 56 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 57 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 58 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 59 static uint32_t isp_pci_rd_reg_2600(ispsoftc_t *, int); 60 static void isp_pci_wr_reg_2600(ispsoftc_t *, int, uint32_t); 61 static void isp_pci_run_isr(ispsoftc_t *); 62 static void isp_pci_run_isr_2300(ispsoftc_t *); 63 static void isp_pci_run_isr_2400(ispsoftc_t *); 64 static int isp_pci_mbxdma(ispsoftc_t *); 65 static void isp_pci_mbxdmafree(ispsoftc_t *); 66 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 67 static int isp_pci_irqsetup(ispsoftc_t *); 68 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 69 70 static struct ispmdvec mdvec = { 71 isp_pci_run_isr, 72 isp_pci_rd_reg, 73 isp_pci_wr_reg, 74 isp_pci_mbxdma, 75 isp_pci_dmasetup, 76 isp_common_dmateardown, 77 isp_pci_irqsetup, 78 isp_pci_dumpregs, 79 NULL, 80 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 81 }; 82 83 static struct ispmdvec mdvec_1080 = { 84 isp_pci_run_isr, 85 isp_pci_rd_reg_1080, 86 isp_pci_wr_reg_1080, 87 isp_pci_mbxdma, 88 isp_pci_dmasetup, 89 isp_common_dmateardown, 90 isp_pci_irqsetup, 91 isp_pci_dumpregs, 92 NULL, 93 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 94 }; 95 96 static struct ispmdvec mdvec_12160 = { 97 isp_pci_run_isr, 98 isp_pci_rd_reg_1080, 99 isp_pci_wr_reg_1080, 100 isp_pci_mbxdma, 101 isp_pci_dmasetup, 102 isp_common_dmateardown, 103 isp_pci_irqsetup, 104 isp_pci_dumpregs, 105 NULL, 106 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 107 }; 108 109 static struct ispmdvec mdvec_2100 = { 110 isp_pci_run_isr, 111 isp_pci_rd_reg, 112 isp_pci_wr_reg, 113 isp_pci_mbxdma, 114 isp_pci_dmasetup, 115 isp_common_dmateardown, 116 isp_pci_irqsetup, 117 isp_pci_dumpregs 118 }; 119 120 static struct ispmdvec mdvec_2200 = { 121 isp_pci_run_isr, 122 isp_pci_rd_reg, 123 isp_pci_wr_reg, 124 isp_pci_mbxdma, 125 isp_pci_dmasetup, 126 isp_common_dmateardown, 127 isp_pci_irqsetup, 128 isp_pci_dumpregs 129 }; 130 131 static struct ispmdvec mdvec_2300 = { 132 isp_pci_run_isr_2300, 133 isp_pci_rd_reg, 134 isp_pci_wr_reg, 135 isp_pci_mbxdma, 136 isp_pci_dmasetup, 137 isp_common_dmateardown, 138 isp_pci_irqsetup, 139 isp_pci_dumpregs 140 }; 141 142 static struct ispmdvec mdvec_2400 = { 143 isp_pci_run_isr_2400, 144 isp_pci_rd_reg_2400, 145 isp_pci_wr_reg_2400, 146 isp_pci_mbxdma, 147 isp_pci_dmasetup, 148 isp_common_dmateardown, 149 isp_pci_irqsetup, 150 NULL 151 }; 152 153 static struct ispmdvec mdvec_2500 = { 154 isp_pci_run_isr_2400, 155 isp_pci_rd_reg_2400, 156 isp_pci_wr_reg_2400, 157 isp_pci_mbxdma, 158 isp_pci_dmasetup, 159 isp_common_dmateardown, 160 isp_pci_irqsetup, 161 NULL 162 }; 163 164 static struct ispmdvec mdvec_2600 = { 165 isp_pci_run_isr_2400, 166 isp_pci_rd_reg_2600, 167 isp_pci_wr_reg_2600, 168 isp_pci_mbxdma, 169 isp_pci_dmasetup, 170 isp_common_dmateardown, 171 isp_pci_irqsetup, 172 NULL 173 }; 174 175 static struct ispmdvec mdvec_2700 = { 176 isp_pci_run_isr_2400, 177 isp_pci_rd_reg_2600, 178 isp_pci_wr_reg_2600, 179 isp_pci_mbxdma, 180 isp_pci_dmasetup, 181 isp_common_dmateardown, 182 isp_pci_irqsetup, 183 NULL 184 }; 185 186 #ifndef PCIM_CMD_INVEN 187 #define PCIM_CMD_INVEN 0x10 188 #endif 189 #ifndef PCIM_CMD_BUSMASTEREN 190 #define PCIM_CMD_BUSMASTEREN 0x0004 191 #endif 192 #ifndef PCIM_CMD_PERRESPEN 193 #define PCIM_CMD_PERRESPEN 0x0040 194 #endif 195 #ifndef PCIM_CMD_SEREN 196 #define PCIM_CMD_SEREN 0x0100 197 #endif 198 #ifndef PCIM_CMD_INTX_DISABLE 199 #define PCIM_CMD_INTX_DISABLE 0x0400 200 #endif 201 202 #ifndef PCIR_COMMAND 203 #define PCIR_COMMAND 0x04 204 #endif 205 206 #ifndef PCIR_CACHELNSZ 207 #define PCIR_CACHELNSZ 0x0c 208 #endif 209 210 #ifndef PCIR_LATTIMER 211 #define PCIR_LATTIMER 0x0d 212 #endif 213 214 #ifndef PCIR_ROMADDR 215 #define PCIR_ROMADDR 0x30 216 #endif 217 218 #define PCI_VENDOR_QLOGIC 0x1077 219 220 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 221 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 222 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 223 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 224 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 225 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 226 227 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 228 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 229 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 230 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 231 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 232 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 233 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 234 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 235 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 236 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 237 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 238 #define PCI_PRODUCT_QLOGIC_ISP2031 0x2031 239 #define PCI_PRODUCT_QLOGIC_ISP8031 0x8031 240 #define PCI_PRODUCT_QLOGIC_ISP2684 0x2171 241 #define PCI_PRODUCT_QLOGIC_ISP2692 0x2b61 242 #define PCI_PRODUCT_QLOGIC_ISP2714 0x2071 243 #define PCI_PRODUCT_QLOGIC_ISP2722 0x2261 244 245 #define PCI_QLOGIC_ISP1020 \ 246 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 247 #define PCI_QLOGIC_ISP1080 \ 248 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 249 #define PCI_QLOGIC_ISP10160 \ 250 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 251 #define PCI_QLOGIC_ISP12160 \ 252 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 253 #define PCI_QLOGIC_ISP1240 \ 254 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 255 #define PCI_QLOGIC_ISP1280 \ 256 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 257 258 #define PCI_QLOGIC_ISP2100 \ 259 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 260 #define PCI_QLOGIC_ISP2200 \ 261 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 262 #define PCI_QLOGIC_ISP2300 \ 263 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 264 #define PCI_QLOGIC_ISP2312 \ 265 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 266 #define PCI_QLOGIC_ISP2322 \ 267 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 268 #define PCI_QLOGIC_ISP2422 \ 269 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 270 #define PCI_QLOGIC_ISP2432 \ 271 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 272 #define PCI_QLOGIC_ISP2532 \ 273 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 274 #define PCI_QLOGIC_ISP5432 \ 275 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 276 #define PCI_QLOGIC_ISP6312 \ 277 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 278 #define PCI_QLOGIC_ISP6322 \ 279 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 280 #define PCI_QLOGIC_ISP2031 \ 281 ((PCI_PRODUCT_QLOGIC_ISP2031 << 16) | PCI_VENDOR_QLOGIC) 282 #define PCI_QLOGIC_ISP8031 \ 283 ((PCI_PRODUCT_QLOGIC_ISP8031 << 16) | PCI_VENDOR_QLOGIC) 284 #define PCI_QLOGIC_ISP2684 \ 285 ((PCI_PRODUCT_QLOGIC_ISP2684 << 16) | PCI_VENDOR_QLOGIC) 286 #define PCI_QLOGIC_ISP2692 \ 287 ((PCI_PRODUCT_QLOGIC_ISP2692 << 16) | PCI_VENDOR_QLOGIC) 288 #define PCI_QLOGIC_ISP2714 \ 289 ((PCI_PRODUCT_QLOGIC_ISP2714 << 16) | PCI_VENDOR_QLOGIC) 290 #define PCI_QLOGIC_ISP2722 \ 291 ((PCI_PRODUCT_QLOGIC_ISP2722 << 16) | PCI_VENDOR_QLOGIC) 292 293 /* 294 * Odd case for some AMI raid cards... We need to *not* attach to this. 295 */ 296 #define AMI_RAID_SUBVENDOR_ID 0x101e 297 298 #define PCI_DFLT_LTNCY 0x40 299 #define PCI_DFLT_LNSZ 0x10 300 301 static int isp_pci_probe (device_t); 302 static int isp_pci_attach (device_t); 303 static int isp_pci_detach (device_t); 304 305 306 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 307 struct isp_pcisoftc { 308 ispsoftc_t pci_isp; 309 device_t pci_dev; 310 struct resource * regs; 311 struct resource * regs1; 312 struct resource * regs2; 313 struct { 314 int iqd; 315 struct resource * irq; 316 void * ih; 317 } irq[ISP_MAX_IRQS]; 318 int rtp; 319 int rgd; 320 int rtp1; 321 int rgd1; 322 int rtp2; 323 int rgd2; 324 int16_t pci_poff[_NREG_BLKS]; 325 bus_dma_tag_t dmat; 326 int msicount; 327 }; 328 329 330 static device_method_t isp_pci_methods[] = { 331 /* Device interface */ 332 DEVMETHOD(device_probe, isp_pci_probe), 333 DEVMETHOD(device_attach, isp_pci_attach), 334 DEVMETHOD(device_detach, isp_pci_detach), 335 { 0, 0 } 336 }; 337 338 static driver_t isp_pci_driver = { 339 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 340 }; 341 static devclass_t isp_devclass; 342 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 343 MODULE_DEPEND(isp, cam, 1, 1, 1); 344 MODULE_DEPEND(isp, firmware, 1, 1, 1); 345 static int isp_nvports = 0; 346 347 static int 348 isp_pci_probe(device_t dev) 349 { 350 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 351 case PCI_QLOGIC_ISP1020: 352 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 353 break; 354 case PCI_QLOGIC_ISP1080: 355 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 356 break; 357 case PCI_QLOGIC_ISP1240: 358 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 359 break; 360 case PCI_QLOGIC_ISP1280: 361 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 362 break; 363 case PCI_QLOGIC_ISP10160: 364 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 365 break; 366 case PCI_QLOGIC_ISP12160: 367 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 368 return (ENXIO); 369 } 370 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 371 break; 372 case PCI_QLOGIC_ISP2100: 373 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 374 break; 375 case PCI_QLOGIC_ISP2200: 376 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 377 break; 378 case PCI_QLOGIC_ISP2300: 379 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 380 break; 381 case PCI_QLOGIC_ISP2312: 382 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 383 break; 384 case PCI_QLOGIC_ISP2322: 385 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 386 break; 387 case PCI_QLOGIC_ISP2422: 388 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 389 break; 390 case PCI_QLOGIC_ISP2432: 391 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 392 break; 393 case PCI_QLOGIC_ISP2532: 394 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 395 break; 396 case PCI_QLOGIC_ISP5432: 397 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 398 break; 399 case PCI_QLOGIC_ISP6312: 400 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 401 break; 402 case PCI_QLOGIC_ISP6322: 403 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 404 break; 405 case PCI_QLOGIC_ISP2031: 406 device_set_desc(dev, "Qlogic ISP 2031 PCI FC-AL Adapter"); 407 break; 408 case PCI_QLOGIC_ISP8031: 409 device_set_desc(dev, "Qlogic ISP 8031 PCI FCoE Adapter"); 410 break; 411 case PCI_QLOGIC_ISP2684: 412 device_set_desc(dev, "Qlogic ISP 2684 PCI FC Adapter"); 413 break; 414 case PCI_QLOGIC_ISP2692: 415 device_set_desc(dev, "Qlogic ISP 2692 PCI FC Adapter"); 416 break; 417 case PCI_QLOGIC_ISP2714: 418 device_set_desc(dev, "Qlogic ISP 2714 PCI FC Adapter"); 419 break; 420 case PCI_QLOGIC_ISP2722: 421 device_set_desc(dev, "Qlogic ISP 2722 PCI FC Adapter"); 422 break; 423 default: 424 return (ENXIO); 425 } 426 if (isp_announced == 0 && bootverbose) { 427 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 428 "Core Version %d.%d\n", 429 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 430 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 431 isp_announced++; 432 } 433 /* 434 * XXXX: Here is where we might load the f/w module 435 * XXXX: (or increase a reference count to it). 436 */ 437 return (BUS_PROBE_DEFAULT); 438 } 439 440 static void 441 isp_get_generic_options(device_t dev, ispsoftc_t *isp) 442 { 443 int tval; 444 445 tval = 0; 446 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 447 isp->isp_confopts |= ISP_CFG_NORELOAD; 448 } 449 tval = 0; 450 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 451 isp->isp_confopts |= ISP_CFG_NONVRAM; 452 } 453 tval = 0; 454 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 455 if (tval) { 456 isp->isp_dblev = tval; 457 } else { 458 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 459 } 460 if (bootverbose) { 461 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 462 } 463 tval = -1; 464 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 465 if (tval > 0 && tval <= 254) { 466 isp_nvports = tval; 467 } 468 tval = 7; 469 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 470 isp_quickboot_time = tval; 471 } 472 473 static void 474 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 475 { 476 const char *sptr; 477 int tval = 0; 478 char prefix[12], name[16]; 479 480 if (chan == 0) 481 prefix[0] = 0; 482 else 483 snprintf(prefix, sizeof(prefix), "chan%d.", chan); 484 snprintf(name, sizeof(name), "%siid", prefix); 485 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 486 name, &tval)) { 487 if (IS_FC(isp)) { 488 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 489 } else { 490 ISP_SPI_PC(isp, chan)->iid = 7; 491 } 492 } else { 493 if (IS_FC(isp)) { 494 ISP_FC_PC(isp, chan)->default_id = tval - chan; 495 } else { 496 ISP_SPI_PC(isp, chan)->iid = tval; 497 } 498 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 499 } 500 501 if (IS_SCSI(isp)) 502 return; 503 504 tval = -1; 505 snprintf(name, sizeof(name), "%srole", prefix); 506 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 507 name, &tval) == 0) { 508 switch (tval) { 509 case ISP_ROLE_NONE: 510 case ISP_ROLE_INITIATOR: 511 case ISP_ROLE_TARGET: 512 case ISP_ROLE_BOTH: 513 device_printf(dev, "Chan %d setting role to 0x%x\n", chan, tval); 514 break; 515 default: 516 tval = -1; 517 break; 518 } 519 } 520 if (tval == -1) { 521 tval = ISP_DEFAULT_ROLES; 522 } 523 ISP_FC_PC(isp, chan)->def_role = tval; 524 525 tval = 0; 526 snprintf(name, sizeof(name), "%sfullduplex", prefix); 527 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 528 name, &tval) == 0 && tval != 0) { 529 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 530 } 531 sptr = NULL; 532 snprintf(name, sizeof(name), "%stopology", prefix); 533 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 534 name, (const char **) &sptr) == 0 && sptr != NULL) { 535 if (strcmp(sptr, "lport") == 0) { 536 isp->isp_confopts |= ISP_CFG_LPORT; 537 } else if (strcmp(sptr, "nport") == 0) { 538 isp->isp_confopts |= ISP_CFG_NPORT; 539 } else if (strcmp(sptr, "lport-only") == 0) { 540 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 541 } else if (strcmp(sptr, "nport-only") == 0) { 542 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 543 } 544 } 545 546 #ifdef ISP_FCTAPE_OFF 547 isp->isp_confopts |= ISP_CFG_NOFCTAPE; 548 #else 549 isp->isp_confopts |= ISP_CFG_FCTAPE; 550 #endif 551 552 tval = 0; 553 snprintf(name, sizeof(name), "%snofctape", prefix); 554 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 555 name, &tval); 556 if (tval) { 557 isp->isp_confopts &= ~ISP_CFG_FCTAPE; 558 isp->isp_confopts |= ISP_CFG_NOFCTAPE; 559 } 560 561 tval = 0; 562 snprintf(name, sizeof(name), "%sfctape", prefix); 563 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 564 name, &tval); 565 if (tval) { 566 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE; 567 isp->isp_confopts |= ISP_CFG_FCTAPE; 568 } 569 570 571 /* 572 * Because the resource_*_value functions can neither return 573 * 64 bit integer values, nor can they be directly coerced 574 * to interpret the right hand side of the assignment as 575 * you want them to interpret it, we have to force WWN 576 * hint replacement to specify WWN strings with a leading 577 * 'w' (e..g w50000000aaaa0001). Sigh. 578 */ 579 sptr = NULL; 580 snprintf(name, sizeof(name), "%sportwwn", prefix); 581 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 582 name, (const char **) &sptr); 583 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 584 char *eptr = NULL; 585 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 586 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 587 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 588 ISP_FC_PC(isp, chan)->def_wwpn = 0; 589 } 590 } 591 592 sptr = NULL; 593 snprintf(name, sizeof(name), "%snodewwn", prefix); 594 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 595 name, (const char **) &sptr); 596 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 597 char *eptr = NULL; 598 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 599 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 600 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 601 ISP_FC_PC(isp, chan)->def_wwnn = 0; 602 } 603 } 604 605 tval = -1; 606 snprintf(name, sizeof(name), "%sloop_down_limit", prefix); 607 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 608 name, &tval); 609 if (tval >= 0 && tval < 0xffff) { 610 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 611 } else { 612 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 613 } 614 615 tval = -1; 616 snprintf(name, sizeof(name), "%sgone_device_time", prefix); 617 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 618 name, &tval); 619 if (tval >= 0 && tval < 0xffff) { 620 ISP_FC_PC(isp, chan)->gone_device_time = tval; 621 } else { 622 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 623 } 624 } 625 626 static int 627 isp_pci_attach(device_t dev) 628 { 629 struct isp_pcisoftc *pcs = device_get_softc(dev); 630 ispsoftc_t *isp = &pcs->pci_isp; 631 int i; 632 uint32_t data, cmd, linesz, did; 633 size_t psize, xsize; 634 char fwname[32]; 635 636 pcs->pci_dev = dev; 637 isp->isp_dev = dev; 638 isp->isp_nchan = 1; 639 mtx_init(&isp->isp_lock, "isp", NULL, MTX_DEF); 640 641 /* 642 * Get Generic Options 643 */ 644 isp_nvports = 0; 645 isp_get_generic_options(dev, isp); 646 647 linesz = PCI_DFLT_LNSZ; 648 pcs->regs = pcs->regs2 = NULL; 649 pcs->rgd = pcs->rtp = 0; 650 651 pcs->pci_dev = dev; 652 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 653 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 654 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 655 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 656 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 657 658 switch (pci_get_devid(dev)) { 659 case PCI_QLOGIC_ISP1020: 660 did = 0x1040; 661 isp->isp_mdvec = &mdvec; 662 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 663 break; 664 case PCI_QLOGIC_ISP1080: 665 did = 0x1080; 666 isp->isp_mdvec = &mdvec_1080; 667 isp->isp_type = ISP_HA_SCSI_1080; 668 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 669 break; 670 case PCI_QLOGIC_ISP1240: 671 did = 0x1080; 672 isp->isp_mdvec = &mdvec_1080; 673 isp->isp_type = ISP_HA_SCSI_1240; 674 isp->isp_nchan = 2; 675 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 676 break; 677 case PCI_QLOGIC_ISP1280: 678 did = 0x1080; 679 isp->isp_mdvec = &mdvec_1080; 680 isp->isp_type = ISP_HA_SCSI_1280; 681 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 682 break; 683 case PCI_QLOGIC_ISP10160: 684 did = 0x12160; 685 isp->isp_mdvec = &mdvec_12160; 686 isp->isp_type = ISP_HA_SCSI_10160; 687 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 688 break; 689 case PCI_QLOGIC_ISP12160: 690 did = 0x12160; 691 isp->isp_nchan = 2; 692 isp->isp_mdvec = &mdvec_12160; 693 isp->isp_type = ISP_HA_SCSI_12160; 694 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 695 break; 696 case PCI_QLOGIC_ISP2100: 697 did = 0x2100; 698 isp->isp_mdvec = &mdvec_2100; 699 isp->isp_type = ISP_HA_FC_2100; 700 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 701 if (pci_get_revid(dev) < 3) { 702 /* 703 * XXX: Need to get the actual revision 704 * XXX: number of the 2100 FB. At any rate, 705 * XXX: lower cache line size for early revision 706 * XXX; boards. 707 */ 708 linesz = 1; 709 } 710 break; 711 case PCI_QLOGIC_ISP2200: 712 did = 0x2200; 713 isp->isp_mdvec = &mdvec_2200; 714 isp->isp_type = ISP_HA_FC_2200; 715 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 716 break; 717 case PCI_QLOGIC_ISP2300: 718 did = 0x2300; 719 isp->isp_mdvec = &mdvec_2300; 720 isp->isp_type = ISP_HA_FC_2300; 721 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 722 break; 723 case PCI_QLOGIC_ISP2312: 724 case PCI_QLOGIC_ISP6312: 725 did = 0x2300; 726 isp->isp_mdvec = &mdvec_2300; 727 isp->isp_type = ISP_HA_FC_2312; 728 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 729 break; 730 case PCI_QLOGIC_ISP2322: 731 case PCI_QLOGIC_ISP6322: 732 did = 0x2322; 733 isp->isp_mdvec = &mdvec_2300; 734 isp->isp_type = ISP_HA_FC_2322; 735 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 736 break; 737 case PCI_QLOGIC_ISP2422: 738 case PCI_QLOGIC_ISP2432: 739 did = 0x2400; 740 isp->isp_nchan += isp_nvports; 741 isp->isp_mdvec = &mdvec_2400; 742 isp->isp_type = ISP_HA_FC_2400; 743 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 744 break; 745 case PCI_QLOGIC_ISP2532: 746 did = 0x2500; 747 isp->isp_nchan += isp_nvports; 748 isp->isp_mdvec = &mdvec_2500; 749 isp->isp_type = ISP_HA_FC_2500; 750 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 751 break; 752 case PCI_QLOGIC_ISP5432: 753 did = 0x2500; 754 isp->isp_mdvec = &mdvec_2500; 755 isp->isp_type = ISP_HA_FC_2500; 756 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 757 break; 758 case PCI_QLOGIC_ISP2031: 759 case PCI_QLOGIC_ISP8031: 760 did = 0x2600; 761 isp->isp_nchan += isp_nvports; 762 isp->isp_mdvec = &mdvec_2600; 763 isp->isp_type = ISP_HA_FC_2600; 764 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 765 break; 766 case PCI_QLOGIC_ISP2684: 767 case PCI_QLOGIC_ISP2692: 768 case PCI_QLOGIC_ISP2714: 769 case PCI_QLOGIC_ISP2722: 770 did = 0x2700; 771 isp->isp_nchan += isp_nvports; 772 isp->isp_mdvec = &mdvec_2700; 773 isp->isp_type = ISP_HA_FC_2700; 774 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 775 break; 776 default: 777 device_printf(dev, "unknown device type\n"); 778 goto bad; 779 break; 780 } 781 isp->isp_revision = pci_get_revid(dev); 782 783 if (IS_26XX(isp)) { 784 pcs->rtp = SYS_RES_MEMORY; 785 pcs->rgd = PCIR_BAR(0); 786 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, 787 RF_ACTIVE); 788 pcs->rtp1 = SYS_RES_MEMORY; 789 pcs->rgd1 = PCIR_BAR(2); 790 pcs->regs1 = bus_alloc_resource_any(dev, pcs->rtp1, &pcs->rgd1, 791 RF_ACTIVE); 792 pcs->rtp2 = SYS_RES_MEMORY; 793 pcs->rgd2 = PCIR_BAR(4); 794 pcs->regs2 = bus_alloc_resource_any(dev, pcs->rtp2, &pcs->rgd2, 795 RF_ACTIVE); 796 } else { 797 pcs->rtp = SYS_RES_MEMORY; 798 pcs->rgd = PCIR_BAR(1); 799 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, 800 RF_ACTIVE); 801 if (pcs->regs == NULL) { 802 pcs->rtp = SYS_RES_IOPORT; 803 pcs->rgd = PCIR_BAR(0); 804 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, 805 &pcs->rgd, RF_ACTIVE); 806 } 807 } 808 if (pcs->regs == NULL) { 809 device_printf(dev, "Unable to map any ports\n"); 810 goto bad; 811 } 812 if (bootverbose) { 813 device_printf(dev, "Using %s space register mapping\n", 814 (pcs->rtp == SYS_RES_IOPORT)? "I/O" : "Memory"); 815 } 816 isp->isp_regs = pcs->regs; 817 isp->isp_regs2 = pcs->regs2; 818 819 if (IS_FC(isp)) { 820 psize = sizeof (fcparam); 821 xsize = sizeof (struct isp_fc); 822 } else { 823 psize = sizeof (sdparam); 824 xsize = sizeof (struct isp_spi); 825 } 826 psize *= isp->isp_nchan; 827 xsize *= isp->isp_nchan; 828 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 829 if (isp->isp_param == NULL) { 830 device_printf(dev, "cannot allocate parameter data\n"); 831 goto bad; 832 } 833 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 834 if (isp->isp_osinfo.pc.ptr == NULL) { 835 device_printf(dev, "cannot allocate parameter data\n"); 836 goto bad; 837 } 838 839 /* 840 * Now that we know who we are (roughly) get/set specific options 841 */ 842 for (i = 0; i < isp->isp_nchan; i++) { 843 isp_get_specific_options(dev, i, isp); 844 } 845 846 isp->isp_osinfo.fw = NULL; 847 if (isp->isp_osinfo.fw == NULL) { 848 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 849 isp->isp_osinfo.fw = firmware_get(fwname); 850 } 851 if (isp->isp_osinfo.fw != NULL) { 852 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname); 853 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 854 } 855 856 /* 857 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 858 */ 859 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 860 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 861 if (IS_2300(isp)) { /* per QLogic errata */ 862 cmd &= ~PCIM_CMD_INVEN; 863 } 864 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 865 cmd &= ~PCIM_CMD_INTX_DISABLE; 866 } 867 if (IS_24XX(isp)) { 868 cmd &= ~PCIM_CMD_INTX_DISABLE; 869 } 870 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 871 872 /* 873 * Make sure the Cache Line Size register is set sensibly. 874 */ 875 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 876 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 877 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data); 878 data = linesz; 879 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 880 } 881 882 /* 883 * Make sure the Latency Timer is sane. 884 */ 885 data = pci_read_config(dev, PCIR_LATTIMER, 1); 886 if (data < PCI_DFLT_LTNCY) { 887 data = PCI_DFLT_LTNCY; 888 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data); 889 pci_write_config(dev, PCIR_LATTIMER, data, 1); 890 } 891 892 /* 893 * Make sure we've disabled the ROM. 894 */ 895 data = pci_read_config(dev, PCIR_ROMADDR, 4); 896 data &= ~1; 897 pci_write_config(dev, PCIR_ROMADDR, data, 4); 898 899 /* 900 * Last minute checks... 901 */ 902 if (IS_23XX(isp) || IS_24XX(isp)) { 903 isp->isp_port = pci_get_function(dev); 904 } 905 906 /* 907 * Make sure we're in reset state. 908 */ 909 ISP_LOCK(isp); 910 if (isp_reinit(isp, 1) != 0) { 911 ISP_UNLOCK(isp); 912 goto bad; 913 } 914 ISP_UNLOCK(isp); 915 if (isp_attach(isp)) { 916 ISP_LOCK(isp); 917 isp_shutdown(isp); 918 ISP_UNLOCK(isp); 919 goto bad; 920 } 921 return (0); 922 923 bad: 924 if (isp->isp_osinfo.fw == NULL && !IS_26XX(isp)) { 925 /* 926 * Failure to attach at boot time might have been caused 927 * by a missing ispfw(4). Except for for 16Gb adapters, 928 * there's no loadable firmware for them. 929 */ 930 isp_prt(isp, ISP_LOGWARN, "See the ispfw(4) man page on " 931 "how to load known good firmware at boot time"); 932 } 933 for (i = 0; i < isp->isp_nirq; i++) { 934 (void) bus_teardown_intr(dev, pcs->irq[i].irq, pcs->irq[i].ih); 935 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->irq[i].iqd, 936 pcs->irq[0].irq); 937 } 938 if (pcs->msicount) { 939 pci_release_msi(dev); 940 } 941 if (pcs->regs) 942 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 943 if (pcs->regs1) 944 (void) bus_release_resource(dev, pcs->rtp1, pcs->rgd1, pcs->regs1); 945 if (pcs->regs2) 946 (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2); 947 if (pcs->pci_isp.isp_param) { 948 free(pcs->pci_isp.isp_param, M_DEVBUF); 949 pcs->pci_isp.isp_param = NULL; 950 } 951 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 952 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 953 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 954 } 955 mtx_destroy(&isp->isp_lock); 956 return (ENXIO); 957 } 958 959 static int 960 isp_pci_detach(device_t dev) 961 { 962 struct isp_pcisoftc *pcs = device_get_softc(dev); 963 ispsoftc_t *isp = &pcs->pci_isp; 964 int i, status; 965 966 status = isp_detach(isp); 967 if (status) 968 return (status); 969 ISP_LOCK(isp); 970 isp_shutdown(isp); 971 ISP_UNLOCK(isp); 972 for (i = 0; i < isp->isp_nirq; i++) { 973 (void) bus_teardown_intr(dev, pcs->irq[i].irq, pcs->irq[i].ih); 974 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->irq[i].iqd, 975 pcs->irq[i].irq); 976 } 977 if (pcs->msicount) 978 pci_release_msi(dev); 979 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 980 if (pcs->regs1) 981 (void) bus_release_resource(dev, pcs->rtp1, pcs->rgd1, pcs->regs1); 982 if (pcs->regs2) 983 (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2); 984 isp_pci_mbxdmafree(isp); 985 if (pcs->pci_isp.isp_param) { 986 free(pcs->pci_isp.isp_param, M_DEVBUF); 987 pcs->pci_isp.isp_param = NULL; 988 } 989 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 990 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 991 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 992 } 993 mtx_destroy(&isp->isp_lock); 994 return (0); 995 } 996 997 #define IspVirt2Off(a, x) \ 998 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 999 _BLK_REG_SHFT] + ((x) & 0xfff)) 1000 1001 #define BXR2(isp, off) bus_read_2((isp)->isp_regs, (off)) 1002 #define BXW2(isp, off, v) bus_write_2((isp)->isp_regs, (off), (v)) 1003 #define BXR4(isp, off) bus_read_4((isp)->isp_regs, (off)) 1004 #define BXW4(isp, off, v) bus_write_4((isp)->isp_regs, (off), (v)) 1005 #define B2R4(isp, off) bus_read_4((isp)->isp_regs2, (off)) 1006 #define B2W4(isp, off, v) bus_write_4((isp)->isp_regs2, (off), (v)) 1007 1008 static ISP_INLINE uint16_t 1009 isp_pci_rd_debounced(ispsoftc_t *isp, int off) 1010 { 1011 uint16_t val, prev; 1012 1013 val = BXR2(isp, IspVirt2Off(isp, off)); 1014 do { 1015 prev = val; 1016 val = BXR2(isp, IspVirt2Off(isp, off)); 1017 } while (val != prev); 1018 return (val); 1019 } 1020 1021 static void 1022 isp_pci_run_isr(ispsoftc_t *isp) 1023 { 1024 uint16_t isr, sema, info; 1025 1026 if (IS_2100(isp)) { 1027 isr = isp_pci_rd_debounced(isp, BIU_ISR); 1028 sema = isp_pci_rd_debounced(isp, BIU_SEMA); 1029 } else { 1030 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1031 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1032 } 1033 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1034 isr &= INT_PENDING_MASK(isp); 1035 sema &= BIU_SEMA_LOCK; 1036 if (isr == 0 && sema == 0) 1037 return; 1038 if (sema != 0) { 1039 if (IS_2100(isp)) 1040 info = isp_pci_rd_debounced(isp, OUTMAILBOX0); 1041 else 1042 info = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1043 if (info & MBOX_COMMAND_COMPLETE) 1044 isp_intr_mbox(isp, info); 1045 else 1046 isp_intr_async(isp, info); 1047 if (!IS_FC(isp) && isp->isp_state == ISP_RUNSTATE) 1048 isp_intr_respq(isp); 1049 } else 1050 isp_intr_respq(isp); 1051 ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); 1052 if (sema) 1053 ISP_WRITE(isp, BIU_SEMA, 0); 1054 } 1055 1056 static void 1057 isp_pci_run_isr_2300(ispsoftc_t *isp) 1058 { 1059 uint32_t hccr, r2hisr; 1060 uint16_t isr, info; 1061 1062 if ((BXR2(isp, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT) == 0) 1063 return; 1064 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1065 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1066 if ((r2hisr & BIU_R2HST_INTR) == 0) 1067 return; 1068 isr = r2hisr & BIU_R2HST_ISTAT_MASK; 1069 info = r2hisr >> 16; 1070 switch (isr) { 1071 case ISPR2HST_ROM_MBX_OK: 1072 case ISPR2HST_ROM_MBX_FAIL: 1073 case ISPR2HST_MBX_OK: 1074 case ISPR2HST_MBX_FAIL: 1075 isp_intr_mbox(isp, info); 1076 break; 1077 case ISPR2HST_ASYNC_EVENT: 1078 isp_intr_async(isp, info); 1079 break; 1080 case ISPR2HST_RIO_16: 1081 isp_intr_async(isp, ASYNC_RIO16_1); 1082 break; 1083 case ISPR2HST_FPOST: 1084 isp_intr_async(isp, ASYNC_CMD_CMPLT); 1085 break; 1086 case ISPR2HST_FPOST_CTIO: 1087 isp_intr_async(isp, ASYNC_CTIO_DONE); 1088 break; 1089 case ISPR2HST_RSPQ_UPDATE: 1090 isp_intr_respq(isp); 1091 break; 1092 default: 1093 hccr = ISP_READ(isp, HCCR); 1094 if (hccr & HCCR_PAUSE) { 1095 ISP_WRITE(isp, HCCR, HCCR_RESET); 1096 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1097 ISP_WRITE(isp, BIU_ICR, 0); 1098 } else { 1099 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1100 } 1101 } 1102 ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); 1103 ISP_WRITE(isp, BIU_SEMA, 0); 1104 } 1105 1106 static void 1107 isp_pci_run_isr_2400(ispsoftc_t *isp) 1108 { 1109 uint32_t r2hisr; 1110 uint16_t isr, info; 1111 1112 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1113 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1114 if ((r2hisr & BIU_R2HST_INTR) == 0) 1115 return; 1116 isr = r2hisr & BIU_R2HST_ISTAT_MASK; 1117 info = (r2hisr >> 16); 1118 switch (isr) { 1119 case ISPR2HST_ROM_MBX_OK: 1120 case ISPR2HST_ROM_MBX_FAIL: 1121 case ISPR2HST_MBX_OK: 1122 case ISPR2HST_MBX_FAIL: 1123 isp_intr_mbox(isp, info); 1124 break; 1125 case ISPR2HST_ASYNC_EVENT: 1126 isp_intr_async(isp, info); 1127 break; 1128 case ISPR2HST_RSPQ_UPDATE: 1129 isp_intr_respq(isp); 1130 break; 1131 case ISPR2HST_RSPQ_UPDATE2: 1132 #ifdef ISP_TARGET_MODE 1133 case ISPR2HST_ATIO_RSPQ_UPDATE: 1134 #endif 1135 isp_intr_respq(isp); 1136 /* FALLTHROUGH */ 1137 #ifdef ISP_TARGET_MODE 1138 case ISPR2HST_ATIO_UPDATE: 1139 case ISPR2HST_ATIO_UPDATE2: 1140 isp_intr_atioq(isp); 1141 #endif 1142 break; 1143 default: 1144 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1145 } 1146 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1147 } 1148 1149 static uint32_t 1150 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1151 { 1152 uint16_t rv; 1153 int oldconf = 0; 1154 1155 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1156 /* 1157 * We will assume that someone has paused the RISC processor. 1158 */ 1159 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1160 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1161 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1162 } 1163 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1164 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1165 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1166 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1167 } 1168 return (rv); 1169 } 1170 1171 static void 1172 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1173 { 1174 int oldconf = 0; 1175 1176 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1177 /* 1178 * We will assume that someone has paused the RISC processor. 1179 */ 1180 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1181 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1182 oldconf | BIU_PCI_CONF1_SXP); 1183 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1184 } 1185 BXW2(isp, IspVirt2Off(isp, regoff), val); 1186 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1187 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1188 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1189 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1190 } 1191 1192 } 1193 1194 static uint32_t 1195 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1196 { 1197 uint32_t rv, oc = 0; 1198 1199 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1200 uint32_t tc; 1201 /* 1202 * We will assume that someone has paused the RISC processor. 1203 */ 1204 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1205 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1206 if (regoff & SXP_BANK1_SELECT) 1207 tc |= BIU_PCI1080_CONF1_SXP1; 1208 else 1209 tc |= BIU_PCI1080_CONF1_SXP0; 1210 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1211 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1212 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1213 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1214 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1215 oc | BIU_PCI1080_CONF1_DMA); 1216 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1217 } 1218 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1219 if (oc) { 1220 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1221 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1222 } 1223 return (rv); 1224 } 1225 1226 static void 1227 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1228 { 1229 int oc = 0; 1230 1231 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1232 uint32_t tc; 1233 /* 1234 * We will assume that someone has paused the RISC processor. 1235 */ 1236 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1237 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1238 if (regoff & SXP_BANK1_SELECT) 1239 tc |= BIU_PCI1080_CONF1_SXP1; 1240 else 1241 tc |= BIU_PCI1080_CONF1_SXP0; 1242 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1243 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1244 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1245 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1246 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1247 oc | BIU_PCI1080_CONF1_DMA); 1248 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1249 } 1250 BXW2(isp, IspVirt2Off(isp, regoff), val); 1251 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1252 if (oc) { 1253 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1254 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1255 } 1256 } 1257 1258 static uint32_t 1259 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1260 { 1261 uint32_t rv; 1262 int block = regoff & _BLK_REG_MASK; 1263 1264 switch (block) { 1265 case BIU_BLOCK: 1266 break; 1267 case MBOX_BLOCK: 1268 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1269 case SXP_BLOCK: 1270 isp_prt(isp, ISP_LOGERR, "SXP_BLOCK read at 0x%x", regoff); 1271 return (0xffffffff); 1272 case RISC_BLOCK: 1273 isp_prt(isp, ISP_LOGERR, "RISC_BLOCK read at 0x%x", regoff); 1274 return (0xffffffff); 1275 case DMA_BLOCK: 1276 isp_prt(isp, ISP_LOGERR, "DMA_BLOCK read at 0x%x", regoff); 1277 return (0xffffffff); 1278 default: 1279 isp_prt(isp, ISP_LOGERR, "unknown block read at 0x%x", regoff); 1280 return (0xffffffff); 1281 } 1282 1283 switch (regoff) { 1284 case BIU2400_FLASH_ADDR: 1285 case BIU2400_FLASH_DATA: 1286 case BIU2400_ICR: 1287 case BIU2400_ISR: 1288 case BIU2400_CSR: 1289 case BIU2400_REQINP: 1290 case BIU2400_REQOUTP: 1291 case BIU2400_RSPINP: 1292 case BIU2400_RSPOUTP: 1293 case BIU2400_PRI_REQINP: 1294 case BIU2400_PRI_REQOUTP: 1295 case BIU2400_ATIO_RSPINP: 1296 case BIU2400_ATIO_RSPOUTP: 1297 case BIU2400_HCCR: 1298 case BIU2400_GPIOD: 1299 case BIU2400_GPIOE: 1300 case BIU2400_HSEMA: 1301 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1302 break; 1303 case BIU2400_R2HSTSLO: 1304 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1305 break; 1306 case BIU2400_R2HSTSHI: 1307 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1308 break; 1309 default: 1310 isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x", 1311 regoff); 1312 rv = 0xffffffff; 1313 break; 1314 } 1315 return (rv); 1316 } 1317 1318 static void 1319 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1320 { 1321 int block = regoff & _BLK_REG_MASK; 1322 1323 switch (block) { 1324 case BIU_BLOCK: 1325 break; 1326 case MBOX_BLOCK: 1327 BXW2(isp, IspVirt2Off(isp, regoff), val); 1328 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1329 return; 1330 case SXP_BLOCK: 1331 isp_prt(isp, ISP_LOGERR, "SXP_BLOCK write at 0x%x", regoff); 1332 return; 1333 case RISC_BLOCK: 1334 isp_prt(isp, ISP_LOGERR, "RISC_BLOCK write at 0x%x", regoff); 1335 return; 1336 case DMA_BLOCK: 1337 isp_prt(isp, ISP_LOGERR, "DMA_BLOCK write at 0x%x", regoff); 1338 return; 1339 default: 1340 isp_prt(isp, ISP_LOGERR, "unknown block write at 0x%x", regoff); 1341 break; 1342 } 1343 1344 switch (regoff) { 1345 case BIU2400_FLASH_ADDR: 1346 case BIU2400_FLASH_DATA: 1347 case BIU2400_ICR: 1348 case BIU2400_ISR: 1349 case BIU2400_CSR: 1350 case BIU2400_REQINP: 1351 case BIU2400_REQOUTP: 1352 case BIU2400_RSPINP: 1353 case BIU2400_RSPOUTP: 1354 case BIU2400_PRI_REQINP: 1355 case BIU2400_PRI_REQOUTP: 1356 case BIU2400_ATIO_RSPINP: 1357 case BIU2400_ATIO_RSPOUTP: 1358 case BIU2400_HCCR: 1359 case BIU2400_GPIOD: 1360 case BIU2400_GPIOE: 1361 case BIU2400_HSEMA: 1362 BXW4(isp, IspVirt2Off(isp, regoff), val); 1363 #ifdef MEMORYBARRIERW 1364 if (regoff == BIU2400_REQINP || 1365 regoff == BIU2400_RSPOUTP || 1366 regoff == BIU2400_PRI_REQINP || 1367 regoff == BIU2400_ATIO_RSPOUTP) 1368 MEMORYBARRIERW(isp, SYNC_REG, 1369 IspVirt2Off(isp, regoff), 4, -1) 1370 else 1371 #endif 1372 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1373 break; 1374 default: 1375 isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x", 1376 regoff); 1377 break; 1378 } 1379 } 1380 1381 static uint32_t 1382 isp_pci_rd_reg_2600(ispsoftc_t *isp, int regoff) 1383 { 1384 uint32_t rv; 1385 1386 switch (regoff) { 1387 case BIU2400_PRI_REQINP: 1388 case BIU2400_PRI_REQOUTP: 1389 isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x", 1390 regoff); 1391 rv = 0xffffffff; 1392 break; 1393 case BIU2400_REQINP: 1394 rv = B2R4(isp, 0x00); 1395 break; 1396 case BIU2400_REQOUTP: 1397 rv = B2R4(isp, 0x04); 1398 break; 1399 case BIU2400_RSPINP: 1400 rv = B2R4(isp, 0x08); 1401 break; 1402 case BIU2400_RSPOUTP: 1403 rv = B2R4(isp, 0x0c); 1404 break; 1405 case BIU2400_ATIO_RSPINP: 1406 rv = B2R4(isp, 0x10); 1407 break; 1408 case BIU2400_ATIO_RSPOUTP: 1409 rv = B2R4(isp, 0x14); 1410 break; 1411 default: 1412 rv = isp_pci_rd_reg_2400(isp, regoff); 1413 break; 1414 } 1415 return (rv); 1416 } 1417 1418 static void 1419 isp_pci_wr_reg_2600(ispsoftc_t *isp, int regoff, uint32_t val) 1420 { 1421 int off; 1422 1423 switch (regoff) { 1424 case BIU2400_PRI_REQINP: 1425 case BIU2400_PRI_REQOUTP: 1426 isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x", 1427 regoff); 1428 return; 1429 case BIU2400_REQINP: 1430 off = 0x00; 1431 break; 1432 case BIU2400_REQOUTP: 1433 off = 0x04; 1434 break; 1435 case BIU2400_RSPINP: 1436 off = 0x08; 1437 break; 1438 case BIU2400_RSPOUTP: 1439 off = 0x0c; 1440 break; 1441 case BIU2400_ATIO_RSPINP: 1442 off = 0x10; 1443 break; 1444 case BIU2400_ATIO_RSPOUTP: 1445 off = 0x14; 1446 break; 1447 default: 1448 isp_pci_wr_reg_2400(isp, regoff, val); 1449 return; 1450 } 1451 B2W4(isp, off, val); 1452 } 1453 1454 1455 struct imush { 1456 bus_addr_t maddr; 1457 int error; 1458 }; 1459 1460 static void 1461 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1462 { 1463 struct imush *imushp = (struct imush *) arg; 1464 1465 if (!(imushp->error = error)) 1466 imushp->maddr = segs[0].ds_addr; 1467 } 1468 1469 static int 1470 isp_pci_mbxdma(ispsoftc_t *isp) 1471 { 1472 caddr_t base; 1473 uint32_t len, nsegs; 1474 int i, error, cmap = 0; 1475 bus_size_t slim; /* segment size */ 1476 bus_addr_t llim; /* low limit of unavailable dma */ 1477 bus_addr_t hlim; /* high limit of unavailable dma */ 1478 struct imush im; 1479 isp_ecmd_t *ecmd; 1480 1481 /* Already been here? If so, leave... */ 1482 if (isp->isp_xflist != NULL) 1483 return (0); 1484 if (isp->isp_rquest != NULL && isp->isp_maxcmds == 0) 1485 return (0); 1486 ISP_UNLOCK(isp); 1487 if (isp->isp_rquest != NULL) 1488 goto gotmaxcmds; 1489 1490 hlim = BUS_SPACE_MAXADDR; 1491 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1492 if (sizeof (bus_size_t) > 4) 1493 slim = (bus_size_t) (1ULL << 32); 1494 else 1495 slim = (bus_size_t) (1UL << 31); 1496 llim = BUS_SPACE_MAXADDR; 1497 } else { 1498 slim = (1UL << 24); 1499 llim = BUS_SPACE_MAXADDR_32BIT; 1500 } 1501 if (sizeof (bus_size_t) > 4) 1502 nsegs = ISP_NSEG64_MAX; 1503 else 1504 nsegs = ISP_NSEG_MAX; 1505 1506 if (bus_dma_tag_create(bus_get_dma_tag(ISP_PCD(isp)), 1, 1507 slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, 1508 busdma_lock_mutex, &isp->isp_lock, &isp->isp_osinfo.dmat)) { 1509 ISP_LOCK(isp); 1510 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1511 return (1); 1512 } 1513 1514 /* 1515 * Allocate and map the request queue and a region for external 1516 * DMA addressable command/status structures (22XX and later). 1517 */ 1518 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1519 if (isp->isp_type >= ISP_HA_FC_2200) 1520 len += (N_XCMDS * XCMD_SIZE); 1521 if (bus_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, 1522 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1523 len, 1, len, 0, busdma_lock_mutex, &isp->isp_lock, 1524 &isp->isp_osinfo.reqdmat)) { 1525 isp_prt(isp, ISP_LOGERR, "cannot create request DMA tag"); 1526 goto bad; 1527 } 1528 if (bus_dmamem_alloc(isp->isp_osinfo.reqdmat, (void **)&base, 1529 BUS_DMA_COHERENT, &isp->isp_osinfo.reqmap) != 0) { 1530 isp_prt(isp, ISP_LOGERR, "cannot allocate request DMA memory"); 1531 bus_dma_tag_destroy(isp->isp_osinfo.reqdmat); 1532 goto bad; 1533 } 1534 isp->isp_rquest = base; 1535 im.error = 0; 1536 if (bus_dmamap_load(isp->isp_osinfo.reqdmat, isp->isp_osinfo.reqmap, 1537 base, len, imc, &im, 0) || im.error) { 1538 isp_prt(isp, ISP_LOGERR, "error loading request DMA map %d", im.error); 1539 goto bad; 1540 } 1541 isp_prt(isp, ISP_LOGDEBUG0, "request area @ 0x%jx/0x%jx", 1542 (uintmax_t)im.maddr, (uintmax_t)len); 1543 isp->isp_rquest_dma = im.maddr; 1544 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1545 im.maddr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1546 if (isp->isp_type >= ISP_HA_FC_2200) { 1547 isp->isp_osinfo.ecmd_dma = im.maddr; 1548 isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)base; 1549 isp->isp_osinfo.ecmd_base = isp->isp_osinfo.ecmd_free; 1550 for (ecmd = isp->isp_osinfo.ecmd_free; 1551 ecmd < &isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) { 1552 if (ecmd == &isp->isp_osinfo.ecmd_free[N_XCMDS - 1]) 1553 ecmd->next = NULL; 1554 else 1555 ecmd->next = ecmd + 1; 1556 } 1557 } 1558 1559 /* 1560 * Allocate and map the result queue. 1561 */ 1562 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1563 if (bus_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, 1564 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1565 len, 1, len, 0, busdma_lock_mutex, &isp->isp_lock, 1566 &isp->isp_osinfo.respdmat)) { 1567 isp_prt(isp, ISP_LOGERR, "cannot create response DMA tag"); 1568 goto bad; 1569 } 1570 if (bus_dmamem_alloc(isp->isp_osinfo.respdmat, (void **)&base, 1571 BUS_DMA_COHERENT, &isp->isp_osinfo.respmap) != 0) { 1572 isp_prt(isp, ISP_LOGERR, "cannot allocate response DMA memory"); 1573 bus_dma_tag_destroy(isp->isp_osinfo.respdmat); 1574 goto bad; 1575 } 1576 isp->isp_result = base; 1577 im.error = 0; 1578 if (bus_dmamap_load(isp->isp_osinfo.respdmat, isp->isp_osinfo.respmap, 1579 base, len, imc, &im, 0) || im.error) { 1580 isp_prt(isp, ISP_LOGERR, "error loading response DMA map %d", im.error); 1581 goto bad; 1582 } 1583 isp_prt(isp, ISP_LOGDEBUG0, "response area @ 0x%jx/0x%jx", 1584 (uintmax_t)im.maddr, (uintmax_t)len); 1585 isp->isp_result_dma = im.maddr; 1586 1587 #ifdef ISP_TARGET_MODE 1588 /* 1589 * Allocate and map ATIO queue on 24xx with target mode. 1590 */ 1591 if (IS_24XX(isp)) { 1592 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1593 if (bus_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, 1594 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1595 len, 1, len, 0, busdma_lock_mutex, &isp->isp_lock, 1596 &isp->isp_osinfo.atiodmat)) { 1597 isp_prt(isp, ISP_LOGERR, "cannot create ATIO DMA tag"); 1598 goto bad; 1599 } 1600 if (bus_dmamem_alloc(isp->isp_osinfo.atiodmat, (void **)&base, 1601 BUS_DMA_COHERENT, &isp->isp_osinfo.atiomap) != 0) { 1602 isp_prt(isp, ISP_LOGERR, "cannot allocate ATIO DMA memory"); 1603 bus_dma_tag_destroy(isp->isp_osinfo.atiodmat); 1604 goto bad; 1605 } 1606 isp->isp_atioq = base; 1607 im.error = 0; 1608 if (bus_dmamap_load(isp->isp_osinfo.atiodmat, isp->isp_osinfo.atiomap, 1609 base, len, imc, &im, 0) || im.error) { 1610 isp_prt(isp, ISP_LOGERR, "error loading ATIO DMA map %d", im.error); 1611 goto bad; 1612 } 1613 isp_prt(isp, ISP_LOGDEBUG0, "ATIO area @ 0x%jx/0x%jx", 1614 (uintmax_t)im.maddr, (uintmax_t)len); 1615 isp->isp_atioq_dma = im.maddr; 1616 } 1617 #endif 1618 1619 if (IS_FC(isp)) { 1620 if (bus_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, 1621 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1622 2*QENTRY_LEN, 1, 2*QENTRY_LEN, 0, busdma_lock_mutex, 1623 &isp->isp_lock, &isp->isp_osinfo.iocbdmat)) { 1624 goto bad; 1625 } 1626 if (bus_dmamem_alloc(isp->isp_osinfo.iocbdmat, 1627 (void **)&base, BUS_DMA_COHERENT, &isp->isp_osinfo.iocbmap) != 0) 1628 goto bad; 1629 isp->isp_iocb = base; 1630 im.error = 0; 1631 if (bus_dmamap_load(isp->isp_osinfo.iocbdmat, isp->isp_osinfo.iocbmap, 1632 base, 2*QENTRY_LEN, imc, &im, 0) || im.error) 1633 goto bad; 1634 isp->isp_iocb_dma = im.maddr; 1635 1636 if (bus_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, 1637 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1638 ISP_FC_SCRLEN, 1, ISP_FC_SCRLEN, 0, busdma_lock_mutex, 1639 &isp->isp_lock, &isp->isp_osinfo.scdmat)) 1640 goto bad; 1641 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1642 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1643 if (bus_dmamem_alloc(isp->isp_osinfo.scdmat, 1644 (void **)&base, BUS_DMA_COHERENT, &fc->scmap) != 0) 1645 goto bad; 1646 FCPARAM(isp, cmap)->isp_scratch = base; 1647 im.error = 0; 1648 if (bus_dmamap_load(isp->isp_osinfo.scdmat, fc->scmap, 1649 base, ISP_FC_SCRLEN, imc, &im, 0) || im.error) { 1650 bus_dmamem_free(isp->isp_osinfo.scdmat, 1651 base, fc->scmap); 1652 FCPARAM(isp, cmap)->isp_scratch = NULL; 1653 goto bad; 1654 } 1655 FCPARAM(isp, cmap)->isp_scdma = im.maddr; 1656 if (!IS_2100(isp)) { 1657 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) { 1658 struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO); 1659 if (n == NULL) { 1660 while (fc->nexus_free_list) { 1661 n = fc->nexus_free_list; 1662 fc->nexus_free_list = n->next; 1663 free(n, M_DEVBUF); 1664 } 1665 goto bad; 1666 } 1667 n->next = fc->nexus_free_list; 1668 fc->nexus_free_list = n; 1669 } 1670 } 1671 } 1672 } 1673 1674 if (isp->isp_maxcmds == 0) { 1675 ISP_LOCK(isp); 1676 return (0); 1677 } 1678 1679 gotmaxcmds: 1680 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1681 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) 1682 malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1683 for (i = 0; i < isp->isp_maxcmds; i++) { 1684 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1685 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1686 if (error) { 1687 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1688 while (--i >= 0) { 1689 bus_dmamap_destroy(isp->isp_osinfo.dmat, 1690 isp->isp_osinfo.pcmd_pool[i].dmap); 1691 } 1692 goto bad; 1693 } 1694 callout_init_mtx(&pcmd->wdog, &isp->isp_lock, 0); 1695 if (i == isp->isp_maxcmds-1) 1696 pcmd->next = NULL; 1697 else 1698 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1699 } 1700 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1701 1702 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1703 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1704 for (len = 0; len < isp->isp_maxcmds - 1; len++) 1705 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1706 isp->isp_xffree = isp->isp_xflist; 1707 1708 ISP_LOCK(isp); 1709 return (0); 1710 1711 bad: 1712 isp_pci_mbxdmafree(isp); 1713 ISP_LOCK(isp); 1714 return (1); 1715 } 1716 1717 static void 1718 isp_pci_mbxdmafree(ispsoftc_t *isp) 1719 { 1720 int i; 1721 1722 if (isp->isp_xflist != NULL) { 1723 free(isp->isp_xflist, M_DEVBUF); 1724 isp->isp_xflist = NULL; 1725 } 1726 if (isp->isp_osinfo.pcmd_pool != NULL) { 1727 for (i = 0; i < isp->isp_maxcmds; i++) { 1728 bus_dmamap_destroy(isp->isp_osinfo.dmat, 1729 isp->isp_osinfo.pcmd_pool[i].dmap); 1730 } 1731 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1732 isp->isp_osinfo.pcmd_pool = NULL; 1733 } 1734 if (IS_FC(isp)) { 1735 for (i = 0; i < isp->isp_nchan; i++) { 1736 struct isp_fc *fc = ISP_FC_PC(isp, i); 1737 if (FCPARAM(isp, i)->isp_scdma != 0) { 1738 bus_dmamap_unload(isp->isp_osinfo.scdmat, 1739 fc->scmap); 1740 FCPARAM(isp, i)->isp_scdma = 0; 1741 } 1742 if (FCPARAM(isp, i)->isp_scratch != NULL) { 1743 bus_dmamem_free(isp->isp_osinfo.scdmat, 1744 FCPARAM(isp, i)->isp_scratch, fc->scmap); 1745 FCPARAM(isp, i)->isp_scratch = NULL; 1746 } 1747 while (fc->nexus_free_list) { 1748 struct isp_nexus *n = fc->nexus_free_list; 1749 fc->nexus_free_list = n->next; 1750 free(n, M_DEVBUF); 1751 } 1752 } 1753 if (isp->isp_iocb_dma != 0) { 1754 bus_dma_tag_destroy(isp->isp_osinfo.scdmat); 1755 bus_dmamap_unload(isp->isp_osinfo.iocbdmat, 1756 isp->isp_osinfo.iocbmap); 1757 isp->isp_iocb_dma = 0; 1758 } 1759 if (isp->isp_iocb != NULL) { 1760 bus_dmamem_free(isp->isp_osinfo.iocbdmat, 1761 isp->isp_iocb, isp->isp_osinfo.iocbmap); 1762 bus_dma_tag_destroy(isp->isp_osinfo.iocbdmat); 1763 } 1764 } 1765 #ifdef ISP_TARGET_MODE 1766 if (IS_24XX(isp)) { 1767 if (isp->isp_atioq_dma != 0) { 1768 bus_dmamap_unload(isp->isp_osinfo.atiodmat, 1769 isp->isp_osinfo.atiomap); 1770 isp->isp_atioq_dma = 0; 1771 } 1772 if (isp->isp_atioq != NULL) { 1773 bus_dmamem_free(isp->isp_osinfo.atiodmat, isp->isp_atioq, 1774 isp->isp_osinfo.atiomap); 1775 bus_dma_tag_destroy(isp->isp_osinfo.atiodmat); 1776 isp->isp_atioq = NULL; 1777 } 1778 } 1779 #endif 1780 if (isp->isp_result_dma != 0) { 1781 bus_dmamap_unload(isp->isp_osinfo.respdmat, 1782 isp->isp_osinfo.respmap); 1783 isp->isp_result_dma = 0; 1784 } 1785 if (isp->isp_result != NULL) { 1786 bus_dmamem_free(isp->isp_osinfo.respdmat, isp->isp_result, 1787 isp->isp_osinfo.respmap); 1788 bus_dma_tag_destroy(isp->isp_osinfo.respdmat); 1789 isp->isp_result = NULL; 1790 } 1791 if (isp->isp_rquest_dma != 0) { 1792 bus_dmamap_unload(isp->isp_osinfo.reqdmat, 1793 isp->isp_osinfo.reqmap); 1794 isp->isp_rquest_dma = 0; 1795 } 1796 if (isp->isp_rquest != NULL) { 1797 bus_dmamem_free(isp->isp_osinfo.reqdmat, isp->isp_rquest, 1798 isp->isp_osinfo.reqmap); 1799 bus_dma_tag_destroy(isp->isp_osinfo.reqdmat); 1800 isp->isp_rquest = NULL; 1801 } 1802 } 1803 1804 typedef struct { 1805 ispsoftc_t *isp; 1806 void *cmd_token; 1807 void *rq; /* original request */ 1808 int error; 1809 } mush_t; 1810 1811 #define MUSHERR_NOQENTRIES -2 1812 1813 static void 1814 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1815 { 1816 mush_t *mp = (mush_t *) arg; 1817 ispsoftc_t *isp= mp->isp; 1818 struct ccb_scsiio *csio = mp->cmd_token; 1819 isp_ddir_t ddir; 1820 int sdir; 1821 1822 if (error) { 1823 mp->error = error; 1824 return; 1825 } 1826 if (nseg == 0) { 1827 ddir = ISP_NOXFR; 1828 } else { 1829 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1830 ddir = ISP_FROM_DEVICE; 1831 } else { 1832 ddir = ISP_TO_DEVICE; 1833 } 1834 if ((csio->ccb_h.func_code == XPT_CONT_TARGET_IO) ^ 1835 ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)) { 1836 sdir = BUS_DMASYNC_PREREAD; 1837 } else { 1838 sdir = BUS_DMASYNC_PREWRITE; 1839 } 1840 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, 1841 sdir); 1842 } 1843 1844 error = isp_send_cmd(isp, mp->rq, dm_segs, nseg, XS_XFRLEN(csio), 1845 ddir, (ispds64_t *)csio->req_map); 1846 switch (error) { 1847 case CMD_EAGAIN: 1848 mp->error = MUSHERR_NOQENTRIES; 1849 break; 1850 case CMD_QUEUED: 1851 break; 1852 default: 1853 mp->error = EIO; 1854 break; 1855 } 1856 } 1857 1858 static int 1859 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1860 { 1861 mush_t mush, *mp; 1862 int error; 1863 1864 mp = &mush; 1865 mp->isp = isp; 1866 mp->cmd_token = csio; 1867 mp->rq = ff; 1868 mp->error = 0; 1869 1870 error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, 1871 (union ccb *)csio, dma2, mp, 0); 1872 if (error == EINPROGRESS) { 1873 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1874 mp->error = EINVAL; 1875 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1876 } else if (error && mp->error == 0) { 1877 #ifdef DIAGNOSTIC 1878 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1879 #endif 1880 mp->error = error; 1881 } 1882 if (mp->error) { 1883 int retval = CMD_COMPLETE; 1884 if (mp->error == MUSHERR_NOQENTRIES) { 1885 retval = CMD_EAGAIN; 1886 } else if (mp->error == EFBIG) { 1887 csio->ccb_h.status = CAM_REQ_TOO_BIG; 1888 } else if (mp->error == EINVAL) { 1889 csio->ccb_h.status = CAM_REQ_INVALID; 1890 } else { 1891 csio->ccb_h.status = CAM_UNREC_HBA_ERROR; 1892 } 1893 return (retval); 1894 } 1895 return (CMD_QUEUED); 1896 } 1897 1898 static int 1899 isp_pci_irqsetup(ispsoftc_t *isp) 1900 { 1901 device_t dev = isp->isp_osinfo.dev; 1902 struct isp_pcisoftc *pcs = device_get_softc(dev); 1903 driver_intr_t *f; 1904 int i, max_irq; 1905 1906 /* Allocate IRQs only once. */ 1907 if (isp->isp_nirq > 0) 1908 return (0); 1909 1910 ISP_UNLOCK(isp); 1911 if (ISP_CAP_MSIX(isp)) { 1912 max_irq = IS_26XX(isp) ? 3 : (IS_25XX(isp) ? 2 : 0); 1913 resource_int_value(device_get_name(dev), 1914 device_get_unit(dev), "msix", &max_irq); 1915 max_irq = imin(ISP_MAX_IRQS, max_irq); 1916 pcs->msicount = imin(pci_msix_count(dev), max_irq); 1917 if (pcs->msicount > 0 && 1918 pci_alloc_msix(dev, &pcs->msicount) != 0) 1919 pcs->msicount = 0; 1920 } 1921 if (pcs->msicount == 0) { 1922 max_irq = 1; 1923 resource_int_value(device_get_name(dev), 1924 device_get_unit(dev), "msi", &max_irq); 1925 max_irq = imin(1, max_irq); 1926 pcs->msicount = imin(pci_msi_count(dev), max_irq); 1927 if (pcs->msicount > 0 && 1928 pci_alloc_msi(dev, &pcs->msicount) != 0) 1929 pcs->msicount = 0; 1930 } 1931 for (i = 0; i < MAX(1, pcs->msicount); i++) { 1932 pcs->irq[i].iqd = i + (pcs->msicount > 0); 1933 pcs->irq[i].irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1934 &pcs->irq[i].iqd, RF_ACTIVE | RF_SHAREABLE); 1935 if (pcs->irq[i].irq == NULL) { 1936 device_printf(dev, "could not allocate interrupt\n"); 1937 break; 1938 } 1939 if (i == 0) 1940 f = isp_platform_intr; 1941 else if (i == 1) 1942 f = isp_platform_intr_resp; 1943 else 1944 f = isp_platform_intr_atio; 1945 if (bus_setup_intr(dev, pcs->irq[i].irq, ISP_IFLAGS, NULL, 1946 f, isp, &pcs->irq[i].ih)) { 1947 device_printf(dev, "could not setup interrupt\n"); 1948 (void) bus_release_resource(dev, SYS_RES_IRQ, 1949 pcs->irq[i].iqd, pcs->irq[i].irq); 1950 break; 1951 } 1952 if (pcs->msicount > 1) { 1953 bus_describe_intr(dev, pcs->irq[i].irq, pcs->irq[i].ih, 1954 "%d", i); 1955 } 1956 isp->isp_nirq = i + 1; 1957 } 1958 ISP_LOCK(isp); 1959 1960 return (isp->isp_nirq == 0); 1961 } 1962 1963 static void 1964 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1965 { 1966 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1967 if (msg) 1968 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1969 else 1970 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1971 if (IS_SCSI(isp)) 1972 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1973 else 1974 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1975 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1976 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1977 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1978 1979 1980 if (IS_SCSI(isp)) { 1981 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1982 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1983 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1984 ISP_READ(isp, CDMA_FIFO_STS)); 1985 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1986 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1987 ISP_READ(isp, DDMA_FIFO_STS)); 1988 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1989 ISP_READ(isp, SXP_INTERRUPT), 1990 ISP_READ(isp, SXP_GROSS_ERR), 1991 ISP_READ(isp, SXP_PINS_CTRL)); 1992 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1993 } 1994 printf(" mbox regs: %x %x %x %x %x\n", 1995 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1996 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1997 ISP_READ(isp, OUTMAILBOX4)); 1998 printf(" PCI Status Command/Status=%x\n", 1999 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2000 } 2001