1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 #include <sys/malloc.h> 47 #include <sys/uio.h> 48 49 #ifdef __sparc64__ 50 #include <dev/ofw/openfirm.h> 51 #include <machine/ofw_machdep.h> 52 #endif 53 54 #include <dev/isp/isp_freebsd.h> 55 56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 62 static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 63 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 64 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 65 static int isp_pci_mbxdma(ispsoftc_t *); 66 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 67 68 69 static void isp_pci_reset0(ispsoftc_t *); 70 static void isp_pci_reset1(ispsoftc_t *); 71 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 72 73 static struct ispmdvec mdvec = { 74 isp_pci_rd_isr, 75 isp_pci_rd_reg, 76 isp_pci_wr_reg, 77 isp_pci_mbxdma, 78 isp_pci_dmasetup, 79 isp_common_dmateardown, 80 isp_pci_reset0, 81 isp_pci_reset1, 82 isp_pci_dumpregs, 83 NULL, 84 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 85 }; 86 87 static struct ispmdvec mdvec_1080 = { 88 isp_pci_rd_isr, 89 isp_pci_rd_reg_1080, 90 isp_pci_wr_reg_1080, 91 isp_pci_mbxdma, 92 isp_pci_dmasetup, 93 isp_common_dmateardown, 94 isp_pci_reset0, 95 isp_pci_reset1, 96 isp_pci_dumpregs, 97 NULL, 98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 99 }; 100 101 static struct ispmdvec mdvec_12160 = { 102 isp_pci_rd_isr, 103 isp_pci_rd_reg_1080, 104 isp_pci_wr_reg_1080, 105 isp_pci_mbxdma, 106 isp_pci_dmasetup, 107 isp_common_dmateardown, 108 isp_pci_reset0, 109 isp_pci_reset1, 110 isp_pci_dumpregs, 111 NULL, 112 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 113 }; 114 115 static struct ispmdvec mdvec_2100 = { 116 isp_pci_rd_isr, 117 isp_pci_rd_reg, 118 isp_pci_wr_reg, 119 isp_pci_mbxdma, 120 isp_pci_dmasetup, 121 isp_common_dmateardown, 122 isp_pci_reset0, 123 isp_pci_reset1, 124 isp_pci_dumpregs 125 }; 126 127 static struct ispmdvec mdvec_2200 = { 128 isp_pci_rd_isr, 129 isp_pci_rd_reg, 130 isp_pci_wr_reg, 131 isp_pci_mbxdma, 132 isp_pci_dmasetup, 133 isp_common_dmateardown, 134 isp_pci_reset0, 135 isp_pci_reset1, 136 isp_pci_dumpregs 137 }; 138 139 static struct ispmdvec mdvec_2300 = { 140 isp_pci_rd_isr_2300, 141 isp_pci_rd_reg, 142 isp_pci_wr_reg, 143 isp_pci_mbxdma, 144 isp_pci_dmasetup, 145 isp_common_dmateardown, 146 isp_pci_reset0, 147 isp_pci_reset1, 148 isp_pci_dumpregs 149 }; 150 151 static struct ispmdvec mdvec_2400 = { 152 isp_pci_rd_isr_2400, 153 isp_pci_rd_reg_2400, 154 isp_pci_wr_reg_2400, 155 isp_pci_mbxdma, 156 isp_pci_dmasetup, 157 isp_common_dmateardown, 158 isp_pci_reset0, 159 isp_pci_reset1, 160 NULL 161 }; 162 163 static struct ispmdvec mdvec_2500 = { 164 isp_pci_rd_isr_2400, 165 isp_pci_rd_reg_2400, 166 isp_pci_wr_reg_2400, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_common_dmateardown, 170 isp_pci_reset0, 171 isp_pci_reset1, 172 NULL 173 }; 174 175 #ifndef PCIM_CMD_INVEN 176 #define PCIM_CMD_INVEN 0x10 177 #endif 178 #ifndef PCIM_CMD_BUSMASTEREN 179 #define PCIM_CMD_BUSMASTEREN 0x0004 180 #endif 181 #ifndef PCIM_CMD_PERRESPEN 182 #define PCIM_CMD_PERRESPEN 0x0040 183 #endif 184 #ifndef PCIM_CMD_SEREN 185 #define PCIM_CMD_SEREN 0x0100 186 #endif 187 #ifndef PCIM_CMD_INTX_DISABLE 188 #define PCIM_CMD_INTX_DISABLE 0x0400 189 #endif 190 191 #ifndef PCIR_COMMAND 192 #define PCIR_COMMAND 0x04 193 #endif 194 195 #ifndef PCIR_CACHELNSZ 196 #define PCIR_CACHELNSZ 0x0c 197 #endif 198 199 #ifndef PCIR_LATTIMER 200 #define PCIR_LATTIMER 0x0d 201 #endif 202 203 #ifndef PCIR_ROMADDR 204 #define PCIR_ROMADDR 0x30 205 #endif 206 207 #ifndef PCI_VENDOR_QLOGIC 208 #define PCI_VENDOR_QLOGIC 0x1077 209 #endif 210 211 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 212 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 213 #endif 214 215 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 216 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 217 #endif 218 219 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 220 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 221 #endif 222 223 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 224 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 225 #endif 226 227 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 228 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 229 #endif 230 231 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 232 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 233 #endif 234 235 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 236 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 237 #endif 238 239 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 240 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 241 #endif 242 243 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 244 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 245 #endif 246 247 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 248 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 249 #endif 250 251 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 252 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 253 #endif 254 255 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 256 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 257 #endif 258 259 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 260 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 261 #endif 262 263 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 264 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 265 #endif 266 267 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 268 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 269 #endif 270 271 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 272 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 273 #endif 274 275 #ifndef PCI_PRODUCT_QLOGIC_ISP5432 276 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 277 #endif 278 279 #define PCI_QLOGIC_ISP5432 \ 280 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP1020 \ 283 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP1080 \ 286 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define PCI_QLOGIC_ISP10160 \ 289 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 290 291 #define PCI_QLOGIC_ISP12160 \ 292 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 293 294 #define PCI_QLOGIC_ISP1240 \ 295 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 296 297 #define PCI_QLOGIC_ISP1280 \ 298 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 299 300 #define PCI_QLOGIC_ISP2100 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 302 303 #define PCI_QLOGIC_ISP2200 \ 304 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 305 306 #define PCI_QLOGIC_ISP2300 \ 307 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 308 309 #define PCI_QLOGIC_ISP2312 \ 310 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 311 312 #define PCI_QLOGIC_ISP2322 \ 313 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 314 315 #define PCI_QLOGIC_ISP2422 \ 316 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 317 318 #define PCI_QLOGIC_ISP2432 \ 319 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 320 321 #define PCI_QLOGIC_ISP2532 \ 322 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 323 324 #define PCI_QLOGIC_ISP6312 \ 325 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 326 327 #define PCI_QLOGIC_ISP6322 \ 328 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 329 330 /* 331 * Odd case for some AMI raid cards... We need to *not* attach to this. 332 */ 333 #define AMI_RAID_SUBVENDOR_ID 0x101e 334 335 #define IO_MAP_REG 0x10 336 #define MEM_MAP_REG 0x14 337 338 #define PCI_DFLT_LTNCY 0x40 339 #define PCI_DFLT_LNSZ 0x10 340 341 static int isp_pci_probe (device_t); 342 static int isp_pci_attach (device_t); 343 static int isp_pci_detach (device_t); 344 345 346 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 347 struct isp_pcisoftc { 348 ispsoftc_t pci_isp; 349 device_t pci_dev; 350 struct resource * regs; 351 void * irq; 352 int iqd; 353 int rtp; 354 int rgd; 355 void * ih; 356 int16_t pci_poff[_NREG_BLKS]; 357 bus_dma_tag_t dmat; 358 int msicount; 359 }; 360 361 362 static device_method_t isp_pci_methods[] = { 363 /* Device interface */ 364 DEVMETHOD(device_probe, isp_pci_probe), 365 DEVMETHOD(device_attach, isp_pci_attach), 366 DEVMETHOD(device_detach, isp_pci_detach), 367 { 0, 0 } 368 }; 369 370 static driver_t isp_pci_driver = { 371 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 372 }; 373 static devclass_t isp_devclass; 374 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 375 MODULE_DEPEND(isp, cam, 1, 1, 1); 376 MODULE_DEPEND(isp, firmware, 1, 1, 1); 377 378 static int 379 isp_pci_probe(device_t dev) 380 { 381 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 382 case PCI_QLOGIC_ISP1020: 383 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 384 break; 385 case PCI_QLOGIC_ISP1080: 386 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 387 break; 388 case PCI_QLOGIC_ISP1240: 389 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 390 break; 391 case PCI_QLOGIC_ISP1280: 392 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 393 break; 394 case PCI_QLOGIC_ISP10160: 395 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 396 break; 397 case PCI_QLOGIC_ISP12160: 398 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 399 return (ENXIO); 400 } 401 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 402 break; 403 case PCI_QLOGIC_ISP2100: 404 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 405 break; 406 case PCI_QLOGIC_ISP2200: 407 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 408 break; 409 case PCI_QLOGIC_ISP2300: 410 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 411 break; 412 case PCI_QLOGIC_ISP2312: 413 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 414 break; 415 case PCI_QLOGIC_ISP2322: 416 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 417 break; 418 case PCI_QLOGIC_ISP2422: 419 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 420 break; 421 case PCI_QLOGIC_ISP2432: 422 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 423 break; 424 case PCI_QLOGIC_ISP2532: 425 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 426 break; 427 case PCI_QLOGIC_ISP5432: 428 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 429 break; 430 case PCI_QLOGIC_ISP6312: 431 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 432 break; 433 case PCI_QLOGIC_ISP6322: 434 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 435 break; 436 default: 437 return (ENXIO); 438 } 439 if (isp_announced == 0 && bootverbose) { 440 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 441 "Core Version %d.%d\n", 442 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 443 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 444 isp_announced++; 445 } 446 /* 447 * XXXX: Here is where we might load the f/w module 448 * XXXX: (or increase a reference count to it). 449 */ 450 return (BUS_PROBE_DEFAULT); 451 } 452 453 static void 454 isp_get_generic_options(device_t dev, ispsoftc_t *isp, int *nvp) 455 { 456 int tval; 457 458 /* 459 * Figure out if we're supposed to skip this one. 460 */ 461 tval = 0; 462 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 463 device_printf(dev, "disabled at user request\n"); 464 isp->isp_osinfo.disabled = 1; 465 return; 466 } 467 468 tval = 0; 469 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 470 isp->isp_confopts |= ISP_CFG_NORELOAD; 471 } 472 tval = 0; 473 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 474 isp->isp_confopts |= ISP_CFG_NONVRAM; 475 } 476 tval = 0; 477 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 478 if (tval) { 479 isp->isp_dblev = tval; 480 } else { 481 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 482 } 483 if (bootverbose) { 484 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 485 } 486 tval = 0; 487 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 488 if (tval > 0 && tval < 127) { 489 *nvp = tval; 490 } else { 491 *nvp = 0; 492 } 493 tval = 1; 494 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 495 isp_autoconfig = tval; 496 tval = 7; 497 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 498 isp_quickboot_time = tval; 499 } 500 501 static void 502 isp_get_pci_options(device_t dev, int *m1, int *m2) 503 { 504 int tval; 505 /* 506 * Which we should try first - memory mapping or i/o mapping? 507 * 508 * We used to try memory first followed by i/o on alpha, otherwise 509 * the reverse, but we should just try memory first all the time now. 510 */ 511 *m1 = PCIM_CMD_MEMEN; 512 *m2 = PCIM_CMD_PORTEN; 513 514 tval = 0; 515 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 516 *m1 = PCIM_CMD_PORTEN; 517 *m2 = PCIM_CMD_MEMEN; 518 } 519 tval = 0; 520 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 521 *m1 = PCIM_CMD_MEMEN; 522 *m2 = PCIM_CMD_PORTEN; 523 } 524 } 525 526 static void 527 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 528 { 529 const char *sptr; 530 int tval; 531 532 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 533 if (IS_FC(isp)) { 534 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 535 } else { 536 #ifdef __sparc64__ 537 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 538 #else 539 ISP_SPI_PC(isp, chan)->iid = 7; 540 #endif 541 } 542 } else { 543 if (IS_FC(isp)) { 544 ISP_FC_PC(isp, chan)->default_id = tval - chan; 545 } else { 546 ISP_SPI_PC(isp, chan)->iid = tval; 547 } 548 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 549 } 550 551 tval = -1; 552 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 553 switch (tval) { 554 case ISP_ROLE_NONE: 555 case ISP_ROLE_INITIATOR: 556 case ISP_ROLE_TARGET: 557 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 558 device_printf(dev, "setting role to 0x%x\n", tval); 559 break; 560 default: 561 tval = -1; 562 break; 563 } 564 } 565 if (tval == -1) { 566 tval = ISP_DEFAULT_ROLES; 567 } 568 569 if (IS_SCSI(isp)) { 570 ISP_SPI_PC(isp, chan)->def_role = tval; 571 return; 572 } 573 ISP_FC_PC(isp, chan)->def_role = tval; 574 575 tval = 0; 576 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 577 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 578 } 579 sptr = 0; 580 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", (const char **) &sptr) == 0 && sptr != 0) { 581 if (strcmp(sptr, "lport") == 0) { 582 isp->isp_confopts |= ISP_CFG_LPORT; 583 } else if (strcmp(sptr, "nport") == 0) { 584 isp->isp_confopts |= ISP_CFG_NPORT; 585 } else if (strcmp(sptr, "lport-only") == 0) { 586 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 587 } else if (strcmp(sptr, "nport-only") == 0) { 588 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 589 } 590 } 591 592 /* 593 * Because the resource_*_value functions can neither return 594 * 64 bit integer values, nor can they be directly coerced 595 * to interpret the right hand side of the assignment as 596 * you want them to interpret it, we have to force WWN 597 * hint replacement to specify WWN strings with a leading 598 * 'w' (e..g w50000000aaaa0001). Sigh. 599 */ 600 sptr = 0; 601 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", (const char **) &sptr); 602 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 603 char *eptr = 0; 604 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 605 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 606 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 607 ISP_FC_PC(isp, chan)->def_wwpn = 0; 608 } 609 } 610 611 sptr = 0; 612 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", (const char **) &sptr); 613 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 614 char *eptr = 0; 615 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 616 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 617 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 618 ISP_FC_PC(isp, chan)->def_wwnn = 0; 619 } 620 } 621 622 tval = 0; 623 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 624 if (tval >= 0 && tval < 256) { 625 ISP_FC_PC(isp, chan)->hysteresis = tval; 626 } else { 627 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 628 } 629 630 tval = -1; 631 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 632 if (tval >= 0 && tval < 0xffff) { 633 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 634 } else { 635 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 636 } 637 638 tval = -1; 639 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 640 if (tval >= 0 && tval < 0xffff) { 641 ISP_FC_PC(isp, chan)->gone_device_time = tval; 642 } else { 643 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 644 } 645 } 646 647 static int 648 isp_pci_attach(device_t dev) 649 { 650 int i, m1, m2, locksetup = 0; 651 int isp_nvports = 0; 652 uint32_t data, cmd, linesz, did; 653 struct isp_pcisoftc *pcs; 654 ispsoftc_t *isp; 655 size_t psize, xsize; 656 char fwname[32]; 657 658 pcs = device_get_softc(dev); 659 if (pcs == NULL) { 660 device_printf(dev, "cannot get softc\n"); 661 return (ENOMEM); 662 } 663 memset(pcs, 0, sizeof (*pcs)); 664 665 pcs->pci_dev = dev; 666 isp = &pcs->pci_isp; 667 isp->isp_dev = dev; 668 isp->isp_nchan = 1; 669 670 /* 671 * Get Generic Options 672 */ 673 isp_get_generic_options(dev, isp, &isp_nvports); 674 675 /* 676 * Check to see if options have us disabled 677 */ 678 if (isp->isp_osinfo.disabled) { 679 /* 680 * But return zero to preserve unit numbering 681 */ 682 return (0); 683 } 684 685 /* 686 * Get PCI options- which in this case are just mapping preferences. 687 */ 688 isp_get_pci_options(dev, &m1, &m2); 689 690 linesz = PCI_DFLT_LNSZ; 691 pcs->irq = pcs->regs = NULL; 692 pcs->rgd = pcs->rtp = pcs->iqd = 0; 693 694 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 695 if (cmd & m1) { 696 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 697 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 698 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 699 } 700 if (pcs->regs == NULL && (cmd & m2)) { 701 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 702 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 703 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 704 } 705 if (pcs->regs == NULL) { 706 device_printf(dev, "unable to map any ports\n"); 707 goto bad; 708 } 709 if (bootverbose) { 710 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 711 } 712 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 713 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 714 715 pcs->pci_dev = dev; 716 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 717 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 718 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 719 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 720 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 721 722 switch (pci_get_devid(dev)) { 723 case PCI_QLOGIC_ISP1020: 724 did = 0x1040; 725 isp->isp_mdvec = &mdvec; 726 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 727 break; 728 case PCI_QLOGIC_ISP1080: 729 did = 0x1080; 730 isp->isp_mdvec = &mdvec_1080; 731 isp->isp_type = ISP_HA_SCSI_1080; 732 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 733 break; 734 case PCI_QLOGIC_ISP1240: 735 did = 0x1080; 736 isp->isp_mdvec = &mdvec_1080; 737 isp->isp_type = ISP_HA_SCSI_1240; 738 isp->isp_nchan = 2; 739 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 740 break; 741 case PCI_QLOGIC_ISP1280: 742 did = 0x1080; 743 isp->isp_mdvec = &mdvec_1080; 744 isp->isp_type = ISP_HA_SCSI_1280; 745 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 746 break; 747 case PCI_QLOGIC_ISP10160: 748 did = 0x12160; 749 isp->isp_mdvec = &mdvec_12160; 750 isp->isp_type = ISP_HA_SCSI_10160; 751 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 752 break; 753 case PCI_QLOGIC_ISP12160: 754 did = 0x12160; 755 isp->isp_nchan = 2; 756 isp->isp_mdvec = &mdvec_12160; 757 isp->isp_type = ISP_HA_SCSI_12160; 758 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 759 break; 760 case PCI_QLOGIC_ISP2100: 761 did = 0x2100; 762 isp->isp_mdvec = &mdvec_2100; 763 isp->isp_type = ISP_HA_FC_2100; 764 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 765 if (pci_get_revid(dev) < 3) { 766 /* 767 * XXX: Need to get the actual revision 768 * XXX: number of the 2100 FB. At any rate, 769 * XXX: lower cache line size for early revision 770 * XXX; boards. 771 */ 772 linesz = 1; 773 } 774 break; 775 case PCI_QLOGIC_ISP2200: 776 did = 0x2200; 777 isp->isp_mdvec = &mdvec_2200; 778 isp->isp_type = ISP_HA_FC_2200; 779 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 780 break; 781 case PCI_QLOGIC_ISP2300: 782 did = 0x2300; 783 isp->isp_mdvec = &mdvec_2300; 784 isp->isp_type = ISP_HA_FC_2300; 785 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 786 break; 787 case PCI_QLOGIC_ISP2312: 788 case PCI_QLOGIC_ISP6312: 789 did = 0x2300; 790 isp->isp_mdvec = &mdvec_2300; 791 isp->isp_type = ISP_HA_FC_2312; 792 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 793 break; 794 case PCI_QLOGIC_ISP2322: 795 case PCI_QLOGIC_ISP6322: 796 did = 0x2322; 797 isp->isp_mdvec = &mdvec_2300; 798 isp->isp_type = ISP_HA_FC_2322; 799 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 800 break; 801 case PCI_QLOGIC_ISP2422: 802 case PCI_QLOGIC_ISP2432: 803 did = 0x2400; 804 isp->isp_nchan += isp_nvports; 805 isp->isp_mdvec = &mdvec_2400; 806 isp->isp_type = ISP_HA_FC_2400; 807 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 808 break; 809 case PCI_QLOGIC_ISP2532: 810 did = 0x2500; 811 isp->isp_nchan += isp_nvports; 812 isp->isp_mdvec = &mdvec_2500; 813 isp->isp_type = ISP_HA_FC_2500; 814 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 815 break; 816 case PCI_QLOGIC_ISP5432: 817 did = 0x2500; 818 isp->isp_mdvec = &mdvec_2500; 819 isp->isp_type = ISP_HA_FC_2500; 820 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 821 break; 822 default: 823 device_printf(dev, "unknown device type\n"); 824 goto bad; 825 break; 826 } 827 isp->isp_revision = pci_get_revid(dev); 828 829 if (IS_FC(isp)) { 830 psize = sizeof (fcparam); 831 xsize = sizeof (struct isp_fc); 832 } else { 833 psize = sizeof (sdparam); 834 xsize = sizeof (struct isp_spi); 835 } 836 psize *= isp->isp_nchan; 837 xsize *= isp->isp_nchan; 838 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 839 if (isp->isp_param == NULL) { 840 device_printf(dev, "cannot allocate parameter data\n"); 841 goto bad; 842 } 843 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 844 if (isp->isp_osinfo.pc.ptr == NULL) { 845 device_printf(dev, "cannot allocate parameter data\n"); 846 goto bad; 847 } 848 849 /* 850 * Now that we know who we are (roughly) get/set specific options 851 */ 852 for (i = 0; i < isp->isp_nchan; i++) { 853 isp_get_specific_options(dev, i, isp); 854 } 855 856 /* 857 * The 'it' suffix really only matters for SCSI cards in target mode. 858 */ 859 isp->isp_osinfo.fw = NULL; 860 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 861 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 862 isp->isp_osinfo.fw = firmware_get(fwname); 863 } else if (IS_24XX(isp)) { 864 snprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 865 isp->isp_osinfo.fw = firmware_get(fwname); 866 } 867 if (isp->isp_osinfo.fw == NULL) { 868 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 869 isp->isp_osinfo.fw = firmware_get(fwname); 870 } 871 if (isp->isp_osinfo.fw != NULL) { 872 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname); 873 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 874 } 875 876 /* 877 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 878 */ 879 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 880 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 881 882 if (IS_2300(isp)) { /* per QLogic errata */ 883 cmd &= ~PCIM_CMD_INVEN; 884 } 885 886 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 887 cmd &= ~PCIM_CMD_INTX_DISABLE; 888 } 889 890 if (IS_24XX(isp)) { 891 cmd &= ~PCIM_CMD_INTX_DISABLE; 892 } 893 894 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 895 896 /* 897 * Make sure the Cache Line Size register is set sensibly. 898 */ 899 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 900 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 901 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data); 902 data = linesz; 903 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 904 } 905 906 /* 907 * Make sure the Latency Timer is sane. 908 */ 909 data = pci_read_config(dev, PCIR_LATTIMER, 1); 910 if (data < PCI_DFLT_LTNCY) { 911 data = PCI_DFLT_LTNCY; 912 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data); 913 pci_write_config(dev, PCIR_LATTIMER, data, 1); 914 } 915 916 /* 917 * Make sure we've disabled the ROM. 918 */ 919 data = pci_read_config(dev, PCIR_ROMADDR, 4); 920 data &= ~1; 921 pci_write_config(dev, PCIR_ROMADDR, data, 4); 922 923 /* 924 * Do MSI 925 * 926 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 927 */ 928 if (IS_24XX(isp) || IS_2322(isp)) { 929 pcs->msicount = pci_msi_count(dev); 930 if (pcs->msicount > 1) { 931 pcs->msicount = 1; 932 } 933 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 934 pcs->iqd = 1; 935 } else { 936 pcs->iqd = 0; 937 } 938 } 939 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE); 940 if (pcs->irq == NULL) { 941 device_printf(dev, "could not allocate interrupt\n"); 942 goto bad; 943 } 944 945 /* Make sure the lock is set up. */ 946 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 947 locksetup++; 948 949 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 950 device_printf(dev, "could not setup interrupt\n"); 951 goto bad; 952 } 953 954 /* 955 * Last minute checks... 956 */ 957 if (IS_23XX(isp) || IS_24XX(isp)) { 958 isp->isp_port = pci_get_function(dev); 959 } 960 961 /* 962 * Make sure we're in reset state. 963 */ 964 ISP_LOCK(isp); 965 isp_reset(isp, 1); 966 if (isp->isp_state != ISP_RESETSTATE) { 967 ISP_UNLOCK(isp); 968 goto bad; 969 } 970 isp_init(isp); 971 if (isp->isp_state == ISP_INITSTATE) { 972 isp->isp_state = ISP_RUNSTATE; 973 } 974 ISP_UNLOCK(isp); 975 if (isp_attach(isp)) { 976 ISP_LOCK(isp); 977 isp_uninit(isp); 978 ISP_UNLOCK(isp); 979 goto bad; 980 } 981 return (0); 982 983 bad: 984 if (pcs->ih) { 985 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 986 } 987 if (locksetup) { 988 mtx_destroy(&isp->isp_osinfo.lock); 989 } 990 if (pcs->irq) { 991 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 992 } 993 if (pcs->msicount) { 994 pci_release_msi(dev); 995 } 996 if (pcs->regs) { 997 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 998 } 999 if (pcs->pci_isp.isp_param) { 1000 free(pcs->pci_isp.isp_param, M_DEVBUF); 1001 pcs->pci_isp.isp_param = NULL; 1002 } 1003 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1004 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1005 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1006 } 1007 return (ENXIO); 1008 } 1009 1010 static int 1011 isp_pci_detach(device_t dev) 1012 { 1013 struct isp_pcisoftc *pcs; 1014 ispsoftc_t *isp; 1015 int status; 1016 1017 pcs = device_get_softc(dev); 1018 if (pcs == NULL) { 1019 return (ENXIO); 1020 } 1021 isp = (ispsoftc_t *) pcs; 1022 status = isp_detach(isp); 1023 if (status) 1024 return (status); 1025 ISP_LOCK(isp); 1026 isp_uninit(isp); 1027 if (pcs->ih) { 1028 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1029 } 1030 ISP_UNLOCK(isp); 1031 mtx_destroy(&isp->isp_osinfo.lock); 1032 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1033 if (pcs->msicount) { 1034 pci_release_msi(dev); 1035 } 1036 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1037 if (pcs->pci_isp.isp_param) { 1038 free(pcs->pci_isp.isp_param, M_DEVBUF); 1039 pcs->pci_isp.isp_param = NULL; 1040 } 1041 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1042 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1043 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1044 } 1045 return (0); 1046 } 1047 1048 #define IspVirt2Off(a, x) \ 1049 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1050 _BLK_REG_SHFT] + ((x) & 0xfff)) 1051 1052 #define BXR2(isp, off) \ 1053 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1054 #define BXW2(isp, off, v) \ 1055 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1056 #define BXR4(isp, off) \ 1057 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1058 #define BXW4(isp, off, v) \ 1059 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1060 1061 1062 static ISP_INLINE int 1063 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1064 { 1065 uint32_t val0, val1; 1066 int i = 0; 1067 1068 do { 1069 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1070 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1071 } while (val0 != val1 && ++i < 1000); 1072 if (val0 != val1) { 1073 return (1); 1074 } 1075 *rp = val0; 1076 return (0); 1077 } 1078 1079 static int 1080 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1081 { 1082 uint16_t isr, sema; 1083 1084 if (IS_2100(isp)) { 1085 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1086 return (0); 1087 } 1088 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1089 return (0); 1090 } 1091 } else { 1092 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1093 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1094 } 1095 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1096 isr &= INT_PENDING_MASK(isp); 1097 sema &= BIU_SEMA_LOCK; 1098 if (isr == 0 && sema == 0) { 1099 return (0); 1100 } 1101 *isrp = isr; 1102 if ((*semap = sema) != 0) { 1103 if (IS_2100(isp)) { 1104 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1105 return (0); 1106 } 1107 } else { 1108 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1109 } 1110 } 1111 return (1); 1112 } 1113 1114 static int 1115 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1116 { 1117 uint32_t hccr; 1118 uint32_t r2hisr; 1119 1120 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1121 *isrp = 0; 1122 return (0); 1123 } 1124 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1125 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1126 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1127 *isrp = 0; 1128 return (0); 1129 } 1130 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1131 case ISPR2HST_ROM_MBX_OK: 1132 case ISPR2HST_ROM_MBX_FAIL: 1133 case ISPR2HST_MBX_OK: 1134 case ISPR2HST_MBX_FAIL: 1135 case ISPR2HST_ASYNC_EVENT: 1136 *isrp = r2hisr & 0xffff; 1137 *mbox0p = (r2hisr >> 16); 1138 *semap = 1; 1139 return (1); 1140 case ISPR2HST_RIO_16: 1141 *isrp = r2hisr & 0xffff; 1142 *mbox0p = ASYNC_RIO16_1; 1143 *semap = 1; 1144 return (1); 1145 case ISPR2HST_FPOST: 1146 *isrp = r2hisr & 0xffff; 1147 *mbox0p = ASYNC_CMD_CMPLT; 1148 *semap = 1; 1149 return (1); 1150 case ISPR2HST_FPOST_CTIO: 1151 *isrp = r2hisr & 0xffff; 1152 *mbox0p = ASYNC_CTIO_DONE; 1153 *semap = 1; 1154 return (1); 1155 case ISPR2HST_RSPQ_UPDATE: 1156 *isrp = r2hisr & 0xffff; 1157 *mbox0p = 0; 1158 *semap = 0; 1159 return (1); 1160 default: 1161 hccr = ISP_READ(isp, HCCR); 1162 if (hccr & HCCR_PAUSE) { 1163 ISP_WRITE(isp, HCCR, HCCR_RESET); 1164 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1165 ISP_WRITE(isp, BIU_ICR, 0); 1166 } else { 1167 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1168 } 1169 return (0); 1170 } 1171 } 1172 1173 static int 1174 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1175 { 1176 uint32_t r2hisr; 1177 1178 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1179 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1180 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1181 *isrp = 0; 1182 return (0); 1183 } 1184 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1185 case ISP2400R2HST_ROM_MBX_OK: 1186 case ISP2400R2HST_ROM_MBX_FAIL: 1187 case ISP2400R2HST_MBX_OK: 1188 case ISP2400R2HST_MBX_FAIL: 1189 case ISP2400R2HST_ASYNC_EVENT: 1190 *isrp = r2hisr & 0xffff; 1191 *mbox0p = (r2hisr >> 16); 1192 *semap = 1; 1193 return (1); 1194 case ISP2400R2HST_RSPQ_UPDATE: 1195 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1196 case ISP2400R2HST_ATIO_RQST_UPDATE: 1197 *isrp = r2hisr & 0xffff; 1198 *mbox0p = 0; 1199 *semap = 0; 1200 return (1); 1201 default: 1202 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1203 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1204 return (0); 1205 } 1206 } 1207 1208 static uint32_t 1209 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1210 { 1211 uint16_t rv; 1212 int oldconf = 0; 1213 1214 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1215 /* 1216 * We will assume that someone has paused the RISC processor. 1217 */ 1218 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1219 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1220 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1221 } 1222 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1223 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1224 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1225 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1226 } 1227 return (rv); 1228 } 1229 1230 static void 1231 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1232 { 1233 int oldconf = 0; 1234 1235 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1236 /* 1237 * We will assume that someone has paused the RISC processor. 1238 */ 1239 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1240 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1241 oldconf | BIU_PCI_CONF1_SXP); 1242 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1243 } 1244 BXW2(isp, IspVirt2Off(isp, regoff), val); 1245 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1246 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1247 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1248 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1249 } 1250 1251 } 1252 1253 static uint32_t 1254 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1255 { 1256 uint32_t rv, oc = 0; 1257 1258 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1259 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1260 uint32_t tc; 1261 /* 1262 * We will assume that someone has paused the RISC processor. 1263 */ 1264 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1265 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1266 if (regoff & SXP_BANK1_SELECT) 1267 tc |= BIU_PCI1080_CONF1_SXP1; 1268 else 1269 tc |= BIU_PCI1080_CONF1_SXP0; 1270 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1271 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1272 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1273 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1274 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1275 oc | BIU_PCI1080_CONF1_DMA); 1276 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1277 } 1278 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1279 if (oc) { 1280 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1281 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1282 } 1283 return (rv); 1284 } 1285 1286 static void 1287 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1288 { 1289 int oc = 0; 1290 1291 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1292 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1293 uint32_t tc; 1294 /* 1295 * We will assume that someone has paused the RISC processor. 1296 */ 1297 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1298 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1299 if (regoff & SXP_BANK1_SELECT) 1300 tc |= BIU_PCI1080_CONF1_SXP1; 1301 else 1302 tc |= BIU_PCI1080_CONF1_SXP0; 1303 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1304 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1305 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1306 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1307 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1308 oc | BIU_PCI1080_CONF1_DMA); 1309 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1310 } 1311 BXW2(isp, IspVirt2Off(isp, regoff), val); 1312 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1313 if (oc) { 1314 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1315 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1316 } 1317 } 1318 1319 static uint32_t 1320 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1321 { 1322 uint32_t rv; 1323 int block = regoff & _BLK_REG_MASK; 1324 1325 switch (block) { 1326 case BIU_BLOCK: 1327 break; 1328 case MBOX_BLOCK: 1329 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1330 case SXP_BLOCK: 1331 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1332 return (0xffffffff); 1333 case RISC_BLOCK: 1334 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1335 return (0xffffffff); 1336 case DMA_BLOCK: 1337 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1338 return (0xffffffff); 1339 default: 1340 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1341 return (0xffffffff); 1342 } 1343 1344 1345 switch (regoff) { 1346 case BIU2400_FLASH_ADDR: 1347 case BIU2400_FLASH_DATA: 1348 case BIU2400_ICR: 1349 case BIU2400_ISR: 1350 case BIU2400_CSR: 1351 case BIU2400_REQINP: 1352 case BIU2400_REQOUTP: 1353 case BIU2400_RSPINP: 1354 case BIU2400_RSPOUTP: 1355 case BIU2400_PRI_REQINP: 1356 case BIU2400_PRI_REQOUTP: 1357 case BIU2400_ATIO_RSPINP: 1358 case BIU2400_ATIO_RSPOUTP: 1359 case BIU2400_HCCR: 1360 case BIU2400_GPIOD: 1361 case BIU2400_GPIOE: 1362 case BIU2400_HSEMA: 1363 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1364 break; 1365 case BIU2400_R2HSTSLO: 1366 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1367 break; 1368 case BIU2400_R2HSTSHI: 1369 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1370 break; 1371 default: 1372 isp_prt(isp, ISP_LOGERR, 1373 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1374 rv = 0xffffffff; 1375 break; 1376 } 1377 return (rv); 1378 } 1379 1380 static void 1381 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1382 { 1383 int block = regoff & _BLK_REG_MASK; 1384 1385 switch (block) { 1386 case BIU_BLOCK: 1387 break; 1388 case MBOX_BLOCK: 1389 BXW2(isp, IspVirt2Off(isp, regoff), val); 1390 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1391 return; 1392 case SXP_BLOCK: 1393 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1394 return; 1395 case RISC_BLOCK: 1396 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1397 return; 1398 case DMA_BLOCK: 1399 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1400 return; 1401 default: 1402 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1403 regoff); 1404 break; 1405 } 1406 1407 switch (regoff) { 1408 case BIU2400_FLASH_ADDR: 1409 case BIU2400_FLASH_DATA: 1410 case BIU2400_ICR: 1411 case BIU2400_ISR: 1412 case BIU2400_CSR: 1413 case BIU2400_REQINP: 1414 case BIU2400_REQOUTP: 1415 case BIU2400_RSPINP: 1416 case BIU2400_RSPOUTP: 1417 case BIU2400_PRI_REQINP: 1418 case BIU2400_PRI_REQOUTP: 1419 case BIU2400_ATIO_RSPINP: 1420 case BIU2400_ATIO_RSPOUTP: 1421 case BIU2400_HCCR: 1422 case BIU2400_GPIOD: 1423 case BIU2400_GPIOE: 1424 case BIU2400_HSEMA: 1425 BXW4(isp, IspVirt2Off(isp, regoff), val); 1426 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1427 break; 1428 default: 1429 isp_prt(isp, ISP_LOGERR, 1430 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1431 break; 1432 } 1433 } 1434 1435 1436 struct imush { 1437 ispsoftc_t *isp; 1438 caddr_t vbase; 1439 int chan; 1440 int error; 1441 }; 1442 1443 static void imc(void *, bus_dma_segment_t *, int, int); 1444 static void imc1(void *, bus_dma_segment_t *, int, int); 1445 1446 static void 1447 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1448 { 1449 struct imush *imushp = (struct imush *) arg; 1450 1451 if (error) { 1452 imushp->error = error; 1453 return; 1454 } 1455 if (nseg != 1) { 1456 imushp->error = EINVAL; 1457 return; 1458 } 1459 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1460 imushp->isp->isp_rquest = imushp->vbase; 1461 imushp->isp->isp_rquest_dma = segs->ds_addr; 1462 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1463 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1464 imushp->isp->isp_result_dma = segs->ds_addr; 1465 imushp->isp->isp_result = imushp->vbase; 1466 1467 #ifdef ISP_TARGET_MODE 1468 if (IS_24XX(imushp->isp)) { 1469 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1470 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1471 imushp->isp->isp_atioq_dma = segs->ds_addr; 1472 imushp->isp->isp_atioq = imushp->vbase; 1473 } 1474 #endif 1475 } 1476 1477 static void 1478 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1479 { 1480 struct imush *imushp = (struct imush *) arg; 1481 if (error) { 1482 imushp->error = error; 1483 return; 1484 } 1485 if (nseg != 1) { 1486 imushp->error = EINVAL; 1487 return; 1488 } 1489 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1490 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1491 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1492 } 1493 1494 static int 1495 isp_pci_mbxdma(ispsoftc_t *isp) 1496 { 1497 caddr_t base; 1498 uint32_t len; 1499 int i, error, ns, cmap = 0; 1500 bus_size_t slim; /* segment size */ 1501 bus_addr_t llim; /* low limit of unavailable dma */ 1502 bus_addr_t hlim; /* high limit of unavailable dma */ 1503 struct imush im; 1504 1505 /* 1506 * Already been here? If so, leave... 1507 */ 1508 if (isp->isp_rquest) { 1509 return (0); 1510 } 1511 ISP_UNLOCK(isp); 1512 1513 if (isp->isp_maxcmds == 0) { 1514 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1515 ISP_LOCK(isp); 1516 return (1); 1517 } 1518 1519 hlim = BUS_SPACE_MAXADDR; 1520 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1521 if (sizeof (bus_size_t) > 4) { 1522 slim = (bus_size_t) (1ULL << 32); 1523 } else { 1524 slim = (bus_size_t) (1UL << 31); 1525 } 1526 llim = BUS_SPACE_MAXADDR; 1527 } else { 1528 llim = BUS_SPACE_MAXADDR_32BIT; 1529 slim = (1UL << 24); 1530 } 1531 1532 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1533 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1534 if (isp->isp_osinfo.pcmd_pool == NULL) { 1535 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1536 ISP_LOCK(isp); 1537 return (1); 1538 } 1539 1540 /* 1541 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1542 */ 1543 #ifdef ISP_TARGET_MODE 1544 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1545 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1546 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1547 ISP_LOCK(isp); 1548 return (1); 1549 } 1550 #endif 1551 1552 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) { 1553 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1554 ISP_LOCK(isp); 1555 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1556 return (1); 1557 } 1558 1559 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1560 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1561 if (isp->isp_xflist == NULL) { 1562 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1563 ISP_LOCK(isp); 1564 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1565 return (1); 1566 } 1567 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1568 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1569 } 1570 isp->isp_xffree = isp->isp_xflist; 1571 #ifdef ISP_TARGET_MODE 1572 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1573 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1574 if (isp->isp_tgtlist == NULL) { 1575 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1576 free(isp->isp_xflist, M_DEVBUF); 1577 ISP_LOCK(isp); 1578 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1579 return (1); 1580 } 1581 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1582 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1583 } 1584 isp->isp_tgtfree = isp->isp_tgtlist; 1585 #endif 1586 1587 /* 1588 * Allocate and map the request and result queues (and ATIO queue 1589 * if we're a 2400 supporting target mode). 1590 */ 1591 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1592 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1593 #ifdef ISP_TARGET_MODE 1594 if (IS_24XX(isp)) { 1595 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1596 } 1597 #endif 1598 1599 ns = (len / PAGE_SIZE) + 1; 1600 1601 /* 1602 * Create a tag for the control spaces. We don't always need this 1603 * to be 32 bits, but we do this for simplicity and speed's sake. 1604 */ 1605 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) { 1606 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1607 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1608 free(isp->isp_xflist, M_DEVBUF); 1609 #ifdef ISP_TARGET_MODE 1610 free(isp->isp_tgtlist, M_DEVBUF); 1611 #endif 1612 ISP_LOCK(isp); 1613 return (1); 1614 } 1615 1616 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1617 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1618 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1619 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1620 free(isp->isp_xflist, M_DEVBUF); 1621 #ifdef ISP_TARGET_MODE 1622 free(isp->isp_tgtlist, M_DEVBUF); 1623 #endif 1624 ISP_LOCK(isp); 1625 return (1); 1626 } 1627 1628 im.isp = isp; 1629 im.chan = 0; 1630 im.vbase = base; 1631 im.error = 0; 1632 1633 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1634 if (im.error) { 1635 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1636 goto bad; 1637 } 1638 1639 if (IS_FC(isp)) { 1640 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1641 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1642 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1643 goto bad; 1644 } 1645 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1646 bus_dma_tag_destroy(fc->tdmat); 1647 goto bad; 1648 } 1649 im.isp = isp; 1650 im.chan = cmap; 1651 im.vbase = base; 1652 im.error = 0; 1653 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1654 if (im.error) { 1655 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1656 bus_dma_tag_destroy(fc->tdmat); 1657 goto bad; 1658 } 1659 } 1660 } 1661 1662 for (i = 0; i < isp->isp_maxcmds; i++) { 1663 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1664 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1665 if (error) { 1666 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1667 while (--i >= 0) { 1668 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1669 } 1670 goto bad; 1671 } 1672 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1673 if (i == isp->isp_maxcmds-1) { 1674 pcmd->next = NULL; 1675 } else { 1676 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1677 } 1678 } 1679 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1680 ISP_LOCK(isp); 1681 return (0); 1682 1683 bad: 1684 while (--cmap >= 0) { 1685 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1686 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1687 bus_dma_tag_destroy(fc->tdmat); 1688 } 1689 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1690 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1691 free(isp->isp_xflist, M_DEVBUF); 1692 #ifdef ISP_TARGET_MODE 1693 free(isp->isp_tgtlist, M_DEVBUF); 1694 #endif 1695 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1696 isp->isp_rquest = NULL; 1697 ISP_LOCK(isp); 1698 return (1); 1699 } 1700 1701 typedef struct { 1702 ispsoftc_t *isp; 1703 void *cmd_token; 1704 void *rq; /* original request */ 1705 int error; 1706 bus_size_t mapsize; 1707 } mush_t; 1708 1709 #define MUSHERR_NOQENTRIES -2 1710 1711 #ifdef ISP_TARGET_MODE 1712 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1713 static void tdma2(void *, bus_dma_segment_t *, int, int); 1714 1715 static void 1716 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1717 { 1718 mush_t *mp; 1719 mp = (mush_t *)arg; 1720 mp->mapsize = mapsize; 1721 tdma2(arg, dm_segs, nseg, error); 1722 } 1723 1724 static void 1725 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1726 { 1727 mush_t *mp; 1728 ispsoftc_t *isp; 1729 struct ccb_scsiio *csio; 1730 isp_ddir_t ddir; 1731 ispreq_t *rq; 1732 1733 mp = (mush_t *) arg; 1734 if (error) { 1735 mp->error = error; 1736 return; 1737 } 1738 csio = mp->cmd_token; 1739 isp = mp->isp; 1740 rq = mp->rq; 1741 if (nseg) { 1742 if (sizeof (bus_addr_t) > 4) { 1743 if (nseg >= ISP_NSEG64_MAX) { 1744 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1745 mp->error = EFAULT; 1746 return; 1747 } 1748 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1749 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1750 } 1751 } else { 1752 if (nseg >= ISP_NSEG_MAX) { 1753 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1754 mp->error = EFAULT; 1755 return; 1756 } 1757 } 1758 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1759 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1760 ddir = ISP_TO_DEVICE; 1761 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1762 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1763 ddir = ISP_FROM_DEVICE; 1764 } else { 1765 dm_segs = NULL; 1766 nseg = 0; 1767 ddir = ISP_NOXFR; 1768 } 1769 } else { 1770 dm_segs = NULL; 1771 nseg = 0; 1772 ddir = ISP_NOXFR; 1773 } 1774 1775 if (isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len) != CMD_QUEUED) { 1776 mp->error = MUSHERR_NOQENTRIES; 1777 } 1778 } 1779 #endif 1780 1781 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1782 static void dma2(void *, bus_dma_segment_t *, int, int); 1783 1784 static void 1785 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1786 { 1787 mush_t *mp; 1788 mp = (mush_t *)arg; 1789 mp->mapsize = mapsize; 1790 dma2(arg, dm_segs, nseg, error); 1791 } 1792 1793 static void 1794 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1795 { 1796 mush_t *mp; 1797 ispsoftc_t *isp; 1798 struct ccb_scsiio *csio; 1799 isp_ddir_t ddir; 1800 ispreq_t *rq; 1801 1802 mp = (mush_t *) arg; 1803 if (error) { 1804 mp->error = error; 1805 return; 1806 } 1807 csio = mp->cmd_token; 1808 isp = mp->isp; 1809 rq = mp->rq; 1810 if (nseg) { 1811 if (sizeof (bus_addr_t) > 4) { 1812 if (nseg >= ISP_NSEG64_MAX) { 1813 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1814 mp->error = EFAULT; 1815 return; 1816 } 1817 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1818 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1819 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1820 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1821 } 1822 } else { 1823 if (nseg >= ISP_NSEG_MAX) { 1824 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1825 mp->error = EFAULT; 1826 return; 1827 } 1828 } 1829 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1830 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1831 ddir = ISP_FROM_DEVICE; 1832 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1833 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1834 ddir = ISP_TO_DEVICE; 1835 } else { 1836 ddir = ISP_NOXFR; 1837 } 1838 } else { 1839 dm_segs = NULL; 1840 nseg = 0; 1841 ddir = ISP_NOXFR; 1842 } 1843 1844 if (isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir) != CMD_QUEUED) { 1845 mp->error = MUSHERR_NOQENTRIES; 1846 } 1847 } 1848 1849 static int 1850 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1851 { 1852 mush_t mush, *mp; 1853 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1854 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1855 1856 mp = &mush; 1857 mp->isp = isp; 1858 mp->cmd_token = csio; 1859 mp->rq = ff; 1860 mp->error = 0; 1861 mp->mapsize = 0; 1862 1863 #ifdef ISP_TARGET_MODE 1864 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1865 eptr = tdma2; 1866 eptr2 = tdma2_2; 1867 } else 1868 #endif 1869 { 1870 eptr = dma2; 1871 eptr2 = dma2_2; 1872 } 1873 1874 1875 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) { 1876 (*eptr)(mp, NULL, 0, 0); 1877 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1878 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1879 int error; 1880 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1881 #if 0 1882 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error); 1883 #endif 1884 1885 if (error == EINPROGRESS) { 1886 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1887 mp->error = EINVAL; 1888 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1889 } else if (error && mp->error == 0) { 1890 #ifdef DIAGNOSTIC 1891 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1892 #endif 1893 mp->error = error; 1894 } 1895 } else { 1896 /* Pointer to physical buffer */ 1897 struct bus_dma_segment seg; 1898 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 1899 seg.ds_len = csio->dxfer_len; 1900 (*eptr)(mp, &seg, 1, 0); 1901 } 1902 } else { 1903 struct bus_dma_segment *segs; 1904 1905 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1906 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported"); 1907 mp->error = EINVAL; 1908 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1909 struct uio sguio; 1910 int error; 1911 1912 /* 1913 * We're taking advantage of the fact that 1914 * the pointer/length sizes and layout of the iovec 1915 * structure are the same as the bus_dma_segment 1916 * structure. This might be a little dangerous, 1917 * but only if they change the structures, which 1918 * seems unlikely. 1919 */ 1920 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) && 1921 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) && 1922 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed")); 1923 sguio.uio_iov = (struct iovec *)csio->data_ptr; 1924 sguio.uio_iovcnt = csio->sglist_cnt; 1925 sguio.uio_resid = csio->dxfer_len; 1926 sguio.uio_segflg = UIO_SYSSPACE; 1927 1928 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0); 1929 1930 if (error != 0 && mp->error == 0) { 1931 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1932 mp->error = error; 1933 } 1934 } else { 1935 /* Just use the segments provided */ 1936 segs = (struct bus_dma_segment *) csio->data_ptr; 1937 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1938 } 1939 } 1940 if (mp->error) { 1941 int retval = CMD_COMPLETE; 1942 if (mp->error == MUSHERR_NOQENTRIES) { 1943 retval = CMD_EAGAIN; 1944 } else if (mp->error == EFBIG) { 1945 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1946 } else if (mp->error == EINVAL) { 1947 XS_SETERR(csio, CAM_REQ_INVALID); 1948 } else { 1949 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1950 } 1951 return (retval); 1952 } 1953 return (CMD_QUEUED); 1954 } 1955 1956 static void 1957 isp_pci_reset0(ispsoftc_t *isp) 1958 { 1959 ISP_DISABLE_INTS(isp); 1960 } 1961 1962 static void 1963 isp_pci_reset1(ispsoftc_t *isp) 1964 { 1965 if (!IS_24XX(isp)) { 1966 /* Make sure the BIOS is disabled */ 1967 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1968 } 1969 /* and enable interrupts */ 1970 ISP_ENABLE_INTS(isp); 1971 } 1972 1973 static void 1974 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1975 { 1976 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1977 if (msg) 1978 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1979 else 1980 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1981 if (IS_SCSI(isp)) 1982 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1983 else 1984 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1985 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1986 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1987 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1988 1989 1990 if (IS_SCSI(isp)) { 1991 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1992 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1993 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1994 ISP_READ(isp, CDMA_FIFO_STS)); 1995 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1996 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1997 ISP_READ(isp, DDMA_FIFO_STS)); 1998 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1999 ISP_READ(isp, SXP_INTERRUPT), 2000 ISP_READ(isp, SXP_GROSS_ERR), 2001 ISP_READ(isp, SXP_PINS_CTRL)); 2002 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2003 } 2004 printf(" mbox regs: %x %x %x %x %x\n", 2005 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2006 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2007 ISP_READ(isp, OUTMAILBOX4)); 2008 printf(" PCI Status Command/Status=%x\n", 2009 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2010 } 2011