1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 #include <sys/malloc.h> 47 #include <sys/uio.h> 48 49 #ifdef __sparc64__ 50 #include <dev/ofw/openfirm.h> 51 #include <machine/ofw_machdep.h> 52 #endif 53 54 #include <dev/isp/isp_freebsd.h> 55 56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 62 static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 63 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 64 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 65 static int isp_pci_mbxdma(ispsoftc_t *); 66 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 67 68 69 static void isp_pci_reset0(ispsoftc_t *); 70 static void isp_pci_reset1(ispsoftc_t *); 71 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 72 73 static struct ispmdvec mdvec = { 74 isp_pci_rd_isr, 75 isp_pci_rd_reg, 76 isp_pci_wr_reg, 77 isp_pci_mbxdma, 78 isp_pci_dmasetup, 79 isp_common_dmateardown, 80 isp_pci_reset0, 81 isp_pci_reset1, 82 isp_pci_dumpregs, 83 NULL, 84 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 85 }; 86 87 static struct ispmdvec mdvec_1080 = { 88 isp_pci_rd_isr, 89 isp_pci_rd_reg_1080, 90 isp_pci_wr_reg_1080, 91 isp_pci_mbxdma, 92 isp_pci_dmasetup, 93 isp_common_dmateardown, 94 isp_pci_reset0, 95 isp_pci_reset1, 96 isp_pci_dumpregs, 97 NULL, 98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 99 }; 100 101 static struct ispmdvec mdvec_12160 = { 102 isp_pci_rd_isr, 103 isp_pci_rd_reg_1080, 104 isp_pci_wr_reg_1080, 105 isp_pci_mbxdma, 106 isp_pci_dmasetup, 107 isp_common_dmateardown, 108 isp_pci_reset0, 109 isp_pci_reset1, 110 isp_pci_dumpregs, 111 NULL, 112 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 113 }; 114 115 static struct ispmdvec mdvec_2100 = { 116 isp_pci_rd_isr, 117 isp_pci_rd_reg, 118 isp_pci_wr_reg, 119 isp_pci_mbxdma, 120 isp_pci_dmasetup, 121 isp_common_dmateardown, 122 isp_pci_reset0, 123 isp_pci_reset1, 124 isp_pci_dumpregs 125 }; 126 127 static struct ispmdvec mdvec_2200 = { 128 isp_pci_rd_isr, 129 isp_pci_rd_reg, 130 isp_pci_wr_reg, 131 isp_pci_mbxdma, 132 isp_pci_dmasetup, 133 isp_common_dmateardown, 134 isp_pci_reset0, 135 isp_pci_reset1, 136 isp_pci_dumpregs 137 }; 138 139 static struct ispmdvec mdvec_2300 = { 140 isp_pci_rd_isr_2300, 141 isp_pci_rd_reg, 142 isp_pci_wr_reg, 143 isp_pci_mbxdma, 144 isp_pci_dmasetup, 145 isp_common_dmateardown, 146 isp_pci_reset0, 147 isp_pci_reset1, 148 isp_pci_dumpregs 149 }; 150 151 static struct ispmdvec mdvec_2400 = { 152 isp_pci_rd_isr_2400, 153 isp_pci_rd_reg_2400, 154 isp_pci_wr_reg_2400, 155 isp_pci_mbxdma, 156 isp_pci_dmasetup, 157 isp_common_dmateardown, 158 isp_pci_reset0, 159 isp_pci_reset1, 160 NULL 161 }; 162 163 static struct ispmdvec mdvec_2500 = { 164 isp_pci_rd_isr_2400, 165 isp_pci_rd_reg_2400, 166 isp_pci_wr_reg_2400, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_common_dmateardown, 170 isp_pci_reset0, 171 isp_pci_reset1, 172 NULL 173 }; 174 175 #ifndef PCIM_CMD_INVEN 176 #define PCIM_CMD_INVEN 0x10 177 #endif 178 #ifndef PCIM_CMD_BUSMASTEREN 179 #define PCIM_CMD_BUSMASTEREN 0x0004 180 #endif 181 #ifndef PCIM_CMD_PERRESPEN 182 #define PCIM_CMD_PERRESPEN 0x0040 183 #endif 184 #ifndef PCIM_CMD_SEREN 185 #define PCIM_CMD_SEREN 0x0100 186 #endif 187 #ifndef PCIM_CMD_INTX_DISABLE 188 #define PCIM_CMD_INTX_DISABLE 0x0400 189 #endif 190 191 #ifndef PCIR_COMMAND 192 #define PCIR_COMMAND 0x04 193 #endif 194 195 #ifndef PCIR_CACHELNSZ 196 #define PCIR_CACHELNSZ 0x0c 197 #endif 198 199 #ifndef PCIR_LATTIMER 200 #define PCIR_LATTIMER 0x0d 201 #endif 202 203 #ifndef PCIR_ROMADDR 204 #define PCIR_ROMADDR 0x30 205 #endif 206 207 #ifndef PCI_VENDOR_QLOGIC 208 #define PCI_VENDOR_QLOGIC 0x1077 209 #endif 210 211 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 212 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 213 #endif 214 215 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 216 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 217 #endif 218 219 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 220 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 221 #endif 222 223 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 224 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 225 #endif 226 227 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 228 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 229 #endif 230 231 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 232 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 233 #endif 234 235 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 236 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 237 #endif 238 239 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 240 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 241 #endif 242 243 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 244 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 245 #endif 246 247 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 248 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 249 #endif 250 251 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 252 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 253 #endif 254 255 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 256 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 257 #endif 258 259 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 260 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 261 #endif 262 263 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 264 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 265 #endif 266 267 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 268 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 269 #endif 270 271 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 272 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 273 #endif 274 275 276 #define PCI_QLOGIC_ISP1020 \ 277 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 278 279 #define PCI_QLOGIC_ISP1080 \ 280 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP10160 \ 283 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP12160 \ 286 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define PCI_QLOGIC_ISP1240 \ 289 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 290 291 #define PCI_QLOGIC_ISP1280 \ 292 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 293 294 #define PCI_QLOGIC_ISP2100 \ 295 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 296 297 #define PCI_QLOGIC_ISP2200 \ 298 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 299 300 #define PCI_QLOGIC_ISP2300 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 302 303 #define PCI_QLOGIC_ISP2312 \ 304 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 305 306 #define PCI_QLOGIC_ISP2322 \ 307 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 308 309 #define PCI_QLOGIC_ISP2422 \ 310 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 311 312 #define PCI_QLOGIC_ISP2432 \ 313 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 314 315 #define PCI_QLOGIC_ISP2532 \ 316 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 317 318 #define PCI_QLOGIC_ISP6312 \ 319 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 320 321 #define PCI_QLOGIC_ISP6322 \ 322 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 323 324 /* 325 * Odd case for some AMI raid cards... We need to *not* attach to this. 326 */ 327 #define AMI_RAID_SUBVENDOR_ID 0x101e 328 329 #define IO_MAP_REG 0x10 330 #define MEM_MAP_REG 0x14 331 332 #define PCI_DFLT_LTNCY 0x40 333 #define PCI_DFLT_LNSZ 0x10 334 335 static int isp_pci_probe (device_t); 336 static int isp_pci_attach (device_t); 337 static int isp_pci_detach (device_t); 338 339 340 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 341 struct isp_pcisoftc { 342 ispsoftc_t pci_isp; 343 device_t pci_dev; 344 struct resource * pci_reg; 345 void * ih; 346 int16_t pci_poff[_NREG_BLKS]; 347 bus_dma_tag_t dmat; 348 int msicount; 349 }; 350 351 352 static device_method_t isp_pci_methods[] = { 353 /* Device interface */ 354 DEVMETHOD(device_probe, isp_pci_probe), 355 DEVMETHOD(device_attach, isp_pci_attach), 356 DEVMETHOD(device_detach, isp_pci_detach), 357 { 0, 0 } 358 }; 359 360 static driver_t isp_pci_driver = { 361 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 362 }; 363 static devclass_t isp_devclass; 364 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 365 366 static int 367 isp_pci_probe(device_t dev) 368 { 369 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 370 case PCI_QLOGIC_ISP1020: 371 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 372 break; 373 case PCI_QLOGIC_ISP1080: 374 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 375 break; 376 case PCI_QLOGIC_ISP1240: 377 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 378 break; 379 case PCI_QLOGIC_ISP1280: 380 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 381 break; 382 case PCI_QLOGIC_ISP10160: 383 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 384 break; 385 case PCI_QLOGIC_ISP12160: 386 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 387 return (ENXIO); 388 } 389 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 390 break; 391 case PCI_QLOGIC_ISP2100: 392 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 393 break; 394 case PCI_QLOGIC_ISP2200: 395 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 396 break; 397 case PCI_QLOGIC_ISP2300: 398 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 399 break; 400 case PCI_QLOGIC_ISP2312: 401 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 402 break; 403 case PCI_QLOGIC_ISP2322: 404 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 405 break; 406 case PCI_QLOGIC_ISP2422: 407 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 408 break; 409 case PCI_QLOGIC_ISP2432: 410 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 411 break; 412 case PCI_QLOGIC_ISP2532: 413 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 414 break; 415 case PCI_QLOGIC_ISP6312: 416 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 417 break; 418 case PCI_QLOGIC_ISP6322: 419 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 420 break; 421 default: 422 return (ENXIO); 423 } 424 if (isp_announced == 0 && bootverbose) { 425 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 426 "Core Version %d.%d\n", 427 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 428 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 429 isp_announced++; 430 } 431 /* 432 * XXXX: Here is where we might load the f/w module 433 * XXXX: (or increase a reference count to it). 434 */ 435 return (BUS_PROBE_DEFAULT); 436 } 437 438 static void 439 isp_get_generic_options(device_t dev, ispsoftc_t *isp, int *nvp) 440 { 441 int tval; 442 443 /* 444 * Figure out if we're supposed to skip this one. 445 */ 446 tval = 0; 447 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 448 device_printf(dev, "disabled at user request\n"); 449 isp->isp_osinfo.disabled = 1; 450 return; 451 } 452 453 tval = 0; 454 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 455 isp->isp_confopts |= ISP_CFG_NORELOAD; 456 } 457 tval = 0; 458 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 459 isp->isp_confopts |= ISP_CFG_NONVRAM; 460 } 461 tval = 0; 462 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 463 if (tval) { 464 isp->isp_dblev = tval; 465 } else { 466 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 467 } 468 if (bootverbose) { 469 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 470 } 471 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 472 if (tval > 0 && tval < 127) { 473 *nvp = tval; 474 } else { 475 *nvp = 0; 476 } 477 tval = 1; 478 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 479 isp_autoconfig = tval; 480 tval = 7; 481 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 482 isp_quickboot_time = tval; 483 484 tval = 0; 485 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "forcemulti", &tval) == 0 && tval != 0) { 486 isp->isp_osinfo.forcemulti = 1; 487 } 488 } 489 490 static void 491 isp_get_pci_options(device_t dev, int *m1, int *m2) 492 { 493 int tval; 494 /* 495 * Which we should try first - memory mapping or i/o mapping? 496 * 497 * We used to try memory first followed by i/o on alpha, otherwise 498 * the reverse, but we should just try memory first all the time now. 499 */ 500 *m1 = PCIM_CMD_MEMEN; 501 *m2 = PCIM_CMD_PORTEN; 502 503 tval = 0; 504 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 505 *m1 = PCIM_CMD_PORTEN; 506 *m2 = PCIM_CMD_MEMEN; 507 } 508 tval = 0; 509 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 510 *m1 = PCIM_CMD_MEMEN; 511 *m2 = PCIM_CMD_PORTEN; 512 } 513 } 514 515 static void 516 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 517 { 518 const char *sptr; 519 int tval; 520 521 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 522 if (IS_FC(isp)) { 523 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 524 } else { 525 #ifdef __sparc64__ 526 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 527 #else 528 ISP_SPI_PC(isp, chan)->iid = 7; 529 #endif 530 } 531 } else { 532 if (IS_FC(isp)) { 533 ISP_FC_PC(isp, chan)->default_id = tval - chan; 534 } else { 535 ISP_SPI_PC(isp, chan)->iid = tval; 536 } 537 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 538 } 539 540 tval = -1; 541 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 542 switch (tval) { 543 case ISP_ROLE_NONE: 544 case ISP_ROLE_INITIATOR: 545 case ISP_ROLE_TARGET: 546 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 547 device_printf(dev, "setting role to 0x%x\n", tval); 548 break; 549 default: 550 tval = -1; 551 break; 552 } 553 } 554 if (tval == -1) { 555 tval = ISP_DEFAULT_ROLES; 556 } 557 558 if (IS_SCSI(isp)) { 559 ISP_SPI_PC(isp, chan)->def_role = tval; 560 return; 561 } 562 ISP_FC_PC(isp, chan)->def_role = tval; 563 564 tval = 0; 565 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 566 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 567 } 568 sptr = 0; 569 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", (const char **) &sptr) == 0 && sptr != 0) { 570 if (strcmp(sptr, "lport") == 0) { 571 isp->isp_confopts |= ISP_CFG_LPORT; 572 } else if (strcmp(sptr, "nport") == 0) { 573 isp->isp_confopts |= ISP_CFG_NPORT; 574 } else if (strcmp(sptr, "lport-only") == 0) { 575 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 576 } else if (strcmp(sptr, "nport-only") == 0) { 577 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 578 } 579 } 580 581 /* 582 * Because the resource_*_value functions can neither return 583 * 64 bit integer values, nor can they be directly coerced 584 * to interpret the right hand side of the assignment as 585 * you want them to interpret it, we have to force WWN 586 * hint replacement to specify WWN strings with a leading 587 * 'w' (e..g w50000000aaaa0001). Sigh. 588 */ 589 sptr = 0; 590 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", (const char **) &sptr); 591 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 592 char *eptr = 0; 593 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 594 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 595 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 596 ISP_FC_PC(isp, chan)->def_wwpn = 0; 597 } 598 } 599 600 sptr = 0; 601 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", (const char **) &sptr); 602 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 603 char *eptr = 0; 604 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 605 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 606 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 607 ISP_FC_PC(isp, chan)->def_wwnn = 0; 608 } 609 } 610 611 tval = 0; 612 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 613 if (tval >= 0 && tval < 256) { 614 ISP_FC_PC(isp, chan)->hysteresis = tval; 615 } else { 616 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 617 } 618 619 tval = -1; 620 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 621 if (tval >= 0 && tval < 0xffff) { 622 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 623 } else { 624 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 625 } 626 627 tval = -1; 628 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 629 if (tval >= 0 && tval < 0xffff) { 630 ISP_FC_PC(isp, chan)->gone_device_time = tval; 631 } else { 632 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 633 } 634 } 635 636 static int 637 isp_pci_attach(device_t dev) 638 { 639 struct resource *regs, *irq; 640 int rtp, rgd, iqd, i, m1, m2, locksetup = 0; 641 int isp_nvports = 0; 642 uint32_t data, cmd, linesz, did; 643 struct isp_pcisoftc *pcs; 644 ispsoftc_t *isp; 645 size_t psize, xsize; 646 char fwname[32]; 647 648 pcs = device_get_softc(dev); 649 if (pcs == NULL) { 650 device_printf(dev, "cannot get softc\n"); 651 return (ENOMEM); 652 } 653 memset(pcs, 0, sizeof (*pcs)); 654 655 pcs->pci_dev = dev; 656 isp = &pcs->pci_isp; 657 isp->isp_dev = dev; 658 isp->isp_nchan = 1; 659 660 /* 661 * Get Generic Options 662 */ 663 isp_get_generic_options(dev, isp, &isp_nvports); 664 665 /* 666 * Check to see if options have us disabled 667 */ 668 if (isp->isp_osinfo.disabled) { 669 /* 670 * But return zero to preserve unit numbering 671 */ 672 return (0); 673 } 674 675 /* 676 * Get PCI options- which in this case are just mapping preferences. 677 */ 678 isp_get_pci_options(dev, &m1, &m2); 679 680 linesz = PCI_DFLT_LNSZ; 681 irq = regs = NULL; 682 rgd = rtp = iqd = 0; 683 684 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 685 if (cmd & m1) { 686 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 687 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 688 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 689 } 690 if (regs == NULL && (cmd & m2)) { 691 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 692 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 693 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 694 } 695 if (regs == NULL) { 696 device_printf(dev, "unable to map any ports\n"); 697 goto bad; 698 } 699 if (bootverbose) { 700 device_printf(dev, "using %s space register mapping\n", (rgd == IO_MAP_REG)? "I/O" : "Memory"); 701 } 702 isp->isp_bus_tag = rman_get_bustag(regs); 703 isp->isp_bus_handle = rman_get_bushandle(regs); 704 705 pcs->pci_dev = dev; 706 pcs->pci_reg = regs; 707 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 708 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 709 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 710 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 711 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 712 713 switch (pci_get_devid(dev)) { 714 case PCI_QLOGIC_ISP1020: 715 did = 0x1040; 716 isp->isp_mdvec = &mdvec; 717 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 718 break; 719 case PCI_QLOGIC_ISP1080: 720 did = 0x1080; 721 isp->isp_mdvec = &mdvec_1080; 722 isp->isp_type = ISP_HA_SCSI_1080; 723 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 724 break; 725 case PCI_QLOGIC_ISP1240: 726 did = 0x1080; 727 isp->isp_mdvec = &mdvec_1080; 728 isp->isp_type = ISP_HA_SCSI_1240; 729 isp->isp_nchan = 2; 730 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 731 break; 732 case PCI_QLOGIC_ISP1280: 733 did = 0x1080; 734 isp->isp_mdvec = &mdvec_1080; 735 isp->isp_type = ISP_HA_SCSI_1280; 736 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 737 break; 738 case PCI_QLOGIC_ISP10160: 739 did = 0x12160; 740 isp->isp_mdvec = &mdvec_12160; 741 isp->isp_type = ISP_HA_SCSI_10160; 742 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 743 break; 744 case PCI_QLOGIC_ISP12160: 745 did = 0x12160; 746 isp->isp_nchan = 2; 747 isp->isp_mdvec = &mdvec_12160; 748 isp->isp_type = ISP_HA_SCSI_12160; 749 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 750 break; 751 case PCI_QLOGIC_ISP2100: 752 did = 0x2100; 753 isp->isp_mdvec = &mdvec_2100; 754 isp->isp_type = ISP_HA_FC_2100; 755 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 756 if (pci_get_revid(dev) < 3) { 757 /* 758 * XXX: Need to get the actual revision 759 * XXX: number of the 2100 FB. At any rate, 760 * XXX: lower cache line size for early revision 761 * XXX; boards. 762 */ 763 linesz = 1; 764 } 765 break; 766 case PCI_QLOGIC_ISP2200: 767 did = 0x2200; 768 isp->isp_mdvec = &mdvec_2200; 769 isp->isp_type = ISP_HA_FC_2200; 770 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 771 break; 772 case PCI_QLOGIC_ISP2300: 773 did = 0x2300; 774 isp->isp_mdvec = &mdvec_2300; 775 isp->isp_type = ISP_HA_FC_2300; 776 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 777 break; 778 case PCI_QLOGIC_ISP2312: 779 case PCI_QLOGIC_ISP6312: 780 did = 0x2300; 781 isp->isp_mdvec = &mdvec_2300; 782 isp->isp_type = ISP_HA_FC_2312; 783 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 784 break; 785 case PCI_QLOGIC_ISP2322: 786 case PCI_QLOGIC_ISP6322: 787 did = 0x2322; 788 isp->isp_mdvec = &mdvec_2300; 789 isp->isp_type = ISP_HA_FC_2322; 790 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 791 break; 792 case PCI_QLOGIC_ISP2422: 793 case PCI_QLOGIC_ISP2432: 794 did = 0x2400; 795 isp->isp_nchan += isp_nvports; 796 isp->isp_mdvec = &mdvec_2400; 797 isp->isp_type = ISP_HA_FC_2400; 798 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 799 break; 800 case PCI_QLOGIC_ISP2532: 801 did = 0x2500; 802 isp->isp_nchan += isp_nvports; 803 isp->isp_mdvec = &mdvec_2500; 804 isp->isp_type = ISP_HA_FC_2500; 805 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 806 break; 807 default: 808 device_printf(dev, "unknown device type\n"); 809 goto bad; 810 break; 811 } 812 isp->isp_revision = pci_get_revid(dev); 813 814 if (IS_FC(isp)) { 815 psize = sizeof (fcparam); 816 xsize = sizeof (struct isp_fc); 817 } else { 818 psize = sizeof (sdparam); 819 xsize = sizeof (struct isp_spi); 820 } 821 psize *= isp->isp_nchan; 822 xsize *= isp->isp_nchan; 823 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 824 if (isp->isp_param == NULL) { 825 device_printf(dev, "cannot allocate parameter data\n"); 826 goto bad; 827 } 828 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 829 if (isp->isp_osinfo.pc.ptr == NULL) { 830 device_printf(dev, "cannot allocate parameter data\n"); 831 goto bad; 832 } 833 834 /* 835 * Now that we know who we are (roughly) get/set specific options 836 */ 837 for (i = 0; i < isp->isp_nchan; i++) { 838 isp_get_specific_options(dev, i, isp); 839 } 840 841 /* 842 * The 'it' suffix really only matters for SCSI cards in target mode. 843 */ 844 isp->isp_osinfo.fw = NULL; 845 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 846 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 847 isp->isp_osinfo.fw = firmware_get(fwname); 848 } else if (IS_24XX(isp) && (isp->isp_nchan > 1 || isp->isp_osinfo.forcemulti)) { 849 snprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 850 isp->isp_osinfo.fw = firmware_get(fwname); 851 } 852 if (isp->isp_osinfo.fw == NULL) { 853 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 854 isp->isp_osinfo.fw = firmware_get(fwname); 855 } 856 if (isp->isp_osinfo.fw != NULL) { 857 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 858 } 859 860 /* 861 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 862 * are set. 863 */ 864 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 865 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 866 867 if (IS_2300(isp)) { /* per QLogic errata */ 868 cmd &= ~PCIM_CMD_INVEN; 869 } 870 871 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 872 cmd &= ~PCIM_CMD_INTX_DISABLE; 873 } 874 875 if (IS_24XX(isp)) { 876 cmd &= ~PCIM_CMD_INTX_DISABLE; 877 } 878 879 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 880 881 /* 882 * Make sure the Cache Line Size register is set sensibly. 883 */ 884 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 885 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 886 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d from %d", linesz, data); 887 data = linesz; 888 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 889 } 890 891 /* 892 * Make sure the Latency Timer is sane. 893 */ 894 data = pci_read_config(dev, PCIR_LATTIMER, 1); 895 if (data < PCI_DFLT_LTNCY) { 896 data = PCI_DFLT_LTNCY; 897 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 898 pci_write_config(dev, PCIR_LATTIMER, data, 1); 899 } 900 901 /* 902 * Make sure we've disabled the ROM. 903 */ 904 data = pci_read_config(dev, PCIR_ROMADDR, 4); 905 data &= ~1; 906 pci_write_config(dev, PCIR_ROMADDR, data, 4); 907 908 /* 909 * Do MSI 910 * 911 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 912 */ 913 if (IS_24XX(isp) || IS_2322(isp)) { 914 pcs->msicount = pci_msi_count(dev); 915 if (pcs->msicount > 1) { 916 pcs->msicount = 1; 917 } 918 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 919 iqd = 1; 920 } else { 921 iqd = 0; 922 } 923 } 924 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd, RF_ACTIVE | RF_SHAREABLE); 925 if (irq == NULL) { 926 device_printf(dev, "could not allocate interrupt\n"); 927 goto bad; 928 } 929 930 /* Make sure the lock is set up. */ 931 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 932 locksetup++; 933 934 if (isp_setup_intr(dev, irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 935 device_printf(dev, "could not setup interrupt\n"); 936 goto bad; 937 } 938 939 /* 940 * Last minute checks... 941 */ 942 if (IS_23XX(isp) || IS_24XX(isp)) { 943 isp->isp_port = pci_get_function(dev); 944 } 945 946 /* 947 * Make sure we're in reset state. 948 */ 949 ISP_LOCK(isp); 950 isp_reset(isp, 1); 951 if (isp->isp_state != ISP_RESETSTATE) { 952 ISP_UNLOCK(isp); 953 goto bad; 954 } 955 isp_init(isp); 956 if (isp->isp_state == ISP_INITSTATE) { 957 isp->isp_state = ISP_RUNSTATE; 958 } 959 ISP_UNLOCK(isp); 960 if (isp_attach(isp)) { 961 ISP_LOCK(isp); 962 isp_uninit(isp); 963 ISP_UNLOCK(isp); 964 goto bad; 965 } 966 return (0); 967 968 bad: 969 if (pcs->ih) { 970 (void) bus_teardown_intr(dev, irq, pcs->ih); 971 } 972 if (locksetup) { 973 mtx_destroy(&isp->isp_osinfo.lock); 974 } 975 if (irq) { 976 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 977 } 978 if (pcs->msicount) { 979 pci_release_msi(dev); 980 } 981 if (regs) { 982 (void) bus_release_resource(dev, rtp, rgd, regs); 983 } 984 if (pcs->pci_isp.isp_param) { 985 free(pcs->pci_isp.isp_param, M_DEVBUF); 986 pcs->pci_isp.isp_param = NULL; 987 } 988 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 989 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 990 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 991 } 992 return (ENXIO); 993 } 994 995 static int 996 isp_pci_detach(device_t dev) 997 { 998 struct isp_pcisoftc *pcs; 999 ispsoftc_t *isp; 1000 1001 pcs = device_get_softc(dev); 1002 if (pcs == NULL) { 1003 return (ENXIO); 1004 } 1005 isp = (ispsoftc_t *) pcs; 1006 ISP_DISABLE_INTS(isp); 1007 mtx_destroy(&isp->isp_osinfo.lock); 1008 return (0); 1009 } 1010 1011 #define IspVirt2Off(a, x) \ 1012 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1013 _BLK_REG_SHFT] + ((x) & 0xfff)) 1014 1015 #define BXR2(isp, off) \ 1016 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1017 #define BXW2(isp, off, v) \ 1018 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1019 #define BXR4(isp, off) \ 1020 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1021 #define BXW4(isp, off, v) \ 1022 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1023 1024 1025 static ISP_INLINE int 1026 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1027 { 1028 uint32_t val0, val1; 1029 int i = 0; 1030 1031 do { 1032 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1033 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1034 } while (val0 != val1 && ++i < 1000); 1035 if (val0 != val1) { 1036 return (1); 1037 } 1038 *rp = val0; 1039 return (0); 1040 } 1041 1042 static int 1043 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1044 { 1045 uint16_t isr, sema; 1046 1047 if (IS_2100(isp)) { 1048 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1049 return (0); 1050 } 1051 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1052 return (0); 1053 } 1054 } else { 1055 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1056 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1057 } 1058 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1059 isr &= INT_PENDING_MASK(isp); 1060 sema &= BIU_SEMA_LOCK; 1061 if (isr == 0 && sema == 0) { 1062 return (0); 1063 } 1064 *isrp = isr; 1065 if ((*semap = sema) != 0) { 1066 if (IS_2100(isp)) { 1067 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1068 return (0); 1069 } 1070 } else { 1071 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1072 } 1073 } 1074 return (1); 1075 } 1076 1077 static int 1078 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1079 { 1080 uint32_t hccr; 1081 uint32_t r2hisr; 1082 1083 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1084 *isrp = 0; 1085 return (0); 1086 } 1087 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1088 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1089 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1090 *isrp = 0; 1091 return (0); 1092 } 1093 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1094 case ISPR2HST_ROM_MBX_OK: 1095 case ISPR2HST_ROM_MBX_FAIL: 1096 case ISPR2HST_MBX_OK: 1097 case ISPR2HST_MBX_FAIL: 1098 case ISPR2HST_ASYNC_EVENT: 1099 *isrp = r2hisr & 0xffff; 1100 *mbox0p = (r2hisr >> 16); 1101 *semap = 1; 1102 return (1); 1103 case ISPR2HST_RIO_16: 1104 *isrp = r2hisr & 0xffff; 1105 *mbox0p = ASYNC_RIO16_1; 1106 *semap = 1; 1107 return (1); 1108 case ISPR2HST_FPOST: 1109 *isrp = r2hisr & 0xffff; 1110 *mbox0p = ASYNC_CMD_CMPLT; 1111 *semap = 1; 1112 return (1); 1113 case ISPR2HST_FPOST_CTIO: 1114 *isrp = r2hisr & 0xffff; 1115 *mbox0p = ASYNC_CTIO_DONE; 1116 *semap = 1; 1117 return (1); 1118 case ISPR2HST_RSPQ_UPDATE: 1119 *isrp = r2hisr & 0xffff; 1120 *mbox0p = 0; 1121 *semap = 0; 1122 return (1); 1123 default: 1124 hccr = ISP_READ(isp, HCCR); 1125 if (hccr & HCCR_PAUSE) { 1126 ISP_WRITE(isp, HCCR, HCCR_RESET); 1127 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1128 ISP_WRITE(isp, BIU_ICR, 0); 1129 } else { 1130 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1131 } 1132 return (0); 1133 } 1134 } 1135 1136 static int 1137 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1138 { 1139 uint32_t r2hisr; 1140 1141 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1142 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1143 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1144 *isrp = 0; 1145 return (0); 1146 } 1147 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1148 case ISP2400R2HST_ROM_MBX_OK: 1149 case ISP2400R2HST_ROM_MBX_FAIL: 1150 case ISP2400R2HST_MBX_OK: 1151 case ISP2400R2HST_MBX_FAIL: 1152 case ISP2400R2HST_ASYNC_EVENT: 1153 *isrp = r2hisr & 0xffff; 1154 *mbox0p = (r2hisr >> 16); 1155 *semap = 1; 1156 return (1); 1157 case ISP2400R2HST_RSPQ_UPDATE: 1158 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1159 case ISP2400R2HST_ATIO_RQST_UPDATE: 1160 *isrp = r2hisr & 0xffff; 1161 *mbox0p = 0; 1162 *semap = 0; 1163 return (1); 1164 default: 1165 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1166 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1167 return (0); 1168 } 1169 } 1170 1171 static uint32_t 1172 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1173 { 1174 uint16_t rv; 1175 int oldconf = 0; 1176 1177 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1178 /* 1179 * We will assume that someone has paused the RISC processor. 1180 */ 1181 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1182 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1183 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1184 } 1185 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1186 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1187 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1188 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1189 } 1190 return (rv); 1191 } 1192 1193 static void 1194 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1195 { 1196 int oldconf = 0; 1197 1198 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1199 /* 1200 * We will assume that someone has paused the RISC processor. 1201 */ 1202 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1203 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1204 oldconf | BIU_PCI_CONF1_SXP); 1205 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1206 } 1207 BXW2(isp, IspVirt2Off(isp, regoff), val); 1208 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1209 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1210 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1211 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1212 } 1213 1214 } 1215 1216 static uint32_t 1217 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1218 { 1219 uint32_t rv, oc = 0; 1220 1221 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1222 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1223 uint32_t tc; 1224 /* 1225 * We will assume that someone has paused the RISC processor. 1226 */ 1227 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1228 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1229 if (regoff & SXP_BANK1_SELECT) 1230 tc |= BIU_PCI1080_CONF1_SXP1; 1231 else 1232 tc |= BIU_PCI1080_CONF1_SXP0; 1233 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1234 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1235 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1236 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1237 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1238 oc | BIU_PCI1080_CONF1_DMA); 1239 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1240 } 1241 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1242 if (oc) { 1243 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1244 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1245 } 1246 return (rv); 1247 } 1248 1249 static void 1250 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1251 { 1252 int oc = 0; 1253 1254 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1255 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1256 uint32_t tc; 1257 /* 1258 * We will assume that someone has paused the RISC processor. 1259 */ 1260 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1261 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1262 if (regoff & SXP_BANK1_SELECT) 1263 tc |= BIU_PCI1080_CONF1_SXP1; 1264 else 1265 tc |= BIU_PCI1080_CONF1_SXP0; 1266 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1267 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1268 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1269 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1270 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1271 oc | BIU_PCI1080_CONF1_DMA); 1272 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1273 } 1274 BXW2(isp, IspVirt2Off(isp, regoff), val); 1275 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1276 if (oc) { 1277 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1278 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1279 } 1280 } 1281 1282 static uint32_t 1283 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1284 { 1285 uint32_t rv; 1286 int block = regoff & _BLK_REG_MASK; 1287 1288 switch (block) { 1289 case BIU_BLOCK: 1290 break; 1291 case MBOX_BLOCK: 1292 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1293 case SXP_BLOCK: 1294 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1295 return (0xffffffff); 1296 case RISC_BLOCK: 1297 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1298 return (0xffffffff); 1299 case DMA_BLOCK: 1300 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1301 return (0xffffffff); 1302 default: 1303 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1304 return (0xffffffff); 1305 } 1306 1307 1308 switch (regoff) { 1309 case BIU2400_FLASH_ADDR: 1310 case BIU2400_FLASH_DATA: 1311 case BIU2400_ICR: 1312 case BIU2400_ISR: 1313 case BIU2400_CSR: 1314 case BIU2400_REQINP: 1315 case BIU2400_REQOUTP: 1316 case BIU2400_RSPINP: 1317 case BIU2400_RSPOUTP: 1318 case BIU2400_PRI_REQINP: 1319 case BIU2400_PRI_REQOUTP: 1320 case BIU2400_ATIO_RSPINP: 1321 case BIU2400_ATIO_RSPOUTP: 1322 case BIU2400_HCCR: 1323 case BIU2400_GPIOD: 1324 case BIU2400_GPIOE: 1325 case BIU2400_HSEMA: 1326 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1327 break; 1328 case BIU2400_R2HSTSLO: 1329 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1330 break; 1331 case BIU2400_R2HSTSHI: 1332 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1333 break; 1334 default: 1335 isp_prt(isp, ISP_LOGERR, 1336 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1337 rv = 0xffffffff; 1338 break; 1339 } 1340 return (rv); 1341 } 1342 1343 static void 1344 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1345 { 1346 int block = regoff & _BLK_REG_MASK; 1347 1348 switch (block) { 1349 case BIU_BLOCK: 1350 break; 1351 case MBOX_BLOCK: 1352 BXW2(isp, IspVirt2Off(isp, regoff), val); 1353 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1354 return; 1355 case SXP_BLOCK: 1356 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1357 return; 1358 case RISC_BLOCK: 1359 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1360 return; 1361 case DMA_BLOCK: 1362 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1363 return; 1364 default: 1365 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1366 regoff); 1367 break; 1368 } 1369 1370 switch (regoff) { 1371 case BIU2400_FLASH_ADDR: 1372 case BIU2400_FLASH_DATA: 1373 case BIU2400_ICR: 1374 case BIU2400_ISR: 1375 case BIU2400_CSR: 1376 case BIU2400_REQINP: 1377 case BIU2400_REQOUTP: 1378 case BIU2400_RSPINP: 1379 case BIU2400_RSPOUTP: 1380 case BIU2400_PRI_REQINP: 1381 case BIU2400_PRI_REQOUTP: 1382 case BIU2400_ATIO_RSPINP: 1383 case BIU2400_ATIO_RSPOUTP: 1384 case BIU2400_HCCR: 1385 case BIU2400_GPIOD: 1386 case BIU2400_GPIOE: 1387 case BIU2400_HSEMA: 1388 BXW4(isp, IspVirt2Off(isp, regoff), val); 1389 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4); 1390 break; 1391 default: 1392 isp_prt(isp, ISP_LOGERR, 1393 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1394 break; 1395 } 1396 } 1397 1398 1399 struct imush { 1400 ispsoftc_t *isp; 1401 caddr_t vbase; 1402 int chan; 1403 int error; 1404 }; 1405 1406 static void imc(void *, bus_dma_segment_t *, int, int); 1407 static void imc1(void *, bus_dma_segment_t *, int, int); 1408 1409 static void 1410 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1411 { 1412 struct imush *imushp = (struct imush *) arg; 1413 1414 if (error) { 1415 imushp->error = error; 1416 return; 1417 } 1418 if (nseg != 1) { 1419 imushp->error = EINVAL; 1420 return; 1421 } 1422 imushp->isp->isp_rquest = imushp->vbase; 1423 imushp->isp->isp_rquest_dma = segs->ds_addr; 1424 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1425 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1426 imushp->isp->isp_result_dma = segs->ds_addr; 1427 imushp->isp->isp_result = imushp->vbase; 1428 1429 #ifdef ISP_TARGET_MODE 1430 if (IS_24XX(imushp->isp)) { 1431 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1432 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1433 imushp->isp->isp_atioq_dma = segs->ds_addr; 1434 imushp->isp->isp_atioq = imushp->vbase; 1435 } 1436 #endif 1437 } 1438 1439 static void 1440 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1441 { 1442 struct imush *imushp = (struct imush *) arg; 1443 if (error) { 1444 imushp->error = error; 1445 return; 1446 } 1447 if (nseg != 1) { 1448 imushp->error = EINVAL; 1449 return; 1450 } 1451 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1452 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1453 } 1454 1455 static int 1456 isp_pci_mbxdma(ispsoftc_t *isp) 1457 { 1458 caddr_t base; 1459 uint32_t len; 1460 int i, error, ns, cmap = 0; 1461 bus_size_t slim; /* segment size */ 1462 bus_addr_t llim; /* low limit of unavailable dma */ 1463 bus_addr_t hlim; /* high limit of unavailable dma */ 1464 struct imush im; 1465 1466 /* 1467 * Already been here? If so, leave... 1468 */ 1469 if (isp->isp_rquest) { 1470 return (0); 1471 } 1472 ISP_UNLOCK(isp); 1473 1474 if (isp->isp_maxcmds == 0) { 1475 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1476 ISP_LOCK(isp); 1477 return (1); 1478 } 1479 1480 hlim = BUS_SPACE_MAXADDR; 1481 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1482 if (sizeof (bus_size_t) > 4) { 1483 slim = (bus_size_t) (1ULL << 32); 1484 } else { 1485 slim = (bus_size_t) (1UL << 31); 1486 } 1487 llim = BUS_SPACE_MAXADDR; 1488 } else { 1489 llim = BUS_SPACE_MAXADDR_32BIT; 1490 slim = (1UL << 24); 1491 } 1492 1493 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1494 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1495 if (isp->isp_osinfo.pcmd_pool == NULL) { 1496 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1497 ISP_LOCK(isp); 1498 return (1); 1499 } 1500 1501 /* 1502 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1503 */ 1504 #ifdef ISP_TARGET_MODE 1505 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1506 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1507 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1508 ISP_LOCK(isp); 1509 return (1); 1510 } 1511 #endif 1512 1513 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) { 1514 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1515 ISP_LOCK(isp); 1516 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1517 return (1); 1518 } 1519 1520 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1521 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1522 if (isp->isp_xflist == NULL) { 1523 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1524 ISP_LOCK(isp); 1525 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1526 return (1); 1527 } 1528 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1529 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1530 } 1531 isp->isp_xffree = isp->isp_xflist; 1532 #ifdef ISP_TARGET_MODE 1533 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1534 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1535 if (isp->isp_tgtlist == NULL) { 1536 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1537 free(isp->isp_xflist, M_DEVBUF); 1538 ISP_LOCK(isp); 1539 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1540 return (1); 1541 } 1542 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1543 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1544 } 1545 isp->isp_tgtfree = isp->isp_tgtlist; 1546 #endif 1547 1548 /* 1549 * Allocate and map the request and result queues (and ATIO queue 1550 * if we're a 2400 supporting target mode). 1551 */ 1552 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1553 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1554 #ifdef ISP_TARGET_MODE 1555 if (IS_24XX(isp)) { 1556 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1557 } 1558 #endif 1559 1560 ns = (len / PAGE_SIZE) + 1; 1561 1562 /* 1563 * Create a tag for the control spaces. We don't always need this 1564 * to be 32 bits, but we do this for simplicity and speed's sake. 1565 */ 1566 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) { 1567 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1568 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1569 free(isp->isp_xflist, M_DEVBUF); 1570 #ifdef ISP_TARGET_MODE 1571 free(isp->isp_tgtlist, M_DEVBUF); 1572 #endif 1573 ISP_LOCK(isp); 1574 return (1); 1575 } 1576 1577 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT, &isp->isp_osinfo.cdmap) != 0) { 1578 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1579 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1580 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1581 free(isp->isp_xflist, M_DEVBUF); 1582 #ifdef ISP_TARGET_MODE 1583 free(isp->isp_tgtlist, M_DEVBUF); 1584 #endif 1585 ISP_LOCK(isp); 1586 return (1); 1587 } 1588 1589 im.isp = isp; 1590 im.chan = 0; 1591 im.vbase = base; 1592 im.error = 0; 1593 1594 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1595 if (im.error) { 1596 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1597 goto bad; 1598 } 1599 1600 if (IS_FC(isp)) { 1601 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1602 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1603 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1604 goto bad; 1605 } 1606 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT, &fc->tdmap) != 0) { 1607 bus_dma_tag_destroy(fc->tdmat); 1608 goto bad; 1609 } 1610 im.isp = isp; 1611 im.chan = cmap; 1612 im.vbase = base; 1613 im.error = 0; 1614 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1615 if (im.error) { 1616 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1617 bus_dma_tag_destroy(fc->tdmat); 1618 goto bad; 1619 } 1620 } 1621 } 1622 1623 for (i = 0; i < isp->isp_maxcmds; i++) { 1624 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1625 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1626 if (error) { 1627 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1628 while (--i >= 0) { 1629 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1630 } 1631 goto bad; 1632 } 1633 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1634 if (i == isp->isp_maxcmds-1) { 1635 pcmd->next = NULL; 1636 } else { 1637 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1638 } 1639 } 1640 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1641 ISP_LOCK(isp); 1642 return (0); 1643 1644 bad: 1645 while (--cmap >= 0) { 1646 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1647 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1648 bus_dma_tag_destroy(fc->tdmat); 1649 } 1650 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1651 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1652 free(isp->isp_xflist, M_DEVBUF); 1653 #ifdef ISP_TARGET_MODE 1654 free(isp->isp_tgtlist, M_DEVBUF); 1655 #endif 1656 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1657 isp->isp_rquest = NULL; 1658 ISP_LOCK(isp); 1659 return (1); 1660 } 1661 1662 typedef struct { 1663 ispsoftc_t *isp; 1664 void *cmd_token; 1665 void *rq; /* original request */ 1666 int error; 1667 bus_size_t mapsize; 1668 } mush_t; 1669 1670 #define MUSHERR_NOQENTRIES -2 1671 1672 #ifdef ISP_TARGET_MODE 1673 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1674 static void tdma2(void *, bus_dma_segment_t *, int, int); 1675 1676 static void 1677 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1678 { 1679 mush_t *mp; 1680 mp = (mush_t *)arg; 1681 mp->mapsize = mapsize; 1682 tdma2(arg, dm_segs, nseg, error); 1683 } 1684 1685 static void 1686 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1687 { 1688 mush_t *mp; 1689 ispsoftc_t *isp; 1690 struct ccb_scsiio *csio; 1691 isp_ddir_t ddir; 1692 ispreq_t *rq; 1693 1694 mp = (mush_t *) arg; 1695 if (error) { 1696 mp->error = error; 1697 return; 1698 } 1699 csio = mp->cmd_token; 1700 isp = mp->isp; 1701 rq = mp->rq; 1702 if (nseg) { 1703 if (sizeof (bus_addr_t) > 4) { 1704 if (nseg >= ISP_NSEG64_MAX) { 1705 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1706 mp->error = EFAULT; 1707 return; 1708 } 1709 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1710 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1711 } 1712 } else { 1713 if (nseg >= ISP_NSEG_MAX) { 1714 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1715 mp->error = EFAULT; 1716 return; 1717 } 1718 } 1719 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1720 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1721 ddir = ISP_TO_DEVICE; 1722 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1723 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1724 ddir = ISP_FROM_DEVICE; 1725 } else { 1726 dm_segs = NULL; 1727 nseg = 0; 1728 ddir = ISP_NOXFR; 1729 } 1730 } else { 1731 dm_segs = NULL; 1732 nseg = 0; 1733 ddir = ISP_NOXFR; 1734 } 1735 1736 if (isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len) != CMD_QUEUED) { 1737 mp->error = MUSHERR_NOQENTRIES; 1738 } 1739 } 1740 #endif 1741 1742 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1743 static void dma2(void *, bus_dma_segment_t *, int, int); 1744 1745 static void 1746 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1747 { 1748 mush_t *mp; 1749 mp = (mush_t *)arg; 1750 mp->mapsize = mapsize; 1751 dma2(arg, dm_segs, nseg, error); 1752 } 1753 1754 static void 1755 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1756 { 1757 mush_t *mp; 1758 ispsoftc_t *isp; 1759 struct ccb_scsiio *csio; 1760 isp_ddir_t ddir; 1761 ispreq_t *rq; 1762 1763 mp = (mush_t *) arg; 1764 if (error) { 1765 mp->error = error; 1766 return; 1767 } 1768 csio = mp->cmd_token; 1769 isp = mp->isp; 1770 rq = mp->rq; 1771 if (nseg) { 1772 if (sizeof (bus_addr_t) > 4) { 1773 if (nseg >= ISP_NSEG64_MAX) { 1774 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1775 mp->error = EFAULT; 1776 return; 1777 } 1778 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1779 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1780 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1781 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1782 } 1783 } else { 1784 if (nseg >= ISP_NSEG_MAX) { 1785 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1786 mp->error = EFAULT; 1787 return; 1788 } 1789 } 1790 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1791 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1792 ddir = ISP_FROM_DEVICE; 1793 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1794 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1795 ddir = ISP_TO_DEVICE; 1796 } else { 1797 ddir = ISP_NOXFR; 1798 } 1799 } else { 1800 dm_segs = NULL; 1801 nseg = 0; 1802 ddir = ISP_NOXFR; 1803 } 1804 1805 if (isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir) != CMD_QUEUED) { 1806 mp->error = MUSHERR_NOQENTRIES; 1807 } 1808 } 1809 1810 static int 1811 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1812 { 1813 mush_t mush, *mp; 1814 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1815 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1816 1817 mp = &mush; 1818 mp->isp = isp; 1819 mp->cmd_token = csio; 1820 mp->rq = ff; 1821 mp->error = 0; 1822 mp->mapsize = 0; 1823 1824 #ifdef ISP_TARGET_MODE 1825 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1826 eptr = tdma2; 1827 eptr2 = tdma2_2; 1828 } else 1829 #endif 1830 { 1831 eptr = dma2; 1832 eptr2 = dma2_2; 1833 } 1834 1835 1836 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) { 1837 (*eptr)(mp, NULL, 0, 0); 1838 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1839 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1840 int error; 1841 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1842 #if 0 1843 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error); 1844 #endif 1845 1846 if (error == EINPROGRESS) { 1847 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1848 mp->error = EINVAL; 1849 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1850 } else if (error && mp->error == 0) { 1851 #ifdef DIAGNOSTIC 1852 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1853 #endif 1854 mp->error = error; 1855 } 1856 } else { 1857 /* Pointer to physical buffer */ 1858 struct bus_dma_segment seg; 1859 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 1860 seg.ds_len = csio->dxfer_len; 1861 (*eptr)(mp, &seg, 1, 0); 1862 } 1863 } else { 1864 struct bus_dma_segment *segs; 1865 1866 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1867 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported"); 1868 mp->error = EINVAL; 1869 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1870 struct uio sguio; 1871 int error; 1872 1873 /* 1874 * We're taking advantage of the fact that 1875 * the pointer/length sizes and layout of the iovec 1876 * structure are the same as the bus_dma_segment 1877 * structure. This might be a little dangerous, 1878 * but only if they change the structures, which 1879 * seems unlikely. 1880 */ 1881 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) && 1882 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) && 1883 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed")); 1884 sguio.uio_iov = (struct iovec *)csio->data_ptr; 1885 sguio.uio_iovcnt = csio->sglist_cnt; 1886 sguio.uio_resid = csio->dxfer_len; 1887 sguio.uio_segflg = UIO_SYSSPACE; 1888 1889 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0); 1890 1891 if (error != 0 && mp->error == 0) { 1892 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1893 mp->error = error; 1894 } 1895 } else { 1896 /* Just use the segments provided */ 1897 segs = (struct bus_dma_segment *) csio->data_ptr; 1898 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1899 } 1900 } 1901 if (mp->error) { 1902 int retval = CMD_COMPLETE; 1903 if (mp->error == MUSHERR_NOQENTRIES) { 1904 retval = CMD_EAGAIN; 1905 } else if (mp->error == EFBIG) { 1906 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1907 } else if (mp->error == EINVAL) { 1908 XS_SETERR(csio, CAM_REQ_INVALID); 1909 } else { 1910 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1911 } 1912 return (retval); 1913 } 1914 return (CMD_QUEUED); 1915 } 1916 1917 static void 1918 isp_pci_reset0(ispsoftc_t *isp) 1919 { 1920 ISP_DISABLE_INTS(isp); 1921 } 1922 1923 static void 1924 isp_pci_reset1(ispsoftc_t *isp) 1925 { 1926 if (!IS_24XX(isp)) { 1927 /* Make sure the BIOS is disabled */ 1928 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1929 } 1930 /* and enable interrupts */ 1931 ISP_ENABLE_INTS(isp); 1932 } 1933 1934 static void 1935 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1936 { 1937 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1938 if (msg) 1939 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1940 else 1941 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1942 if (IS_SCSI(isp)) 1943 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1944 else 1945 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1946 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1947 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1948 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1949 1950 1951 if (IS_SCSI(isp)) { 1952 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1953 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1954 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1955 ISP_READ(isp, CDMA_FIFO_STS)); 1956 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1957 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1958 ISP_READ(isp, DDMA_FIFO_STS)); 1959 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1960 ISP_READ(isp, SXP_INTERRUPT), 1961 ISP_READ(isp, SXP_GROSS_ERR), 1962 ISP_READ(isp, SXP_PINS_CTRL)); 1963 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1964 } 1965 printf(" mbox regs: %x %x %x %x %x\n", 1966 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1967 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1968 ISP_READ(isp, OUTMAILBOX4)); 1969 printf(" PCI Status Command/Status=%x\n", 1970 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1971 } 1972