1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 #include <sys/malloc.h> 47 #include <sys/uio.h> 48 49 #ifdef __sparc64__ 50 #include <dev/ofw/openfirm.h> 51 #include <machine/ofw_machdep.h> 52 #endif 53 54 #include <dev/isp/isp_freebsd.h> 55 56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 62 static int isp_pci_rd_isr(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *); 63 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *); 64 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *); 65 static int isp_pci_mbxdma(ispsoftc_t *); 66 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 67 68 69 static void isp_pci_reset0(ispsoftc_t *); 70 static void isp_pci_reset1(ispsoftc_t *); 71 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 72 73 static struct ispmdvec mdvec = { 74 isp_pci_rd_isr, 75 isp_pci_rd_reg, 76 isp_pci_wr_reg, 77 isp_pci_mbxdma, 78 isp_pci_dmasetup, 79 isp_common_dmateardown, 80 isp_pci_reset0, 81 isp_pci_reset1, 82 isp_pci_dumpregs, 83 NULL, 84 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 85 }; 86 87 static struct ispmdvec mdvec_1080 = { 88 isp_pci_rd_isr, 89 isp_pci_rd_reg_1080, 90 isp_pci_wr_reg_1080, 91 isp_pci_mbxdma, 92 isp_pci_dmasetup, 93 isp_common_dmateardown, 94 isp_pci_reset0, 95 isp_pci_reset1, 96 isp_pci_dumpregs, 97 NULL, 98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 99 }; 100 101 static struct ispmdvec mdvec_12160 = { 102 isp_pci_rd_isr, 103 isp_pci_rd_reg_1080, 104 isp_pci_wr_reg_1080, 105 isp_pci_mbxdma, 106 isp_pci_dmasetup, 107 isp_common_dmateardown, 108 isp_pci_reset0, 109 isp_pci_reset1, 110 isp_pci_dumpregs, 111 NULL, 112 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 113 }; 114 115 static struct ispmdvec mdvec_2100 = { 116 isp_pci_rd_isr, 117 isp_pci_rd_reg, 118 isp_pci_wr_reg, 119 isp_pci_mbxdma, 120 isp_pci_dmasetup, 121 isp_common_dmateardown, 122 isp_pci_reset0, 123 isp_pci_reset1, 124 isp_pci_dumpregs 125 }; 126 127 static struct ispmdvec mdvec_2200 = { 128 isp_pci_rd_isr, 129 isp_pci_rd_reg, 130 isp_pci_wr_reg, 131 isp_pci_mbxdma, 132 isp_pci_dmasetup, 133 isp_common_dmateardown, 134 isp_pci_reset0, 135 isp_pci_reset1, 136 isp_pci_dumpregs 137 }; 138 139 static struct ispmdvec mdvec_2300 = { 140 isp_pci_rd_isr_2300, 141 isp_pci_rd_reg, 142 isp_pci_wr_reg, 143 isp_pci_mbxdma, 144 isp_pci_dmasetup, 145 isp_common_dmateardown, 146 isp_pci_reset0, 147 isp_pci_reset1, 148 isp_pci_dumpregs 149 }; 150 151 static struct ispmdvec mdvec_2400 = { 152 isp_pci_rd_isr_2400, 153 isp_pci_rd_reg_2400, 154 isp_pci_wr_reg_2400, 155 isp_pci_mbxdma, 156 isp_pci_dmasetup, 157 isp_common_dmateardown, 158 isp_pci_reset0, 159 isp_pci_reset1, 160 NULL 161 }; 162 163 static struct ispmdvec mdvec_2500 = { 164 isp_pci_rd_isr_2400, 165 isp_pci_rd_reg_2400, 166 isp_pci_wr_reg_2400, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_common_dmateardown, 170 isp_pci_reset0, 171 isp_pci_reset1, 172 NULL 173 }; 174 175 #ifndef PCIM_CMD_INVEN 176 #define PCIM_CMD_INVEN 0x10 177 #endif 178 #ifndef PCIM_CMD_BUSMASTEREN 179 #define PCIM_CMD_BUSMASTEREN 0x0004 180 #endif 181 #ifndef PCIM_CMD_PERRESPEN 182 #define PCIM_CMD_PERRESPEN 0x0040 183 #endif 184 #ifndef PCIM_CMD_SEREN 185 #define PCIM_CMD_SEREN 0x0100 186 #endif 187 #ifndef PCIM_CMD_INTX_DISABLE 188 #define PCIM_CMD_INTX_DISABLE 0x0400 189 #endif 190 191 #ifndef PCIR_COMMAND 192 #define PCIR_COMMAND 0x04 193 #endif 194 195 #ifndef PCIR_CACHELNSZ 196 #define PCIR_CACHELNSZ 0x0c 197 #endif 198 199 #ifndef PCIR_LATTIMER 200 #define PCIR_LATTIMER 0x0d 201 #endif 202 203 #ifndef PCIR_ROMADDR 204 #define PCIR_ROMADDR 0x30 205 #endif 206 207 #ifndef PCI_VENDOR_QLOGIC 208 #define PCI_VENDOR_QLOGIC 0x1077 209 #endif 210 211 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 212 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 213 #endif 214 215 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 216 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 217 #endif 218 219 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 220 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 221 #endif 222 223 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 224 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 225 #endif 226 227 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 228 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 229 #endif 230 231 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 232 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 233 #endif 234 235 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 236 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 237 #endif 238 239 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 240 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 241 #endif 242 243 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 244 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 245 #endif 246 247 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 248 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 249 #endif 250 251 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 252 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 253 #endif 254 255 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 256 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 257 #endif 258 259 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 260 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 261 #endif 262 263 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 264 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 265 #endif 266 267 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 268 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 269 #endif 270 271 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 272 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 273 #endif 274 275 #ifndef PCI_PRODUCT_QLOGIC_ISP5432 276 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 277 #endif 278 279 #define PCI_QLOGIC_ISP5432 \ 280 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP1020 \ 283 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP1080 \ 286 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define PCI_QLOGIC_ISP10160 \ 289 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 290 291 #define PCI_QLOGIC_ISP12160 \ 292 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 293 294 #define PCI_QLOGIC_ISP1240 \ 295 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 296 297 #define PCI_QLOGIC_ISP1280 \ 298 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 299 300 #define PCI_QLOGIC_ISP2100 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 302 303 #define PCI_QLOGIC_ISP2200 \ 304 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 305 306 #define PCI_QLOGIC_ISP2300 \ 307 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 308 309 #define PCI_QLOGIC_ISP2312 \ 310 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 311 312 #define PCI_QLOGIC_ISP2322 \ 313 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 314 315 #define PCI_QLOGIC_ISP2422 \ 316 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 317 318 #define PCI_QLOGIC_ISP2432 \ 319 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 320 321 #define PCI_QLOGIC_ISP2532 \ 322 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 323 324 #define PCI_QLOGIC_ISP6312 \ 325 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 326 327 #define PCI_QLOGIC_ISP6322 \ 328 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 329 330 /* 331 * Odd case for some AMI raid cards... We need to *not* attach to this. 332 */ 333 #define AMI_RAID_SUBVENDOR_ID 0x101e 334 335 #define IO_MAP_REG 0x10 336 #define MEM_MAP_REG 0x14 337 338 #define PCI_DFLT_LTNCY 0x40 339 #define PCI_DFLT_LNSZ 0x10 340 341 static int isp_pci_probe (device_t); 342 static int isp_pci_attach (device_t); 343 static int isp_pci_detach (device_t); 344 345 346 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 347 struct isp_pcisoftc { 348 ispsoftc_t pci_isp; 349 device_t pci_dev; 350 struct resource * regs; 351 void * irq; 352 int iqd; 353 int rtp; 354 int rgd; 355 void * ih; 356 int16_t pci_poff[_NREG_BLKS]; 357 bus_dma_tag_t dmat; 358 int msicount; 359 }; 360 361 362 static device_method_t isp_pci_methods[] = { 363 /* Device interface */ 364 DEVMETHOD(device_probe, isp_pci_probe), 365 DEVMETHOD(device_attach, isp_pci_attach), 366 DEVMETHOD(device_detach, isp_pci_detach), 367 { 0, 0 } 368 }; 369 370 static driver_t isp_pci_driver = { 371 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 372 }; 373 static devclass_t isp_devclass; 374 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 375 MODULE_DEPEND(isp, cam, 1, 1, 1); 376 MODULE_DEPEND(isp, firmware, 1, 1, 1); 377 static int isp_nvports = 0; 378 379 static int 380 isp_pci_probe(device_t dev) 381 { 382 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 383 case PCI_QLOGIC_ISP1020: 384 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 385 break; 386 case PCI_QLOGIC_ISP1080: 387 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 388 break; 389 case PCI_QLOGIC_ISP1240: 390 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 391 break; 392 case PCI_QLOGIC_ISP1280: 393 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 394 break; 395 case PCI_QLOGIC_ISP10160: 396 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 397 break; 398 case PCI_QLOGIC_ISP12160: 399 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 400 return (ENXIO); 401 } 402 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 403 break; 404 case PCI_QLOGIC_ISP2100: 405 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 406 break; 407 case PCI_QLOGIC_ISP2200: 408 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 409 break; 410 case PCI_QLOGIC_ISP2300: 411 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 412 break; 413 case PCI_QLOGIC_ISP2312: 414 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 415 break; 416 case PCI_QLOGIC_ISP2322: 417 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 418 break; 419 case PCI_QLOGIC_ISP2422: 420 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 421 break; 422 case PCI_QLOGIC_ISP2432: 423 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 424 break; 425 case PCI_QLOGIC_ISP2532: 426 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 427 break; 428 case PCI_QLOGIC_ISP5432: 429 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 430 break; 431 case PCI_QLOGIC_ISP6312: 432 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 433 break; 434 case PCI_QLOGIC_ISP6322: 435 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 436 break; 437 default: 438 return (ENXIO); 439 } 440 if (isp_announced == 0 && bootverbose) { 441 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 442 "Core Version %d.%d\n", 443 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 444 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 445 isp_announced++; 446 } 447 /* 448 * XXXX: Here is where we might load the f/w module 449 * XXXX: (or increase a reference count to it). 450 */ 451 return (BUS_PROBE_DEFAULT); 452 } 453 454 static void 455 isp_get_generic_options(device_t dev, ispsoftc_t *isp) 456 { 457 int tval; 458 459 /* 460 * Figure out if we're supposed to skip this one. 461 */ 462 tval = 0; 463 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 464 device_printf(dev, "disabled at user request\n"); 465 isp->isp_osinfo.disabled = 1; 466 return; 467 } 468 469 tval = 0; 470 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 471 isp->isp_confopts |= ISP_CFG_NORELOAD; 472 } 473 tval = 0; 474 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 475 isp->isp_confopts |= ISP_CFG_NONVRAM; 476 } 477 tval = 0; 478 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 479 if (tval) { 480 isp->isp_dblev = tval; 481 } else { 482 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 483 } 484 if (bootverbose) { 485 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 486 } 487 tval = -1; 488 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 489 if (tval > 0 && tval < 127) { 490 isp_nvports = tval; 491 } 492 tval = 7; 493 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 494 isp_quickboot_time = tval; 495 } 496 497 static void 498 isp_get_pci_options(device_t dev, int *m1, int *m2) 499 { 500 int tval; 501 /* 502 * Which we should try first - memory mapping or i/o mapping? 503 * 504 * We used to try memory first followed by i/o on alpha, otherwise 505 * the reverse, but we should just try memory first all the time now. 506 */ 507 *m1 = PCIM_CMD_MEMEN; 508 *m2 = PCIM_CMD_PORTEN; 509 510 tval = 0; 511 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 512 *m1 = PCIM_CMD_PORTEN; 513 *m2 = PCIM_CMD_MEMEN; 514 } 515 tval = 0; 516 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 517 *m1 = PCIM_CMD_MEMEN; 518 *m2 = PCIM_CMD_PORTEN; 519 } 520 } 521 522 static void 523 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 524 { 525 const char *sptr; 526 int tval = 0; 527 char prefix[12], name[16]; 528 529 if (chan == 0) 530 prefix[0] = 0; 531 else 532 snprintf(prefix, sizeof(prefix), "chan%d.", chan); 533 snprintf(name, sizeof(name), "%siid", prefix); 534 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 535 name, &tval)) { 536 if (IS_FC(isp)) { 537 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 538 } else { 539 #ifdef __sparc64__ 540 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 541 #else 542 ISP_SPI_PC(isp, chan)->iid = 7; 543 #endif 544 } 545 } else { 546 if (IS_FC(isp)) { 547 ISP_FC_PC(isp, chan)->default_id = tval - chan; 548 } else { 549 ISP_SPI_PC(isp, chan)->iid = tval; 550 } 551 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 552 } 553 554 tval = -1; 555 snprintf(name, sizeof(name), "%srole", prefix); 556 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 557 name, &tval) == 0) { 558 switch (tval) { 559 case ISP_ROLE_NONE: 560 case ISP_ROLE_INITIATOR: 561 case ISP_ROLE_TARGET: 562 case ISP_ROLE_BOTH: 563 device_printf(dev, "Chan %d setting role to 0x%x\n", chan, tval); 564 break; 565 default: 566 tval = -1; 567 break; 568 } 569 } 570 if (tval == -1) { 571 tval = ISP_DEFAULT_ROLES; 572 } 573 574 if (IS_SCSI(isp)) { 575 ISP_SPI_PC(isp, chan)->def_role = tval; 576 return; 577 } 578 ISP_FC_PC(isp, chan)->def_role = tval; 579 580 tval = 0; 581 snprintf(name, sizeof(name), "%sfullduplex", prefix); 582 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 583 name, &tval) == 0 && tval != 0) { 584 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 585 } 586 sptr = 0; 587 snprintf(name, sizeof(name), "%stopology", prefix); 588 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 589 name, (const char **) &sptr) == 0 && sptr != 0) { 590 if (strcmp(sptr, "lport") == 0) { 591 isp->isp_confopts |= ISP_CFG_LPORT; 592 } else if (strcmp(sptr, "nport") == 0) { 593 isp->isp_confopts |= ISP_CFG_NPORT; 594 } else if (strcmp(sptr, "lport-only") == 0) { 595 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 596 } else if (strcmp(sptr, "nport-only") == 0) { 597 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 598 } 599 } 600 601 tval = 0; 602 snprintf(name, sizeof(name), "%snofctape", prefix); 603 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 604 name, &tval); 605 if (tval) { 606 isp->isp_confopts |= ISP_CFG_NOFCTAPE; 607 } 608 609 tval = 0; 610 snprintf(name, sizeof(name), "%sfctape", prefix); 611 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 612 name, &tval); 613 if (tval) { 614 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE; 615 isp->isp_confopts |= ISP_CFG_FCTAPE; 616 } 617 618 619 /* 620 * Because the resource_*_value functions can neither return 621 * 64 bit integer values, nor can they be directly coerced 622 * to interpret the right hand side of the assignment as 623 * you want them to interpret it, we have to force WWN 624 * hint replacement to specify WWN strings with a leading 625 * 'w' (e..g w50000000aaaa0001). Sigh. 626 */ 627 sptr = 0; 628 snprintf(name, sizeof(name), "%sportwwn", prefix); 629 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 630 name, (const char **) &sptr); 631 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 632 char *eptr = 0; 633 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 634 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 635 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 636 ISP_FC_PC(isp, chan)->def_wwpn = 0; 637 } 638 } 639 640 sptr = 0; 641 snprintf(name, sizeof(name), "%snodewwn", prefix); 642 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 643 name, (const char **) &sptr); 644 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 645 char *eptr = 0; 646 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 647 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 648 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 649 ISP_FC_PC(isp, chan)->def_wwnn = 0; 650 } 651 } 652 653 tval = 0; 654 snprintf(name, sizeof(name), "%shysteresis", prefix); 655 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 656 "name", &tval); 657 if (tval >= 0 && tval < 256) { 658 ISP_FC_PC(isp, chan)->hysteresis = tval; 659 } else { 660 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 661 } 662 663 tval = -1; 664 snprintf(name, sizeof(name), "%sloop_down_limit", prefix); 665 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 666 name, &tval); 667 if (tval >= 0 && tval < 0xffff) { 668 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 669 } else { 670 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 671 } 672 673 tval = -1; 674 snprintf(name, sizeof(name), "%sgone_device_time", prefix); 675 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 676 name, &tval); 677 if (tval >= 0 && tval < 0xffff) { 678 ISP_FC_PC(isp, chan)->gone_device_time = tval; 679 } else { 680 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 681 } 682 } 683 684 static int 685 isp_pci_attach(device_t dev) 686 { 687 int i, m1, m2, locksetup = 0; 688 uint32_t data, cmd, linesz, did; 689 struct isp_pcisoftc *pcs; 690 ispsoftc_t *isp; 691 size_t psize, xsize; 692 char fwname[32]; 693 694 pcs = device_get_softc(dev); 695 if (pcs == NULL) { 696 device_printf(dev, "cannot get softc\n"); 697 return (ENOMEM); 698 } 699 memset(pcs, 0, sizeof (*pcs)); 700 701 pcs->pci_dev = dev; 702 isp = &pcs->pci_isp; 703 isp->isp_dev = dev; 704 isp->isp_nchan = 1; 705 if (sizeof (bus_addr_t) > 4) 706 isp->isp_osinfo.sixtyfourbit = 1; 707 708 /* 709 * Get Generic Options 710 */ 711 isp_nvports = 0; 712 isp_get_generic_options(dev, isp); 713 714 /* 715 * Check to see if options have us disabled 716 */ 717 if (isp->isp_osinfo.disabled) { 718 /* 719 * But return zero to preserve unit numbering 720 */ 721 return (0); 722 } 723 724 /* 725 * Get PCI options- which in this case are just mapping preferences. 726 */ 727 isp_get_pci_options(dev, &m1, &m2); 728 729 linesz = PCI_DFLT_LNSZ; 730 pcs->irq = pcs->regs = NULL; 731 pcs->rgd = pcs->rtp = pcs->iqd = 0; 732 733 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 734 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 735 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 736 if (pcs->regs == NULL) { 737 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 738 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 739 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 740 } 741 if (pcs->regs == NULL) { 742 device_printf(dev, "unable to map any ports\n"); 743 goto bad; 744 } 745 if (bootverbose) { 746 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 747 } 748 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 749 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 750 751 pcs->pci_dev = dev; 752 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 753 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 754 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 755 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 756 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 757 758 switch (pci_get_devid(dev)) { 759 case PCI_QLOGIC_ISP1020: 760 did = 0x1040; 761 isp->isp_mdvec = &mdvec; 762 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 763 break; 764 case PCI_QLOGIC_ISP1080: 765 did = 0x1080; 766 isp->isp_mdvec = &mdvec_1080; 767 isp->isp_type = ISP_HA_SCSI_1080; 768 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 769 break; 770 case PCI_QLOGIC_ISP1240: 771 did = 0x1080; 772 isp->isp_mdvec = &mdvec_1080; 773 isp->isp_type = ISP_HA_SCSI_1240; 774 isp->isp_nchan = 2; 775 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 776 break; 777 case PCI_QLOGIC_ISP1280: 778 did = 0x1080; 779 isp->isp_mdvec = &mdvec_1080; 780 isp->isp_type = ISP_HA_SCSI_1280; 781 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 782 break; 783 case PCI_QLOGIC_ISP10160: 784 did = 0x12160; 785 isp->isp_mdvec = &mdvec_12160; 786 isp->isp_type = ISP_HA_SCSI_10160; 787 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 788 break; 789 case PCI_QLOGIC_ISP12160: 790 did = 0x12160; 791 isp->isp_nchan = 2; 792 isp->isp_mdvec = &mdvec_12160; 793 isp->isp_type = ISP_HA_SCSI_12160; 794 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 795 break; 796 case PCI_QLOGIC_ISP2100: 797 did = 0x2100; 798 isp->isp_mdvec = &mdvec_2100; 799 isp->isp_type = ISP_HA_FC_2100; 800 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 801 if (pci_get_revid(dev) < 3) { 802 /* 803 * XXX: Need to get the actual revision 804 * XXX: number of the 2100 FB. At any rate, 805 * XXX: lower cache line size for early revision 806 * XXX; boards. 807 */ 808 linesz = 1; 809 } 810 break; 811 case PCI_QLOGIC_ISP2200: 812 did = 0x2200; 813 isp->isp_mdvec = &mdvec_2200; 814 isp->isp_type = ISP_HA_FC_2200; 815 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 816 break; 817 case PCI_QLOGIC_ISP2300: 818 did = 0x2300; 819 isp->isp_mdvec = &mdvec_2300; 820 isp->isp_type = ISP_HA_FC_2300; 821 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 822 break; 823 case PCI_QLOGIC_ISP2312: 824 case PCI_QLOGIC_ISP6312: 825 did = 0x2300; 826 isp->isp_mdvec = &mdvec_2300; 827 isp->isp_type = ISP_HA_FC_2312; 828 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 829 break; 830 case PCI_QLOGIC_ISP2322: 831 case PCI_QLOGIC_ISP6322: 832 did = 0x2322; 833 isp->isp_mdvec = &mdvec_2300; 834 isp->isp_type = ISP_HA_FC_2322; 835 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 836 break; 837 case PCI_QLOGIC_ISP2422: 838 case PCI_QLOGIC_ISP2432: 839 did = 0x2400; 840 isp->isp_nchan += isp_nvports; 841 isp->isp_mdvec = &mdvec_2400; 842 isp->isp_type = ISP_HA_FC_2400; 843 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 844 break; 845 case PCI_QLOGIC_ISP2532: 846 did = 0x2500; 847 isp->isp_nchan += isp_nvports; 848 isp->isp_mdvec = &mdvec_2500; 849 isp->isp_type = ISP_HA_FC_2500; 850 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 851 break; 852 case PCI_QLOGIC_ISP5432: 853 did = 0x2500; 854 isp->isp_mdvec = &mdvec_2500; 855 isp->isp_type = ISP_HA_FC_2500; 856 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 857 break; 858 default: 859 device_printf(dev, "unknown device type\n"); 860 goto bad; 861 break; 862 } 863 isp->isp_revision = pci_get_revid(dev); 864 865 if (IS_FC(isp)) { 866 psize = sizeof (fcparam); 867 xsize = sizeof (struct isp_fc); 868 } else { 869 psize = sizeof (sdparam); 870 xsize = sizeof (struct isp_spi); 871 } 872 psize *= isp->isp_nchan; 873 xsize *= isp->isp_nchan; 874 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 875 if (isp->isp_param == NULL) { 876 device_printf(dev, "cannot allocate parameter data\n"); 877 goto bad; 878 } 879 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 880 if (isp->isp_osinfo.pc.ptr == NULL) { 881 device_printf(dev, "cannot allocate parameter data\n"); 882 goto bad; 883 } 884 885 /* 886 * Now that we know who we are (roughly) get/set specific options 887 */ 888 for (i = 0; i < isp->isp_nchan; i++) { 889 isp_get_specific_options(dev, i, isp); 890 } 891 892 /* 893 * The 'it' suffix really only matters for SCSI cards in target mode. 894 */ 895 isp->isp_osinfo.fw = NULL; 896 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 897 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 898 isp->isp_osinfo.fw = firmware_get(fwname); 899 } 900 if (isp->isp_osinfo.fw == NULL) { 901 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 902 isp->isp_osinfo.fw = firmware_get(fwname); 903 } 904 if (isp->isp_osinfo.fw != NULL) { 905 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname); 906 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 907 } 908 909 /* 910 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 911 */ 912 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 913 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 914 if (IS_2300(isp)) { /* per QLogic errata */ 915 cmd &= ~PCIM_CMD_INVEN; 916 } 917 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 918 cmd &= ~PCIM_CMD_INTX_DISABLE; 919 } 920 if (IS_24XX(isp)) { 921 cmd &= ~PCIM_CMD_INTX_DISABLE; 922 } 923 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 924 925 /* 926 * Make sure the Cache Line Size register is set sensibly. 927 */ 928 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 929 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 930 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data); 931 data = linesz; 932 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 933 } 934 935 /* 936 * Make sure the Latency Timer is sane. 937 */ 938 data = pci_read_config(dev, PCIR_LATTIMER, 1); 939 if (data < PCI_DFLT_LTNCY) { 940 data = PCI_DFLT_LTNCY; 941 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data); 942 pci_write_config(dev, PCIR_LATTIMER, data, 1); 943 } 944 945 /* 946 * Make sure we've disabled the ROM. 947 */ 948 data = pci_read_config(dev, PCIR_ROMADDR, 4); 949 data &= ~1; 950 pci_write_config(dev, PCIR_ROMADDR, data, 4); 951 952 /* 953 * Do MSI 954 * 955 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 956 */ 957 if (IS_24XX(isp) || IS_2322(isp)) { 958 pcs->msicount = pci_msi_count(dev); 959 if (pcs->msicount > 1) { 960 pcs->msicount = 1; 961 } 962 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 963 pcs->iqd = 1; 964 } else { 965 pcs->iqd = 0; 966 } 967 } 968 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE); 969 if (pcs->irq == NULL) { 970 device_printf(dev, "could not allocate interrupt\n"); 971 goto bad; 972 } 973 974 /* Make sure the lock is set up. */ 975 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 976 locksetup++; 977 978 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 979 device_printf(dev, "could not setup interrupt\n"); 980 goto bad; 981 } 982 983 /* 984 * Last minute checks... 985 */ 986 if (IS_23XX(isp) || IS_24XX(isp)) { 987 isp->isp_port = pci_get_function(dev); 988 } 989 990 /* 991 * Make sure we're in reset state. 992 */ 993 ISP_LOCK(isp); 994 isp_reset(isp, 1); 995 if (isp->isp_state != ISP_RESETSTATE) { 996 ISP_UNLOCK(isp); 997 goto bad; 998 } 999 isp_init(isp); 1000 if (isp->isp_state == ISP_INITSTATE) { 1001 isp->isp_state = ISP_RUNSTATE; 1002 } 1003 ISP_UNLOCK(isp); 1004 if (isp_attach(isp)) { 1005 ISP_LOCK(isp); 1006 isp_uninit(isp); 1007 ISP_UNLOCK(isp); 1008 goto bad; 1009 } 1010 return (0); 1011 1012 bad: 1013 if (pcs->ih) { 1014 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1015 } 1016 if (locksetup) { 1017 mtx_destroy(&isp->isp_osinfo.lock); 1018 } 1019 if (pcs->irq) { 1020 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1021 } 1022 if (pcs->msicount) { 1023 pci_release_msi(dev); 1024 } 1025 if (pcs->regs) { 1026 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1027 } 1028 if (pcs->pci_isp.isp_param) { 1029 free(pcs->pci_isp.isp_param, M_DEVBUF); 1030 pcs->pci_isp.isp_param = NULL; 1031 } 1032 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1033 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1034 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1035 } 1036 return (ENXIO); 1037 } 1038 1039 static int 1040 isp_pci_detach(device_t dev) 1041 { 1042 struct isp_pcisoftc *pcs; 1043 ispsoftc_t *isp; 1044 int status; 1045 1046 pcs = device_get_softc(dev); 1047 if (pcs == NULL) { 1048 return (ENXIO); 1049 } 1050 isp = (ispsoftc_t *) pcs; 1051 status = isp_detach(isp); 1052 if (status) 1053 return (status); 1054 ISP_LOCK(isp); 1055 isp_uninit(isp); 1056 if (pcs->ih) { 1057 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1058 } 1059 ISP_UNLOCK(isp); 1060 mtx_destroy(&isp->isp_osinfo.lock); 1061 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1062 if (pcs->msicount) { 1063 pci_release_msi(dev); 1064 } 1065 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1066 /* 1067 * XXX: THERE IS A LOT OF LEAKAGE HERE 1068 */ 1069 if (pcs->pci_isp.isp_param) { 1070 free(pcs->pci_isp.isp_param, M_DEVBUF); 1071 pcs->pci_isp.isp_param = NULL; 1072 } 1073 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1074 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1075 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1076 } 1077 return (0); 1078 } 1079 1080 #define IspVirt2Off(a, x) \ 1081 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1082 _BLK_REG_SHFT] + ((x) & 0xfff)) 1083 1084 #define BXR2(isp, off) \ 1085 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1086 #define BXW2(isp, off, v) \ 1087 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1088 #define BXR4(isp, off) \ 1089 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1090 #define BXW4(isp, off, v) \ 1091 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1092 1093 1094 static ISP_INLINE int 1095 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1096 { 1097 uint32_t val0, val1; 1098 int i = 0; 1099 1100 do { 1101 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1102 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1103 } while (val0 != val1 && ++i < 1000); 1104 if (val0 != val1) { 1105 return (1); 1106 } 1107 *rp = val0; 1108 return (0); 1109 } 1110 1111 static int 1112 isp_pci_rd_isr(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info) 1113 { 1114 uint16_t isr, sema; 1115 1116 if (IS_2100(isp)) { 1117 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1118 return (0); 1119 } 1120 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1121 return (0); 1122 } 1123 } else { 1124 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1125 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1126 } 1127 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1128 isr &= INT_PENDING_MASK(isp); 1129 sema &= BIU_SEMA_LOCK; 1130 if (isr == 0 && sema == 0) { 1131 return (0); 1132 } 1133 *isrp = isr; 1134 if ((*semap = sema) != 0) { 1135 if (IS_2100(isp)) { 1136 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, info)) { 1137 return (0); 1138 } 1139 } else { 1140 *info = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1141 } 1142 } 1143 return (1); 1144 } 1145 1146 static int 1147 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info) 1148 { 1149 uint32_t hccr, r2hisr; 1150 1151 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1152 *isrp = 0; 1153 return (0); 1154 } 1155 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1156 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1157 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1158 *isrp = 0; 1159 return (0); 1160 } 1161 switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) { 1162 case ISPR2HST_ROM_MBX_OK: 1163 case ISPR2HST_ROM_MBX_FAIL: 1164 case ISPR2HST_MBX_OK: 1165 case ISPR2HST_MBX_FAIL: 1166 case ISPR2HST_ASYNC_EVENT: 1167 *semap = 1; 1168 break; 1169 case ISPR2HST_RIO_16: 1170 *info = ASYNC_RIO16_1; 1171 *semap = 1; 1172 return (1); 1173 case ISPR2HST_FPOST: 1174 *info = ASYNC_CMD_CMPLT; 1175 *semap = 1; 1176 return (1); 1177 case ISPR2HST_FPOST_CTIO: 1178 *info = ASYNC_CTIO_DONE; 1179 *semap = 1; 1180 return (1); 1181 case ISPR2HST_RSPQ_UPDATE: 1182 *semap = 0; 1183 break; 1184 default: 1185 hccr = ISP_READ(isp, HCCR); 1186 if (hccr & HCCR_PAUSE) { 1187 ISP_WRITE(isp, HCCR, HCCR_RESET); 1188 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1189 ISP_WRITE(isp, BIU_ICR, 0); 1190 } else { 1191 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1192 } 1193 return (0); 1194 } 1195 *info = (r2hisr >> 16); 1196 return (1); 1197 } 1198 1199 static int 1200 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info) 1201 { 1202 uint32_t r2hisr; 1203 1204 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1205 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1206 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1207 *isrp = 0; 1208 return (0); 1209 } 1210 switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) { 1211 case ISPR2HST_ROM_MBX_OK: 1212 case ISPR2HST_ROM_MBX_FAIL: 1213 case ISPR2HST_MBX_OK: 1214 case ISPR2HST_MBX_FAIL: 1215 case ISPR2HST_ASYNC_EVENT: 1216 *semap = 1; 1217 break; 1218 case ISPR2HST_RSPQ_UPDATE: 1219 case ISPR2HST_RSPQ_UPDATE2: 1220 case ISPR2HST_ATIO_UPDATE: 1221 case ISPR2HST_ATIO_RSPQ_UPDATE: 1222 case ISPR2HST_ATIO_UPDATE2: 1223 *semap = 0; 1224 break; 1225 default: 1226 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1227 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1228 return (0); 1229 } 1230 *info = (r2hisr >> 16); 1231 return (1); 1232 } 1233 1234 static uint32_t 1235 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1236 { 1237 uint16_t rv; 1238 int oldconf = 0; 1239 1240 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1241 /* 1242 * We will assume that someone has paused the RISC processor. 1243 */ 1244 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1245 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1246 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1247 } 1248 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1249 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1250 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1251 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1252 } 1253 return (rv); 1254 } 1255 1256 static void 1257 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1258 { 1259 int oldconf = 0; 1260 1261 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1262 /* 1263 * We will assume that someone has paused the RISC processor. 1264 */ 1265 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1266 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1267 oldconf | BIU_PCI_CONF1_SXP); 1268 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1269 } 1270 BXW2(isp, IspVirt2Off(isp, regoff), val); 1271 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1272 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1273 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1274 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1275 } 1276 1277 } 1278 1279 static uint32_t 1280 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1281 { 1282 uint32_t rv, oc = 0; 1283 1284 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1285 uint32_t tc; 1286 /* 1287 * We will assume that someone has paused the RISC processor. 1288 */ 1289 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1290 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1291 if (regoff & SXP_BANK1_SELECT) 1292 tc |= BIU_PCI1080_CONF1_SXP1; 1293 else 1294 tc |= BIU_PCI1080_CONF1_SXP0; 1295 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1296 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1297 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1298 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1299 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1300 oc | BIU_PCI1080_CONF1_DMA); 1301 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1302 } 1303 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1304 if (oc) { 1305 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1306 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1307 } 1308 return (rv); 1309 } 1310 1311 static void 1312 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1313 { 1314 int oc = 0; 1315 1316 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1317 uint32_t tc; 1318 /* 1319 * We will assume that someone has paused the RISC processor. 1320 */ 1321 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1322 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1323 if (regoff & SXP_BANK1_SELECT) 1324 tc |= BIU_PCI1080_CONF1_SXP1; 1325 else 1326 tc |= BIU_PCI1080_CONF1_SXP0; 1327 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1328 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1329 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1330 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1331 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1332 oc | BIU_PCI1080_CONF1_DMA); 1333 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1334 } 1335 BXW2(isp, IspVirt2Off(isp, regoff), val); 1336 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1337 if (oc) { 1338 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1339 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1340 } 1341 } 1342 1343 static uint32_t 1344 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1345 { 1346 uint32_t rv; 1347 int block = regoff & _BLK_REG_MASK; 1348 1349 switch (block) { 1350 case BIU_BLOCK: 1351 break; 1352 case MBOX_BLOCK: 1353 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1354 case SXP_BLOCK: 1355 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1356 return (0xffffffff); 1357 case RISC_BLOCK: 1358 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1359 return (0xffffffff); 1360 case DMA_BLOCK: 1361 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1362 return (0xffffffff); 1363 default: 1364 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1365 return (0xffffffff); 1366 } 1367 1368 1369 switch (regoff) { 1370 case BIU2400_FLASH_ADDR: 1371 case BIU2400_FLASH_DATA: 1372 case BIU2400_ICR: 1373 case BIU2400_ISR: 1374 case BIU2400_CSR: 1375 case BIU2400_REQINP: 1376 case BIU2400_REQOUTP: 1377 case BIU2400_RSPINP: 1378 case BIU2400_RSPOUTP: 1379 case BIU2400_PRI_REQINP: 1380 case BIU2400_PRI_REQOUTP: 1381 case BIU2400_ATIO_RSPINP: 1382 case BIU2400_ATIO_RSPOUTP: 1383 case BIU2400_HCCR: 1384 case BIU2400_GPIOD: 1385 case BIU2400_GPIOE: 1386 case BIU2400_HSEMA: 1387 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1388 break; 1389 case BIU2400_R2HSTSLO: 1390 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1391 break; 1392 case BIU2400_R2HSTSHI: 1393 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1394 break; 1395 default: 1396 isp_prt(isp, ISP_LOGERR, 1397 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1398 rv = 0xffffffff; 1399 break; 1400 } 1401 return (rv); 1402 } 1403 1404 static void 1405 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1406 { 1407 int block = regoff & _BLK_REG_MASK; 1408 1409 switch (block) { 1410 case BIU_BLOCK: 1411 break; 1412 case MBOX_BLOCK: 1413 BXW2(isp, IspVirt2Off(isp, regoff), val); 1414 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1415 return; 1416 case SXP_BLOCK: 1417 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1418 return; 1419 case RISC_BLOCK: 1420 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1421 return; 1422 case DMA_BLOCK: 1423 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1424 return; 1425 default: 1426 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1427 regoff); 1428 break; 1429 } 1430 1431 switch (regoff) { 1432 case BIU2400_FLASH_ADDR: 1433 case BIU2400_FLASH_DATA: 1434 case BIU2400_ICR: 1435 case BIU2400_ISR: 1436 case BIU2400_CSR: 1437 case BIU2400_REQINP: 1438 case BIU2400_REQOUTP: 1439 case BIU2400_RSPINP: 1440 case BIU2400_RSPOUTP: 1441 case BIU2400_PRI_REQINP: 1442 case BIU2400_PRI_REQOUTP: 1443 case BIU2400_ATIO_RSPINP: 1444 case BIU2400_ATIO_RSPOUTP: 1445 case BIU2400_HCCR: 1446 case BIU2400_GPIOD: 1447 case BIU2400_GPIOE: 1448 case BIU2400_HSEMA: 1449 BXW4(isp, IspVirt2Off(isp, regoff), val); 1450 #ifdef MEMORYBARRIERW 1451 if (regoff == BIU2400_REQINP || 1452 regoff == BIU2400_RSPOUTP || 1453 regoff == BIU2400_PRI_REQINP || 1454 regoff == BIU2400_ATIO_RSPOUTP) 1455 MEMORYBARRIERW(isp, SYNC_REG, 1456 IspVirt2Off(isp, regoff), 4, -1) 1457 else 1458 #endif 1459 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1460 break; 1461 default: 1462 isp_prt(isp, ISP_LOGERR, 1463 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1464 break; 1465 } 1466 } 1467 1468 1469 struct imush { 1470 ispsoftc_t *isp; 1471 caddr_t vbase; 1472 int chan; 1473 int error; 1474 }; 1475 1476 static void imc(void *, bus_dma_segment_t *, int, int); 1477 static void imc1(void *, bus_dma_segment_t *, int, int); 1478 1479 static void 1480 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1481 { 1482 struct imush *imushp = (struct imush *) arg; 1483 isp_ecmd_t *ecmd; 1484 1485 if (error) { 1486 imushp->error = error; 1487 return; 1488 } 1489 if (nseg != 1) { 1490 imushp->error = EINVAL; 1491 return; 1492 } 1493 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1494 1495 imushp->isp->isp_rquest = imushp->vbase; 1496 imushp->isp->isp_rquest_dma = segs->ds_addr; 1497 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1498 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1499 1500 imushp->isp->isp_result_dma = segs->ds_addr; 1501 imushp->isp->isp_result = imushp->vbase; 1502 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1503 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1504 1505 if (imushp->isp->isp_type >= ISP_HA_FC_2300) { 1506 imushp->isp->isp_osinfo.ecmd_dma = segs->ds_addr; 1507 imushp->isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)imushp->vbase; 1508 imushp->isp->isp_osinfo.ecmd_base = imushp->isp->isp_osinfo.ecmd_free; 1509 for (ecmd = imushp->isp->isp_osinfo.ecmd_free; ecmd < &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) { 1510 if (ecmd == &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS - 1]) { 1511 ecmd->next = NULL; 1512 } else { 1513 ecmd->next = ecmd + 1; 1514 } 1515 } 1516 } 1517 #ifdef ISP_TARGET_MODE 1518 segs->ds_addr += (N_XCMDS * XCMD_SIZE); 1519 imushp->vbase += (N_XCMDS * XCMD_SIZE); 1520 if (IS_24XX(imushp->isp)) { 1521 imushp->isp->isp_atioq_dma = segs->ds_addr; 1522 imushp->isp->isp_atioq = imushp->vbase; 1523 } 1524 #endif 1525 } 1526 1527 static void 1528 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1529 { 1530 struct imush *imushp = (struct imush *) arg; 1531 if (error) { 1532 imushp->error = error; 1533 return; 1534 } 1535 if (nseg != 1) { 1536 imushp->error = EINVAL; 1537 return; 1538 } 1539 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1540 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1541 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1542 } 1543 1544 static int 1545 isp_pci_mbxdma(ispsoftc_t *isp) 1546 { 1547 caddr_t base; 1548 uint32_t len, nsegs; 1549 int i, error, cmap = 0; 1550 bus_size_t slim; /* segment size */ 1551 bus_addr_t llim; /* low limit of unavailable dma */ 1552 bus_addr_t hlim; /* high limit of unavailable dma */ 1553 struct imush im; 1554 1555 /* 1556 * Already been here? If so, leave... 1557 */ 1558 if (isp->isp_rquest) { 1559 return (0); 1560 } 1561 ISP_UNLOCK(isp); 1562 1563 if (isp->isp_maxcmds == 0) { 1564 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1565 ISP_LOCK(isp); 1566 return (1); 1567 } 1568 1569 hlim = BUS_SPACE_MAXADDR; 1570 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1571 if (sizeof (bus_size_t) > 4) { 1572 slim = (bus_size_t) (1ULL << 32); 1573 } else { 1574 slim = (bus_size_t) (1UL << 31); 1575 } 1576 llim = BUS_SPACE_MAXADDR; 1577 } else { 1578 llim = BUS_SPACE_MAXADDR_32BIT; 1579 slim = (1UL << 24); 1580 } 1581 1582 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1583 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1584 if (isp->isp_osinfo.pcmd_pool == NULL) { 1585 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1586 ISP_LOCK(isp); 1587 return (1); 1588 } 1589 1590 if (isp->isp_osinfo.sixtyfourbit) { 1591 nsegs = ISP_NSEG64_MAX; 1592 } else { 1593 nsegs = ISP_NSEG_MAX; 1594 } 1595 #ifdef ISP_TARGET_MODE 1596 /* 1597 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1598 */ 1599 if (IS_SCSI(isp) && isp->isp_osinfo.sixtyfourbit) { 1600 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1601 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1602 ISP_LOCK(isp); 1603 return (1); 1604 } 1605 #endif 1606 1607 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, &isp->isp_osinfo.dmat)) { 1608 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1609 ISP_LOCK(isp); 1610 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1611 return (1); 1612 } 1613 1614 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1615 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1616 if (isp->isp_xflist == NULL) { 1617 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1618 ISP_LOCK(isp); 1619 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1620 return (1); 1621 } 1622 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1623 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1624 } 1625 isp->isp_xffree = isp->isp_xflist; 1626 #ifdef ISP_TARGET_MODE 1627 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1628 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1629 if (isp->isp_tgtlist == NULL) { 1630 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1631 free(isp->isp_xflist, M_DEVBUF); 1632 ISP_LOCK(isp); 1633 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1634 return (1); 1635 } 1636 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1637 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1638 } 1639 isp->isp_tgtfree = isp->isp_tgtlist; 1640 #endif 1641 1642 /* 1643 * Allocate and map the request and result queues (and ATIO queue 1644 * if we're a 2400 supporting target mode), and a region for 1645 * external dma addressable command/status structures (23XX and 1646 * later). 1647 */ 1648 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1649 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1650 #ifdef ISP_TARGET_MODE 1651 if (IS_24XX(isp)) { 1652 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1653 } 1654 #endif 1655 if (isp->isp_type >= ISP_HA_FC_2300) { 1656 len += (N_XCMDS * XCMD_SIZE); 1657 } 1658 1659 /* 1660 * Create a tag for the control spaces. We don't always need this 1661 * to be 32 bits, but we do this for simplicity and speed's sake. 1662 */ 1663 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, slim, 0, &isp->isp_osinfo.cdmat)) { 1664 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1665 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1666 free(isp->isp_xflist, M_DEVBUF); 1667 #ifdef ISP_TARGET_MODE 1668 free(isp->isp_tgtlist, M_DEVBUF); 1669 #endif 1670 ISP_LOCK(isp); 1671 return (1); 1672 } 1673 1674 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1675 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1676 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1677 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1678 free(isp->isp_xflist, M_DEVBUF); 1679 #ifdef ISP_TARGET_MODE 1680 free(isp->isp_tgtlist, M_DEVBUF); 1681 #endif 1682 ISP_LOCK(isp); 1683 return (1); 1684 } 1685 1686 im.isp = isp; 1687 im.chan = 0; 1688 im.vbase = base; 1689 im.error = 0; 1690 1691 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1692 if (im.error) { 1693 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1694 goto bad; 1695 } 1696 1697 if (IS_FC(isp)) { 1698 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1699 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1700 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1701 goto bad; 1702 } 1703 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1704 bus_dma_tag_destroy(fc->tdmat); 1705 goto bad; 1706 } 1707 im.isp = isp; 1708 im.chan = cmap; 1709 im.vbase = base; 1710 im.error = 0; 1711 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1712 if (im.error) { 1713 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1714 bus_dma_tag_destroy(fc->tdmat); 1715 goto bad; 1716 } 1717 if (isp->isp_type >= ISP_HA_FC_2300) { 1718 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) { 1719 struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO); 1720 if (n == NULL) { 1721 while (fc->nexus_free_list) { 1722 n = fc->nexus_free_list; 1723 fc->nexus_free_list = n->next; 1724 free(n, M_DEVBUF); 1725 } 1726 goto bad; 1727 } 1728 n->next = fc->nexus_free_list; 1729 fc->nexus_free_list = n; 1730 } 1731 } 1732 } 1733 } 1734 1735 for (i = 0; i < isp->isp_maxcmds; i++) { 1736 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1737 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1738 if (error) { 1739 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1740 while (--i >= 0) { 1741 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1742 } 1743 goto bad; 1744 } 1745 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1746 if (i == isp->isp_maxcmds-1) { 1747 pcmd->next = NULL; 1748 } else { 1749 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1750 } 1751 } 1752 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1753 ISP_LOCK(isp); 1754 return (0); 1755 1756 bad: 1757 while (--cmap >= 0) { 1758 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1759 bus_dmamap_unload(fc->tdmat, fc->tdmap); 1760 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1761 bus_dma_tag_destroy(fc->tdmat); 1762 while (fc->nexus_free_list) { 1763 struct isp_nexus *n = fc->nexus_free_list; 1764 fc->nexus_free_list = n->next; 1765 free(n, M_DEVBUF); 1766 } 1767 } 1768 if (isp->isp_rquest_dma != 0) 1769 bus_dmamap_unload(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap); 1770 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1771 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1772 free(isp->isp_xflist, M_DEVBUF); 1773 #ifdef ISP_TARGET_MODE 1774 free(isp->isp_tgtlist, M_DEVBUF); 1775 #endif 1776 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1777 isp->isp_rquest = NULL; 1778 ISP_LOCK(isp); 1779 return (1); 1780 } 1781 1782 typedef struct { 1783 ispsoftc_t *isp; 1784 void *cmd_token; 1785 void *rq; /* original request */ 1786 int error; 1787 bus_size_t mapsize; 1788 } mush_t; 1789 1790 #define MUSHERR_NOQENTRIES -2 1791 1792 #ifdef ISP_TARGET_MODE 1793 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1794 static void tdma2(void *, bus_dma_segment_t *, int, int); 1795 1796 static void 1797 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1798 { 1799 mush_t *mp; 1800 mp = (mush_t *)arg; 1801 mp->mapsize = mapsize; 1802 tdma2(arg, dm_segs, nseg, error); 1803 } 1804 1805 static void 1806 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1807 { 1808 mush_t *mp; 1809 ispsoftc_t *isp; 1810 struct ccb_scsiio *csio; 1811 isp_ddir_t ddir; 1812 ispreq_t *rq; 1813 1814 mp = (mush_t *) arg; 1815 if (error) { 1816 mp->error = error; 1817 return; 1818 } 1819 csio = mp->cmd_token; 1820 isp = mp->isp; 1821 rq = mp->rq; 1822 if (nseg) { 1823 if (isp->isp_osinfo.sixtyfourbit) { 1824 if (nseg >= ISP_NSEG64_MAX) { 1825 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1826 mp->error = EFAULT; 1827 return; 1828 } 1829 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1830 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1831 } 1832 } else { 1833 if (nseg >= ISP_NSEG_MAX) { 1834 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1835 mp->error = EFAULT; 1836 return; 1837 } 1838 } 1839 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1840 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1841 ddir = ISP_TO_DEVICE; 1842 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1843 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1844 ddir = ISP_FROM_DEVICE; 1845 } else { 1846 dm_segs = NULL; 1847 nseg = 0; 1848 ddir = ISP_NOXFR; 1849 } 1850 } else { 1851 dm_segs = NULL; 1852 nseg = 0; 1853 ddir = ISP_NOXFR; 1854 } 1855 1856 error = isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len); 1857 switch (error) { 1858 case CMD_EAGAIN: 1859 mp->error = MUSHERR_NOQENTRIES; 1860 case CMD_QUEUED: 1861 break; 1862 default: 1863 mp->error = EIO; 1864 } 1865 } 1866 #endif 1867 1868 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1869 static void dma2(void *, bus_dma_segment_t *, int, int); 1870 1871 static void 1872 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1873 { 1874 mush_t *mp; 1875 mp = (mush_t *)arg; 1876 mp->mapsize = mapsize; 1877 dma2(arg, dm_segs, nseg, error); 1878 } 1879 1880 static void 1881 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1882 { 1883 mush_t *mp; 1884 ispsoftc_t *isp; 1885 struct ccb_scsiio *csio; 1886 isp_ddir_t ddir; 1887 ispreq_t *rq; 1888 1889 mp = (mush_t *) arg; 1890 if (error) { 1891 mp->error = error; 1892 return; 1893 } 1894 csio = mp->cmd_token; 1895 isp = mp->isp; 1896 rq = mp->rq; 1897 if (nseg) { 1898 if (isp->isp_osinfo.sixtyfourbit) { 1899 if (nseg >= ISP_NSEG64_MAX) { 1900 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1901 mp->error = EFAULT; 1902 return; 1903 } 1904 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1905 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1906 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1907 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1908 } 1909 } else { 1910 if (nseg >= ISP_NSEG_MAX) { 1911 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1912 mp->error = EFAULT; 1913 return; 1914 } 1915 } 1916 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1917 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1918 ddir = ISP_FROM_DEVICE; 1919 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1920 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1921 ddir = ISP_TO_DEVICE; 1922 } else { 1923 ddir = ISP_NOXFR; 1924 } 1925 } else { 1926 dm_segs = NULL; 1927 nseg = 0; 1928 ddir = ISP_NOXFR; 1929 } 1930 1931 error = isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, (ispds64_t *)csio->req_map); 1932 switch (error) { 1933 case CMD_EAGAIN: 1934 mp->error = MUSHERR_NOQENTRIES; 1935 break; 1936 case CMD_QUEUED: 1937 break; 1938 default: 1939 mp->error = EIO; 1940 break; 1941 } 1942 } 1943 1944 static int 1945 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1946 { 1947 mush_t mush, *mp; 1948 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1949 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1950 int error; 1951 1952 mp = &mush; 1953 mp->isp = isp; 1954 mp->cmd_token = csio; 1955 mp->rq = ff; 1956 mp->error = 0; 1957 mp->mapsize = 0; 1958 1959 #ifdef ISP_TARGET_MODE 1960 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1961 eptr = tdma2; 1962 eptr2 = tdma2_2; 1963 } else 1964 #endif 1965 { 1966 eptr = dma2; 1967 eptr2 = dma2_2; 1968 } 1969 1970 1971 error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, 1972 (union ccb *)csio, eptr, mp, 0); 1973 if (error == EINPROGRESS) { 1974 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1975 mp->error = EINVAL; 1976 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1977 } else if (error && mp->error == 0) { 1978 #ifdef DIAGNOSTIC 1979 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1980 #endif 1981 mp->error = error; 1982 } 1983 if (mp->error) { 1984 int retval = CMD_COMPLETE; 1985 if (mp->error == MUSHERR_NOQENTRIES) { 1986 retval = CMD_EAGAIN; 1987 } else if (mp->error == EFBIG) { 1988 csio->ccb_h.status = CAM_REQ_TOO_BIG; 1989 } else if (mp->error == EINVAL) { 1990 csio->ccb_h.status = CAM_REQ_INVALID; 1991 } else { 1992 csio->ccb_h.status = CAM_UNREC_HBA_ERROR; 1993 } 1994 return (retval); 1995 } 1996 return (CMD_QUEUED); 1997 } 1998 1999 static void 2000 isp_pci_reset0(ispsoftc_t *isp) 2001 { 2002 ISP_DISABLE_INTS(isp); 2003 } 2004 2005 static void 2006 isp_pci_reset1(ispsoftc_t *isp) 2007 { 2008 if (!IS_24XX(isp)) { 2009 /* Make sure the BIOS is disabled */ 2010 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 2011 } 2012 /* and enable interrupts */ 2013 ISP_ENABLE_INTS(isp); 2014 } 2015 2016 static void 2017 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 2018 { 2019 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 2020 if (msg) 2021 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 2022 else 2023 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 2024 if (IS_SCSI(isp)) 2025 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 2026 else 2027 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 2028 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 2029 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 2030 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 2031 2032 2033 if (IS_SCSI(isp)) { 2034 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 2035 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 2036 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 2037 ISP_READ(isp, CDMA_FIFO_STS)); 2038 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 2039 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 2040 ISP_READ(isp, DDMA_FIFO_STS)); 2041 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 2042 ISP_READ(isp, SXP_INTERRUPT), 2043 ISP_READ(isp, SXP_GROSS_ERR), 2044 ISP_READ(isp, SXP_PINS_CTRL)); 2045 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2046 } 2047 printf(" mbox regs: %x %x %x %x %x\n", 2048 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2049 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2050 ISP_READ(isp, OUTMAILBOX4)); 2051 printf(" PCI Status Command/Status=%x\n", 2052 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2053 } 2054