1 /*- 2 * Copyright (c) 1997-2006 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #if __FreeBSD_version >= 700000 38 #include <sys/linker.h> 39 #include <sys/firmware.h> 40 #endif 41 #include <sys/bus.h> 42 #if __FreeBSD_version < 500000 43 #include <pci/pcireg.h> 44 #include <pci/pcivar.h> 45 #include <machine/bus_memio.h> 46 #include <machine/bus_pio.h> 47 #else 48 #include <sys/stdint.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #endif 52 #include <machine/bus.h> 53 #include <machine/resource.h> 54 #include <sys/rman.h> 55 #include <sys/malloc.h> 56 57 #include <dev/isp/isp_freebsd.h> 58 59 #if __FreeBSD_version < 500000 60 #define BUS_PROBE_DEFAULT 0 61 #endif 62 63 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 64 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 65 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 66 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 67 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 68 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 69 static int 70 isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 71 static int 72 isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 73 static int 74 isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 75 static int isp_pci_mbxdma(ispsoftc_t *); 76 static int 77 isp_pci_dmasetup(ispsoftc_t *, XS_T *, ispreq_t *, uint32_t *, uint32_t); 78 79 80 static void isp_pci_reset0(ispsoftc_t *); 81 static void isp_pci_reset1(ispsoftc_t *); 82 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 83 84 static struct ispmdvec mdvec = { 85 isp_pci_rd_isr, 86 isp_pci_rd_reg, 87 isp_pci_wr_reg, 88 isp_pci_mbxdma, 89 isp_pci_dmasetup, 90 isp_common_dmateardown, 91 isp_pci_reset0, 92 isp_pci_reset1, 93 isp_pci_dumpregs, 94 NULL, 95 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 96 }; 97 98 static struct ispmdvec mdvec_1080 = { 99 isp_pci_rd_isr, 100 isp_pci_rd_reg_1080, 101 isp_pci_wr_reg_1080, 102 isp_pci_mbxdma, 103 isp_pci_dmasetup, 104 isp_common_dmateardown, 105 isp_pci_reset0, 106 isp_pci_reset1, 107 isp_pci_dumpregs, 108 NULL, 109 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 110 }; 111 112 static struct ispmdvec mdvec_12160 = { 113 isp_pci_rd_isr, 114 isp_pci_rd_reg_1080, 115 isp_pci_wr_reg_1080, 116 isp_pci_mbxdma, 117 isp_pci_dmasetup, 118 isp_common_dmateardown, 119 isp_pci_reset0, 120 isp_pci_reset1, 121 isp_pci_dumpregs, 122 NULL, 123 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 124 }; 125 126 static struct ispmdvec mdvec_2100 = { 127 isp_pci_rd_isr, 128 isp_pci_rd_reg, 129 isp_pci_wr_reg, 130 isp_pci_mbxdma, 131 isp_pci_dmasetup, 132 isp_common_dmateardown, 133 isp_pci_reset0, 134 isp_pci_reset1, 135 isp_pci_dumpregs 136 }; 137 138 static struct ispmdvec mdvec_2200 = { 139 isp_pci_rd_isr, 140 isp_pci_rd_reg, 141 isp_pci_wr_reg, 142 isp_pci_mbxdma, 143 isp_pci_dmasetup, 144 isp_common_dmateardown, 145 isp_pci_reset0, 146 isp_pci_reset1, 147 isp_pci_dumpregs 148 }; 149 150 static struct ispmdvec mdvec_2300 = { 151 isp_pci_rd_isr_2300, 152 isp_pci_rd_reg, 153 isp_pci_wr_reg, 154 isp_pci_mbxdma, 155 isp_pci_dmasetup, 156 isp_common_dmateardown, 157 isp_pci_reset0, 158 isp_pci_reset1, 159 isp_pci_dumpregs 160 }; 161 162 static struct ispmdvec mdvec_2400 = { 163 isp_pci_rd_isr_2400, 164 isp_pci_rd_reg_2400, 165 isp_pci_wr_reg_2400, 166 isp_pci_mbxdma, 167 isp_pci_dmasetup, 168 isp_common_dmateardown, 169 isp_pci_reset0, 170 isp_pci_reset1, 171 NULL 172 }; 173 174 #ifndef PCIM_CMD_INVEN 175 #define PCIM_CMD_INVEN 0x10 176 #endif 177 #ifndef PCIM_CMD_BUSMASTEREN 178 #define PCIM_CMD_BUSMASTEREN 0x0004 179 #endif 180 #ifndef PCIM_CMD_PERRESPEN 181 #define PCIM_CMD_PERRESPEN 0x0040 182 #endif 183 #ifndef PCIM_CMD_SEREN 184 #define PCIM_CMD_SEREN 0x0100 185 #endif 186 #ifndef PCIM_CMD_INTX_DISABLE 187 #define PCIM_CMD_INTX_DISABLE 0x0400 188 #endif 189 190 #ifndef PCIR_COMMAND 191 #define PCIR_COMMAND 0x04 192 #endif 193 194 #ifndef PCIR_CACHELNSZ 195 #define PCIR_CACHELNSZ 0x0c 196 #endif 197 198 #ifndef PCIR_LATTIMER 199 #define PCIR_LATTIMER 0x0d 200 #endif 201 202 #ifndef PCIR_ROMADDR 203 #define PCIR_ROMADDR 0x30 204 #endif 205 206 #ifndef PCI_VENDOR_QLOGIC 207 #define PCI_VENDOR_QLOGIC 0x1077 208 #endif 209 210 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 211 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 212 #endif 213 214 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 215 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 216 #endif 217 218 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 219 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 220 #endif 221 222 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 223 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 224 #endif 225 226 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 227 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 228 #endif 229 230 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 231 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 232 #endif 233 234 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 235 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 236 #endif 237 238 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 239 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 240 #endif 241 242 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 243 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 244 #endif 245 246 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 247 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 248 #endif 249 250 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 251 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 252 #endif 253 254 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 255 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 256 #endif 257 258 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 259 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 260 #endif 261 262 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 263 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 264 #endif 265 266 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 267 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 268 #endif 269 270 271 #define PCI_QLOGIC_ISP1020 \ 272 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 273 274 #define PCI_QLOGIC_ISP1080 \ 275 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 276 277 #define PCI_QLOGIC_ISP10160 \ 278 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 279 280 #define PCI_QLOGIC_ISP12160 \ 281 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 282 283 #define PCI_QLOGIC_ISP1240 \ 284 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 285 286 #define PCI_QLOGIC_ISP1280 \ 287 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 288 289 #define PCI_QLOGIC_ISP2100 \ 290 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 291 292 #define PCI_QLOGIC_ISP2200 \ 293 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 294 295 #define PCI_QLOGIC_ISP2300 \ 296 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 297 298 #define PCI_QLOGIC_ISP2312 \ 299 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 300 301 #define PCI_QLOGIC_ISP2322 \ 302 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 303 304 #define PCI_QLOGIC_ISP2422 \ 305 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 306 307 #define PCI_QLOGIC_ISP2432 \ 308 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 309 310 #define PCI_QLOGIC_ISP6312 \ 311 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 312 313 #define PCI_QLOGIC_ISP6322 \ 314 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 315 316 /* 317 * Odd case for some AMI raid cards... We need to *not* attach to this. 318 */ 319 #define AMI_RAID_SUBVENDOR_ID 0x101e 320 321 #define IO_MAP_REG 0x10 322 #define MEM_MAP_REG 0x14 323 324 #define PCI_DFLT_LTNCY 0x40 325 #define PCI_DFLT_LNSZ 0x10 326 327 static int isp_pci_probe (device_t); 328 static int isp_pci_attach (device_t); 329 static int isp_pci_detach (device_t); 330 331 332 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 333 struct isp_pcisoftc { 334 ispsoftc_t pci_isp; 335 device_t pci_dev; 336 struct resource * pci_reg; 337 void * ih; 338 int16_t pci_poff[_NREG_BLKS]; 339 bus_dma_tag_t dmat; 340 #if __FreeBSD_version > 700025 341 int msicount; 342 #endif 343 }; 344 345 346 static device_method_t isp_pci_methods[] = { 347 /* Device interface */ 348 DEVMETHOD(device_probe, isp_pci_probe), 349 DEVMETHOD(device_attach, isp_pci_attach), 350 DEVMETHOD(device_detach, isp_pci_detach), 351 { 0, 0 } 352 }; 353 354 static driver_t isp_pci_driver = { 355 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 356 }; 357 static devclass_t isp_devclass; 358 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 359 #if __FreeBSD_version < 700000 360 extern ispfwfunc *isp_get_firmware_p; 361 #endif 362 363 static int 364 isp_pci_probe(device_t dev) 365 { 366 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 367 case PCI_QLOGIC_ISP1020: 368 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 369 break; 370 case PCI_QLOGIC_ISP1080: 371 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 372 break; 373 case PCI_QLOGIC_ISP1240: 374 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 375 break; 376 case PCI_QLOGIC_ISP1280: 377 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 378 break; 379 case PCI_QLOGIC_ISP10160: 380 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 381 break; 382 case PCI_QLOGIC_ISP12160: 383 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 384 return (ENXIO); 385 } 386 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 387 break; 388 case PCI_QLOGIC_ISP2100: 389 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 390 break; 391 case PCI_QLOGIC_ISP2200: 392 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 393 break; 394 case PCI_QLOGIC_ISP2300: 395 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 396 break; 397 case PCI_QLOGIC_ISP2312: 398 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 399 break; 400 case PCI_QLOGIC_ISP2322: 401 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 402 break; 403 case PCI_QLOGIC_ISP2422: 404 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 405 break; 406 case PCI_QLOGIC_ISP2432: 407 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 408 break; 409 case PCI_QLOGIC_ISP6312: 410 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 411 break; 412 case PCI_QLOGIC_ISP6322: 413 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 414 break; 415 default: 416 return (ENXIO); 417 } 418 if (isp_announced == 0 && bootverbose) { 419 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 420 "Core Version %d.%d\n", 421 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 422 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 423 isp_announced++; 424 } 425 /* 426 * XXXX: Here is where we might load the f/w module 427 * XXXX: (or increase a reference count to it). 428 */ 429 return (BUS_PROBE_DEFAULT); 430 } 431 432 #if __FreeBSD_version < 500000 433 static void 434 isp_get_generic_options(device_t dev, ispsoftc_t *isp) 435 { 436 int bitmap, unit; 437 438 unit = device_get_unit(dev); 439 if (getenv_int("isp_disable", &bitmap)) { 440 if (bitmap & (1 << unit)) { 441 isp->isp_osinfo.disabled = 1; 442 return; 443 } 444 } 445 if (getenv_int("isp_no_fwload", &bitmap)) { 446 if (bitmap & (1 << unit)) 447 isp->isp_confopts |= ISP_CFG_NORELOAD; 448 } 449 if (getenv_int("isp_fwload", &bitmap)) { 450 if (bitmap & (1 << unit)) 451 isp->isp_confopts &= ~ISP_CFG_NORELOAD; 452 } 453 if (getenv_int("isp_no_nvram", &bitmap)) { 454 if (bitmap & (1 << unit)) 455 isp->isp_confopts |= ISP_CFG_NONVRAM; 456 } 457 if (getenv_int("isp_nvram", &bitmap)) { 458 if (bitmap & (1 << unit)) 459 isp->isp_confopts &= ~ISP_CFG_NONVRAM; 460 } 461 462 bitmap = 0; 463 (void) getenv_int("isp_debug", &bitmap); 464 if (bitmap) { 465 isp->isp_dblev = bitmap; 466 } else { 467 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 468 } 469 if (bootverbose) { 470 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 471 } 472 473 bitmap = 0; 474 if (getenv_int("role", &bitmap)) { 475 isp->isp_role = bitmap; 476 } else { 477 isp->isp_role = ISP_DEFAULT_ROLES; 478 } 479 480 } 481 482 static void 483 isp_get_pci_options(device_t dev, int *m1, int *m2) 484 { 485 int bitmap; 486 int unit = device_get_unit(dev); 487 488 *m1 = PCIM_CMD_MEMEN; 489 *m2 = PCIM_CMD_PORTEN; 490 if (getenv_int("isp_mem_map", &bitmap)) { 491 if (bitmap & (1 << unit)) { 492 *m1 = PCIM_CMD_MEMEN; 493 *m2 = PCIM_CMD_PORTEN; 494 } 495 } 496 bitmap = 0; 497 if (getenv_int("isp_io_map", &bitmap)) { 498 if (bitmap & (1 << unit)) { 499 *m1 = PCIM_CMD_PORTEN; 500 *m2 = PCIM_CMD_MEMEN; 501 } 502 } 503 } 504 505 static void 506 isp_get_specific_options(device_t dev, ispsoftc_t *isp) 507 { 508 uint64_t wwn; 509 int bitmap; 510 int unit = device_get_unit(dev); 511 512 513 if (IS_SCSI(isp)) { 514 return; 515 } 516 517 if (getenv_int("isp_fcduplex", &bitmap)) { 518 if (bitmap & (1 << unit)) 519 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 520 } 521 if (getenv_int("isp_no_fcduplex", &bitmap)) { 522 if (bitmap & (1 << unit)) 523 isp->isp_confopts &= ~ISP_CFG_FULL_DUPLEX; 524 } 525 if (getenv_int("isp_nport", &bitmap)) { 526 if (bitmap & (1 << unit)) 527 isp->isp_confopts |= ISP_CFG_NPORT; 528 } 529 530 /* 531 * Because the resource_*_value functions can neither return 532 * 64 bit integer values, nor can they be directly coerced 533 * to interpret the right hand side of the assignment as 534 * you want them to interpret it, we have to force WWN 535 * hint replacement to specify WWN strings with a leading 536 * 'w' (e..g w50000000aaaa0001). Sigh. 537 */ 538 if (getenv_quad("isp_portwwn", &wwn)) { 539 isp->isp_osinfo.default_port_wwn = wwn; 540 isp->isp_confopts |= ISP_CFG_OWNWWPN; 541 } 542 if (isp->isp_osinfo.default_port_wwn == 0) { 543 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 544 } 545 546 if (getenv_quad("isp_nodewwn", &wwn)) { 547 isp->isp_osinfo.default_node_wwn = wwn; 548 isp->isp_confopts |= ISP_CFG_OWNWWNN; 549 } 550 if (isp->isp_osinfo.default_node_wwn == 0) { 551 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 552 } 553 554 bitmap = 0; 555 (void) getenv_int("isp_fabric_hysteresis", &bitmap); 556 if (bitmap >= 0 && bitmap < 256) { 557 isp->isp_osinfo.hysteresis = bitmap; 558 } else { 559 isp->isp_osinfo.hysteresis = isp_fabric_hysteresis; 560 } 561 562 bitmap = 0; 563 (void) getenv_int("isp_loop_down_limit", &bitmap); 564 if (bitmap >= 0 && bitmap < 0xffff) { 565 isp->isp_osinfo.loop_down_limit = bitmap; 566 } else { 567 isp->isp_osinfo.loop_down_limit = isp_loop_down_limit; 568 } 569 570 bitmap = 0; 571 (void) getenv_int("isp_gone_device_time", &bitmap); 572 if (bitmap >= 0 && bitmap < 0xffff) { 573 isp->isp_osinfo.gone_device_time = bitmap; 574 } else { 575 isp->isp_osinfo.gone_device_time = isp_gone_device_time; 576 } 577 #ifdef ISP_FW_CRASH_DUMP 578 bitmap = 0; 579 if (getenv_int("isp_fw_dump_enable", &bitmap)) { 580 if (bitmap & (1 << unit) { 581 size_t amt = 0; 582 if (IS_2200(isp)) { 583 amt = QLA2200_RISC_IMAGE_DUMP_SIZE; 584 } else if (IS_23XX(isp)) { 585 amt = QLA2300_RISC_IMAGE_DUMP_SIZE; 586 } 587 if (amt) { 588 FCPARAM(isp)->isp_dump_data = 589 malloc(amt, M_DEVBUF, M_WAITOK); 590 memset(FCPARAM(isp)->isp_dump_data, 0, amt); 591 } else { 592 device_printf(dev, 593 "f/w crash dumps not supported for card\n"); 594 } 595 } 596 } 597 #endif 598 } 599 #else 600 static void 601 isp_get_generic_options(device_t dev, ispsoftc_t *isp) 602 { 603 int tval; 604 605 /* 606 * Figure out if we're supposed to skip this one. 607 */ 608 tval = 0; 609 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 610 "disable", &tval) == 0 && tval) { 611 device_printf(dev, "disabled at user request\n"); 612 isp->isp_osinfo.disabled = 1; 613 return; 614 } 615 616 tval = -1; 617 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 618 "role", &tval) == 0 && tval != -1) { 619 tval &= (ISP_ROLE_INITIATOR|ISP_ROLE_TARGET); 620 isp->isp_role = tval; 621 device_printf(dev, "setting role to 0x%x\n", isp->isp_role); 622 } else { 623 #ifdef ISP_TARGET_MODE 624 isp->isp_role = ISP_ROLE_TARGET; 625 #else 626 isp->isp_role = ISP_DEFAULT_ROLES; 627 #endif 628 } 629 630 tval = 0; 631 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 632 "fwload_disable", &tval) == 0 && tval != 0) { 633 isp->isp_confopts |= ISP_CFG_NORELOAD; 634 } 635 tval = 0; 636 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 637 "ignore_nvram", &tval) == 0 && tval != 0) { 638 isp->isp_confopts |= ISP_CFG_NONVRAM; 639 } 640 641 tval = 0; 642 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 643 "debug", &tval); 644 if (tval) { 645 isp->isp_dblev = tval; 646 } else { 647 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 648 } 649 if (bootverbose) { 650 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 651 } 652 653 } 654 655 static void 656 isp_get_pci_options(device_t dev, int *m1, int *m2) 657 { 658 int tval; 659 /* 660 * Which we should try first - memory mapping or i/o mapping? 661 * 662 * We used to try memory first followed by i/o on alpha, otherwise 663 * the reverse, but we should just try memory first all the time now. 664 */ 665 *m1 = PCIM_CMD_MEMEN; 666 *m2 = PCIM_CMD_PORTEN; 667 668 tval = 0; 669 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 670 "prefer_iomap", &tval) == 0 && tval != 0) { 671 *m1 = PCIM_CMD_PORTEN; 672 *m2 = PCIM_CMD_MEMEN; 673 } 674 tval = 0; 675 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 676 "prefer_memmap", &tval) == 0 && tval != 0) { 677 *m1 = PCIM_CMD_MEMEN; 678 *m2 = PCIM_CMD_PORTEN; 679 } 680 } 681 682 static void 683 isp_get_specific_options(device_t dev, ispsoftc_t *isp) 684 { 685 const char *sptr; 686 int tval; 687 688 isp->isp_osinfo.default_id = -1; 689 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 690 "iid", &tval) == 0) { 691 isp->isp_osinfo.default_id = tval; 692 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 693 } 694 if (isp->isp_osinfo.default_id == -1) { 695 if (IS_FC(isp)) { 696 isp->isp_osinfo.default_id = 109; 697 } else { 698 isp->isp_osinfo.default_id = 7; 699 } 700 } 701 702 if (IS_SCSI(isp)) { 703 return; 704 } 705 706 tval = 0; 707 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 708 "fullduplex", &tval) == 0 && tval != 0) { 709 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 710 } 711 #ifdef ISP_FW_CRASH_DUMP 712 tval = 0; 713 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 714 "fw_dump_enable", &tval) == 0 && tval != 0) { 715 size_t amt = 0; 716 if (IS_2200(isp)) { 717 amt = QLA2200_RISC_IMAGE_DUMP_SIZE; 718 } else if (IS_23XX(isp)) { 719 amt = QLA2300_RISC_IMAGE_DUMP_SIZE; 720 } 721 if (amt) { 722 FCPARAM(isp)->isp_dump_data = 723 malloc(amt, M_DEVBUF, M_WAITOK | M_ZERO); 724 } else { 725 device_printf(dev, 726 "f/w crash dumps not supported for this model\n"); 727 } 728 } 729 #endif 730 sptr = 0; 731 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 732 "topology", (const char **) &sptr) == 0 && sptr != 0) { 733 if (strcmp(sptr, "lport") == 0) { 734 isp->isp_confopts |= ISP_CFG_LPORT; 735 } else if (strcmp(sptr, "nport") == 0) { 736 isp->isp_confopts |= ISP_CFG_NPORT; 737 } else if (strcmp(sptr, "lport-only") == 0) { 738 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 739 } else if (strcmp(sptr, "nport-only") == 0) { 740 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 741 } 742 } 743 744 /* 745 * Because the resource_*_value functions can neither return 746 * 64 bit integer values, nor can they be directly coerced 747 * to interpret the right hand side of the assignment as 748 * you want them to interpret it, we have to force WWN 749 * hint replacement to specify WWN strings with a leading 750 * 'w' (e..g w50000000aaaa0001). Sigh. 751 */ 752 sptr = 0; 753 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 754 "portwwn", (const char **) &sptr); 755 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 756 char *eptr = 0; 757 isp->isp_osinfo.default_port_wwn = strtouq(sptr, &eptr, 16); 758 if (eptr < sptr + 16 || isp->isp_osinfo.default_port_wwn == 0) { 759 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 760 isp->isp_osinfo.default_port_wwn = 0; 761 } else { 762 isp->isp_confopts |= ISP_CFG_OWNWWPN; 763 } 764 } 765 if (isp->isp_osinfo.default_port_wwn == 0) { 766 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 767 } 768 769 sptr = 0; 770 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 771 "nodewwn", (const char **) &sptr); 772 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 773 char *eptr = 0; 774 isp->isp_osinfo.default_node_wwn = strtouq(sptr, &eptr, 16); 775 if (eptr < sptr + 16 || isp->isp_osinfo.default_node_wwn == 0) { 776 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 777 isp->isp_osinfo.default_node_wwn = 0; 778 } else { 779 isp->isp_confopts |= ISP_CFG_OWNWWNN; 780 } 781 } 782 if (isp->isp_osinfo.default_node_wwn == 0) { 783 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 784 } 785 786 787 tval = 0; 788 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 789 "hysteresis", &tval); 790 if (tval >= 0 && tval < 256) { 791 isp->isp_osinfo.hysteresis = tval; 792 } else { 793 isp->isp_osinfo.hysteresis = isp_fabric_hysteresis; 794 } 795 796 tval = -1; 797 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 798 "loop_down_limit", &tval); 799 if (tval >= 0 && tval < 0xffff) { 800 isp->isp_osinfo.loop_down_limit = tval; 801 } else { 802 isp->isp_osinfo.loop_down_limit = isp_loop_down_limit; 803 } 804 805 tval = -1; 806 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 807 "gone_device_time", &tval); 808 if (tval >= 0 && tval < 0xffff) { 809 isp->isp_osinfo.gone_device_time = tval; 810 } else { 811 isp->isp_osinfo.gone_device_time = isp_gone_device_time; 812 } 813 } 814 #endif 815 816 static int 817 isp_pci_attach(device_t dev) 818 { 819 struct resource *regs, *irq; 820 int rtp, rgd, iqd, m1, m2; 821 uint32_t data, cmd, linesz, psize, basetype; 822 struct isp_pcisoftc *pcs; 823 ispsoftc_t *isp = NULL; 824 struct ispmdvec *mdvp; 825 #if __FreeBSD_version >= 500000 826 int locksetup = 0; 827 #endif 828 829 pcs = device_get_softc(dev); 830 if (pcs == NULL) { 831 device_printf(dev, "cannot get softc\n"); 832 return (ENOMEM); 833 } 834 memset(pcs, 0, sizeof (*pcs)); 835 pcs->pci_dev = dev; 836 isp = &pcs->pci_isp; 837 838 /* 839 * Get Generic Options 840 */ 841 isp_get_generic_options(dev, isp); 842 843 /* 844 * Check to see if options have us disabled 845 */ 846 if (isp->isp_osinfo.disabled) { 847 /* 848 * But return zero to preserve unit numbering 849 */ 850 return (0); 851 } 852 853 /* 854 * Get PCI options- which in this case are just mapping preferences. 855 */ 856 isp_get_pci_options(dev, &m1, &m2); 857 858 linesz = PCI_DFLT_LNSZ; 859 irq = regs = NULL; 860 rgd = rtp = iqd = 0; 861 862 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 863 if (cmd & m1) { 864 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 865 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 866 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 867 } 868 if (regs == NULL && (cmd & m2)) { 869 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 870 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 871 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 872 } 873 if (regs == NULL) { 874 device_printf(dev, "unable to map any ports\n"); 875 goto bad; 876 } 877 if (bootverbose) { 878 device_printf(dev, "using %s space register mapping\n", 879 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 880 } 881 pcs->pci_dev = dev; 882 pcs->pci_reg = regs; 883 isp->isp_bus_tag = rman_get_bustag(regs); 884 isp->isp_bus_handle = rman_get_bushandle(regs); 885 886 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 887 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 888 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 889 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 890 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 891 mdvp = &mdvec; 892 basetype = ISP_HA_SCSI_UNKNOWN; 893 psize = sizeof (sdparam); 894 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 895 mdvp = &mdvec; 896 basetype = ISP_HA_SCSI_UNKNOWN; 897 psize = sizeof (sdparam); 898 } 899 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 900 mdvp = &mdvec_1080; 901 basetype = ISP_HA_SCSI_1080; 902 psize = sizeof (sdparam); 903 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 904 ISP1080_DMA_REGS_OFF; 905 } 906 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 907 mdvp = &mdvec_1080; 908 basetype = ISP_HA_SCSI_1240; 909 psize = 2 * sizeof (sdparam); 910 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 911 ISP1080_DMA_REGS_OFF; 912 } 913 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 914 mdvp = &mdvec_1080; 915 basetype = ISP_HA_SCSI_1280; 916 psize = 2 * sizeof (sdparam); 917 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 918 ISP1080_DMA_REGS_OFF; 919 } 920 if (pci_get_devid(dev) == PCI_QLOGIC_ISP10160) { 921 mdvp = &mdvec_12160; 922 basetype = ISP_HA_SCSI_10160; 923 psize = sizeof (sdparam); 924 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 925 ISP1080_DMA_REGS_OFF; 926 } 927 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 928 mdvp = &mdvec_12160; 929 basetype = ISP_HA_SCSI_12160; 930 psize = 2 * sizeof (sdparam); 931 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 932 ISP1080_DMA_REGS_OFF; 933 } 934 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 935 mdvp = &mdvec_2100; 936 basetype = ISP_HA_FC_2100; 937 psize = sizeof (fcparam); 938 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 939 PCI_MBOX_REGS2100_OFF; 940 if (pci_get_revid(dev) < 3) { 941 /* 942 * XXX: Need to get the actual revision 943 * XXX: number of the 2100 FB. At any rate, 944 * XXX: lower cache line size for early revision 945 * XXX; boards. 946 */ 947 linesz = 1; 948 } 949 } 950 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 951 mdvp = &mdvec_2200; 952 basetype = ISP_HA_FC_2200; 953 psize = sizeof (fcparam); 954 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 955 PCI_MBOX_REGS2100_OFF; 956 } 957 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2300) { 958 mdvp = &mdvec_2300; 959 basetype = ISP_HA_FC_2300; 960 psize = sizeof (fcparam); 961 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 962 PCI_MBOX_REGS2300_OFF; 963 } 964 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2312 || 965 pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 966 mdvp = &mdvec_2300; 967 basetype = ISP_HA_FC_2312; 968 psize = sizeof (fcparam); 969 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 970 PCI_MBOX_REGS2300_OFF; 971 } 972 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2322 || 973 pci_get_devid(dev) == PCI_QLOGIC_ISP6322) { 974 mdvp = &mdvec_2300; 975 basetype = ISP_HA_FC_2322; 976 psize = sizeof (fcparam); 977 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 978 PCI_MBOX_REGS2300_OFF; 979 } 980 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2422 || 981 pci_get_devid(dev) == PCI_QLOGIC_ISP2432) { 982 mdvp = &mdvec_2400; 983 basetype = ISP_HA_FC_2400; 984 psize = sizeof (fcparam); 985 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 986 PCI_MBOX_REGS2400_OFF; 987 } 988 isp = &pcs->pci_isp; 989 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 990 if (isp->isp_param == NULL) { 991 device_printf(dev, "cannot allocate parameter data\n"); 992 goto bad; 993 } 994 isp->isp_mdvec = mdvp; 995 isp->isp_type = basetype; 996 isp->isp_revision = pci_get_revid(dev); 997 isp->isp_dev = dev; 998 999 /* 1000 * Now that we know who we are (roughly) get/set specific options 1001 */ 1002 isp_get_specific_options(dev, isp); 1003 1004 #if __FreeBSD_version >= 700000 1005 /* 1006 * Try and find firmware for this device. 1007 */ 1008 { 1009 char fwname[32]; 1010 unsigned int did = pci_get_device(dev); 1011 1012 /* 1013 * Map a few pci ids to fw names 1014 */ 1015 switch (did) { 1016 case PCI_PRODUCT_QLOGIC_ISP1020: 1017 did = 0x1040; 1018 break; 1019 case PCI_PRODUCT_QLOGIC_ISP1240: 1020 did = 0x1080; 1021 break; 1022 case PCI_PRODUCT_QLOGIC_ISP10160: 1023 case PCI_PRODUCT_QLOGIC_ISP12160: 1024 did = 0x12160; 1025 break; 1026 case PCI_PRODUCT_QLOGIC_ISP6312: 1027 case PCI_PRODUCT_QLOGIC_ISP2312: 1028 did = 0x2300; 1029 break; 1030 case PCI_PRODUCT_QLOGIC_ISP6322: 1031 did = 0x2322; 1032 break; 1033 case PCI_PRODUCT_QLOGIC_ISP2422: 1034 case PCI_PRODUCT_QLOGIC_ISP2432: 1035 did = 0x2400; 1036 break; 1037 default: 1038 break; 1039 } 1040 1041 isp->isp_osinfo.fw = NULL; 1042 if (isp->isp_role & ISP_ROLE_TARGET) { 1043 snprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 1044 isp->isp_osinfo.fw = firmware_get(fwname); 1045 } 1046 if (isp->isp_osinfo.fw == NULL) { 1047 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 1048 isp->isp_osinfo.fw = firmware_get(fwname); 1049 } 1050 if (isp->isp_osinfo.fw != NULL) { 1051 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 1052 } 1053 } 1054 #else 1055 if (isp_get_firmware_p) { 1056 int device = (int) pci_get_device(dev); 1057 #ifdef ISP_TARGET_MODE 1058 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 1059 #else 1060 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 1061 #endif 1062 } 1063 #endif 1064 1065 /* 1066 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 1067 * are set. 1068 */ 1069 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 1070 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 1071 1072 if (IS_2300(isp)) { /* per QLogic errata */ 1073 cmd &= ~PCIM_CMD_INVEN; 1074 } 1075 1076 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 1077 cmd &= ~PCIM_CMD_INTX_DISABLE; 1078 } 1079 1080 #ifdef WE_KNEW_WHAT_WE_WERE_DOING 1081 if (IS_24XX(isp)) { 1082 int reg; 1083 1084 cmd &= ~PCIM_CMD_INTX_DISABLE; 1085 1086 /* 1087 * Is this a PCI-X card? If so, set max read byte count. 1088 */ 1089 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 1090 uint16_t pxcmd; 1091 reg += 2; 1092 1093 pxcmd = pci_read_config(dev, reg, 2); 1094 pxcmd &= ~0xc; 1095 pxcmd |= 0x8; 1096 pci_write_config(dev, reg, 2, pxcmd); 1097 } 1098 1099 /* 1100 * Is this a PCI Express card? If so, set max read byte count. 1101 */ 1102 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1103 uint16_t pectl; 1104 1105 reg += 0x8; 1106 pectl = pci_read_config(dev, reg, 2); 1107 pectl &= ~0x7000; 1108 pectl |= 0x4000; 1109 pci_write_config(dev, reg, 2, pectl); 1110 } 1111 } 1112 #else 1113 if (IS_24XX(isp)) { 1114 cmd &= ~PCIM_CMD_INTX_DISABLE; 1115 } 1116 #endif 1117 1118 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 1119 1120 /* 1121 * Make sure the Cache Line Size register is set sensibly. 1122 */ 1123 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1124 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 1125 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d from %d", 1126 linesz, data); 1127 data = linesz; 1128 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 1129 } 1130 1131 /* 1132 * Make sure the Latency Timer is sane. 1133 */ 1134 data = pci_read_config(dev, PCIR_LATTIMER, 1); 1135 if (data < PCI_DFLT_LTNCY) { 1136 data = PCI_DFLT_LTNCY; 1137 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 1138 pci_write_config(dev, PCIR_LATTIMER, data, 1); 1139 } 1140 1141 /* 1142 * Make sure we've disabled the ROM. 1143 */ 1144 data = pci_read_config(dev, PCIR_ROMADDR, 4); 1145 data &= ~1; 1146 pci_write_config(dev, PCIR_ROMADDR, data, 4); 1147 #if __FreeBSD_version > 700025 1148 if (IS_24XX(isp) || IS_2322(isp)) { 1149 pcs->msicount = pci_msi_count(dev); 1150 if (pcs->msicount > 1) { 1151 pcs->msicount = 1; 1152 } 1153 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 1154 iqd = 1; 1155 } else { 1156 iqd = 0; 1157 } 1158 } 1159 #else 1160 iqd = 0; 1161 #endif 1162 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd, 1163 RF_ACTIVE | RF_SHAREABLE); 1164 if (irq == NULL) { 1165 device_printf(dev, "could not allocate interrupt\n"); 1166 goto bad; 1167 } 1168 1169 #if __FreeBSD_version >= 500000 1170 /* Make sure the lock is set up. */ 1171 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 1172 locksetup++; 1173 #endif 1174 1175 if (isp_setup_intr(dev, irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, 1176 &pcs->ih)) { 1177 device_printf(dev, "could not setup interrupt\n"); 1178 goto bad; 1179 } 1180 1181 /* 1182 * Last minute checks... 1183 */ 1184 if (IS_23XX(isp) || IS_24XX(isp)) { 1185 isp->isp_port = pci_get_function(dev); 1186 } 1187 1188 if (IS_23XX(isp)) { 1189 /* 1190 * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command. 1191 */ 1192 isp->isp_touched = 1; 1193 } 1194 1195 /* 1196 * Make sure we're in reset state. 1197 */ 1198 ISP_LOCK(isp); 1199 isp_reset(isp); 1200 if (isp->isp_state != ISP_RESETSTATE) { 1201 ISP_UNLOCK(isp); 1202 goto bad; 1203 } 1204 isp_init(isp); 1205 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_INITSTATE) { 1206 isp_uninit(isp); 1207 ISP_UNLOCK(isp); 1208 goto bad; 1209 } 1210 isp_attach(isp); 1211 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_RUNSTATE) { 1212 isp_uninit(isp); 1213 ISP_UNLOCK(isp); 1214 goto bad; 1215 } 1216 ISP_UNLOCK(isp); 1217 return (0); 1218 1219 bad: 1220 if (pcs && pcs->ih) { 1221 (void) bus_teardown_intr(dev, irq, pcs->ih); 1222 } 1223 #if __FreeBSD_version >= 500000 1224 if (locksetup && isp) { 1225 mtx_destroy(&isp->isp_osinfo.lock); 1226 } 1227 #endif 1228 if (irq) { 1229 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 1230 } 1231 #if __FreeBSD_version > 700025 1232 if (pcs && pcs->msicount) { 1233 pci_release_msi(dev); 1234 } 1235 #endif 1236 if (regs) { 1237 (void) bus_release_resource(dev, rtp, rgd, regs); 1238 } 1239 if (pcs) { 1240 if (pcs->pci_isp.isp_param) { 1241 #ifdef ISP_FW_CRASH_DUMP 1242 if (IS_FC(isp) && FCPARAM(isp)->isp_dump_data) { 1243 free(FCPARAM(isp)->isp_dump_data, M_DEVBUF); 1244 } 1245 #endif 1246 free(pcs->pci_isp.isp_param, M_DEVBUF); 1247 } 1248 } 1249 return (ENXIO); 1250 } 1251 1252 static int 1253 isp_pci_detach(device_t dev) 1254 { 1255 struct isp_pcisoftc *pcs; 1256 ispsoftc_t *isp; 1257 1258 pcs = device_get_softc(dev); 1259 if (pcs == NULL) { 1260 return (ENXIO); 1261 } 1262 isp = (ispsoftc_t *) pcs; 1263 ISP_DISABLE_INTS(isp); 1264 return (0); 1265 } 1266 1267 #define IspVirt2Off(a, x) \ 1268 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1269 _BLK_REG_SHFT] + ((x) & 0xfff)) 1270 1271 #define BXR2(isp, off) \ 1272 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1273 #define BXW2(isp, off, v) \ 1274 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1275 #define BXR4(isp, off) \ 1276 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1277 #define BXW4(isp, off, v) \ 1278 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1279 1280 1281 static __inline int 1282 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1283 { 1284 uint32_t val0, val1; 1285 int i = 0; 1286 1287 do { 1288 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1289 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1290 } while (val0 != val1 && ++i < 1000); 1291 if (val0 != val1) { 1292 return (1); 1293 } 1294 *rp = val0; 1295 return (0); 1296 } 1297 1298 static int 1299 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1300 { 1301 uint16_t isr, sema; 1302 1303 if (IS_2100(isp)) { 1304 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1305 return (0); 1306 } 1307 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1308 return (0); 1309 } 1310 } else { 1311 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1312 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1313 } 1314 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1315 isr &= INT_PENDING_MASK(isp); 1316 sema &= BIU_SEMA_LOCK; 1317 if (isr == 0 && sema == 0) { 1318 return (0); 1319 } 1320 *isrp = isr; 1321 if ((*semap = sema) != 0) { 1322 if (IS_2100(isp)) { 1323 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1324 return (0); 1325 } 1326 } else { 1327 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1328 } 1329 } 1330 return (1); 1331 } 1332 1333 static int 1334 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, 1335 uint16_t *semap, uint16_t *mbox0p) 1336 { 1337 uint32_t hccr; 1338 uint32_t r2hisr; 1339 1340 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1341 *isrp = 0; 1342 return (0); 1343 } 1344 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1345 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1346 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1347 *isrp = 0; 1348 return (0); 1349 } 1350 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1351 case ISPR2HST_ROM_MBX_OK: 1352 case ISPR2HST_ROM_MBX_FAIL: 1353 case ISPR2HST_MBX_OK: 1354 case ISPR2HST_MBX_FAIL: 1355 case ISPR2HST_ASYNC_EVENT: 1356 *isrp = r2hisr & 0xffff; 1357 *mbox0p = (r2hisr >> 16); 1358 *semap = 1; 1359 return (1); 1360 case ISPR2HST_RIO_16: 1361 *isrp = r2hisr & 0xffff; 1362 *mbox0p = ASYNC_RIO1; 1363 *semap = 1; 1364 return (1); 1365 case ISPR2HST_FPOST: 1366 *isrp = r2hisr & 0xffff; 1367 *mbox0p = ASYNC_CMD_CMPLT; 1368 *semap = 1; 1369 return (1); 1370 case ISPR2HST_FPOST_CTIO: 1371 *isrp = r2hisr & 0xffff; 1372 *mbox0p = ASYNC_CTIO_DONE; 1373 *semap = 1; 1374 return (1); 1375 case ISPR2HST_RSPQ_UPDATE: 1376 *isrp = r2hisr & 0xffff; 1377 *mbox0p = 0; 1378 *semap = 0; 1379 return (1); 1380 default: 1381 hccr = ISP_READ(isp, HCCR); 1382 if (hccr & HCCR_PAUSE) { 1383 ISP_WRITE(isp, HCCR, HCCR_RESET); 1384 isp_prt(isp, ISP_LOGERR, 1385 "RISC paused at interrupt (%x->%x)", hccr, 1386 ISP_READ(isp, HCCR)); 1387 ISP_WRITE(isp, BIU_ICR, 0); 1388 } else { 1389 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", 1390 r2hisr); 1391 } 1392 return (0); 1393 } 1394 } 1395 1396 static int 1397 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, 1398 uint16_t *semap, uint16_t *mbox0p) 1399 { 1400 uint32_t r2hisr; 1401 1402 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1403 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1404 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1405 *isrp = 0; 1406 return (0); 1407 } 1408 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1409 case ISP2400R2HST_ROM_MBX_OK: 1410 case ISP2400R2HST_ROM_MBX_FAIL: 1411 case ISP2400R2HST_MBX_OK: 1412 case ISP2400R2HST_MBX_FAIL: 1413 case ISP2400R2HST_ASYNC_EVENT: 1414 *isrp = r2hisr & 0xffff; 1415 *mbox0p = (r2hisr >> 16); 1416 *semap = 1; 1417 return (1); 1418 case ISP2400R2HST_RSPQ_UPDATE: 1419 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1420 case ISP2400R2HST_ATIO_RQST_UPDATE: 1421 *isrp = r2hisr & 0xffff; 1422 *mbox0p = 0; 1423 *semap = 0; 1424 return (1); 1425 default: 1426 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1427 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1428 return (0); 1429 } 1430 } 1431 1432 static uint32_t 1433 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1434 { 1435 uint16_t rv; 1436 int oldconf = 0; 1437 1438 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1439 /* 1440 * We will assume that someone has paused the RISC processor. 1441 */ 1442 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1443 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1444 oldconf | BIU_PCI_CONF1_SXP); 1445 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1446 } 1447 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1448 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1449 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1450 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1451 } 1452 return (rv); 1453 } 1454 1455 static void 1456 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1457 { 1458 int oldconf = 0; 1459 1460 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1461 /* 1462 * We will assume that someone has paused the RISC processor. 1463 */ 1464 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1465 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1466 oldconf | BIU_PCI_CONF1_SXP); 1467 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1468 } 1469 BXW2(isp, IspVirt2Off(isp, regoff), val); 1470 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1471 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1472 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1473 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1474 } 1475 1476 } 1477 1478 static uint32_t 1479 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1480 { 1481 uint32_t rv, oc = 0; 1482 1483 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1484 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1485 uint32_t tc; 1486 /* 1487 * We will assume that someone has paused the RISC processor. 1488 */ 1489 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1490 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1491 if (regoff & SXP_BANK1_SELECT) 1492 tc |= BIU_PCI1080_CONF1_SXP1; 1493 else 1494 tc |= BIU_PCI1080_CONF1_SXP0; 1495 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1496 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1497 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1498 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1499 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1500 oc | BIU_PCI1080_CONF1_DMA); 1501 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1502 } 1503 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1504 if (oc) { 1505 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1506 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1507 } 1508 return (rv); 1509 } 1510 1511 static void 1512 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1513 { 1514 int oc = 0; 1515 1516 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1517 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1518 uint32_t tc; 1519 /* 1520 * We will assume that someone has paused the RISC processor. 1521 */ 1522 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1523 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1524 if (regoff & SXP_BANK1_SELECT) 1525 tc |= BIU_PCI1080_CONF1_SXP1; 1526 else 1527 tc |= BIU_PCI1080_CONF1_SXP0; 1528 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1529 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1530 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1531 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1532 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1533 oc | BIU_PCI1080_CONF1_DMA); 1534 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1535 } 1536 BXW2(isp, IspVirt2Off(isp, regoff), val); 1537 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1538 if (oc) { 1539 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1540 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2); 1541 } 1542 } 1543 1544 static uint32_t 1545 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1546 { 1547 uint32_t rv; 1548 int block = regoff & _BLK_REG_MASK; 1549 1550 switch (block) { 1551 case BIU_BLOCK: 1552 break; 1553 case MBOX_BLOCK: 1554 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1555 case SXP_BLOCK: 1556 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1557 return (0xffffffff); 1558 case RISC_BLOCK: 1559 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1560 return (0xffffffff); 1561 case DMA_BLOCK: 1562 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1563 return (0xffffffff); 1564 default: 1565 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1566 return (0xffffffff); 1567 } 1568 1569 1570 switch (regoff) { 1571 case BIU2400_FLASH_ADDR: 1572 case BIU2400_FLASH_DATA: 1573 case BIU2400_ICR: 1574 case BIU2400_ISR: 1575 case BIU2400_CSR: 1576 case BIU2400_REQINP: 1577 case BIU2400_REQOUTP: 1578 case BIU2400_RSPINP: 1579 case BIU2400_RSPOUTP: 1580 case BIU2400_PRI_RQINP: 1581 case BIU2400_PRI_RSPINP: 1582 case BIU2400_ATIO_RSPINP: 1583 case BIU2400_ATIO_REQINP: 1584 case BIU2400_HCCR: 1585 case BIU2400_GPIOD: 1586 case BIU2400_GPIOE: 1587 case BIU2400_HSEMA: 1588 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1589 break; 1590 case BIU2400_R2HSTSLO: 1591 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1592 break; 1593 case BIU2400_R2HSTSHI: 1594 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1595 break; 1596 default: 1597 isp_prt(isp, ISP_LOGERR, 1598 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1599 rv = 0xffffffff; 1600 break; 1601 } 1602 return (rv); 1603 } 1604 1605 static void 1606 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1607 { 1608 int block = regoff & _BLK_REG_MASK; 1609 1610 switch (block) { 1611 case BIU_BLOCK: 1612 break; 1613 case MBOX_BLOCK: 1614 BXW2(isp, IspVirt2Off(isp, regoff), val); 1615 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2); 1616 return; 1617 case SXP_BLOCK: 1618 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1619 return; 1620 case RISC_BLOCK: 1621 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1622 return; 1623 case DMA_BLOCK: 1624 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1625 return; 1626 default: 1627 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1628 regoff); 1629 break; 1630 } 1631 1632 switch (regoff) { 1633 case BIU2400_FLASH_ADDR: 1634 case BIU2400_FLASH_DATA: 1635 case BIU2400_ICR: 1636 case BIU2400_ISR: 1637 case BIU2400_CSR: 1638 case BIU2400_REQINP: 1639 case BIU2400_REQOUTP: 1640 case BIU2400_RSPINP: 1641 case BIU2400_RSPOUTP: 1642 case BIU2400_PRI_RQINP: 1643 case BIU2400_PRI_RSPINP: 1644 case BIU2400_ATIO_RSPINP: 1645 case BIU2400_ATIO_REQINP: 1646 case BIU2400_HCCR: 1647 case BIU2400_GPIOD: 1648 case BIU2400_GPIOE: 1649 case BIU2400_HSEMA: 1650 BXW4(isp, IspVirt2Off(isp, regoff), val); 1651 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4); 1652 break; 1653 default: 1654 isp_prt(isp, ISP_LOGERR, 1655 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1656 break; 1657 } 1658 } 1659 1660 1661 struct imush { 1662 ispsoftc_t *isp; 1663 int error; 1664 }; 1665 1666 static void imc(void *, bus_dma_segment_t *, int, int); 1667 1668 static void 1669 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1670 { 1671 struct imush *imushp = (struct imush *) arg; 1672 if (error) { 1673 imushp->error = error; 1674 } else { 1675 ispsoftc_t *isp =imushp->isp; 1676 bus_addr_t addr = segs->ds_addr; 1677 1678 isp->isp_rquest_dma = addr; 1679 addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1680 isp->isp_result_dma = addr; 1681 if (IS_FC(isp)) { 1682 addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1683 FCPARAM(isp)->isp_scdma = addr; 1684 } 1685 } 1686 } 1687 1688 static int 1689 isp_pci_mbxdma(ispsoftc_t *isp) 1690 { 1691 caddr_t base; 1692 uint32_t len; 1693 int i, error, ns; 1694 bus_size_t slim; /* segment size */ 1695 bus_addr_t llim; /* low limit of unavailable dma */ 1696 bus_addr_t hlim; /* high limit of unavailable dma */ 1697 struct imush im; 1698 1699 /* 1700 * Already been here? If so, leave... 1701 */ 1702 if (isp->isp_rquest) { 1703 return (0); 1704 } 1705 ISP_UNLOCK(isp); 1706 1707 if (isp->isp_maxcmds == 0) { 1708 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1709 ISP_LOCK(isp); 1710 return (1); 1711 } 1712 1713 hlim = BUS_SPACE_MAXADDR; 1714 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1715 slim = (bus_size_t) (1ULL << 32); 1716 llim = BUS_SPACE_MAXADDR; 1717 } else { 1718 llim = BUS_SPACE_MAXADDR_32BIT; 1719 slim = (1 << 24); 1720 } 1721 1722 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1723 isp->isp_osinfo.pcmd_pool = 1724 (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1725 if (isp->isp_osinfo.pcmd_pool == NULL) { 1726 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1727 ISP_LOCK(isp); 1728 return (1); 1729 } 1730 1731 /* 1732 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1733 */ 1734 #ifdef ISP_TARGET_MODE 1735 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1736 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1737 ISP_LOCK(isp); 1738 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1739 return (1); 1740 } 1741 #endif 1742 1743 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, 1744 slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, 1745 slim, 0, &isp->isp_osinfo.dmat)) { 1746 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1747 ISP_LOCK(isp); 1748 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1749 return (1); 1750 } 1751 1752 1753 len = sizeof (XS_T **) * isp->isp_maxcmds; 1754 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1755 if (isp->isp_xflist == NULL) { 1756 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1757 ISP_LOCK(isp); 1758 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1759 return (1); 1760 } 1761 #ifdef ISP_TARGET_MODE 1762 len = sizeof (void **) * isp->isp_maxcmds; 1763 isp->isp_tgtlist = (void **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1764 if (isp->isp_tgtlist == NULL) { 1765 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1766 free(isp->isp_xflist, M_DEVBUF); 1767 ISP_LOCK(isp); 1768 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1769 return (1); 1770 } 1771 #endif 1772 1773 /* 1774 * Allocate and map the request, result queues, plus FC scratch area. 1775 */ 1776 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1777 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1778 if (IS_FC(isp)) { 1779 len += ISP2100_SCRLEN; 1780 } 1781 1782 ns = (len / PAGE_SIZE) + 1; 1783 /* 1784 * Create a tag for the control spaces- force it to within 32 bits. 1785 */ 1786 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, 1787 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1788 NULL, NULL, len, ns, slim, 0, &isp->isp_cdmat)) { 1789 isp_prt(isp, ISP_LOGERR, 1790 "cannot create a dma tag for control spaces"); 1791 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1792 free(isp->isp_xflist, M_DEVBUF); 1793 #ifdef ISP_TARGET_MODE 1794 free(isp->isp_tgtlist, M_DEVBUF); 1795 #endif 1796 ISP_LOCK(isp); 1797 return (1); 1798 } 1799 1800 if (bus_dmamem_alloc(isp->isp_cdmat, (void **)&base, BUS_DMA_NOWAIT, 1801 &isp->isp_cdmap) != 0) { 1802 isp_prt(isp, ISP_LOGERR, 1803 "cannot allocate %d bytes of CCB memory", len); 1804 bus_dma_tag_destroy(isp->isp_cdmat); 1805 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1806 free(isp->isp_xflist, M_DEVBUF); 1807 #ifdef ISP_TARGET_MODE 1808 free(isp->isp_tgtlist, M_DEVBUF); 1809 #endif 1810 ISP_LOCK(isp); 1811 return (1); 1812 } 1813 1814 for (i = 0; i < isp->isp_maxcmds; i++) { 1815 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1816 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1817 if (error) { 1818 isp_prt(isp, ISP_LOGERR, 1819 "error %d creating per-cmd DMA maps", error); 1820 while (--i >= 0) { 1821 bus_dmamap_destroy(isp->isp_osinfo.dmat, 1822 isp->isp_osinfo.pcmd_pool[i].dmap); 1823 } 1824 goto bad; 1825 } 1826 isp_callout_init(&pcmd->wdog); 1827 if (i == isp->isp_maxcmds-1) { 1828 pcmd->next = NULL; 1829 } else { 1830 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1831 } 1832 } 1833 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1834 1835 im.isp = isp; 1836 im.error = 0; 1837 bus_dmamap_load(isp->isp_cdmat, isp->isp_cdmap, base, len, imc, &im, 0); 1838 if (im.error) { 1839 isp_prt(isp, ISP_LOGERR, 1840 "error %d loading dma map for control areas", im.error); 1841 goto bad; 1842 } 1843 1844 isp->isp_rquest = base; 1845 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1846 isp->isp_result = base; 1847 if (IS_FC(isp)) { 1848 base += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1849 FCPARAM(isp)->isp_scratch = base; 1850 } 1851 ISP_LOCK(isp); 1852 return (0); 1853 1854 bad: 1855 bus_dmamem_free(isp->isp_cdmat, base, isp->isp_cdmap); 1856 bus_dma_tag_destroy(isp->isp_cdmat); 1857 free(isp->isp_xflist, M_DEVBUF); 1858 #ifdef ISP_TARGET_MODE 1859 free(isp->isp_tgtlist, M_DEVBUF); 1860 #endif 1861 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1862 isp->isp_rquest = NULL; 1863 ISP_LOCK(isp); 1864 return (1); 1865 } 1866 1867 typedef struct { 1868 ispsoftc_t *isp; 1869 void *cmd_token; 1870 void *rq; 1871 uint32_t *nxtip; 1872 uint32_t optr; 1873 int error; 1874 } mush_t; 1875 1876 #define MUSHERR_NOQENTRIES -2 1877 1878 #ifdef ISP_TARGET_MODE 1879 /* 1880 * We need to handle DMA for target mode differently from initiator mode. 1881 * 1882 * DMA mapping and construction and submission of CTIO Request Entries 1883 * and rendevous for completion are very tightly coupled because we start 1884 * out by knowing (per platform) how much data we have to move, but we 1885 * don't know, up front, how many DMA mapping segments will have to be used 1886 * cover that data, so we don't know how many CTIO Request Entries we 1887 * will end up using. Further, for performance reasons we may want to 1888 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1889 * 1890 * The standard vector still goes through isp_pci_dmasetup, but the callback 1891 * for the DMA mapping routines comes here instead with the whole transfer 1892 * mapped and a pointer to a partially filled in already allocated request 1893 * queue entry. We finish the job. 1894 */ 1895 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1896 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1897 1898 #define STATUS_WITH_DATA 1 1899 1900 static void 1901 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1902 { 1903 mush_t *mp; 1904 struct ccb_scsiio *csio; 1905 ispsoftc_t *isp; 1906 ct_entry_t *cto, *qe; 1907 uint8_t scsi_status; 1908 uint32_t curi, nxti, handle; 1909 uint32_t sflags; 1910 int32_t resid; 1911 int nth_ctio, nctios, send_status; 1912 1913 mp = (mush_t *) arg; 1914 if (error) { 1915 mp->error = error; 1916 return; 1917 } 1918 1919 isp = mp->isp; 1920 csio = mp->cmd_token; 1921 cto = mp->rq; 1922 curi = isp->isp_reqidx; 1923 qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1924 1925 cto->ct_xfrlen = 0; 1926 cto->ct_seg_count = 0; 1927 cto->ct_header.rqs_entry_count = 1; 1928 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1929 1930 if (nseg == 0) { 1931 cto->ct_header.rqs_seqno = 1; 1932 isp_prt(isp, ISP_LOGTDEBUG1, 1933 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1934 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1935 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1936 cto->ct_scsi_status, cto->ct_resid); 1937 ISP_TDQE(isp, "tdma_mk[no data]", curi, cto); 1938 isp_put_ctio(isp, cto, qe); 1939 return; 1940 } 1941 1942 nctios = nseg / ISP_RQDSEG; 1943 if (nseg % ISP_RQDSEG) { 1944 nctios++; 1945 } 1946 1947 /* 1948 * Save syshandle, and potentially any SCSI status, which we'll 1949 * reinsert on the last CTIO we're going to send. 1950 */ 1951 1952 handle = cto->ct_syshandle; 1953 cto->ct_syshandle = 0; 1954 cto->ct_header.rqs_seqno = 0; 1955 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1956 1957 if (send_status) { 1958 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1959 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1960 /* 1961 * Preserve residual. 1962 */ 1963 resid = cto->ct_resid; 1964 1965 /* 1966 * Save actual SCSI status. 1967 */ 1968 scsi_status = cto->ct_scsi_status; 1969 1970 #ifndef STATUS_WITH_DATA 1971 sflags |= CT_NO_DATA; 1972 /* 1973 * We can't do a status at the same time as a data CTIO, so 1974 * we need to synthesize an extra CTIO at this level. 1975 */ 1976 nctios++; 1977 #endif 1978 } else { 1979 sflags = scsi_status = resid = 0; 1980 } 1981 1982 cto->ct_resid = 0; 1983 cto->ct_scsi_status = 0; 1984 1985 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1986 bus_dmamap_sync(isp->isp_osinfo.dmat, 1987 PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1988 } else { 1989 bus_dmamap_sync(isp->isp_osinfo.dmat, 1990 PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1991 } 1992 1993 nxti = *mp->nxtip; 1994 1995 for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { 1996 int seglim; 1997 1998 seglim = nseg; 1999 if (seglim) { 2000 int seg; 2001 2002 if (seglim > ISP_RQDSEG) 2003 seglim = ISP_RQDSEG; 2004 2005 for (seg = 0; seg < seglim; seg++, nseg--) { 2006 /* 2007 * Unlike normal initiator commands, we don't 2008 * do any swizzling here. 2009 */ 2010 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 2011 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 2012 cto->ct_xfrlen += dm_segs->ds_len; 2013 dm_segs++; 2014 } 2015 cto->ct_seg_count = seg; 2016 } else { 2017 /* 2018 * This case should only happen when we're sending an 2019 * extra CTIO with final status. 2020 */ 2021 if (send_status == 0) { 2022 isp_prt(isp, ISP_LOGWARN, 2023 "tdma_mk ran out of segments"); 2024 mp->error = EINVAL; 2025 return; 2026 } 2027 } 2028 2029 /* 2030 * At this point, the fields ct_lun, ct_iid, ct_tagval, 2031 * ct_tagtype, and ct_timeout have been carried over 2032 * unchanged from what our caller had set. 2033 * 2034 * The dataseg fields and the seg_count fields we just got 2035 * through setting. The data direction we've preserved all 2036 * along and only clear it if we're now sending status. 2037 */ 2038 2039 if (nth_ctio == nctios - 1) { 2040 /* 2041 * We're the last in a sequence of CTIOs, so mark 2042 * this CTIO and save the handle to the CCB such that 2043 * when this CTIO completes we can free dma resources 2044 * and do whatever else we need to do to finish the 2045 * rest of the command. We *don't* give this to the 2046 * firmware to work on- the caller will do that. 2047 */ 2048 2049 cto->ct_syshandle = handle; 2050 cto->ct_header.rqs_seqno = 1; 2051 2052 if (send_status) { 2053 cto->ct_scsi_status = scsi_status; 2054 cto->ct_flags |= sflags; 2055 cto->ct_resid = resid; 2056 } 2057 if (send_status) { 2058 isp_prt(isp, ISP_LOGTDEBUG1, 2059 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 2060 "scsi status %x resid %d", 2061 cto->ct_fwhandle, csio->ccb_h.target_lun, 2062 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 2063 cto->ct_scsi_status, cto->ct_resid); 2064 } else { 2065 isp_prt(isp, ISP_LOGTDEBUG1, 2066 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 2067 cto->ct_fwhandle, csio->ccb_h.target_lun, 2068 cto->ct_iid, cto->ct_tag_val, 2069 cto->ct_flags); 2070 } 2071 isp_put_ctio(isp, cto, qe); 2072 ISP_TDQE(isp, "last tdma_mk", curi, cto); 2073 if (nctios > 1) { 2074 MEMORYBARRIER(isp, SYNC_REQUEST, 2075 curi, QENTRY_LEN); 2076 } 2077 } else { 2078 ct_entry_t *oqe = qe; 2079 2080 /* 2081 * Make sure syshandle fields are clean 2082 */ 2083 cto->ct_syshandle = 0; 2084 cto->ct_header.rqs_seqno = 0; 2085 2086 isp_prt(isp, ISP_LOGTDEBUG1, 2087 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 2088 cto->ct_fwhandle, csio->ccb_h.target_lun, 2089 cto->ct_iid, cto->ct_flags); 2090 2091 /* 2092 * Get a new CTIO 2093 */ 2094 qe = (ct_entry_t *) 2095 ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 2096 nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); 2097 if (nxti == mp->optr) { 2098 isp_prt(isp, ISP_LOGTDEBUG0, 2099 "Queue Overflow in tdma_mk"); 2100 mp->error = MUSHERR_NOQENTRIES; 2101 return; 2102 } 2103 2104 /* 2105 * Now that we're done with the old CTIO, 2106 * flush it out to the request queue. 2107 */ 2108 ISP_TDQE(isp, "dma_tgt_fc", curi, cto); 2109 isp_put_ctio(isp, cto, oqe); 2110 if (nth_ctio != 0) { 2111 MEMORYBARRIER(isp, SYNC_REQUEST, curi, 2112 QENTRY_LEN); 2113 } 2114 curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); 2115 2116 /* 2117 * Reset some fields in the CTIO so we can reuse 2118 * for the next one we'll flush to the request 2119 * queue. 2120 */ 2121 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 2122 cto->ct_header.rqs_entry_count = 1; 2123 cto->ct_header.rqs_flags = 0; 2124 cto->ct_status = 0; 2125 cto->ct_scsi_status = 0; 2126 cto->ct_xfrlen = 0; 2127 cto->ct_resid = 0; 2128 cto->ct_seg_count = 0; 2129 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 2130 } 2131 } 2132 *mp->nxtip = nxti; 2133 } 2134 2135 /* 2136 * We don't have to do multiple CTIOs here. Instead, we can just do 2137 * continuation segments as needed. This greatly simplifies the code 2138 * improves performance. 2139 */ 2140 2141 static void 2142 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2143 { 2144 mush_t *mp; 2145 struct ccb_scsiio *csio; 2146 ispsoftc_t *isp; 2147 ct2_entry_t *cto, *qe; 2148 uint32_t curi, nxti; 2149 ispds_t *ds; 2150 ispds64_t *ds64; 2151 int segcnt, seglim; 2152 2153 mp = (mush_t *) arg; 2154 if (error) { 2155 mp->error = error; 2156 return; 2157 } 2158 2159 isp = mp->isp; 2160 csio = mp->cmd_token; 2161 cto = mp->rq; 2162 2163 curi = isp->isp_reqidx; 2164 qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 2165 2166 if (nseg == 0) { 2167 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 2168 isp_prt(isp, ISP_LOGWARN, 2169 "dma2_tgt_fc, a status CTIO2 without MODE1 " 2170 "set (0x%x)", cto->ct_flags); 2171 mp->error = EINVAL; 2172 return; 2173 } 2174 /* 2175 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 2176 * flags to NO DATA and clear relative offset flags. 2177 * We preserve the ct_resid and the response area. 2178 */ 2179 cto->ct_header.rqs_seqno = 1; 2180 cto->ct_seg_count = 0; 2181 cto->ct_reloff = 0; 2182 isp_prt(isp, ISP_LOGTDEBUG1, 2183 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 2184 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 2185 cto->ct_iid, cto->ct_flags, cto->ct_status, 2186 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 2187 if (FCPARAM(isp)->isp_2klogin) { 2188 isp_put_ctio2e(isp, 2189 (ct2e_entry_t *)cto, (ct2e_entry_t *)qe); 2190 } else { 2191 isp_put_ctio2(isp, cto, qe); 2192 } 2193 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe); 2194 return; 2195 } 2196 2197 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 2198 isp_prt(isp, ISP_LOGERR, 2199 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 2200 "(0x%x)", cto->ct_flags); 2201 mp->error = EINVAL; 2202 return; 2203 } 2204 2205 2206 nxti = *mp->nxtip; 2207 2208 /* 2209 * Check to see if we need to DAC addressing or not. 2210 * 2211 * Any address that's over the 4GB boundary causes this 2212 * to happen. 2213 */ 2214 segcnt = nseg; 2215 if (sizeof (bus_addr_t) > 4) { 2216 for (segcnt = 0; segcnt < nseg; segcnt++) { 2217 uint64_t addr = dm_segs[segcnt].ds_addr; 2218 if (addr >= 0x100000000LL) { 2219 break; 2220 } 2221 } 2222 } 2223 if (segcnt != nseg) { 2224 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO3; 2225 seglim = ISP_RQDSEG_T3; 2226 ds64 = &cto->rsp.m0.u.ct_dataseg64[0]; 2227 ds = NULL; 2228 } else { 2229 seglim = ISP_RQDSEG_T2; 2230 ds64 = NULL; 2231 ds = &cto->rsp.m0.u.ct_dataseg[0]; 2232 } 2233 cto->ct_seg_count = 0; 2234 2235 /* 2236 * Set up the CTIO2 data segments. 2237 */ 2238 for (segcnt = 0; cto->ct_seg_count < seglim && segcnt < nseg; 2239 cto->ct_seg_count++, segcnt++) { 2240 if (ds64) { 2241 ds64->ds_basehi = 2242 ((uint64_t) (dm_segs[segcnt].ds_addr) >> 32); 2243 ds64->ds_base = dm_segs[segcnt].ds_addr; 2244 ds64->ds_count = dm_segs[segcnt].ds_len; 2245 ds64++; 2246 } else { 2247 ds->ds_base = dm_segs[segcnt].ds_addr; 2248 ds->ds_count = dm_segs[segcnt].ds_len; 2249 ds++; 2250 } 2251 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 2252 #if __FreeBSD_version < 500000 2253 isp_prt(isp, ISP_LOGTDEBUG1, 2254 "isp_send_ctio2: ent0[%d]0x%llx:%llu", 2255 cto->ct_seg_count, (uint64_t)dm_segs[segcnt].ds_addr, 2256 (uint64_t)dm_segs[segcnt].ds_len); 2257 #else 2258 isp_prt(isp, ISP_LOGTDEBUG1, 2259 "isp_send_ctio2: ent0[%d]0x%jx:%ju", 2260 cto->ct_seg_count, (uintmax_t)dm_segs[segcnt].ds_addr, 2261 (uintmax_t)dm_segs[segcnt].ds_len); 2262 #endif 2263 } 2264 2265 while (segcnt < nseg) { 2266 uint32_t curip; 2267 int seg; 2268 ispcontreq_t local, *crq = &local, *qep; 2269 2270 qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 2271 curip = nxti; 2272 nxti = ISP_NXT_QENTRY(curip, RQUEST_QUEUE_LEN(isp)); 2273 if (nxti == mp->optr) { 2274 isp_prt(isp, ISP_LOGTDEBUG0, 2275 "tdma_mkfc: request queue overflow"); 2276 mp->error = MUSHERR_NOQENTRIES; 2277 return; 2278 } 2279 cto->ct_header.rqs_entry_count++; 2280 MEMZERO((void *)crq, sizeof (*crq)); 2281 crq->req_header.rqs_entry_count = 1; 2282 if (cto->ct_header.rqs_entry_type == RQSTYPE_CTIO3) { 2283 seglim = ISP_CDSEG64; 2284 ds = NULL; 2285 ds64 = &((ispcontreq64_t *)crq)->req_dataseg[0]; 2286 crq->req_header.rqs_entry_type = RQSTYPE_A64_CONT; 2287 } else { 2288 seglim = ISP_CDSEG; 2289 ds = &crq->req_dataseg[0]; 2290 ds64 = NULL; 2291 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 2292 } 2293 for (seg = 0; segcnt < nseg && seg < seglim; 2294 segcnt++, seg++) { 2295 if (ds64) { 2296 ds64->ds_basehi = 2297 ((uint64_t) (dm_segs[segcnt].ds_addr) >> 32); 2298 ds64->ds_base = dm_segs[segcnt].ds_addr; 2299 ds64->ds_count = dm_segs[segcnt].ds_len; 2300 ds64++; 2301 } else { 2302 ds->ds_base = dm_segs[segcnt].ds_addr; 2303 ds->ds_count = dm_segs[segcnt].ds_len; 2304 ds++; 2305 } 2306 #if __FreeBSD_version < 500000 2307 isp_prt(isp, ISP_LOGTDEBUG1, 2308 "isp_send_ctio2: ent%d[%d]%llx:%llu", 2309 cto->ct_header.rqs_entry_count-1, seg, 2310 (uint64_t)dm_segs[segcnt].ds_addr, 2311 (uint64_t)dm_segs[segcnt].ds_len); 2312 #else 2313 isp_prt(isp, ISP_LOGTDEBUG1, 2314 "isp_send_ctio2: ent%d[%d]%jx:%ju", 2315 cto->ct_header.rqs_entry_count-1, seg, 2316 (uintmax_t)dm_segs[segcnt].ds_addr, 2317 (uintmax_t)dm_segs[segcnt].ds_len); 2318 #endif 2319 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 2320 cto->ct_seg_count++; 2321 } 2322 MEMORYBARRIER(isp, SYNC_REQUEST, curip, QENTRY_LEN); 2323 isp_put_cont_req(isp, crq, qep); 2324 ISP_TDQE(isp, "cont entry", curi, qep); 2325 } 2326 2327 /* 2328 * No do final twiddling for the CTIO itself. 2329 */ 2330 cto->ct_header.rqs_seqno = 1; 2331 isp_prt(isp, ISP_LOGTDEBUG1, 2332 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x resid %d", 2333 cto->ct_rxid, csio->ccb_h.target_lun, (int) cto->ct_iid, 2334 cto->ct_flags, cto->ct_status, cto->rsp.m1.ct_scsi_status, 2335 cto->ct_resid); 2336 if (FCPARAM(isp)->isp_2klogin) { 2337 isp_put_ctio2e(isp, (ct2e_entry_t *)cto, (ct2e_entry_t *)qe); 2338 } else { 2339 isp_put_ctio2(isp, cto, qe); 2340 } 2341 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe); 2342 *mp->nxtip = nxti; 2343 } 2344 #endif 2345 2346 static void dma_2400(void *, bus_dma_segment_t *, int, int); 2347 static void dma2_a64(void *, bus_dma_segment_t *, int, int); 2348 static void dma2(void *, bus_dma_segment_t *, int, int); 2349 2350 static void 2351 dma_2400(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2352 { 2353 mush_t *mp; 2354 ispsoftc_t *isp; 2355 struct ccb_scsiio *csio; 2356 bus_dma_segment_t *eseg; 2357 ispreqt7_t *rq; 2358 int seglim, datalen; 2359 uint32_t nxti; 2360 2361 mp = (mush_t *) arg; 2362 if (error) { 2363 mp->error = error; 2364 return; 2365 } 2366 2367 if (nseg < 1) { 2368 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 2369 mp->error = EFAULT; 2370 return; 2371 } 2372 2373 csio = mp->cmd_token; 2374 isp = mp->isp; 2375 rq = mp->rq; 2376 nxti = *mp->nxtip; 2377 2378 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2379 bus_dmamap_sync(isp->isp_osinfo.dmat, 2380 PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 2381 } else { 2382 bus_dmamap_sync(isp->isp_osinfo.dmat, 2383 PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 2384 } 2385 datalen = XS_XFRLEN(csio); 2386 2387 /* 2388 * We're passed an initial partially filled in entry that 2389 * has most fields filled in except for data transfer 2390 * related values. 2391 * 2392 * Our job is to fill in the initial request queue entry and 2393 * then to start allocating and filling in continuation entries 2394 * until we've covered the entire transfer. 2395 */ 2396 2397 rq->req_header.rqs_entry_type = RQSTYPE_T7RQS; 2398 rq->req_dl = datalen; 2399 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2400 rq->req_alen_datadir = 0x2; 2401 } else { 2402 rq->req_alen_datadir = 0x1; 2403 } 2404 2405 eseg = dm_segs + nseg; 2406 2407 rq->req_dataseg.ds_base = DMA_LO32(dm_segs->ds_addr); 2408 rq->req_dataseg.ds_basehi = DMA_HI32(dm_segs->ds_addr); 2409 rq->req_dataseg.ds_count = dm_segs->ds_len; 2410 2411 datalen -= dm_segs->ds_len; 2412 2413 dm_segs++; 2414 rq->req_seg_count++; 2415 2416 while (datalen > 0 && dm_segs != eseg) { 2417 uint32_t onxti; 2418 ispcontreq64_t local, *crq = &local, *cqe; 2419 2420 cqe = (ispcontreq64_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 2421 onxti = nxti; 2422 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 2423 if (nxti == mp->optr) { 2424 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 2425 mp->error = MUSHERR_NOQENTRIES; 2426 return; 2427 } 2428 rq->req_header.rqs_entry_count++; 2429 MEMZERO((void *)crq, sizeof (*crq)); 2430 crq->req_header.rqs_entry_count = 1; 2431 crq->req_header.rqs_entry_type = RQSTYPE_A64_CONT; 2432 2433 seglim = 0; 2434 while (datalen > 0 && seglim < ISP_CDSEG64 && dm_segs != eseg) { 2435 crq->req_dataseg[seglim].ds_base = 2436 DMA_LO32(dm_segs->ds_addr); 2437 crq->req_dataseg[seglim].ds_basehi = 2438 DMA_HI32(dm_segs->ds_addr); 2439 crq->req_dataseg[seglim].ds_count = 2440 dm_segs->ds_len; 2441 rq->req_seg_count++; 2442 dm_segs++; 2443 seglim++; 2444 datalen -= dm_segs->ds_len; 2445 } 2446 if (isp->isp_dblev & ISP_LOGDEBUG1) { 2447 isp_print_bytes(isp, "Continuation", QENTRY_LEN, crq); 2448 } 2449 isp_put_cont64_req(isp, crq, cqe); 2450 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 2451 } 2452 *mp->nxtip = nxti; 2453 } 2454 2455 static void 2456 dma2_a64(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2457 { 2458 mush_t *mp; 2459 ispsoftc_t *isp; 2460 struct ccb_scsiio *csio; 2461 bus_dma_segment_t *eseg; 2462 ispreq64_t *rq; 2463 int seglim, datalen; 2464 uint32_t nxti; 2465 2466 mp = (mush_t *) arg; 2467 if (error) { 2468 mp->error = error; 2469 return; 2470 } 2471 2472 if (nseg < 1) { 2473 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 2474 mp->error = EFAULT; 2475 return; 2476 } 2477 csio = mp->cmd_token; 2478 isp = mp->isp; 2479 rq = mp->rq; 2480 nxti = *mp->nxtip; 2481 2482 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2483 bus_dmamap_sync(isp->isp_osinfo.dmat, 2484 PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 2485 } else { 2486 bus_dmamap_sync(isp->isp_osinfo.dmat, 2487 PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 2488 } 2489 datalen = XS_XFRLEN(csio); 2490 2491 /* 2492 * We're passed an initial partially filled in entry that 2493 * has most fields filled in except for data transfer 2494 * related values. 2495 * 2496 * Our job is to fill in the initial request queue entry and 2497 * then to start allocating and filling in continuation entries 2498 * until we've covered the entire transfer. 2499 */ 2500 2501 if (IS_FC(isp)) { 2502 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 2503 seglim = ISP_RQDSEG_T3; 2504 ((ispreqt3_t *)rq)->req_totalcnt = datalen; 2505 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2506 ((ispreqt3_t *)rq)->req_flags |= REQFLAG_DATA_IN; 2507 } else { 2508 ((ispreqt3_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 2509 } 2510 } else { 2511 rq->req_header.rqs_entry_type = RQSTYPE_A64; 2512 if (csio->cdb_len > 12) { 2513 seglim = 0; 2514 } else { 2515 seglim = ISP_RQDSEG_A64; 2516 } 2517 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2518 rq->req_flags |= REQFLAG_DATA_IN; 2519 } else { 2520 rq->req_flags |= REQFLAG_DATA_OUT; 2521 } 2522 } 2523 2524 eseg = dm_segs + nseg; 2525 2526 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 2527 if (IS_FC(isp)) { 2528 ispreqt3_t *rq3 = (ispreqt3_t *)rq; 2529 rq3->req_dataseg[rq3->req_seg_count].ds_base = 2530 DMA_LO32(dm_segs->ds_addr); 2531 rq3->req_dataseg[rq3->req_seg_count].ds_basehi = 2532 DMA_HI32(dm_segs->ds_addr); 2533 rq3->req_dataseg[rq3->req_seg_count].ds_count = 2534 dm_segs->ds_len; 2535 } else { 2536 rq->req_dataseg[rq->req_seg_count].ds_base = 2537 DMA_LO32(dm_segs->ds_addr); 2538 rq->req_dataseg[rq->req_seg_count].ds_basehi = 2539 DMA_HI32(dm_segs->ds_addr); 2540 rq->req_dataseg[rq->req_seg_count].ds_count = 2541 dm_segs->ds_len; 2542 } 2543 datalen -= dm_segs->ds_len; 2544 rq->req_seg_count++; 2545 dm_segs++; 2546 } 2547 2548 while (datalen > 0 && dm_segs != eseg) { 2549 uint32_t onxti; 2550 ispcontreq64_t local, *crq = &local, *cqe; 2551 2552 cqe = (ispcontreq64_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 2553 onxti = nxti; 2554 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 2555 if (nxti == mp->optr) { 2556 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 2557 mp->error = MUSHERR_NOQENTRIES; 2558 return; 2559 } 2560 rq->req_header.rqs_entry_count++; 2561 MEMZERO((void *)crq, sizeof (*crq)); 2562 crq->req_header.rqs_entry_count = 1; 2563 crq->req_header.rqs_entry_type = RQSTYPE_A64_CONT; 2564 2565 seglim = 0; 2566 while (datalen > 0 && seglim < ISP_CDSEG64 && dm_segs != eseg) { 2567 crq->req_dataseg[seglim].ds_base = 2568 DMA_LO32(dm_segs->ds_addr); 2569 crq->req_dataseg[seglim].ds_basehi = 2570 DMA_HI32(dm_segs->ds_addr); 2571 crq->req_dataseg[seglim].ds_count = 2572 dm_segs->ds_len; 2573 rq->req_seg_count++; 2574 dm_segs++; 2575 seglim++; 2576 datalen -= dm_segs->ds_len; 2577 } 2578 if (isp->isp_dblev & ISP_LOGDEBUG1) { 2579 isp_print_bytes(isp, "Continuation", QENTRY_LEN, crq); 2580 } 2581 isp_put_cont64_req(isp, crq, cqe); 2582 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 2583 } 2584 *mp->nxtip = nxti; 2585 } 2586 2587 static void 2588 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2589 { 2590 mush_t *mp; 2591 ispsoftc_t *isp; 2592 struct ccb_scsiio *csio; 2593 bus_dma_segment_t *eseg; 2594 ispreq_t *rq; 2595 int seglim, datalen; 2596 uint32_t nxti; 2597 2598 mp = (mush_t *) arg; 2599 if (error) { 2600 mp->error = error; 2601 return; 2602 } 2603 2604 if (nseg < 1) { 2605 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 2606 mp->error = EFAULT; 2607 return; 2608 } 2609 csio = mp->cmd_token; 2610 isp = mp->isp; 2611 rq = mp->rq; 2612 nxti = *mp->nxtip; 2613 2614 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2615 bus_dmamap_sync(isp->isp_osinfo.dmat, 2616 PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 2617 } else { 2618 bus_dmamap_sync(isp->isp_osinfo.dmat, 2619 PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 2620 } 2621 2622 datalen = XS_XFRLEN(csio); 2623 2624 /* 2625 * We're passed an initial partially filled in entry that 2626 * has most fields filled in except for data transfer 2627 * related values. 2628 * 2629 * Our job is to fill in the initial request queue entry and 2630 * then to start allocating and filling in continuation entries 2631 * until we've covered the entire transfer. 2632 */ 2633 2634 if (IS_FC(isp)) { 2635 seglim = ISP_RQDSEG_T2; 2636 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 2637 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2638 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 2639 } else { 2640 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 2641 } 2642 } else { 2643 if (csio->cdb_len > 12) { 2644 seglim = 0; 2645 } else { 2646 seglim = ISP_RQDSEG; 2647 } 2648 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2649 rq->req_flags |= REQFLAG_DATA_IN; 2650 } else { 2651 rq->req_flags |= REQFLAG_DATA_OUT; 2652 } 2653 } 2654 2655 eseg = dm_segs + nseg; 2656 2657 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 2658 if (IS_FC(isp)) { 2659 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 2660 rq2->req_dataseg[rq2->req_seg_count].ds_base = 2661 DMA_LO32(dm_segs->ds_addr); 2662 rq2->req_dataseg[rq2->req_seg_count].ds_count = 2663 dm_segs->ds_len; 2664 } else { 2665 rq->req_dataseg[rq->req_seg_count].ds_base = 2666 DMA_LO32(dm_segs->ds_addr); 2667 rq->req_dataseg[rq->req_seg_count].ds_count = 2668 dm_segs->ds_len; 2669 } 2670 datalen -= dm_segs->ds_len; 2671 rq->req_seg_count++; 2672 dm_segs++; 2673 } 2674 2675 while (datalen > 0 && dm_segs != eseg) { 2676 uint32_t onxti; 2677 ispcontreq_t local, *crq = &local, *cqe; 2678 2679 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 2680 onxti = nxti; 2681 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 2682 if (nxti == mp->optr) { 2683 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 2684 mp->error = MUSHERR_NOQENTRIES; 2685 return; 2686 } 2687 rq->req_header.rqs_entry_count++; 2688 MEMZERO((void *)crq, sizeof (*crq)); 2689 crq->req_header.rqs_entry_count = 1; 2690 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 2691 2692 seglim = 0; 2693 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 2694 crq->req_dataseg[seglim].ds_base = 2695 DMA_LO32(dm_segs->ds_addr); 2696 crq->req_dataseg[seglim].ds_count = 2697 dm_segs->ds_len; 2698 rq->req_seg_count++; 2699 dm_segs++; 2700 seglim++; 2701 datalen -= dm_segs->ds_len; 2702 } 2703 if (isp->isp_dblev & ISP_LOGDEBUG1) { 2704 isp_print_bytes(isp, "Continuation", QENTRY_LEN, crq); 2705 } 2706 isp_put_cont_req(isp, crq, cqe); 2707 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 2708 } 2709 *mp->nxtip = nxti; 2710 } 2711 2712 /* 2713 */ 2714 static int 2715 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, ispreq_t *rq, 2716 uint32_t *nxtip, uint32_t optr) 2717 { 2718 ispreq_t *qep; 2719 mush_t mush, *mp; 2720 void (*eptr)(void *, bus_dma_segment_t *, int, int); 2721 2722 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); 2723 #ifdef ISP_TARGET_MODE 2724 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 2725 if (IS_FC(isp)) { 2726 eptr = tdma_mkfc; 2727 } else { 2728 eptr = tdma_mk; 2729 } 2730 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 2731 (csio->dxfer_len == 0)) { 2732 mp = &mush; 2733 mp->isp = isp; 2734 mp->cmd_token = csio; 2735 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 2736 mp->nxtip = nxtip; 2737 mp->optr = optr; 2738 mp->error = 0; 2739 (*eptr)(mp, NULL, 0, 0); 2740 goto mbxsync; 2741 } 2742 } else 2743 #endif 2744 if (IS_24XX(isp)) { 2745 eptr = dma_2400; 2746 } else if (sizeof (bus_addr_t) > 4) { 2747 eptr = dma2_a64; 2748 } else { 2749 eptr = dma2; 2750 } 2751 2752 2753 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 2754 (csio->dxfer_len == 0)) { 2755 rq->req_seg_count = 1; 2756 goto mbxsync; 2757 } 2758 2759 /* 2760 * Do a virtual grapevine step to collect info for 2761 * the callback dma allocation that we have to use... 2762 */ 2763 mp = &mush; 2764 mp->isp = isp; 2765 mp->cmd_token = csio; 2766 mp->rq = rq; 2767 mp->nxtip = nxtip; 2768 mp->optr = optr; 2769 mp->error = 0; 2770 2771 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 2772 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 2773 int error; 2774 #if __FreeBSD_version < 500000 2775 int s = splsoftvm(); 2776 #endif 2777 error = bus_dmamap_load(isp->isp_osinfo.dmat, 2778 PISP_PCMD(csio)->dmap, csio->data_ptr, 2779 csio->dxfer_len, eptr, mp, 0); 2780 #if __FreeBSD_version < 500000 2781 splx(s); 2782 #endif 2783 if (error == EINPROGRESS) { 2784 bus_dmamap_unload(isp->isp_osinfo.dmat, 2785 PISP_PCMD(csio)->dmap); 2786 mp->error = EINVAL; 2787 isp_prt(isp, ISP_LOGERR, 2788 "deferred dma allocation not supported"); 2789 } else if (error && mp->error == 0) { 2790 #ifdef DIAGNOSTIC 2791 isp_prt(isp, ISP_LOGERR, 2792 "error %d in dma mapping code", error); 2793 #endif 2794 mp->error = error; 2795 } 2796 } else { 2797 /* Pointer to physical buffer */ 2798 struct bus_dma_segment seg; 2799 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 2800 seg.ds_len = csio->dxfer_len; 2801 (*eptr)(mp, &seg, 1, 0); 2802 } 2803 } else { 2804 struct bus_dma_segment *segs; 2805 2806 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 2807 isp_prt(isp, ISP_LOGERR, 2808 "Physical segment pointers unsupported"); 2809 mp->error = EINVAL; 2810 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 2811 isp_prt(isp, ISP_LOGERR, 2812 "Virtual segment addresses unsupported"); 2813 mp->error = EINVAL; 2814 } else { 2815 /* Just use the segments provided */ 2816 segs = (struct bus_dma_segment *) csio->data_ptr; 2817 (*eptr)(mp, segs, csio->sglist_cnt, 0); 2818 } 2819 } 2820 if (mp->error) { 2821 int retval = CMD_COMPLETE; 2822 if (mp->error == MUSHERR_NOQENTRIES) { 2823 retval = CMD_EAGAIN; 2824 } else if (mp->error == EFBIG) { 2825 XS_SETERR(csio, CAM_REQ_TOO_BIG); 2826 } else if (mp->error == EINVAL) { 2827 XS_SETERR(csio, CAM_REQ_INVALID); 2828 } else { 2829 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 2830 } 2831 return (retval); 2832 } 2833 mbxsync: 2834 if (isp->isp_dblev & ISP_LOGDEBUG1) { 2835 isp_print_bytes(isp, "Request Queue Entry", QENTRY_LEN, rq); 2836 } 2837 switch (rq->req_header.rqs_entry_type) { 2838 case RQSTYPE_REQUEST: 2839 isp_put_request(isp, rq, qep); 2840 break; 2841 case RQSTYPE_CMDONLY: 2842 isp_put_extended_request(isp, (ispextreq_t *)rq, 2843 (ispextreq_t *)qep); 2844 break; 2845 case RQSTYPE_T2RQS: 2846 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 2847 break; 2848 case RQSTYPE_A64: 2849 case RQSTYPE_T3RQS: 2850 isp_put_request_t3(isp, (ispreqt3_t *) rq, (ispreqt3_t *) qep); 2851 break; 2852 case RQSTYPE_T7RQS: 2853 isp_put_request_t7(isp, (ispreqt7_t *) rq, (ispreqt7_t *) qep); 2854 break; 2855 } 2856 return (CMD_QUEUED); 2857 } 2858 2859 static void 2860 isp_pci_reset0(ispsoftc_t *isp) 2861 { 2862 ISP_DISABLE_INTS(isp); 2863 } 2864 2865 static void 2866 isp_pci_reset1(ispsoftc_t *isp) 2867 { 2868 if (!IS_24XX(isp)) { 2869 /* Make sure the BIOS is disabled */ 2870 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 2871 } 2872 /* and enable interrupts */ 2873 ISP_ENABLE_INTS(isp); 2874 } 2875 2876 static void 2877 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 2878 { 2879 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 2880 if (msg) 2881 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 2882 else 2883 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 2884 if (IS_SCSI(isp)) 2885 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 2886 else 2887 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 2888 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 2889 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 2890 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 2891 2892 2893 if (IS_SCSI(isp)) { 2894 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 2895 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 2896 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 2897 ISP_READ(isp, CDMA_FIFO_STS)); 2898 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 2899 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 2900 ISP_READ(isp, DDMA_FIFO_STS)); 2901 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 2902 ISP_READ(isp, SXP_INTERRUPT), 2903 ISP_READ(isp, SXP_GROSS_ERR), 2904 ISP_READ(isp, SXP_PINS_CTRL)); 2905 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2906 } 2907 printf(" mbox regs: %x %x %x %x %x\n", 2908 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2909 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2910 ISP_READ(isp, OUTMAILBOX4)); 2911 printf(" PCI Status Command/Status=%x\n", 2912 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2913 } 2914