1 /*- 2 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 3 * FreeBSD Version. 4 * 5 * Copyright (c) 1997-2006 by Matthew Jacob 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #if __FreeBSD_version < 500000 40 #include <sys/bus.h> 41 #include <pci/pcireg.h> 42 #include <pci/pcivar.h> 43 #include <machine/bus_memio.h> 44 #include <machine/bus_pio.h> 45 #else 46 #include <sys/stdint.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #endif 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <sys/rman.h> 53 #include <sys/malloc.h> 54 55 #include <dev/isp/isp_freebsd.h> 56 57 #if __FreeBSD_version < 500000 58 #define BUS_PROBE_DEFAULT 0 59 #endif 60 61 static uint16_t isp_pci_rd_reg(ispsoftc_t *, int); 62 static void isp_pci_wr_reg(ispsoftc_t *, int, uint16_t); 63 static uint16_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 64 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint16_t); 65 static int 66 isp_pci_rd_isr(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *); 67 static int 68 isp_pci_rd_isr_2300(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *); 69 static int isp_pci_mbxdma(ispsoftc_t *); 70 static int 71 isp_pci_dmasetup(ispsoftc_t *, XS_T *, ispreq_t *, uint16_t *, uint16_t); 72 static void 73 isp_pci_dmateardown(ispsoftc_t *, XS_T *, uint16_t); 74 75 static void isp_pci_reset1(ispsoftc_t *); 76 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 77 78 static struct ispmdvec mdvec = { 79 isp_pci_rd_isr, 80 isp_pci_rd_reg, 81 isp_pci_wr_reg, 82 isp_pci_mbxdma, 83 isp_pci_dmasetup, 84 isp_pci_dmateardown, 85 NULL, 86 isp_pci_reset1, 87 isp_pci_dumpregs, 88 NULL, 89 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 90 }; 91 92 static struct ispmdvec mdvec_1080 = { 93 isp_pci_rd_isr, 94 isp_pci_rd_reg_1080, 95 isp_pci_wr_reg_1080, 96 isp_pci_mbxdma, 97 isp_pci_dmasetup, 98 isp_pci_dmateardown, 99 NULL, 100 isp_pci_reset1, 101 isp_pci_dumpregs, 102 NULL, 103 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 104 }; 105 106 static struct ispmdvec mdvec_12160 = { 107 isp_pci_rd_isr, 108 isp_pci_rd_reg_1080, 109 isp_pci_wr_reg_1080, 110 isp_pci_mbxdma, 111 isp_pci_dmasetup, 112 isp_pci_dmateardown, 113 NULL, 114 isp_pci_reset1, 115 isp_pci_dumpregs, 116 NULL, 117 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 118 }; 119 120 static struct ispmdvec mdvec_2100 = { 121 isp_pci_rd_isr, 122 isp_pci_rd_reg, 123 isp_pci_wr_reg, 124 isp_pci_mbxdma, 125 isp_pci_dmasetup, 126 isp_pci_dmateardown, 127 NULL, 128 isp_pci_reset1, 129 isp_pci_dumpregs 130 }; 131 132 static struct ispmdvec mdvec_2200 = { 133 isp_pci_rd_isr, 134 isp_pci_rd_reg, 135 isp_pci_wr_reg, 136 isp_pci_mbxdma, 137 isp_pci_dmasetup, 138 isp_pci_dmateardown, 139 NULL, 140 isp_pci_reset1, 141 isp_pci_dumpregs 142 }; 143 144 static struct ispmdvec mdvec_2300 = { 145 isp_pci_rd_isr_2300, 146 isp_pci_rd_reg, 147 isp_pci_wr_reg, 148 isp_pci_mbxdma, 149 isp_pci_dmasetup, 150 isp_pci_dmateardown, 151 NULL, 152 isp_pci_reset1, 153 isp_pci_dumpregs 154 }; 155 156 #ifndef PCIM_CMD_INVEN 157 #define PCIM_CMD_INVEN 0x10 158 #endif 159 #ifndef PCIM_CMD_BUSMASTEREN 160 #define PCIM_CMD_BUSMASTEREN 0x0004 161 #endif 162 #ifndef PCIM_CMD_PERRESPEN 163 #define PCIM_CMD_PERRESPEN 0x0040 164 #endif 165 #ifndef PCIM_CMD_SEREN 166 #define PCIM_CMD_SEREN 0x0100 167 #endif 168 #ifndef PCIM_CMD_INTX_DISABLE 169 #define PCIM_CMD_INTX_DISABLE 0x0400 170 #endif 171 172 #ifndef PCIR_COMMAND 173 #define PCIR_COMMAND 0x04 174 #endif 175 176 #ifndef PCIR_CACHELNSZ 177 #define PCIR_CACHELNSZ 0x0c 178 #endif 179 180 #ifndef PCIR_LATTIMER 181 #define PCIR_LATTIMER 0x0d 182 #endif 183 184 #ifndef PCIR_ROMADDR 185 #define PCIR_ROMADDR 0x30 186 #endif 187 188 #ifndef PCI_VENDOR_QLOGIC 189 #define PCI_VENDOR_QLOGIC 0x1077 190 #endif 191 192 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 193 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 194 #endif 195 196 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 197 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 198 #endif 199 200 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 201 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 202 #endif 203 204 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 205 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 206 #endif 207 208 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 209 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 210 #endif 211 212 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 213 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 214 #endif 215 216 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 217 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 218 #endif 219 220 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 221 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 222 #endif 223 224 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 225 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 226 #endif 227 228 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 229 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 230 #endif 231 232 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 233 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 234 #endif 235 236 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 237 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 238 #endif 239 240 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 241 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 242 #endif 243 244 #define PCI_QLOGIC_ISP1020 \ 245 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 246 247 #define PCI_QLOGIC_ISP1080 \ 248 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 249 250 #define PCI_QLOGIC_ISP10160 \ 251 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 252 253 #define PCI_QLOGIC_ISP12160 \ 254 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 255 256 #define PCI_QLOGIC_ISP1240 \ 257 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 258 259 #define PCI_QLOGIC_ISP1280 \ 260 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 261 262 #define PCI_QLOGIC_ISP2100 \ 263 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 264 265 #define PCI_QLOGIC_ISP2200 \ 266 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 267 268 #define PCI_QLOGIC_ISP2300 \ 269 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 270 271 #define PCI_QLOGIC_ISP2312 \ 272 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 273 274 #define PCI_QLOGIC_ISP2322 \ 275 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 276 277 #define PCI_QLOGIC_ISP2422 \ 278 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 279 280 #define PCI_QLOGIC_ISP6312 \ 281 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 282 283 /* 284 * Odd case for some AMI raid cards... We need to *not* attach to this. 285 */ 286 #define AMI_RAID_SUBVENDOR_ID 0x101e 287 288 #define IO_MAP_REG 0x10 289 #define MEM_MAP_REG 0x14 290 291 #define PCI_DFLT_LTNCY 0x40 292 #define PCI_DFLT_LNSZ 0x10 293 294 static int isp_pci_probe (device_t); 295 static int isp_pci_attach (device_t); 296 297 298 struct isp_pcisoftc { 299 ispsoftc_t pci_isp; 300 device_t pci_dev; 301 struct resource * pci_reg; 302 bus_space_tag_t pci_st; 303 bus_space_handle_t pci_sh; 304 void * ih; 305 int16_t pci_poff[_NREG_BLKS]; 306 bus_dma_tag_t dmat; 307 bus_dmamap_t *dmaps; 308 }; 309 extern ispfwfunc *isp_get_firmware_p; 310 311 static device_method_t isp_pci_methods[] = { 312 /* Device interface */ 313 DEVMETHOD(device_probe, isp_pci_probe), 314 DEVMETHOD(device_attach, isp_pci_attach), 315 { 0, 0 } 316 }; 317 static void isp_pci_intr(void *); 318 319 static driver_t isp_pci_driver = { 320 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 321 }; 322 static devclass_t isp_devclass; 323 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 324 325 static int 326 isp_pci_probe(device_t dev) 327 { 328 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 329 case PCI_QLOGIC_ISP1020: 330 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 331 break; 332 case PCI_QLOGIC_ISP1080: 333 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 334 break; 335 case PCI_QLOGIC_ISP1240: 336 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 337 break; 338 case PCI_QLOGIC_ISP1280: 339 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 340 break; 341 case PCI_QLOGIC_ISP10160: 342 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 343 break; 344 case PCI_QLOGIC_ISP12160: 345 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 346 return (ENXIO); 347 } 348 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 349 break; 350 case PCI_QLOGIC_ISP2100: 351 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 352 break; 353 case PCI_QLOGIC_ISP2200: 354 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 355 break; 356 case PCI_QLOGIC_ISP2300: 357 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 358 break; 359 case PCI_QLOGIC_ISP2312: 360 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 361 break; 362 case PCI_QLOGIC_ISP2322: 363 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 364 break; 365 case PCI_QLOGIC_ISP2422: 366 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 367 break; 368 case PCI_QLOGIC_ISP6312: 369 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 370 break; 371 default: 372 return (ENXIO); 373 } 374 if (isp_announced == 0 && bootverbose) { 375 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 376 "Core Version %d.%d\n", 377 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 378 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 379 isp_announced++; 380 } 381 /* 382 * XXXX: Here is where we might load the f/w module 383 * XXXX: (or increase a reference count to it). 384 */ 385 return (BUS_PROBE_DEFAULT); 386 } 387 388 #if __FreeBSD_version < 500000 389 static void 390 isp_get_options(device_t dev, ispsoftc_t *isp) 391 { 392 uint64_t wwn; 393 int bitmap, unit; 394 395 unit = device_get_unit(dev); 396 if (getenv_int("isp_disable", &bitmap)) { 397 if (bitmap & (1 << unit)) { 398 isp->isp_osinfo.disabled = 1; 399 return; 400 } 401 } 402 403 if (getenv_int("isp_no_fwload", &bitmap)) { 404 if (bitmap & (1 << unit)) 405 isp->isp_confopts |= ISP_CFG_NORELOAD; 406 } 407 if (getenv_int("isp_fwload", &bitmap)) { 408 if (bitmap & (1 << unit)) 409 isp->isp_confopts &= ~ISP_CFG_NORELOAD; 410 } 411 if (getenv_int("isp_no_nvram", &bitmap)) { 412 if (bitmap & (1 << unit)) 413 isp->isp_confopts |= ISP_CFG_NONVRAM; 414 } 415 if (getenv_int("isp_nvram", &bitmap)) { 416 if (bitmap & (1 << unit)) 417 isp->isp_confopts &= ~ISP_CFG_NONVRAM; 418 } 419 if (getenv_int("isp_fcduplex", &bitmap)) { 420 if (bitmap & (1 << unit)) 421 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 422 } 423 if (getenv_int("isp_no_fcduplex", &bitmap)) { 424 if (bitmap & (1 << unit)) 425 isp->isp_confopts &= ~ISP_CFG_FULL_DUPLEX; 426 } 427 if (getenv_int("isp_nport", &bitmap)) { 428 if (bitmap & (1 << unit)) 429 isp->isp_confopts |= ISP_CFG_NPORT; 430 } 431 432 /* 433 * Because the resource_*_value functions can neither return 434 * 64 bit integer values, nor can they be directly coerced 435 * to interpret the right hand side of the assignment as 436 * you want them to interpret it, we have to force WWN 437 * hint replacement to specify WWN strings with a leading 438 * 'w' (e..g w50000000aaaa0001). Sigh. 439 */ 440 if (getenv_quad("isp_portwwn", &wwn)) { 441 isp->isp_osinfo.default_port_wwn = wwn; 442 isp->isp_confopts |= ISP_CFG_OWNWWPN; 443 } 444 if (isp->isp_osinfo.default_port_wwn == 0) { 445 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 446 } 447 448 if (getenv_quad("isp_nodewwn", &wwn)) { 449 isp->isp_osinfo.default_node_wwn = wwn; 450 isp->isp_confopts |= ISP_CFG_OWNWWNN; 451 } 452 if (isp->isp_osinfo.default_node_wwn == 0) { 453 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 454 } 455 456 bitmap = 0; 457 (void) getenv_int("isp_debug", &bitmap); 458 if (bitmap) { 459 isp->isp_dblev = bitmap; 460 } else { 461 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 462 } 463 if (bootverbose) { 464 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 465 } 466 467 #ifdef ISP_FW_CRASH_DUMP 468 bitmap = 0; 469 if (getenv_int("isp_fw_dump_enable", &bitmap)) { 470 if (bitmap & (1 << unit) { 471 size_t amt = 0; 472 if (IS_2200(isp)) { 473 amt = QLA2200_RISC_IMAGE_DUMP_SIZE; 474 } else if (IS_23XX(isp)) { 475 amt = QLA2300_RISC_IMAGE_DUMP_SIZE; 476 } 477 if (amt) { 478 FCPARAM(isp)->isp_dump_data = 479 malloc(amt, M_DEVBUF, M_WAITOK); 480 memset(FCPARAM(isp)->isp_dump_data, 0, amt); 481 } else { 482 device_printf(dev, 483 "f/w crash dumps not supported for card\n"); 484 } 485 } 486 } 487 #endif 488 } 489 490 static void 491 isp_get_pci_options(device_t dev, int *m1, int *m2) 492 { 493 int bitmap; 494 int unit = device_get_unit(dev); 495 496 *m1 = PCIM_CMD_MEMEN; 497 *m2 = PCIM_CMD_PORTEN; 498 if (getenv_int("isp_mem_map", &bitmap)) { 499 if (bitmap & (1 << unit)) { 500 *m1 = PCIM_CMD_MEMEN; 501 *m2 = PCIM_CMD_PORTEN; 502 } 503 } 504 bitmap = 0; 505 if (getenv_int("isp_io_map", &bitmap)) { 506 if (bitmap & (1 << unit)) { 507 *m1 = PCIM_CMD_PORTEN; 508 *m2 = PCIM_CMD_MEMEN; 509 } 510 } 511 } 512 #else 513 static void 514 isp_get_options(device_t dev, ispsoftc_t *isp) 515 { 516 int tval; 517 const char *sptr; 518 /* 519 * Figure out if we're supposed to skip this one. 520 */ 521 522 tval = 0; 523 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 524 "disable", &tval) == 0 && tval) { 525 device_printf(dev, "disabled at user request\n"); 526 isp->isp_osinfo.disabled = 1; 527 return; 528 } 529 530 tval = -1; 531 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "role", &tval) == 0 && tval != -1) { 533 tval &= (ISP_ROLE_INITIATOR|ISP_ROLE_TARGET); 534 isp->isp_role = tval; 535 device_printf(dev, "setting role to 0x%x\n", isp->isp_role); 536 } else { 537 #ifdef ISP_TARGET_MODE 538 isp->isp_role = ISP_ROLE_TARGET; 539 #else 540 isp->isp_role = ISP_DEFAULT_ROLES; 541 #endif 542 } 543 544 tval = 0; 545 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 546 "fwload_disable", &tval) == 0 && tval != 0) { 547 isp->isp_confopts |= ISP_CFG_NORELOAD; 548 } 549 tval = 0; 550 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 551 "ignore_nvram", &tval) == 0 && tval != 0) { 552 isp->isp_confopts |= ISP_CFG_NONVRAM; 553 } 554 tval = 0; 555 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 556 "fullduplex", &tval) == 0 && tval != 0) { 557 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 558 } 559 #ifdef ISP_FW_CRASH_DUMP 560 tval = 0; 561 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 562 "fw_dump_enable", &tval) == 0 && tval != 0) { 563 size_t amt = 0; 564 if (IS_2200(isp)) { 565 amt = QLA2200_RISC_IMAGE_DUMP_SIZE; 566 } else if (IS_23XX(isp)) { 567 amt = QLA2300_RISC_IMAGE_DUMP_SIZE; 568 } 569 if (amt) { 570 FCPARAM(isp)->isp_dump_data = 571 malloc(amt, M_DEVBUF, M_WAITOK | M_ZERO); 572 } else { 573 device_printf(dev, 574 "f/w crash dumps not supported for this model\n"); 575 } 576 } 577 #endif 578 579 sptr = 0; 580 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 581 "topology", (const char **) &sptr) == 0 && sptr != 0) { 582 if (strcmp(sptr, "lport") == 0) { 583 isp->isp_confopts |= ISP_CFG_LPORT; 584 } else if (strcmp(sptr, "nport") == 0) { 585 isp->isp_confopts |= ISP_CFG_NPORT; 586 } else if (strcmp(sptr, "lport-only") == 0) { 587 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 588 } else if (strcmp(sptr, "nport-only") == 0) { 589 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 590 } 591 } 592 593 /* 594 * Because the resource_*_value functions can neither return 595 * 64 bit integer values, nor can they be directly coerced 596 * to interpret the right hand side of the assignment as 597 * you want them to interpret it, we have to force WWN 598 * hint replacement to specify WWN strings with a leading 599 * 'w' (e..g w50000000aaaa0001). Sigh. 600 */ 601 sptr = 0; 602 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 603 "portwwn", (const char **) &sptr); 604 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 605 char *eptr = 0; 606 isp->isp_osinfo.default_port_wwn = strtouq(sptr, &eptr, 16); 607 if (eptr < sptr + 16 || isp->isp_osinfo.default_port_wwn == 0) { 608 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 609 isp->isp_osinfo.default_port_wwn = 0; 610 } else { 611 isp->isp_confopts |= ISP_CFG_OWNWWPN; 612 } 613 } 614 if (isp->isp_osinfo.default_port_wwn == 0) { 615 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 616 } 617 618 sptr = 0; 619 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 620 "nodewwn", (const char **) &sptr); 621 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 622 char *eptr = 0; 623 isp->isp_osinfo.default_node_wwn = strtouq(sptr, &eptr, 16); 624 if (eptr < sptr + 16 || isp->isp_osinfo.default_node_wwn == 0) { 625 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 626 isp->isp_osinfo.default_node_wwn = 0; 627 } else { 628 isp->isp_confopts |= ISP_CFG_OWNWWNN; 629 } 630 } 631 if (isp->isp_osinfo.default_node_wwn == 0) { 632 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 633 } 634 635 isp->isp_osinfo.default_id = -1; 636 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 637 "iid", &tval) == 0) { 638 isp->isp_osinfo.default_id = tval; 639 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 640 } 641 if (isp->isp_osinfo.default_id == -1) { 642 if (IS_FC(isp)) { 643 isp->isp_osinfo.default_id = 109; 644 } else { 645 isp->isp_osinfo.default_id = 7; 646 } 647 } 648 649 /* 650 * Set up logging levels. 651 */ 652 tval = 0; 653 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 654 "debug", &tval); 655 if (tval) { 656 isp->isp_dblev = tval; 657 } else { 658 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 659 } 660 if (bootverbose) { 661 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 662 } 663 664 } 665 666 static void 667 isp_get_pci_options(device_t dev, int *m1, int *m2) 668 { 669 int tval; 670 /* 671 * Which we should try first - memory mapping or i/o mapping? 672 * 673 * We used to try memory first followed by i/o on alpha, otherwise 674 * the reverse, but we should just try memory first all the time now. 675 */ 676 *m1 = PCIM_CMD_MEMEN; 677 *m2 = PCIM_CMD_PORTEN; 678 679 tval = 0; 680 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 681 "prefer_iomap", &tval) == 0 && tval != 0) { 682 *m1 = PCIM_CMD_PORTEN; 683 *m2 = PCIM_CMD_MEMEN; 684 } 685 tval = 0; 686 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 687 "prefer_memmap", &tval) == 0 && tval != 0) { 688 *m1 = PCIM_CMD_MEMEN; 689 *m2 = PCIM_CMD_PORTEN; 690 } 691 } 692 #endif 693 694 static int 695 isp_pci_attach(device_t dev) 696 { 697 struct resource *regs, *irq; 698 int rtp, rgd, iqd, m1, m2; 699 uint32_t data, cmd, linesz, psize, basetype; 700 struct isp_pcisoftc *pcs; 701 ispsoftc_t *isp = NULL; 702 struct ispmdvec *mdvp; 703 #if __FreeBSD_version >= 500000 704 int locksetup = 0; 705 #endif 706 707 pcs = device_get_softc(dev); 708 if (pcs == NULL) { 709 device_printf(dev, "cannot get softc\n"); 710 return (ENOMEM); 711 } 712 memset(pcs, 0, sizeof (*pcs)); 713 pcs->pci_dev = dev; 714 isp = &pcs->pci_isp; 715 716 /* 717 * Get Generic Options 718 */ 719 isp_get_options(dev, isp); 720 721 /* 722 * Check to see if options have us disabled 723 */ 724 if (isp->isp_osinfo.disabled) { 725 /* 726 * But return zero to preserve unit numbering 727 */ 728 return (0); 729 } 730 731 /* 732 * Get PCI options- which in this case are just mapping preferences. 733 */ 734 isp_get_pci_options(dev, &m1, &m2); 735 736 737 linesz = PCI_DFLT_LNSZ; 738 irq = regs = NULL; 739 rgd = rtp = iqd = 0; 740 741 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 742 if (cmd & m1) { 743 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 744 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 745 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 746 } 747 if (regs == NULL && (cmd & m2)) { 748 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 749 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 750 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 751 } 752 if (regs == NULL) { 753 device_printf(dev, "unable to map any ports\n"); 754 goto bad; 755 } 756 if (bootverbose) { 757 device_printf(dev, "using %s space register mapping\n", 758 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 759 } 760 pcs->pci_dev = dev; 761 pcs->pci_reg = regs; 762 pcs->pci_st = rman_get_bustag(regs); 763 pcs->pci_sh = rman_get_bushandle(regs); 764 765 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 766 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 767 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 768 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 769 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 770 mdvp = &mdvec; 771 basetype = ISP_HA_SCSI_UNKNOWN; 772 psize = sizeof (sdparam); 773 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 774 mdvp = &mdvec; 775 basetype = ISP_HA_SCSI_UNKNOWN; 776 psize = sizeof (sdparam); 777 } 778 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 779 mdvp = &mdvec_1080; 780 basetype = ISP_HA_SCSI_1080; 781 psize = sizeof (sdparam); 782 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 783 ISP1080_DMA_REGS_OFF; 784 } 785 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 786 mdvp = &mdvec_1080; 787 basetype = ISP_HA_SCSI_1240; 788 psize = 2 * sizeof (sdparam); 789 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 790 ISP1080_DMA_REGS_OFF; 791 } 792 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 793 mdvp = &mdvec_1080; 794 basetype = ISP_HA_SCSI_1280; 795 psize = 2 * sizeof (sdparam); 796 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 797 ISP1080_DMA_REGS_OFF; 798 } 799 if (pci_get_devid(dev) == PCI_QLOGIC_ISP10160) { 800 mdvp = &mdvec_12160; 801 basetype = ISP_HA_SCSI_10160; 802 psize = sizeof (sdparam); 803 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 804 ISP1080_DMA_REGS_OFF; 805 } 806 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 807 mdvp = &mdvec_12160; 808 basetype = ISP_HA_SCSI_12160; 809 psize = 2 * sizeof (sdparam); 810 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 811 ISP1080_DMA_REGS_OFF; 812 } 813 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 814 mdvp = &mdvec_2100; 815 basetype = ISP_HA_FC_2100; 816 psize = sizeof (fcparam); 817 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 818 PCI_MBOX_REGS2100_OFF; 819 if (pci_get_revid(dev) < 3) { 820 /* 821 * XXX: Need to get the actual revision 822 * XXX: number of the 2100 FB. At any rate, 823 * XXX: lower cache line size for early revision 824 * XXX; boards. 825 */ 826 linesz = 1; 827 } 828 } 829 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 830 mdvp = &mdvec_2200; 831 basetype = ISP_HA_FC_2200; 832 psize = sizeof (fcparam); 833 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 834 PCI_MBOX_REGS2100_OFF; 835 } 836 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2300) { 837 mdvp = &mdvec_2300; 838 basetype = ISP_HA_FC_2300; 839 psize = sizeof (fcparam); 840 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 841 PCI_MBOX_REGS2300_OFF; 842 } 843 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2312 || 844 pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 845 mdvp = &mdvec_2300; 846 basetype = ISP_HA_FC_2312; 847 psize = sizeof (fcparam); 848 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 849 PCI_MBOX_REGS2300_OFF; 850 } 851 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2322) { 852 mdvp = &mdvec_2300; 853 basetype = ISP_HA_FC_2322; 854 psize = sizeof (fcparam); 855 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 856 PCI_MBOX_REGS2300_OFF; 857 } 858 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2422) { 859 mdvp = &mdvec_2300; 860 basetype = ISP_HA_FC_2422; 861 psize = sizeof (fcparam); 862 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 863 PCI_MBOX_REGS2300_OFF; 864 } 865 isp = &pcs->pci_isp; 866 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 867 if (isp->isp_param == NULL) { 868 device_printf(dev, "cannot allocate parameter data\n"); 869 goto bad; 870 } 871 isp->isp_mdvec = mdvp; 872 isp->isp_type = basetype; 873 isp->isp_revision = pci_get_revid(dev); 874 isp->isp_dev = dev; 875 876 /* 877 * Try and find firmware for this device. 878 */ 879 880 if (isp_get_firmware_p) { 881 int device = (int) pci_get_device(dev); 882 #ifdef ISP_TARGET_MODE 883 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 884 #else 885 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 886 #endif 887 } 888 889 /* 890 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 891 * are set. 892 */ 893 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 894 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 895 if (IS_2300(isp)) { /* per QLogic errata */ 896 cmd &= ~PCIM_CMD_INVEN; 897 } 898 if (IS_23XX(isp)) { 899 /* 900 * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command. 901 */ 902 isp->isp_touched = 1; 903 904 } 905 906 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 907 cmd &= ~PCIM_CMD_INTX_DISABLE; 908 } 909 910 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 911 912 /* 913 * Make sure the Cache Line Size register is set sensibly. 914 */ 915 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 916 if (data != linesz) { 917 data = PCI_DFLT_LNSZ; 918 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 919 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 920 } 921 922 /* 923 * Make sure the Latency Timer is sane. 924 */ 925 data = pci_read_config(dev, PCIR_LATTIMER, 1); 926 if (data < PCI_DFLT_LTNCY) { 927 data = PCI_DFLT_LTNCY; 928 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 929 pci_write_config(dev, PCIR_LATTIMER, data, 1); 930 } 931 932 /* 933 * Make sure we've disabled the ROM. 934 */ 935 data = pci_read_config(dev, PCIR_ROMADDR, 4); 936 data &= ~1; 937 pci_write_config(dev, PCIR_ROMADDR, data, 4); 938 939 iqd = 0; 940 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd, 941 RF_ACTIVE | RF_SHAREABLE); 942 if (irq == NULL) { 943 device_printf(dev, "could not allocate interrupt\n"); 944 goto bad; 945 } 946 947 #if __FreeBSD_version >= 500000 948 /* Make sure the lock is set up. */ 949 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 950 locksetup++; 951 #endif 952 953 if (bus_setup_intr(dev, irq, ISP_IFLAGS, isp_pci_intr, isp, &pcs->ih)) { 954 device_printf(dev, "could not setup interrupt\n"); 955 goto bad; 956 } 957 958 /* 959 * Last minute checks... 960 */ 961 if (IS_23XX(isp)) { 962 isp->isp_port = pci_get_function(dev); 963 } 964 965 /* 966 * Make sure we're in reset state. 967 */ 968 ISP_LOCK(isp); 969 isp_reset(isp); 970 if (isp->isp_state != ISP_RESETSTATE) { 971 ISP_UNLOCK(isp); 972 goto bad; 973 } 974 isp_init(isp); 975 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_INITSTATE) { 976 isp_uninit(isp); 977 ISP_UNLOCK(isp); 978 goto bad; 979 } 980 isp_attach(isp); 981 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_RUNSTATE) { 982 isp_uninit(isp); 983 ISP_UNLOCK(isp); 984 goto bad; 985 } 986 /* 987 * XXXX: Here is where we might unload the f/w module 988 * XXXX: (or decrease the reference count to it). 989 */ 990 ISP_UNLOCK(isp); 991 return (0); 992 993 bad: 994 995 if (pcs && pcs->ih) { 996 (void) bus_teardown_intr(dev, irq, pcs->ih); 997 } 998 999 #if __FreeBSD_version >= 500000 1000 if (locksetup && isp) { 1001 mtx_destroy(&isp->isp_osinfo.lock); 1002 } 1003 #endif 1004 1005 if (irq) { 1006 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 1007 } 1008 1009 1010 if (regs) { 1011 (void) bus_release_resource(dev, rtp, rgd, regs); 1012 } 1013 1014 if (pcs) { 1015 if (pcs->pci_isp.isp_param) { 1016 #ifdef ISP_FW_CRASH_DUMP 1017 if (IS_FC(isp) && FCPARAM(isp)->isp_dump_data) { 1018 free(FCPARAM(isp)->isp_dump_data, M_DEVBUF); 1019 } 1020 #endif 1021 free(pcs->pci_isp.isp_param, M_DEVBUF); 1022 } 1023 } 1024 1025 /* 1026 * XXXX: Here is where we might unload the f/w module 1027 * XXXX: (or decrease the reference count to it). 1028 */ 1029 return (ENXIO); 1030 } 1031 1032 static void 1033 isp_pci_intr(void *arg) 1034 { 1035 ispsoftc_t *isp = arg; 1036 uint16_t isr, sema, mbox; 1037 1038 ISP_LOCK(isp); 1039 isp->isp_intcnt++; 1040 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1041 isp->isp_intbogus++; 1042 } else { 1043 int iok = isp->isp_osinfo.intsok; 1044 isp->isp_osinfo.intsok = 0; 1045 isp_intr(isp, isr, sema, mbox); 1046 isp->isp_osinfo.intsok = iok; 1047 } 1048 ISP_UNLOCK(isp); 1049 } 1050 1051 1052 #define IspVirt2Off(a, x) \ 1053 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1054 _BLK_REG_SHFT] + ((x) & 0xff)) 1055 1056 #define BXR2(pcs, off) \ 1057 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 1058 #define BXW2(pcs, off, v) \ 1059 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 1060 1061 1062 static __inline int 1063 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1064 { 1065 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1066 uint16_t val0, val1; 1067 int i = 0; 1068 1069 do { 1070 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 1071 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 1072 } while (val0 != val1 && ++i < 1000); 1073 if (val0 != val1) { 1074 return (1); 1075 } 1076 *rp = val0; 1077 return (0); 1078 } 1079 1080 static int 1081 isp_pci_rd_isr(ispsoftc_t *isp, uint16_t *isrp, 1082 uint16_t *semap, uint16_t *mbp) 1083 { 1084 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1085 uint16_t isr, sema; 1086 1087 if (IS_2100(isp)) { 1088 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1089 return (0); 1090 } 1091 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1092 return (0); 1093 } 1094 } else { 1095 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 1096 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 1097 } 1098 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1099 isr &= INT_PENDING_MASK(isp); 1100 sema &= BIU_SEMA_LOCK; 1101 if (isr == 0 && sema == 0) { 1102 return (0); 1103 } 1104 *isrp = isr; 1105 if ((*semap = sema) != 0) { 1106 if (IS_2100(isp)) { 1107 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1108 return (0); 1109 } 1110 } else { 1111 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 1112 } 1113 } 1114 return (1); 1115 } 1116 1117 static int 1118 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint16_t *isrp, 1119 uint16_t *semap, uint16_t *mbox0p) 1120 { 1121 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1122 uint16_t hccr; 1123 uint32_t r2hisr; 1124 1125 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1126 *isrp = 0; 1127 return (0); 1128 } 1129 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 1130 IspVirt2Off(pcs, BIU_R2HSTSLO)); 1131 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1132 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1133 *isrp = 0; 1134 return (0); 1135 } 1136 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1137 case ISPR2HST_ROM_MBX_OK: 1138 case ISPR2HST_ROM_MBX_FAIL: 1139 case ISPR2HST_MBX_OK: 1140 case ISPR2HST_MBX_FAIL: 1141 case ISPR2HST_ASYNC_EVENT: 1142 *isrp = r2hisr & 0xffff; 1143 *mbox0p = (r2hisr >> 16); 1144 *semap = 1; 1145 return (1); 1146 case ISPR2HST_RIO_16: 1147 *isrp = r2hisr & 0xffff; 1148 *mbox0p = ASYNC_RIO1; 1149 *semap = 1; 1150 return (1); 1151 case ISPR2HST_FPOST: 1152 *isrp = r2hisr & 0xffff; 1153 *mbox0p = ASYNC_CMD_CMPLT; 1154 *semap = 1; 1155 return (1); 1156 case ISPR2HST_FPOST_CTIO: 1157 *isrp = r2hisr & 0xffff; 1158 *mbox0p = ASYNC_CTIO_DONE; 1159 *semap = 1; 1160 return (1); 1161 case ISPR2HST_RSPQ_UPDATE: 1162 *isrp = r2hisr & 0xffff; 1163 *mbox0p = 0; 1164 *semap = 0; 1165 return (1); 1166 default: 1167 hccr = ISP_READ(isp, HCCR); 1168 if (hccr & HCCR_PAUSE) { 1169 ISP_WRITE(isp, HCCR, HCCR_RESET); 1170 isp_prt(isp, ISP_LOGERR, 1171 "RISC paused at interrupt (%x->%x\n", hccr, 1172 ISP_READ(isp, HCCR)); 1173 } else { 1174 isp_prt(isp, ISP_LOGERR, "unknown interrerupt 0x%x\n", 1175 r2hisr); 1176 } 1177 return (0); 1178 } 1179 } 1180 1181 static uint16_t 1182 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1183 { 1184 uint16_t rv; 1185 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1186 int oldconf = 0; 1187 1188 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1189 /* 1190 * We will assume that someone has paused the RISC processor. 1191 */ 1192 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1193 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1194 oldconf | BIU_PCI_CONF1_SXP); 1195 } 1196 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1197 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1198 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1199 } 1200 return (rv); 1201 } 1202 1203 static void 1204 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint16_t val) 1205 { 1206 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1207 int oldconf = 0; 1208 1209 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1210 /* 1211 * We will assume that someone has paused the RISC processor. 1212 */ 1213 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1214 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1215 oldconf | BIU_PCI_CONF1_SXP); 1216 } 1217 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1218 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1219 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1220 } 1221 } 1222 1223 static uint16_t 1224 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1225 { 1226 uint16_t rv, oc = 0; 1227 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1228 1229 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1230 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1231 uint16_t tc; 1232 /* 1233 * We will assume that someone has paused the RISC processor. 1234 */ 1235 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1236 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1237 if (regoff & SXP_BANK1_SELECT) 1238 tc |= BIU_PCI1080_CONF1_SXP1; 1239 else 1240 tc |= BIU_PCI1080_CONF1_SXP0; 1241 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1242 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1243 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1244 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1245 oc | BIU_PCI1080_CONF1_DMA); 1246 } 1247 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1248 if (oc) { 1249 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1250 } 1251 return (rv); 1252 } 1253 1254 static void 1255 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint16_t val) 1256 { 1257 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1258 int oc = 0; 1259 1260 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1261 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1262 uint16_t tc; 1263 /* 1264 * We will assume that someone has paused the RISC processor. 1265 */ 1266 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1267 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1268 if (regoff & SXP_BANK1_SELECT) 1269 tc |= BIU_PCI1080_CONF1_SXP1; 1270 else 1271 tc |= BIU_PCI1080_CONF1_SXP0; 1272 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1273 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1274 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1275 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1276 oc | BIU_PCI1080_CONF1_DMA); 1277 } 1278 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1279 if (oc) { 1280 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1281 } 1282 } 1283 1284 1285 struct imush { 1286 ispsoftc_t *isp; 1287 int error; 1288 }; 1289 1290 static void imc(void *, bus_dma_segment_t *, int, int); 1291 1292 static void 1293 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1294 { 1295 struct imush *imushp = (struct imush *) arg; 1296 if (error) { 1297 imushp->error = error; 1298 } else { 1299 ispsoftc_t *isp =imushp->isp; 1300 bus_addr_t addr = segs->ds_addr; 1301 1302 isp->isp_rquest_dma = addr; 1303 addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1304 isp->isp_result_dma = addr; 1305 if (IS_FC(isp)) { 1306 addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1307 FCPARAM(isp)->isp_scdma = addr; 1308 } 1309 } 1310 } 1311 1312 /* 1313 * Should be BUS_SPACE_MAXSIZE, but MAXPHYS is larger than BUS_SPACE_MAXSIZE 1314 */ 1315 #define ISP_NSEGS ((MAXPHYS / PAGE_SIZE) + 1) 1316 1317 #if __FreeBSD_version < 500000 1318 #define isp_dma_tag_create bus_dma_tag_create 1319 #else 1320 #define isp_dma_tag_create(a, b, c, d, e, f, g, h, i, j, k, z) \ 1321 bus_dma_tag_create(a, b, c, d, e, f, g, h, i, j, k, \ 1322 busdma_lock_mutex, &Giant, z) 1323 #endif 1324 1325 static int 1326 isp_pci_mbxdma(ispsoftc_t *isp) 1327 { 1328 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1329 caddr_t base; 1330 uint32_t len; 1331 int i, error, ns; 1332 bus_size_t slim; /* segment size */ 1333 bus_addr_t llim; /* low limit of unavailable dma */ 1334 bus_addr_t hlim; /* high limit of unavailable dma */ 1335 struct imush im; 1336 1337 /* 1338 * Already been here? If so, leave... 1339 */ 1340 if (isp->isp_rquest) { 1341 return (0); 1342 } 1343 1344 hlim = BUS_SPACE_MAXADDR; 1345 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1346 slim = (bus_size_t) (1ULL << 32); 1347 llim = BUS_SPACE_MAXADDR; 1348 } else { 1349 llim = BUS_SPACE_MAXADDR_32BIT; 1350 slim = (1 << 24); 1351 } 1352 1353 /* 1354 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1355 */ 1356 #ifdef ISP_TARGET_MODE 1357 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1358 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1359 return (1); 1360 } 1361 #endif 1362 1363 ISP_UNLOCK(isp); 1364 if (isp_dma_tag_create(NULL, 1, slim, llim, hlim, 1365 NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &pcs->dmat)) { 1366 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1367 ISP_LOCK(isp); 1368 return (1); 1369 } 1370 1371 1372 len = sizeof (XS_T **) * isp->isp_maxcmds; 1373 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1374 if (isp->isp_xflist == NULL) { 1375 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1376 ISP_LOCK(isp); 1377 return (1); 1378 } 1379 #ifdef ISP_TARGET_MODE 1380 len = sizeof (void **) * isp->isp_maxcmds; 1381 isp->isp_tgtlist = (void **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1382 if (isp->isp_tgtlist == NULL) { 1383 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1384 ISP_LOCK(isp); 1385 return (1); 1386 } 1387 #endif 1388 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 1389 pcs->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1390 if (pcs->dmaps == NULL) { 1391 isp_prt(isp, ISP_LOGERR, "can't alloc dma map storage"); 1392 free(isp->isp_xflist, M_DEVBUF); 1393 #ifdef ISP_TARGET_MODE 1394 free(isp->isp_tgtlist, M_DEVBUF); 1395 #endif 1396 ISP_LOCK(isp); 1397 return (1); 1398 } 1399 1400 /* 1401 * Allocate and map the request, result queues, plus FC scratch area. 1402 */ 1403 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1404 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1405 if (IS_FC(isp)) { 1406 len += ISP2100_SCRLEN; 1407 } 1408 1409 ns = (len / PAGE_SIZE) + 1; 1410 /* 1411 * Create a tag for the control spaces- force it to within 32 bits. 1412 */ 1413 if (isp_dma_tag_create(pcs->dmat, QENTRY_LEN, slim, 1414 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1415 NULL, NULL, len, ns, slim, 0, &isp->isp_cdmat)) { 1416 isp_prt(isp, ISP_LOGERR, 1417 "cannot create a dma tag for control spaces"); 1418 free(pcs->dmaps, M_DEVBUF); 1419 free(isp->isp_xflist, M_DEVBUF); 1420 #ifdef ISP_TARGET_MODE 1421 free(isp->isp_tgtlist, M_DEVBUF); 1422 #endif 1423 ISP_LOCK(isp); 1424 return (1); 1425 } 1426 1427 if (bus_dmamem_alloc(isp->isp_cdmat, (void **)&base, BUS_DMA_NOWAIT, 1428 &isp->isp_cdmap) != 0) { 1429 isp_prt(isp, ISP_LOGERR, 1430 "cannot allocate %d bytes of CCB memory", len); 1431 bus_dma_tag_destroy(isp->isp_cdmat); 1432 free(isp->isp_xflist, M_DEVBUF); 1433 #ifdef ISP_TARGET_MODE 1434 free(isp->isp_tgtlist, M_DEVBUF); 1435 #endif 1436 free(pcs->dmaps, M_DEVBUF); 1437 ISP_LOCK(isp); 1438 return (1); 1439 } 1440 1441 for (i = 0; i < isp->isp_maxcmds; i++) { 1442 error = bus_dmamap_create(pcs->dmat, 0, &pcs->dmaps[i]); 1443 if (error) { 1444 isp_prt(isp, ISP_LOGERR, 1445 "error %d creating per-cmd DMA maps", error); 1446 while (--i >= 0) { 1447 bus_dmamap_destroy(pcs->dmat, pcs->dmaps[i]); 1448 } 1449 goto bad; 1450 } 1451 } 1452 1453 im.isp = isp; 1454 im.error = 0; 1455 bus_dmamap_load(isp->isp_cdmat, isp->isp_cdmap, base, len, imc, &im, 0); 1456 if (im.error) { 1457 isp_prt(isp, ISP_LOGERR, 1458 "error %d loading dma map for control areas", im.error); 1459 goto bad; 1460 } 1461 1462 isp->isp_rquest = base; 1463 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1464 isp->isp_result = base; 1465 if (IS_FC(isp)) { 1466 base += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1467 FCPARAM(isp)->isp_scratch = base; 1468 } 1469 ISP_LOCK(isp); 1470 return (0); 1471 1472 bad: 1473 bus_dmamem_free(isp->isp_cdmat, base, isp->isp_cdmap); 1474 bus_dma_tag_destroy(isp->isp_cdmat); 1475 free(isp->isp_xflist, M_DEVBUF); 1476 #ifdef ISP_TARGET_MODE 1477 free(isp->isp_tgtlist, M_DEVBUF); 1478 #endif 1479 free(pcs->dmaps, M_DEVBUF); 1480 ISP_LOCK(isp); 1481 isp->isp_rquest = NULL; 1482 return (1); 1483 } 1484 1485 typedef struct { 1486 ispsoftc_t *isp; 1487 void *cmd_token; 1488 void *rq; 1489 uint16_t *nxtip; 1490 uint16_t optr; 1491 int error; 1492 } mush_t; 1493 1494 #define MUSHERR_NOQENTRIES -2 1495 1496 #ifdef ISP_TARGET_MODE 1497 /* 1498 * We need to handle DMA for target mode differently from initiator mode. 1499 * 1500 * DMA mapping and construction and submission of CTIO Request Entries 1501 * and rendevous for completion are very tightly coupled because we start 1502 * out by knowing (per platform) how much data we have to move, but we 1503 * don't know, up front, how many DMA mapping segments will have to be used 1504 * cover that data, so we don't know how many CTIO Request Entries we 1505 * will end up using. Further, for performance reasons we may want to 1506 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1507 * 1508 * The standard vector still goes through isp_pci_dmasetup, but the callback 1509 * for the DMA mapping routines comes here instead with the whole transfer 1510 * mapped and a pointer to a partially filled in already allocated request 1511 * queue entry. We finish the job. 1512 */ 1513 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1514 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1515 1516 #define STATUS_WITH_DATA 1 1517 1518 static void 1519 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1520 { 1521 mush_t *mp; 1522 struct ccb_scsiio *csio; 1523 ispsoftc_t *isp; 1524 struct isp_pcisoftc *pcs; 1525 bus_dmamap_t *dp; 1526 ct_entry_t *cto, *qe; 1527 uint8_t scsi_status; 1528 uint16_t curi, nxti, handle; 1529 uint32_t sflags; 1530 int32_t resid; 1531 int nth_ctio, nctios, send_status; 1532 1533 mp = (mush_t *) arg; 1534 if (error) { 1535 mp->error = error; 1536 return; 1537 } 1538 1539 isp = mp->isp; 1540 csio = mp->cmd_token; 1541 cto = mp->rq; 1542 curi = isp->isp_reqidx; 1543 qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1544 1545 cto->ct_xfrlen = 0; 1546 cto->ct_seg_count = 0; 1547 cto->ct_header.rqs_entry_count = 1; 1548 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1549 1550 if (nseg == 0) { 1551 cto->ct_header.rqs_seqno = 1; 1552 isp_prt(isp, ISP_LOGTDEBUG1, 1553 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1554 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1555 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1556 cto->ct_scsi_status, cto->ct_resid); 1557 ISP_TDQE(isp, "tdma_mk[no data]", curi, cto); 1558 isp_put_ctio(isp, cto, qe); 1559 return; 1560 } 1561 1562 nctios = nseg / ISP_RQDSEG; 1563 if (nseg % ISP_RQDSEG) { 1564 nctios++; 1565 } 1566 1567 /* 1568 * Save syshandle, and potentially any SCSI status, which we'll 1569 * reinsert on the last CTIO we're going to send. 1570 */ 1571 1572 handle = cto->ct_syshandle; 1573 cto->ct_syshandle = 0; 1574 cto->ct_header.rqs_seqno = 0; 1575 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1576 1577 if (send_status) { 1578 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1579 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1580 /* 1581 * Preserve residual. 1582 */ 1583 resid = cto->ct_resid; 1584 1585 /* 1586 * Save actual SCSI status. 1587 */ 1588 scsi_status = cto->ct_scsi_status; 1589 1590 #ifndef STATUS_WITH_DATA 1591 sflags |= CT_NO_DATA; 1592 /* 1593 * We can't do a status at the same time as a data CTIO, so 1594 * we need to synthesize an extra CTIO at this level. 1595 */ 1596 nctios++; 1597 #endif 1598 } else { 1599 sflags = scsi_status = resid = 0; 1600 } 1601 1602 cto->ct_resid = 0; 1603 cto->ct_scsi_status = 0; 1604 1605 pcs = (struct isp_pcisoftc *)isp; 1606 dp = &pcs->dmaps[isp_handle_index(handle)]; 1607 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1608 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1609 } else { 1610 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1611 } 1612 1613 nxti = *mp->nxtip; 1614 1615 for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { 1616 int seglim; 1617 1618 seglim = nseg; 1619 if (seglim) { 1620 int seg; 1621 1622 if (seglim > ISP_RQDSEG) 1623 seglim = ISP_RQDSEG; 1624 1625 for (seg = 0; seg < seglim; seg++, nseg--) { 1626 /* 1627 * Unlike normal initiator commands, we don't 1628 * do any swizzling here. 1629 */ 1630 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1631 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1632 cto->ct_xfrlen += dm_segs->ds_len; 1633 dm_segs++; 1634 } 1635 cto->ct_seg_count = seg; 1636 } else { 1637 /* 1638 * This case should only happen when we're sending an 1639 * extra CTIO with final status. 1640 */ 1641 if (send_status == 0) { 1642 isp_prt(isp, ISP_LOGWARN, 1643 "tdma_mk ran out of segments"); 1644 mp->error = EINVAL; 1645 return; 1646 } 1647 } 1648 1649 /* 1650 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1651 * ct_tagtype, and ct_timeout have been carried over 1652 * unchanged from what our caller had set. 1653 * 1654 * The dataseg fields and the seg_count fields we just got 1655 * through setting. The data direction we've preserved all 1656 * along and only clear it if we're now sending status. 1657 */ 1658 1659 if (nth_ctio == nctios - 1) { 1660 /* 1661 * We're the last in a sequence of CTIOs, so mark 1662 * this CTIO and save the handle to the CCB such that 1663 * when this CTIO completes we can free dma resources 1664 * and do whatever else we need to do to finish the 1665 * rest of the command. We *don't* give this to the 1666 * firmware to work on- the caller will do that. 1667 */ 1668 1669 cto->ct_syshandle = handle; 1670 cto->ct_header.rqs_seqno = 1; 1671 1672 if (send_status) { 1673 cto->ct_scsi_status = scsi_status; 1674 cto->ct_flags |= sflags; 1675 cto->ct_resid = resid; 1676 } 1677 if (send_status) { 1678 isp_prt(isp, ISP_LOGTDEBUG1, 1679 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 1680 "scsi status %x resid %d", 1681 cto->ct_fwhandle, csio->ccb_h.target_lun, 1682 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 1683 cto->ct_scsi_status, cto->ct_resid); 1684 } else { 1685 isp_prt(isp, ISP_LOGTDEBUG1, 1686 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 1687 cto->ct_fwhandle, csio->ccb_h.target_lun, 1688 cto->ct_iid, cto->ct_tag_val, 1689 cto->ct_flags); 1690 } 1691 isp_put_ctio(isp, cto, qe); 1692 ISP_TDQE(isp, "last tdma_mk", curi, cto); 1693 if (nctios > 1) { 1694 MEMORYBARRIER(isp, SYNC_REQUEST, 1695 curi, QENTRY_LEN); 1696 } 1697 } else { 1698 ct_entry_t *oqe = qe; 1699 1700 /* 1701 * Make sure syshandle fields are clean 1702 */ 1703 cto->ct_syshandle = 0; 1704 cto->ct_header.rqs_seqno = 0; 1705 1706 isp_prt(isp, ISP_LOGTDEBUG1, 1707 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 1708 cto->ct_fwhandle, csio->ccb_h.target_lun, 1709 cto->ct_iid, cto->ct_flags); 1710 1711 /* 1712 * Get a new CTIO 1713 */ 1714 qe = (ct_entry_t *) 1715 ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1716 nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); 1717 if (nxti == mp->optr) { 1718 isp_prt(isp, ISP_LOGTDEBUG0, 1719 "Queue Overflow in tdma_mk"); 1720 mp->error = MUSHERR_NOQENTRIES; 1721 return; 1722 } 1723 1724 /* 1725 * Now that we're done with the old CTIO, 1726 * flush it out to the request queue. 1727 */ 1728 ISP_TDQE(isp, "dma_tgt_fc", curi, cto); 1729 isp_put_ctio(isp, cto, oqe); 1730 if (nth_ctio != 0) { 1731 MEMORYBARRIER(isp, SYNC_REQUEST, curi, 1732 QENTRY_LEN); 1733 } 1734 curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); 1735 1736 /* 1737 * Reset some fields in the CTIO so we can reuse 1738 * for the next one we'll flush to the request 1739 * queue. 1740 */ 1741 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1742 cto->ct_header.rqs_entry_count = 1; 1743 cto->ct_header.rqs_flags = 0; 1744 cto->ct_status = 0; 1745 cto->ct_scsi_status = 0; 1746 cto->ct_xfrlen = 0; 1747 cto->ct_resid = 0; 1748 cto->ct_seg_count = 0; 1749 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1750 } 1751 } 1752 *mp->nxtip = nxti; 1753 } 1754 1755 /* 1756 * We don't have to do multiple CTIOs here. Instead, we can just do 1757 * continuation segments as needed. This greatly simplifies the code 1758 * improves performance. 1759 */ 1760 1761 static void 1762 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1763 { 1764 mush_t *mp; 1765 struct ccb_scsiio *csio; 1766 ispsoftc_t *isp; 1767 ct2_entry_t *cto, *qe; 1768 uint16_t curi, nxti; 1769 ispds_t *ds; 1770 ispds64_t *ds64; 1771 int segcnt, seglim; 1772 1773 mp = (mush_t *) arg; 1774 if (error) { 1775 mp->error = error; 1776 return; 1777 } 1778 1779 isp = mp->isp; 1780 csio = mp->cmd_token; 1781 cto = mp->rq; 1782 1783 curi = isp->isp_reqidx; 1784 qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1785 1786 if (nseg == 0) { 1787 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1788 isp_prt(isp, ISP_LOGWARN, 1789 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1790 "set (0x%x)", cto->ct_flags); 1791 mp->error = EINVAL; 1792 return; 1793 } 1794 /* 1795 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1796 * flags to NO DATA and clear relative offset flags. 1797 * We preserve the ct_resid and the response area. 1798 */ 1799 cto->ct_header.rqs_seqno = 1; 1800 cto->ct_seg_count = 0; 1801 cto->ct_reloff = 0; 1802 isp_prt(isp, ISP_LOGTDEBUG1, 1803 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1804 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1805 cto->ct_iid, cto->ct_flags, cto->ct_status, 1806 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1807 if (IS_2KLOGIN(isp)) { 1808 isp_put_ctio2e(isp, 1809 (ct2e_entry_t *)cto, (ct2e_entry_t *)qe); 1810 } else { 1811 isp_put_ctio2(isp, cto, qe); 1812 } 1813 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe); 1814 return; 1815 } 1816 1817 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1818 isp_prt(isp, ISP_LOGERR, 1819 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1820 "(0x%x)", cto->ct_flags); 1821 mp->error = EINVAL; 1822 return; 1823 } 1824 1825 1826 nxti = *mp->nxtip; 1827 1828 /* 1829 * Check to see if we need to DAC addressing or not. 1830 * 1831 * Any address that's over the 4GB boundary causes this 1832 * to happen. 1833 */ 1834 segcnt = nseg; 1835 if (sizeof (bus_addr_t) > 4) { 1836 for (segcnt = 0; segcnt < nseg; segcnt++) { 1837 uint64_t addr = dm_segs[segcnt].ds_addr; 1838 if (addr >= 0x100000000LL) { 1839 break; 1840 } 1841 } 1842 } 1843 if (segcnt != nseg) { 1844 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO3; 1845 seglim = ISP_RQDSEG_T3; 1846 ds64 = &cto->rsp.m0.ct_dataseg64[0]; 1847 ds = NULL; 1848 } else { 1849 seglim = ISP_RQDSEG_T2; 1850 ds64 = NULL; 1851 ds = &cto->rsp.m0.ct_dataseg[0]; 1852 } 1853 cto->ct_seg_count = 0; 1854 1855 /* 1856 * Set up the CTIO2 data segments. 1857 */ 1858 for (segcnt = 0; cto->ct_seg_count < seglim && segcnt < nseg; 1859 cto->ct_seg_count++, segcnt++) { 1860 if (ds64) { 1861 ds64->ds_basehi = 1862 ((uint64_t) (dm_segs[segcnt].ds_addr) >> 32); 1863 ds64->ds_base = dm_segs[segcnt].ds_addr; 1864 ds64->ds_count = dm_segs[segcnt].ds_len; 1865 ds64++; 1866 } else { 1867 ds->ds_base = dm_segs[segcnt].ds_addr; 1868 ds->ds_count = dm_segs[segcnt].ds_len; 1869 ds++; 1870 } 1871 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1872 #if __FreeBSD_version < 500000 1873 isp_prt(isp, ISP_LOGTDEBUG1, 1874 "isp_send_ctio2: ent0[%d]0x%llx:%llu", 1875 cto->ct_seg_count, (uint64_t)dm_segs[segcnt].ds_addr, 1876 (uint64_t)dm_segs[segcnt].ds_len); 1877 #else 1878 isp_prt(isp, ISP_LOGTDEBUG1, 1879 "isp_send_ctio2: ent0[%d]0x%jx:%ju", 1880 cto->ct_seg_count, (uintmax_t)dm_segs[segcnt].ds_addr, 1881 (uintmax_t)dm_segs[segcnt].ds_len); 1882 #endif 1883 } 1884 1885 while (segcnt < nseg) { 1886 uint16_t curip; 1887 int seg; 1888 ispcontreq_t local, *crq = &local, *qep; 1889 1890 qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1891 curip = nxti; 1892 nxti = ISP_NXT_QENTRY(curip, RQUEST_QUEUE_LEN(isp)); 1893 if (nxti == mp->optr) { 1894 ISP_UNLOCK(isp); 1895 isp_prt(isp, ISP_LOGTDEBUG0, 1896 "tdma_mkfc: request queue overflow"); 1897 mp->error = MUSHERR_NOQENTRIES; 1898 return; 1899 } 1900 cto->ct_header.rqs_entry_count++; 1901 MEMZERO((void *)crq, sizeof (*crq)); 1902 crq->req_header.rqs_entry_count = 1; 1903 if (cto->ct_header.rqs_entry_type == RQSTYPE_CTIO3) { 1904 seglim = ISP_CDSEG64; 1905 ds = NULL; 1906 ds64 = &((ispcontreq64_t *)crq)->req_dataseg[0]; 1907 crq->req_header.rqs_entry_type = RQSTYPE_A64_CONT; 1908 } else { 1909 seglim = ISP_CDSEG; 1910 ds = &crq->req_dataseg[0]; 1911 ds64 = NULL; 1912 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1913 } 1914 for (seg = 0; segcnt < nseg && seg < seglim; 1915 segcnt++, seg++) { 1916 if (ds64) { 1917 ds64->ds_basehi = 1918 ((uint64_t) (dm_segs[segcnt].ds_addr) >> 32); 1919 ds64->ds_base = dm_segs[segcnt].ds_addr; 1920 ds64->ds_count = dm_segs[segcnt].ds_len; 1921 ds64++; 1922 } else { 1923 ds->ds_base = dm_segs[segcnt].ds_addr; 1924 ds->ds_count = dm_segs[segcnt].ds_len; 1925 ds++; 1926 } 1927 #if __FreeBSD_version < 500000 1928 isp_prt(isp, ISP_LOGTDEBUG1, 1929 "isp_send_ctio2: ent%d[%d]%llx:%llu", 1930 cto->ct_header.rqs_entry_count-1, seg, 1931 (uint64_t)dm_segs[segcnt].ds_addr, 1932 (uint64_t)dm_segs[segcnt].ds_len); 1933 #else 1934 isp_prt(isp, ISP_LOGTDEBUG1, 1935 "isp_send_ctio2: ent%d[%d]%jx:%ju", 1936 cto->ct_header.rqs_entry_count-1, seg, 1937 (uintmax_t)dm_segs[segcnt].ds_addr, 1938 (uintmax_t)dm_segs[segcnt].ds_len); 1939 #endif 1940 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1941 cto->ct_seg_count++; 1942 } 1943 MEMORYBARRIER(isp, SYNC_REQUEST, curip, QENTRY_LEN); 1944 isp_put_cont_req(isp, crq, qep); 1945 ISP_TDQE(isp, "cont entry", curi, qep); 1946 } 1947 1948 /* 1949 * No do final twiddling for the CTIO itself. 1950 */ 1951 cto->ct_header.rqs_seqno = 1; 1952 isp_prt(isp, ISP_LOGTDEBUG1, 1953 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x resid %d", 1954 cto->ct_rxid, csio->ccb_h.target_lun, (int) cto->ct_iid, 1955 cto->ct_flags, cto->ct_status, cto->rsp.m1.ct_scsi_status, 1956 cto->ct_resid); 1957 if (IS_2KLOGIN(isp)) 1958 isp_put_ctio2e(isp, (ct2e_entry_t *)cto, (ct2e_entry_t *)qe); 1959 else 1960 isp_put_ctio2(isp, cto, qe); 1961 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe); 1962 *mp->nxtip = nxti; 1963 } 1964 #endif 1965 1966 static void dma2_a64(void *, bus_dma_segment_t *, int, int); 1967 static void dma2(void *, bus_dma_segment_t *, int, int); 1968 1969 static void 1970 dma2_a64(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1971 { 1972 mush_t *mp; 1973 ispsoftc_t *isp; 1974 struct ccb_scsiio *csio; 1975 struct isp_pcisoftc *pcs; 1976 bus_dmamap_t *dp; 1977 bus_dma_segment_t *eseg; 1978 ispreq64_t *rq; 1979 int seglim, datalen; 1980 uint16_t nxti; 1981 1982 mp = (mush_t *) arg; 1983 if (error) { 1984 mp->error = error; 1985 return; 1986 } 1987 1988 if (nseg < 1) { 1989 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1990 mp->error = EFAULT; 1991 return; 1992 } 1993 csio = mp->cmd_token; 1994 isp = mp->isp; 1995 rq = mp->rq; 1996 pcs = (struct isp_pcisoftc *)mp->isp; 1997 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1998 nxti = *mp->nxtip; 1999 2000 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2001 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 2002 } else { 2003 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 2004 } 2005 datalen = XS_XFRLEN(csio); 2006 2007 /* 2008 * We're passed an initial partially filled in entry that 2009 * has most fields filled in except for data transfer 2010 * related values. 2011 * 2012 * Our job is to fill in the initial request queue entry and 2013 * then to start allocating and filling in continuation entries 2014 * until we've covered the entire transfer. 2015 */ 2016 2017 if (IS_FC(isp)) { 2018 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 2019 seglim = ISP_RQDSEG_T3; 2020 ((ispreqt3_t *)rq)->req_totalcnt = datalen; 2021 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2022 ((ispreqt3_t *)rq)->req_flags |= REQFLAG_DATA_IN; 2023 } else { 2024 ((ispreqt3_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 2025 } 2026 } else { 2027 rq->req_header.rqs_entry_type = RQSTYPE_A64; 2028 if (csio->cdb_len > 12) { 2029 seglim = 0; 2030 } else { 2031 seglim = ISP_RQDSEG_A64; 2032 } 2033 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2034 rq->req_flags |= REQFLAG_DATA_IN; 2035 } else { 2036 rq->req_flags |= REQFLAG_DATA_OUT; 2037 } 2038 } 2039 2040 eseg = dm_segs + nseg; 2041 2042 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 2043 if (IS_FC(isp)) { 2044 ispreqt3_t *rq3 = (ispreqt3_t *)rq; 2045 rq3->req_dataseg[rq3->req_seg_count].ds_base = 2046 DMA_LO32(dm_segs->ds_addr); 2047 rq3->req_dataseg[rq3->req_seg_count].ds_basehi = 2048 DMA_HI32(dm_segs->ds_addr); 2049 rq3->req_dataseg[rq3->req_seg_count].ds_count = 2050 dm_segs->ds_len; 2051 } else { 2052 rq->req_dataseg[rq->req_seg_count].ds_base = 2053 DMA_LO32(dm_segs->ds_addr); 2054 rq->req_dataseg[rq->req_seg_count].ds_basehi = 2055 DMA_HI32(dm_segs->ds_addr); 2056 rq->req_dataseg[rq->req_seg_count].ds_count = 2057 dm_segs->ds_len; 2058 } 2059 datalen -= dm_segs->ds_len; 2060 rq->req_seg_count++; 2061 dm_segs++; 2062 } 2063 2064 while (datalen > 0 && dm_segs != eseg) { 2065 uint16_t onxti; 2066 ispcontreq64_t local, *crq = &local, *cqe; 2067 2068 cqe = (ispcontreq64_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 2069 onxti = nxti; 2070 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 2071 if (nxti == mp->optr) { 2072 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 2073 mp->error = MUSHERR_NOQENTRIES; 2074 return; 2075 } 2076 rq->req_header.rqs_entry_count++; 2077 MEMZERO((void *)crq, sizeof (*crq)); 2078 crq->req_header.rqs_entry_count = 1; 2079 crq->req_header.rqs_entry_type = RQSTYPE_A64_CONT; 2080 2081 seglim = 0; 2082 while (datalen > 0 && seglim < ISP_CDSEG64 && dm_segs != eseg) { 2083 crq->req_dataseg[seglim].ds_base = 2084 DMA_LO32(dm_segs->ds_addr); 2085 crq->req_dataseg[seglim].ds_basehi = 2086 DMA_HI32(dm_segs->ds_addr); 2087 crq->req_dataseg[seglim].ds_count = 2088 dm_segs->ds_len; 2089 rq->req_seg_count++; 2090 dm_segs++; 2091 seglim++; 2092 datalen -= dm_segs->ds_len; 2093 } 2094 isp_put_cont64_req(isp, crq, cqe); 2095 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 2096 } 2097 *mp->nxtip = nxti; 2098 } 2099 2100 static void 2101 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2102 { 2103 mush_t *mp; 2104 ispsoftc_t *isp; 2105 struct ccb_scsiio *csio; 2106 struct isp_pcisoftc *pcs; 2107 bus_dmamap_t *dp; 2108 bus_dma_segment_t *eseg; 2109 ispreq_t *rq; 2110 int seglim, datalen; 2111 uint16_t nxti; 2112 2113 mp = (mush_t *) arg; 2114 if (error) { 2115 mp->error = error; 2116 return; 2117 } 2118 2119 if (nseg < 1) { 2120 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 2121 mp->error = EFAULT; 2122 return; 2123 } 2124 csio = mp->cmd_token; 2125 isp = mp->isp; 2126 rq = mp->rq; 2127 pcs = (struct isp_pcisoftc *)mp->isp; 2128 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 2129 nxti = *mp->nxtip; 2130 2131 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2132 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 2133 } else { 2134 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 2135 } 2136 2137 datalen = XS_XFRLEN(csio); 2138 2139 /* 2140 * We're passed an initial partially filled in entry that 2141 * has most fields filled in except for data transfer 2142 * related values. 2143 * 2144 * Our job is to fill in the initial request queue entry and 2145 * then to start allocating and filling in continuation entries 2146 * until we've covered the entire transfer. 2147 */ 2148 2149 if (IS_FC(isp)) { 2150 seglim = ISP_RQDSEG_T2; 2151 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 2152 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2153 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 2154 } else { 2155 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 2156 } 2157 } else { 2158 if (csio->cdb_len > 12) { 2159 seglim = 0; 2160 } else { 2161 seglim = ISP_RQDSEG; 2162 } 2163 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2164 rq->req_flags |= REQFLAG_DATA_IN; 2165 } else { 2166 rq->req_flags |= REQFLAG_DATA_OUT; 2167 } 2168 } 2169 2170 eseg = dm_segs + nseg; 2171 2172 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 2173 if (IS_FC(isp)) { 2174 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 2175 rq2->req_dataseg[rq2->req_seg_count].ds_base = 2176 DMA_LO32(dm_segs->ds_addr); 2177 rq2->req_dataseg[rq2->req_seg_count].ds_count = 2178 dm_segs->ds_len; 2179 } else { 2180 rq->req_dataseg[rq->req_seg_count].ds_base = 2181 DMA_LO32(dm_segs->ds_addr); 2182 rq->req_dataseg[rq->req_seg_count].ds_count = 2183 dm_segs->ds_len; 2184 } 2185 datalen -= dm_segs->ds_len; 2186 rq->req_seg_count++; 2187 dm_segs++; 2188 } 2189 2190 while (datalen > 0 && dm_segs != eseg) { 2191 uint16_t onxti; 2192 ispcontreq_t local, *crq = &local, *cqe; 2193 2194 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 2195 onxti = nxti; 2196 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 2197 if (nxti == mp->optr) { 2198 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 2199 mp->error = MUSHERR_NOQENTRIES; 2200 return; 2201 } 2202 rq->req_header.rqs_entry_count++; 2203 MEMZERO((void *)crq, sizeof (*crq)); 2204 crq->req_header.rqs_entry_count = 1; 2205 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 2206 2207 seglim = 0; 2208 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 2209 crq->req_dataseg[seglim].ds_base = 2210 DMA_LO32(dm_segs->ds_addr); 2211 crq->req_dataseg[seglim].ds_count = 2212 dm_segs->ds_len; 2213 rq->req_seg_count++; 2214 dm_segs++; 2215 seglim++; 2216 datalen -= dm_segs->ds_len; 2217 } 2218 isp_put_cont_req(isp, crq, cqe); 2219 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 2220 } 2221 *mp->nxtip = nxti; 2222 } 2223 2224 /* 2225 * We enter with ISP_LOCK held 2226 */ 2227 static int 2228 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, ispreq_t *rq, 2229 uint16_t *nxtip, uint16_t optr) 2230 { 2231 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 2232 ispreq_t *qep; 2233 bus_dmamap_t *dp = NULL; 2234 mush_t mush, *mp; 2235 void (*eptr)(void *, bus_dma_segment_t *, int, int); 2236 2237 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); 2238 #ifdef ISP_TARGET_MODE 2239 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 2240 if (IS_FC(isp)) { 2241 eptr = tdma_mkfc; 2242 } else { 2243 eptr = tdma_mk; 2244 } 2245 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 2246 (csio->dxfer_len == 0)) { 2247 mp = &mush; 2248 mp->isp = isp; 2249 mp->cmd_token = csio; 2250 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 2251 mp->nxtip = nxtip; 2252 mp->optr = optr; 2253 mp->error = 0; 2254 ISPLOCK_2_CAMLOCK(isp); 2255 (*eptr)(mp, NULL, 0, 0); 2256 CAMLOCK_2_ISPLOCK(isp); 2257 goto mbxsync; 2258 } 2259 } else 2260 #endif 2261 if (sizeof (bus_addr_t) > 4) { 2262 eptr = dma2_a64; 2263 } else { 2264 eptr = dma2; 2265 } 2266 2267 2268 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 2269 (csio->dxfer_len == 0)) { 2270 rq->req_seg_count = 1; 2271 goto mbxsync; 2272 } 2273 2274 /* 2275 * Do a virtual grapevine step to collect info for 2276 * the callback dma allocation that we have to use... 2277 */ 2278 mp = &mush; 2279 mp->isp = isp; 2280 mp->cmd_token = csio; 2281 mp->rq = rq; 2282 mp->nxtip = nxtip; 2283 mp->optr = optr; 2284 mp->error = 0; 2285 2286 ISPLOCK_2_CAMLOCK(isp); 2287 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 2288 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 2289 int error, s; 2290 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 2291 s = splsoftvm(); 2292 error = bus_dmamap_load(pcs->dmat, *dp, 2293 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 2294 if (error == EINPROGRESS) { 2295 bus_dmamap_unload(pcs->dmat, *dp); 2296 mp->error = EINVAL; 2297 isp_prt(isp, ISP_LOGERR, 2298 "deferred dma allocation not supported"); 2299 } else if (error && mp->error == 0) { 2300 #ifdef DIAGNOSTIC 2301 isp_prt(isp, ISP_LOGERR, 2302 "error %d in dma mapping code", error); 2303 #endif 2304 mp->error = error; 2305 } 2306 splx(s); 2307 } else { 2308 /* Pointer to physical buffer */ 2309 struct bus_dma_segment seg; 2310 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 2311 seg.ds_len = csio->dxfer_len; 2312 (*eptr)(mp, &seg, 1, 0); 2313 } 2314 } else { 2315 struct bus_dma_segment *segs; 2316 2317 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 2318 isp_prt(isp, ISP_LOGERR, 2319 "Physical segment pointers unsupported"); 2320 mp->error = EINVAL; 2321 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 2322 isp_prt(isp, ISP_LOGERR, 2323 "Virtual segment addresses unsupported"); 2324 mp->error = EINVAL; 2325 } else { 2326 /* Just use the segments provided */ 2327 segs = (struct bus_dma_segment *) csio->data_ptr; 2328 (*eptr)(mp, segs, csio->sglist_cnt, 0); 2329 } 2330 } 2331 CAMLOCK_2_ISPLOCK(isp); 2332 if (mp->error) { 2333 int retval = CMD_COMPLETE; 2334 if (mp->error == MUSHERR_NOQENTRIES) { 2335 retval = CMD_EAGAIN; 2336 } else if (mp->error == EFBIG) { 2337 XS_SETERR(csio, CAM_REQ_TOO_BIG); 2338 } else if (mp->error == EINVAL) { 2339 XS_SETERR(csio, CAM_REQ_INVALID); 2340 } else { 2341 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 2342 } 2343 return (retval); 2344 } 2345 mbxsync: 2346 switch (rq->req_header.rqs_entry_type) { 2347 case RQSTYPE_REQUEST: 2348 isp_put_request(isp, rq, qep); 2349 break; 2350 case RQSTYPE_CMDONLY: 2351 isp_put_extended_request(isp, (ispextreq_t *)rq, 2352 (ispextreq_t *)qep); 2353 break; 2354 case RQSTYPE_T2RQS: 2355 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 2356 break; 2357 case RQSTYPE_A64: 2358 case RQSTYPE_T3RQS: 2359 isp_put_request_t3(isp, (ispreqt3_t *) rq, (ispreqt3_t *) qep); 2360 break; 2361 } 2362 return (CMD_QUEUED); 2363 } 2364 2365 static void 2366 isp_pci_dmateardown(ispsoftc_t *isp, XS_T *xs, uint16_t handle) 2367 { 2368 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 2369 bus_dmamap_t *dp = &pcs->dmaps[isp_handle_index(handle)]; 2370 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 2371 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTREAD); 2372 } else { 2373 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTWRITE); 2374 } 2375 bus_dmamap_unload(pcs->dmat, *dp); 2376 } 2377 2378 2379 static void 2380 isp_pci_reset1(ispsoftc_t *isp) 2381 { 2382 /* Make sure the BIOS is disabled */ 2383 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 2384 /* and enable interrupts */ 2385 ENABLE_INTS(isp); 2386 } 2387 2388 static void 2389 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 2390 { 2391 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 2392 if (msg) 2393 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 2394 else 2395 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 2396 if (IS_SCSI(isp)) 2397 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 2398 else 2399 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 2400 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 2401 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 2402 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 2403 2404 2405 if (IS_SCSI(isp)) { 2406 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 2407 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 2408 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 2409 ISP_READ(isp, CDMA_FIFO_STS)); 2410 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 2411 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 2412 ISP_READ(isp, DDMA_FIFO_STS)); 2413 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 2414 ISP_READ(isp, SXP_INTERRUPT), 2415 ISP_READ(isp, SXP_GROSS_ERR), 2416 ISP_READ(isp, SXP_PINS_CTRL)); 2417 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2418 } 2419 printf(" mbox regs: %x %x %x %x %x\n", 2420 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2421 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2422 ISP_READ(isp, OUTMAILBOX4)); 2423 printf(" PCI Status Command/Status=%x\n", 2424 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2425 } 2426