1 /*- 2 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 3 * FreeBSD Version. 4 * 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 by Matthew Jacob 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice immediately at the beginning of the file, without modification, 12 * this list of conditions, and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <machine/bus_memio.h> 42 #include <machine/bus_pio.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 #include <sys/malloc.h> 47 48 #include <dev/isp/isp_freebsd.h> 49 50 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 51 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 52 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 53 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 54 static int 55 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 56 static int 57 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 58 static int isp_pci_mbxdma(struct ispsoftc *); 59 static int 60 isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, u_int16_t *, u_int16_t); 61 static void 62 isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 63 64 static void isp_pci_reset1(struct ispsoftc *); 65 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 66 67 static struct ispmdvec mdvec = { 68 isp_pci_rd_isr, 69 isp_pci_rd_reg, 70 isp_pci_wr_reg, 71 isp_pci_mbxdma, 72 isp_pci_dmasetup, 73 isp_pci_dmateardown, 74 NULL, 75 isp_pci_reset1, 76 isp_pci_dumpregs, 77 NULL, 78 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 79 }; 80 81 static struct ispmdvec mdvec_1080 = { 82 isp_pci_rd_isr, 83 isp_pci_rd_reg_1080, 84 isp_pci_wr_reg_1080, 85 isp_pci_mbxdma, 86 isp_pci_dmasetup, 87 isp_pci_dmateardown, 88 NULL, 89 isp_pci_reset1, 90 isp_pci_dumpregs, 91 NULL, 92 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 93 }; 94 95 static struct ispmdvec mdvec_12160 = { 96 isp_pci_rd_isr, 97 isp_pci_rd_reg_1080, 98 isp_pci_wr_reg_1080, 99 isp_pci_mbxdma, 100 isp_pci_dmasetup, 101 isp_pci_dmateardown, 102 NULL, 103 isp_pci_reset1, 104 isp_pci_dumpregs, 105 NULL, 106 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 107 }; 108 109 static struct ispmdvec mdvec_2100 = { 110 isp_pci_rd_isr, 111 isp_pci_rd_reg, 112 isp_pci_wr_reg, 113 isp_pci_mbxdma, 114 isp_pci_dmasetup, 115 isp_pci_dmateardown, 116 NULL, 117 isp_pci_reset1, 118 isp_pci_dumpregs 119 }; 120 121 static struct ispmdvec mdvec_2200 = { 122 isp_pci_rd_isr, 123 isp_pci_rd_reg, 124 isp_pci_wr_reg, 125 isp_pci_mbxdma, 126 isp_pci_dmasetup, 127 isp_pci_dmateardown, 128 NULL, 129 isp_pci_reset1, 130 isp_pci_dumpregs 131 }; 132 133 static struct ispmdvec mdvec_2300 = { 134 isp_pci_rd_isr_2300, 135 isp_pci_rd_reg, 136 isp_pci_wr_reg, 137 isp_pci_mbxdma, 138 isp_pci_dmasetup, 139 isp_pci_dmateardown, 140 NULL, 141 isp_pci_reset1, 142 isp_pci_dumpregs 143 }; 144 145 #ifndef PCIM_CMD_INVEN 146 #define PCIM_CMD_INVEN 0x10 147 #endif 148 #ifndef PCIM_CMD_BUSMASTEREN 149 #define PCIM_CMD_BUSMASTEREN 0x0004 150 #endif 151 #ifndef PCIM_CMD_PERRESPEN 152 #define PCIM_CMD_PERRESPEN 0x0040 153 #endif 154 #ifndef PCIM_CMD_SEREN 155 #define PCIM_CMD_SEREN 0x0100 156 #endif 157 158 #ifndef PCIR_COMMAND 159 #define PCIR_COMMAND 0x04 160 #endif 161 162 #ifndef PCIR_CACHELNSZ 163 #define PCIR_CACHELNSZ 0x0c 164 #endif 165 166 #ifndef PCIR_LATTIMER 167 #define PCIR_LATTIMER 0x0d 168 #endif 169 170 #ifndef PCIR_ROMADDR 171 #define PCIR_ROMADDR 0x30 172 #endif 173 174 #ifndef PCI_VENDOR_QLOGIC 175 #define PCI_VENDOR_QLOGIC 0x1077 176 #endif 177 178 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 179 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 180 #endif 181 182 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 183 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 184 #endif 185 186 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 187 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 188 #endif 189 190 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 191 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 192 #endif 193 194 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 195 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 196 #endif 197 198 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 199 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 200 #endif 201 202 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 203 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 204 #endif 205 206 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 207 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 208 #endif 209 210 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 211 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 212 #endif 213 214 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 215 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 216 #endif 217 218 #define PCI_QLOGIC_ISP1020 \ 219 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 220 221 #define PCI_QLOGIC_ISP1080 \ 222 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 223 224 #define PCI_QLOGIC_ISP10160 \ 225 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 226 227 #define PCI_QLOGIC_ISP12160 \ 228 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 229 230 #define PCI_QLOGIC_ISP1240 \ 231 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 232 233 #define PCI_QLOGIC_ISP1280 \ 234 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 235 236 #define PCI_QLOGIC_ISP2100 \ 237 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 238 239 #define PCI_QLOGIC_ISP2200 \ 240 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 241 242 #define PCI_QLOGIC_ISP2300 \ 243 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 244 245 #define PCI_QLOGIC_ISP2312 \ 246 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 247 248 /* 249 * Odd case for some AMI raid cards... We need to *not* attach to this. 250 */ 251 #define AMI_RAID_SUBVENDOR_ID 0x101e 252 253 #define IO_MAP_REG 0x10 254 #define MEM_MAP_REG 0x14 255 256 #define PCI_DFLT_LTNCY 0x40 257 #define PCI_DFLT_LNSZ 0x10 258 259 static int isp_pci_probe (device_t); 260 static int isp_pci_attach (device_t); 261 262 263 struct isp_pcisoftc { 264 struct ispsoftc pci_isp; 265 device_t pci_dev; 266 struct resource * pci_reg; 267 bus_space_tag_t pci_st; 268 bus_space_handle_t pci_sh; 269 void * ih; 270 int16_t pci_poff[_NREG_BLKS]; 271 bus_dma_tag_t dmat; 272 bus_dmamap_t *dmaps; 273 }; 274 extern ispfwfunc *isp_get_firmware_p; 275 276 static device_method_t isp_pci_methods[] = { 277 /* Device interface */ 278 DEVMETHOD(device_probe, isp_pci_probe), 279 DEVMETHOD(device_attach, isp_pci_attach), 280 { 0, 0 } 281 }; 282 static void isp_pci_intr(void *); 283 284 static driver_t isp_pci_driver = { 285 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 286 }; 287 static devclass_t isp_devclass; 288 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 289 290 static int 291 isp_pci_probe(device_t dev) 292 { 293 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 294 case PCI_QLOGIC_ISP1020: 295 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 296 break; 297 case PCI_QLOGIC_ISP1080: 298 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 299 break; 300 case PCI_QLOGIC_ISP1240: 301 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 302 break; 303 case PCI_QLOGIC_ISP1280: 304 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 305 break; 306 case PCI_QLOGIC_ISP10160: 307 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 308 break; 309 case PCI_QLOGIC_ISP12160: 310 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 311 return (ENXIO); 312 } 313 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 314 break; 315 case PCI_QLOGIC_ISP2100: 316 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 317 break; 318 case PCI_QLOGIC_ISP2200: 319 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 320 break; 321 case PCI_QLOGIC_ISP2300: 322 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 323 break; 324 case PCI_QLOGIC_ISP2312: 325 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 326 break; 327 default: 328 return (ENXIO); 329 } 330 if (isp_announced == 0 && bootverbose) { 331 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 332 "Core Version %d.%d\n", 333 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 334 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 335 isp_announced++; 336 } 337 /* 338 * XXXX: Here is where we might load the f/w module 339 * XXXX: (or increase a reference count to it). 340 */ 341 return (0); 342 } 343 344 static int 345 isp_pci_attach(device_t dev) 346 { 347 struct resource *regs, *irq; 348 int tval, rtp, rgd, iqd, m1, m2, isp_debug, role; 349 u_int32_t data, cmd, linesz, psize, basetype; 350 struct isp_pcisoftc *pcs; 351 struct ispsoftc *isp = NULL; 352 struct ispmdvec *mdvp; 353 const char *sptr; 354 int locksetup = 0; 355 356 /* 357 * Figure out if we're supposed to skip this one. 358 * If we are, we actually go to ISP_ROLE_NONE. 359 */ 360 361 tval = 0; 362 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 363 "disable", &tval) == 0 && tval) { 364 device_printf(dev, "device is disabled\n"); 365 /* but return 0 so the !$)$)*!$*) unit isn't reused */ 366 return (0); 367 } 368 369 role = 0; 370 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 371 "role", &role) == 0 && 372 ((role & ~(ISP_ROLE_INITIATOR|ISP_ROLE_TARGET)) == 0)) { 373 device_printf(dev, "setting role to 0x%x\n", role); 374 } else { 375 #ifdef ISP_TARGET_MODE 376 role = ISP_ROLE_INITIATOR|ISP_ROLE_TARGET; 377 #else 378 role = ISP_DEFAULT_ROLES; 379 #endif 380 } 381 382 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT | M_ZERO); 383 if (pcs == NULL) { 384 device_printf(dev, "cannot allocate softc\n"); 385 return (ENOMEM); 386 } 387 388 /* 389 * Figure out which we should try first - memory mapping or i/o mapping? 390 */ 391 #ifdef __alpha__ 392 m1 = PCIM_CMD_MEMEN; 393 m2 = PCIM_CMD_PORTEN; 394 #else 395 m1 = PCIM_CMD_PORTEN; 396 m2 = PCIM_CMD_MEMEN; 397 #endif 398 399 tval = 0; 400 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 401 "prefer_iomap", &tval) == 0 && tval != 0) { 402 m1 = PCIM_CMD_PORTEN; 403 m2 = PCIM_CMD_MEMEN; 404 } 405 tval = 0; 406 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 407 "prefer_memmap", &tval) == 0 && tval != 0) { 408 m1 = PCIM_CMD_MEMEN; 409 m2 = PCIM_CMD_PORTEN; 410 } 411 412 linesz = PCI_DFLT_LNSZ; 413 irq = regs = NULL; 414 rgd = rtp = iqd = 0; 415 416 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 417 if (cmd & m1) { 418 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 419 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 420 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 421 } 422 if (regs == NULL && (cmd & m2)) { 423 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 424 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 425 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 426 } 427 if (regs == NULL) { 428 device_printf(dev, "unable to map any ports\n"); 429 goto bad; 430 } 431 if (bootverbose) 432 device_printf(dev, "using %s space register mapping\n", 433 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 434 pcs->pci_dev = dev; 435 pcs->pci_reg = regs; 436 pcs->pci_st = rman_get_bustag(regs); 437 pcs->pci_sh = rman_get_bushandle(regs); 438 439 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 440 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 441 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 442 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 443 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 444 mdvp = &mdvec; 445 basetype = ISP_HA_SCSI_UNKNOWN; 446 psize = sizeof (sdparam); 447 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 448 mdvp = &mdvec; 449 basetype = ISP_HA_SCSI_UNKNOWN; 450 psize = sizeof (sdparam); 451 } 452 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 453 mdvp = &mdvec_1080; 454 basetype = ISP_HA_SCSI_1080; 455 psize = sizeof (sdparam); 456 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 457 ISP1080_DMA_REGS_OFF; 458 } 459 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 460 mdvp = &mdvec_1080; 461 basetype = ISP_HA_SCSI_1240; 462 psize = 2 * sizeof (sdparam); 463 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 464 ISP1080_DMA_REGS_OFF; 465 } 466 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 467 mdvp = &mdvec_1080; 468 basetype = ISP_HA_SCSI_1280; 469 psize = 2 * sizeof (sdparam); 470 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 471 ISP1080_DMA_REGS_OFF; 472 } 473 if (pci_get_devid(dev) == PCI_QLOGIC_ISP10160) { 474 mdvp = &mdvec_12160; 475 basetype = ISP_HA_SCSI_10160; 476 psize = sizeof (sdparam); 477 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 478 ISP1080_DMA_REGS_OFF; 479 } 480 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 481 mdvp = &mdvec_12160; 482 basetype = ISP_HA_SCSI_12160; 483 psize = 2 * sizeof (sdparam); 484 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 485 ISP1080_DMA_REGS_OFF; 486 } 487 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 488 mdvp = &mdvec_2100; 489 basetype = ISP_HA_FC_2100; 490 psize = sizeof (fcparam); 491 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 492 PCI_MBOX_REGS2100_OFF; 493 if (pci_get_revid(dev) < 3) { 494 /* 495 * XXX: Need to get the actual revision 496 * XXX: number of the 2100 FB. At any rate, 497 * XXX: lower cache line size for early revision 498 * XXX; boards. 499 */ 500 linesz = 1; 501 } 502 } 503 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 504 mdvp = &mdvec_2200; 505 basetype = ISP_HA_FC_2200; 506 psize = sizeof (fcparam); 507 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 508 PCI_MBOX_REGS2100_OFF; 509 } 510 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2300) { 511 mdvp = &mdvec_2300; 512 basetype = ISP_HA_FC_2300; 513 psize = sizeof (fcparam); 514 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 515 PCI_MBOX_REGS2300_OFF; 516 } 517 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2312) { 518 mdvp = &mdvec_2300; 519 basetype = ISP_HA_FC_2312; 520 psize = sizeof (fcparam); 521 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 522 PCI_MBOX_REGS2300_OFF; 523 } 524 isp = &pcs->pci_isp; 525 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 526 if (isp->isp_param == NULL) { 527 device_printf(dev, "cannot allocate parameter data\n"); 528 goto bad; 529 } 530 isp->isp_mdvec = mdvp; 531 isp->isp_type = basetype; 532 isp->isp_revision = pci_get_revid(dev); 533 isp->isp_role = role; 534 isp->isp_dev = dev; 535 536 /* 537 * Try and find firmware for this device. 538 */ 539 540 if (isp_get_firmware_p) { 541 int device = (int) pci_get_device(dev); 542 #ifdef ISP_TARGET_MODE 543 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 544 #else 545 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 546 #endif 547 } 548 549 /* 550 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 551 * are set. 552 */ 553 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 554 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 555 if (IS_2300(isp)) { /* per QLogic errata */ 556 cmd &= ~PCIM_CMD_INVEN; 557 } 558 if (IS_23XX(isp)) { 559 /* 560 * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command. 561 */ 562 isp->isp_touched = 1; 563 564 } 565 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 566 567 /* 568 * Make sure the Cache Line Size register is set sensibly. 569 */ 570 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 571 if (data != linesz) { 572 data = PCI_DFLT_LNSZ; 573 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 574 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 575 } 576 577 /* 578 * Make sure the Latency Timer is sane. 579 */ 580 data = pci_read_config(dev, PCIR_LATTIMER, 1); 581 if (data < PCI_DFLT_LTNCY) { 582 data = PCI_DFLT_LTNCY; 583 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 584 pci_write_config(dev, PCIR_LATTIMER, data, 1); 585 } 586 587 /* 588 * Make sure we've disabled the ROM. 589 */ 590 data = pci_read_config(dev, PCIR_ROMADDR, 4); 591 data &= ~1; 592 pci_write_config(dev, PCIR_ROMADDR, data, 4); 593 594 iqd = 0; 595 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 596 1, RF_ACTIVE | RF_SHAREABLE); 597 if (irq == NULL) { 598 device_printf(dev, "could not allocate interrupt\n"); 599 goto bad; 600 } 601 602 tval = 0; 603 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 604 "fwload_disable", &tval) == 0 && tval != 0) { 605 isp->isp_confopts |= ISP_CFG_NORELOAD; 606 } 607 tval = 0; 608 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 609 "ignore_nvram", &tval) == 0 && tval != 0) { 610 isp->isp_confopts |= ISP_CFG_NONVRAM; 611 } 612 tval = 0; 613 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 614 "fullduplex", &tval) == 0 && tval != 0) { 615 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 616 } 617 #ifdef ISP_FW_CRASH_DUMP 618 tval = 0; 619 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 620 "fw_dump_enable", &tval) == 0 && tval != 0) { 621 size_t amt = 0; 622 if (IS_2200(isp)) { 623 amt = QLA2200_RISC_IMAGE_DUMP_SIZE; 624 } else if (IS_23XX(isp)) { 625 amt = QLA2300_RISC_IMAGE_DUMP_SIZE; 626 } 627 if (amt) { 628 FCPARAM(isp)->isp_dump_data = 629 malloc(amt, M_DEVBUF, M_WAITOK | M_ZERO); 630 } else { 631 device_printf(dev, 632 "f/w crash dumps not supported for this model\n"); 633 } 634 } 635 #endif 636 637 sptr = 0; 638 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 639 "topology", (const char **) &sptr) == 0 && sptr != 0) { 640 if (strcmp(sptr, "lport") == 0) { 641 isp->isp_confopts |= ISP_CFG_LPORT; 642 } else if (strcmp(sptr, "nport") == 0) { 643 isp->isp_confopts |= ISP_CFG_NPORT; 644 } else if (strcmp(sptr, "lport-only") == 0) { 645 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 646 } else if (strcmp(sptr, "nport-only") == 0) { 647 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 648 } 649 } 650 651 /* 652 * Because the resource_*_value functions can neither return 653 * 64 bit integer values, nor can they be directly coerced 654 * to interpret the right hand side of the assignment as 655 * you want them to interpret it, we have to force WWN 656 * hint replacement to specify WWN strings with a leading 657 * 'w' (e..g w50000000aaaa0001). Sigh. 658 */ 659 sptr = 0; 660 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 661 "portwwn", (const char **) &sptr); 662 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 663 char *eptr = 0; 664 isp->isp_osinfo.default_port_wwn = strtouq(sptr, &eptr, 16); 665 if (eptr < sptr + 16 || isp->isp_osinfo.default_port_wwn == 0) { 666 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 667 isp->isp_osinfo.default_port_wwn = 0; 668 } else { 669 isp->isp_confopts |= ISP_CFG_OWNWWPN; 670 } 671 } 672 if (isp->isp_osinfo.default_port_wwn == 0) { 673 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 674 } 675 676 sptr = 0; 677 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 678 "nodewwn", (const char **) &sptr); 679 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 680 char *eptr = 0; 681 isp->isp_osinfo.default_node_wwn = strtouq(sptr, &eptr, 16); 682 if (eptr < sptr + 16 || isp->isp_osinfo.default_node_wwn == 0) { 683 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 684 isp->isp_osinfo.default_node_wwn = 0; 685 } else { 686 isp->isp_confopts |= ISP_CFG_OWNWWNN; 687 } 688 } 689 if (isp->isp_osinfo.default_node_wwn == 0) { 690 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 691 } 692 693 isp->isp_osinfo.default_id = -1; 694 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 695 "iid", &tval) == 0) { 696 isp->isp_osinfo.default_id = tval; 697 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 698 } 699 if (isp->isp_osinfo.default_id == -1) { 700 if (IS_FC(isp)) { 701 isp->isp_osinfo.default_id = 109; 702 } else { 703 isp->isp_osinfo.default_id = 7; 704 } 705 } 706 707 isp_debug = 0; 708 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 709 "debug", &isp_debug); 710 711 /* Make sure the lock is set up. */ 712 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 713 locksetup++; 714 715 if (bus_setup_intr(dev, irq, ISP_IFLAGS, isp_pci_intr, isp, &pcs->ih)) { 716 device_printf(dev, "could not setup interrupt\n"); 717 goto bad; 718 } 719 720 /* 721 * Set up logging levels. 722 */ 723 if (isp_debug) { 724 isp->isp_dblev = isp_debug; 725 } else { 726 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 727 } 728 if (bootverbose) 729 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 730 731 /* 732 * Last minute checks... 733 */ 734 if (IS_2312(isp)) { 735 isp->isp_port = pci_get_function(dev); 736 } 737 738 /* 739 * Make sure we're in reset state. 740 */ 741 ISP_LOCK(isp); 742 isp_reset(isp); 743 if (isp->isp_state != ISP_RESETSTATE) { 744 ISP_UNLOCK(isp); 745 goto bad; 746 } 747 isp_init(isp); 748 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_INITSTATE) { 749 isp_uninit(isp); 750 ISP_UNLOCK(isp); 751 goto bad; 752 } 753 isp_attach(isp); 754 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_RUNSTATE) { 755 isp_uninit(isp); 756 ISP_UNLOCK(isp); 757 goto bad; 758 } 759 /* 760 * XXXX: Here is where we might unload the f/w module 761 * XXXX: (or decrease the reference count to it). 762 */ 763 ISP_UNLOCK(isp); 764 return (0); 765 766 bad: 767 768 if (pcs && pcs->ih) { 769 (void) bus_teardown_intr(dev, irq, pcs->ih); 770 } 771 772 if (locksetup && isp) { 773 mtx_destroy(&isp->isp_osinfo.lock); 774 } 775 776 if (irq) { 777 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 778 } 779 780 781 if (regs) { 782 (void) bus_release_resource(dev, rtp, rgd, regs); 783 } 784 785 if (pcs) { 786 if (pcs->pci_isp.isp_param) 787 free(pcs->pci_isp.isp_param, M_DEVBUF); 788 free(pcs, M_DEVBUF); 789 } 790 791 /* 792 * XXXX: Here is where we might unload the f/w module 793 * XXXX: (or decrease the reference count to it). 794 */ 795 return (ENXIO); 796 } 797 798 static void 799 isp_pci_intr(void *arg) 800 { 801 struct ispsoftc *isp = arg; 802 u_int16_t isr, sema, mbox; 803 804 ISP_LOCK(isp); 805 isp->isp_intcnt++; 806 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 807 isp->isp_intbogus++; 808 } else { 809 int iok = isp->isp_osinfo.intsok; 810 isp->isp_osinfo.intsok = 0; 811 isp_intr(isp, isr, sema, mbox); 812 isp->isp_osinfo.intsok = iok; 813 } 814 ISP_UNLOCK(isp); 815 } 816 817 818 #define IspVirt2Off(a, x) \ 819 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 820 _BLK_REG_SHFT] + ((x) & 0xff)) 821 822 #define BXR2(pcs, off) \ 823 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 824 #define BXW2(pcs, off, v) \ 825 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 826 827 828 static INLINE int 829 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 830 { 831 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 832 u_int16_t val0, val1; 833 int i = 0; 834 835 do { 836 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 837 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 838 } while (val0 != val1 && ++i < 1000); 839 if (val0 != val1) { 840 return (1); 841 } 842 *rp = val0; 843 return (0); 844 } 845 846 static int 847 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 848 u_int16_t *semap, u_int16_t *mbp) 849 { 850 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 851 u_int16_t isr, sema; 852 853 if (IS_2100(isp)) { 854 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 855 return (0); 856 } 857 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 858 return (0); 859 } 860 } else { 861 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 862 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 863 } 864 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 865 isr &= INT_PENDING_MASK(isp); 866 sema &= BIU_SEMA_LOCK; 867 if (isr == 0 && sema == 0) { 868 return (0); 869 } 870 *isrp = isr; 871 if ((*semap = sema) != 0) { 872 if (IS_2100(isp)) { 873 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 874 return (0); 875 } 876 } else { 877 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 878 } 879 } 880 return (1); 881 } 882 883 static int 884 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 885 u_int16_t *semap, u_int16_t *mbox0p) 886 { 887 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 888 u_int32_t r2hisr; 889 890 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 891 *isrp = 0; 892 return (0); 893 } 894 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 895 IspVirt2Off(pcs, BIU_R2HSTSLO)); 896 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 897 if ((r2hisr & BIU_R2HST_INTR) == 0) { 898 *isrp = 0; 899 return (0); 900 } 901 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 902 case ISPR2HST_ROM_MBX_OK: 903 case ISPR2HST_ROM_MBX_FAIL: 904 case ISPR2HST_MBX_OK: 905 case ISPR2HST_MBX_FAIL: 906 case ISPR2HST_ASYNC_EVENT: 907 *isrp = r2hisr & 0xffff; 908 *mbox0p = (r2hisr >> 16); 909 *semap = 1; 910 return (1); 911 case ISPR2HST_RIO_16: 912 *isrp = r2hisr & 0xffff; 913 *mbox0p = ASYNC_RIO1; 914 *semap = 1; 915 return (1); 916 case ISPR2HST_FPOST: 917 *isrp = r2hisr & 0xffff; 918 *mbox0p = ASYNC_CMD_CMPLT; 919 *semap = 1; 920 return (1); 921 case ISPR2HST_FPOST_CTIO: 922 *isrp = r2hisr & 0xffff; 923 *mbox0p = ASYNC_CTIO_DONE; 924 *semap = 1; 925 return (1); 926 case ISPR2HST_RSPQ_UPDATE: 927 *isrp = r2hisr & 0xffff; 928 *mbox0p = 0; 929 *semap = 0; 930 return (1); 931 default: 932 return (0); 933 } 934 } 935 936 static u_int16_t 937 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 938 { 939 u_int16_t rv; 940 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 941 int oldconf = 0; 942 943 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 944 /* 945 * We will assume that someone has paused the RISC processor. 946 */ 947 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 948 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 949 oldconf | BIU_PCI_CONF1_SXP); 950 } 951 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 952 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 953 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 954 } 955 return (rv); 956 } 957 958 static void 959 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 960 { 961 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 962 int oldconf = 0; 963 964 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 965 /* 966 * We will assume that someone has paused the RISC processor. 967 */ 968 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 969 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 970 oldconf | BIU_PCI_CONF1_SXP); 971 } 972 BXW2(pcs, IspVirt2Off(isp, regoff), val); 973 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 974 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 975 } 976 } 977 978 static u_int16_t 979 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 980 { 981 u_int16_t rv, oc = 0; 982 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 983 984 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 985 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 986 u_int16_t tc; 987 /* 988 * We will assume that someone has paused the RISC processor. 989 */ 990 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 991 tc = oc & ~BIU_PCI1080_CONF1_DMA; 992 if (regoff & SXP_BANK1_SELECT) 993 tc |= BIU_PCI1080_CONF1_SXP1; 994 else 995 tc |= BIU_PCI1080_CONF1_SXP0; 996 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 997 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 998 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 999 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1000 oc | BIU_PCI1080_CONF1_DMA); 1001 } 1002 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1003 if (oc) { 1004 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1005 } 1006 return (rv); 1007 } 1008 1009 static void 1010 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 1011 { 1012 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1013 int oc = 0; 1014 1015 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1016 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1017 u_int16_t tc; 1018 /* 1019 * We will assume that someone has paused the RISC processor. 1020 */ 1021 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1022 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1023 if (regoff & SXP_BANK1_SELECT) 1024 tc |= BIU_PCI1080_CONF1_SXP1; 1025 else 1026 tc |= BIU_PCI1080_CONF1_SXP0; 1027 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1028 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1029 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1030 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1031 oc | BIU_PCI1080_CONF1_DMA); 1032 } 1033 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1034 if (oc) { 1035 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1036 } 1037 } 1038 1039 1040 struct imush { 1041 struct ispsoftc *isp; 1042 int error; 1043 }; 1044 1045 static void imc(void *, bus_dma_segment_t *, int, int); 1046 1047 static void 1048 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1049 { 1050 struct imush *imushp = (struct imush *) arg; 1051 if (error) { 1052 imushp->error = error; 1053 } else { 1054 struct ispsoftc *isp =imushp->isp; 1055 bus_addr_t addr = segs->ds_addr; 1056 1057 isp->isp_rquest_dma = addr; 1058 addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1059 isp->isp_result_dma = addr; 1060 if (IS_FC(isp)) { 1061 addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1062 FCPARAM(isp)->isp_scdma = addr; 1063 } 1064 } 1065 } 1066 1067 /* 1068 * Should be BUS_SPACE_MAXSIZE, but MAXPHYS is larger than BUS_SPACE_MAXSIZE 1069 */ 1070 #define ISP_NSEGS ((MAXPHYS / PAGE_SIZE) + 1) 1071 1072 static int 1073 isp_pci_mbxdma(struct ispsoftc *isp) 1074 { 1075 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1076 caddr_t base; 1077 u_int32_t len; 1078 int i, error, ns; 1079 bus_size_t alim, slim; 1080 struct imush im; 1081 1082 /* 1083 * Already been here? If so, leave... 1084 */ 1085 if (isp->isp_rquest) { 1086 return (0); 1087 } 1088 1089 #ifdef ISP_DAC_SUPPORTED 1090 alim = BUS_SPACE_UNRESTRICTED; 1091 #else 1092 alim = BUS_SPACE_MAXADDR_32BIT; 1093 #endif 1094 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1095 slim = BUS_SPACE_MAXADDR_32BIT; 1096 } else { 1097 slim = BUS_SPACE_MAXADDR_24BIT; 1098 } 1099 1100 ISP_UNLOCK(isp); 1101 if (bus_dma_tag_create(NULL, 1, slim+1, alim, alim, 1102 NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, 1103 busdma_lock_mutex, &Giant, &pcs->dmat)) { 1104 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1105 ISP_LOCK(isp); 1106 return(1); 1107 } 1108 1109 1110 len = sizeof (XS_T **) * isp->isp_maxcmds; 1111 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1112 if (isp->isp_xflist == NULL) { 1113 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1114 ISP_LOCK(isp); 1115 return (1); 1116 } 1117 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 1118 pcs->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1119 if (pcs->dmaps == NULL) { 1120 isp_prt(isp, ISP_LOGERR, "can't alloc dma map storage"); 1121 free(isp->isp_xflist, M_DEVBUF); 1122 ISP_LOCK(isp); 1123 return (1); 1124 } 1125 1126 /* 1127 * Allocate and map the request, result queues, plus FC scratch area. 1128 */ 1129 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1130 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1131 if (IS_FC(isp)) { 1132 len += ISP2100_SCRLEN; 1133 } 1134 1135 ns = (len / PAGE_SIZE) + 1; 1136 if (bus_dma_tag_create(pcs->dmat, QENTRY_LEN, slim+1, alim, alim, 1137 NULL, NULL, len, ns, slim, 0, busdma_lock_mutex, &Giant, 1138 &isp->isp_cdmat)) { 1139 isp_prt(isp, ISP_LOGERR, 1140 "cannot create a dma tag for control spaces"); 1141 free(pcs->dmaps, M_DEVBUF); 1142 free(isp->isp_xflist, M_DEVBUF); 1143 ISP_LOCK(isp); 1144 return (1); 1145 } 1146 1147 if (bus_dmamem_alloc(isp->isp_cdmat, (void **)&base, BUS_DMA_NOWAIT, 1148 &isp->isp_cdmap) != 0) { 1149 isp_prt(isp, ISP_LOGERR, 1150 "cannot allocate %d bytes of CCB memory", len); 1151 bus_dma_tag_destroy(isp->isp_cdmat); 1152 free(isp->isp_xflist, M_DEVBUF); 1153 free(pcs->dmaps, M_DEVBUF); 1154 ISP_LOCK(isp); 1155 return (1); 1156 } 1157 1158 for (i = 0; i < isp->isp_maxcmds; i++) { 1159 error = bus_dmamap_create(pcs->dmat, 0, &pcs->dmaps[i]); 1160 if (error) { 1161 isp_prt(isp, ISP_LOGERR, 1162 "error %d creating per-cmd DMA maps", error); 1163 while (--i >= 0) { 1164 bus_dmamap_destroy(pcs->dmat, pcs->dmaps[i]); 1165 } 1166 goto bad; 1167 } 1168 } 1169 1170 im.isp = isp; 1171 im.error = 0; 1172 bus_dmamap_load(isp->isp_cdmat, isp->isp_cdmap, base, len, imc, &im, 0); 1173 if (im.error) { 1174 isp_prt(isp, ISP_LOGERR, 1175 "error %d loading dma map for control areas", im.error); 1176 goto bad; 1177 } 1178 1179 isp->isp_rquest = base; 1180 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1181 isp->isp_result = base; 1182 if (IS_FC(isp)) { 1183 base += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1184 FCPARAM(isp)->isp_scratch = base; 1185 } 1186 ISP_LOCK(isp); 1187 return (0); 1188 1189 bad: 1190 bus_dmamem_free(isp->isp_cdmat, base, isp->isp_cdmap); 1191 bus_dma_tag_destroy(isp->isp_cdmat); 1192 free(isp->isp_xflist, M_DEVBUF); 1193 free(pcs->dmaps, M_DEVBUF); 1194 ISP_LOCK(isp); 1195 isp->isp_rquest = NULL; 1196 return (1); 1197 } 1198 1199 typedef struct { 1200 struct ispsoftc *isp; 1201 void *cmd_token; 1202 void *rq; 1203 u_int16_t *nxtip; 1204 u_int16_t optr; 1205 u_int error; 1206 } mush_t; 1207 1208 #define MUSHERR_NOQENTRIES -2 1209 1210 #ifdef ISP_TARGET_MODE 1211 /* 1212 * We need to handle DMA for target mode differently from initiator mode. 1213 * 1214 * DMA mapping and construction and submission of CTIO Request Entries 1215 * and rendevous for completion are very tightly coupled because we start 1216 * out by knowing (per platform) how much data we have to move, but we 1217 * don't know, up front, how many DMA mapping segments will have to be used 1218 * cover that data, so we don't know how many CTIO Request Entries we 1219 * will end up using. Further, for performance reasons we may want to 1220 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1221 * 1222 * The standard vector still goes through isp_pci_dmasetup, but the callback 1223 * for the DMA mapping routines comes here instead with the whole transfer 1224 * mapped and a pointer to a partially filled in already allocated request 1225 * queue entry. We finish the job. 1226 */ 1227 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1228 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1229 1230 #define STATUS_WITH_DATA 1 1231 1232 static void 1233 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1234 { 1235 mush_t *mp; 1236 struct ccb_scsiio *csio; 1237 struct ispsoftc *isp; 1238 struct isp_pcisoftc *pcs; 1239 bus_dmamap_t *dp; 1240 ct_entry_t *cto, *qe; 1241 u_int8_t scsi_status; 1242 u_int16_t curi, nxti, handle; 1243 u_int32_t sflags; 1244 int32_t resid; 1245 int nth_ctio, nctios, send_status; 1246 1247 mp = (mush_t *) arg; 1248 if (error) { 1249 mp->error = error; 1250 return; 1251 } 1252 1253 isp = mp->isp; 1254 csio = mp->cmd_token; 1255 cto = mp->rq; 1256 curi = isp->isp_reqidx; 1257 qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1258 1259 cto->ct_xfrlen = 0; 1260 cto->ct_seg_count = 0; 1261 cto->ct_header.rqs_entry_count = 1; 1262 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1263 1264 if (nseg == 0) { 1265 cto->ct_header.rqs_seqno = 1; 1266 isp_prt(isp, ISP_LOGTDEBUG1, 1267 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1268 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1269 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1270 cto->ct_scsi_status, cto->ct_resid); 1271 ISP_TDQE(isp, "tdma_mk[no data]", curi, cto); 1272 isp_put_ctio(isp, cto, qe); 1273 return; 1274 } 1275 1276 nctios = nseg / ISP_RQDSEG; 1277 if (nseg % ISP_RQDSEG) { 1278 nctios++; 1279 } 1280 1281 /* 1282 * Save syshandle, and potentially any SCSI status, which we'll 1283 * reinsert on the last CTIO we're going to send. 1284 */ 1285 1286 handle = cto->ct_syshandle; 1287 cto->ct_syshandle = 0; 1288 cto->ct_header.rqs_seqno = 0; 1289 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1290 1291 if (send_status) { 1292 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1293 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1294 /* 1295 * Preserve residual. 1296 */ 1297 resid = cto->ct_resid; 1298 1299 /* 1300 * Save actual SCSI status. 1301 */ 1302 scsi_status = cto->ct_scsi_status; 1303 1304 #ifndef STATUS_WITH_DATA 1305 sflags |= CT_NO_DATA; 1306 /* 1307 * We can't do a status at the same time as a data CTIO, so 1308 * we need to synthesize an extra CTIO at this level. 1309 */ 1310 nctios++; 1311 #endif 1312 } else { 1313 sflags = scsi_status = resid = 0; 1314 } 1315 1316 cto->ct_resid = 0; 1317 cto->ct_scsi_status = 0; 1318 1319 pcs = (struct isp_pcisoftc *)isp; 1320 dp = &pcs->dmaps[isp_handle_index(handle)]; 1321 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1322 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1323 } else { 1324 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1325 } 1326 1327 nxti = *mp->nxtip; 1328 1329 for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { 1330 int seglim; 1331 1332 seglim = nseg; 1333 if (seglim) { 1334 int seg; 1335 1336 if (seglim > ISP_RQDSEG) 1337 seglim = ISP_RQDSEG; 1338 1339 for (seg = 0; seg < seglim; seg++, nseg--) { 1340 /* 1341 * Unlike normal initiator commands, we don't 1342 * do any swizzling here. 1343 */ 1344 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1345 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1346 cto->ct_xfrlen += dm_segs->ds_len; 1347 dm_segs++; 1348 } 1349 cto->ct_seg_count = seg; 1350 } else { 1351 /* 1352 * This case should only happen when we're sending an 1353 * extra CTIO with final status. 1354 */ 1355 if (send_status == 0) { 1356 isp_prt(isp, ISP_LOGWARN, 1357 "tdma_mk ran out of segments"); 1358 mp->error = EINVAL; 1359 return; 1360 } 1361 } 1362 1363 /* 1364 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1365 * ct_tagtype, and ct_timeout have been carried over 1366 * unchanged from what our caller had set. 1367 * 1368 * The dataseg fields and the seg_count fields we just got 1369 * through setting. The data direction we've preserved all 1370 * along and only clear it if we're now sending status. 1371 */ 1372 1373 if (nth_ctio == nctios - 1) { 1374 /* 1375 * We're the last in a sequence of CTIOs, so mark 1376 * this CTIO and save the handle to the CCB such that 1377 * when this CTIO completes we can free dma resources 1378 * and do whatever else we need to do to finish the 1379 * rest of the command. We *don't* give this to the 1380 * firmware to work on- the caller will do that. 1381 */ 1382 1383 cto->ct_syshandle = handle; 1384 cto->ct_header.rqs_seqno = 1; 1385 1386 if (send_status) { 1387 cto->ct_scsi_status = scsi_status; 1388 cto->ct_flags |= sflags; 1389 cto->ct_resid = resid; 1390 } 1391 if (send_status) { 1392 isp_prt(isp, ISP_LOGTDEBUG1, 1393 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 1394 "scsi status %x resid %d", 1395 cto->ct_fwhandle, csio->ccb_h.target_lun, 1396 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 1397 cto->ct_scsi_status, cto->ct_resid); 1398 } else { 1399 isp_prt(isp, ISP_LOGTDEBUG1, 1400 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 1401 cto->ct_fwhandle, csio->ccb_h.target_lun, 1402 cto->ct_iid, cto->ct_tag_val, 1403 cto->ct_flags); 1404 } 1405 isp_put_ctio(isp, cto, qe); 1406 ISP_TDQE(isp, "last tdma_mk", curi, cto); 1407 if (nctios > 1) { 1408 MEMORYBARRIER(isp, SYNC_REQUEST, 1409 curi, QENTRY_LEN); 1410 } 1411 } else { 1412 ct_entry_t *oqe = qe; 1413 1414 /* 1415 * Make sure syshandle fields are clean 1416 */ 1417 cto->ct_syshandle = 0; 1418 cto->ct_header.rqs_seqno = 0; 1419 1420 isp_prt(isp, ISP_LOGTDEBUG1, 1421 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 1422 cto->ct_fwhandle, csio->ccb_h.target_lun, 1423 cto->ct_iid, cto->ct_flags); 1424 1425 /* 1426 * Get a new CTIO 1427 */ 1428 qe = (ct_entry_t *) 1429 ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1430 nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); 1431 if (nxti == mp->optr) { 1432 isp_prt(isp, ISP_LOGTDEBUG0, 1433 "Queue Overflow in tdma_mk"); 1434 mp->error = MUSHERR_NOQENTRIES; 1435 return; 1436 } 1437 1438 /* 1439 * Now that we're done with the old CTIO, 1440 * flush it out to the request queue. 1441 */ 1442 ISP_TDQE(isp, "dma_tgt_fc", curi, cto); 1443 isp_put_ctio(isp, cto, oqe); 1444 if (nth_ctio != 0) { 1445 MEMORYBARRIER(isp, SYNC_REQUEST, curi, 1446 QENTRY_LEN); 1447 } 1448 curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); 1449 1450 /* 1451 * Reset some fields in the CTIO so we can reuse 1452 * for the next one we'll flush to the request 1453 * queue. 1454 */ 1455 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1456 cto->ct_header.rqs_entry_count = 1; 1457 cto->ct_header.rqs_flags = 0; 1458 cto->ct_status = 0; 1459 cto->ct_scsi_status = 0; 1460 cto->ct_xfrlen = 0; 1461 cto->ct_resid = 0; 1462 cto->ct_seg_count = 0; 1463 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1464 } 1465 } 1466 *mp->nxtip = nxti; 1467 } 1468 1469 /* 1470 * We don't have to do multiple CTIOs here. Instead, we can just do 1471 * continuation segments as needed. This greatly simplifies the code 1472 * improves performance. 1473 */ 1474 1475 static void 1476 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1477 { 1478 mush_t *mp; 1479 struct ccb_scsiio *csio; 1480 struct ispsoftc *isp; 1481 ct2_entry_t *cto, *qe; 1482 u_int16_t curi, nxti; 1483 int segcnt; 1484 1485 mp = (mush_t *) arg; 1486 if (error) { 1487 mp->error = error; 1488 return; 1489 } 1490 1491 isp = mp->isp; 1492 csio = mp->cmd_token; 1493 cto = mp->rq; 1494 1495 curi = isp->isp_reqidx; 1496 qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1497 1498 if (nseg == 0) { 1499 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1500 isp_prt(isp, ISP_LOGWARN, 1501 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1502 "set (0x%x)", cto->ct_flags); 1503 mp->error = EINVAL; 1504 return; 1505 } 1506 /* 1507 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1508 * flags to NO DATA and clear relative offset flags. 1509 * We preserve the ct_resid and the response area. 1510 */ 1511 cto->ct_header.rqs_seqno = 1; 1512 cto->ct_seg_count = 0; 1513 cto->ct_reloff = 0; 1514 isp_prt(isp, ISP_LOGTDEBUG1, 1515 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1516 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1517 cto->ct_iid, cto->ct_flags, cto->ct_status, 1518 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1519 isp_put_ctio2(isp, cto, qe); 1520 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe); 1521 return; 1522 } 1523 1524 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1525 isp_prt(isp, ISP_LOGERR, 1526 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1527 "(0x%x)", cto->ct_flags); 1528 mp->error = EINVAL; 1529 return; 1530 } 1531 1532 1533 nxti = *mp->nxtip; 1534 1535 /* 1536 * Set up the CTIO2 data segments. 1537 */ 1538 for (segcnt = 0; cto->ct_seg_count < ISP_RQDSEG_T2 && segcnt < nseg; 1539 cto->ct_seg_count++, segcnt++) { 1540 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_base = 1541 dm_segs[segcnt].ds_addr; 1542 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_count = 1543 dm_segs[segcnt].ds_len; 1544 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1545 isp_prt(isp, ISP_LOGTDEBUG1, 1546 "isp_send_ctio2: ent0[%d]0x%llx:%lld", 1547 cto->ct_seg_count, (long long)dm_segs[segcnt].ds_addr, 1548 (long long)dm_segs[segcnt].ds_len); 1549 } 1550 1551 while (segcnt < nseg) { 1552 u_int16_t curip; 1553 int seg; 1554 ispcontreq_t local, *crq = &local, *qep; 1555 1556 qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1557 curip = nxti; 1558 nxti = ISP_NXT_QENTRY(curip, RQUEST_QUEUE_LEN(isp)); 1559 if (nxti == mp->optr) { 1560 ISP_UNLOCK(isp); 1561 isp_prt(isp, ISP_LOGTDEBUG0, 1562 "tdma_mkfc: request queue overflow"); 1563 mp->error = MUSHERR_NOQENTRIES; 1564 return; 1565 } 1566 cto->ct_header.rqs_entry_count++; 1567 MEMZERO((void *)crq, sizeof (*crq)); 1568 crq->req_header.rqs_entry_count = 1; 1569 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1570 for (seg = 0; segcnt < nseg && seg < ISP_CDSEG; 1571 segcnt++, seg++) { 1572 crq->req_dataseg[seg].ds_base = dm_segs[segcnt].ds_addr; 1573 crq->req_dataseg[seg].ds_count = dm_segs[segcnt].ds_len; 1574 isp_prt(isp, ISP_LOGTDEBUG1, 1575 "isp_send_ctio2: ent%d[%d]0x%llx:%lld", 1576 cto->ct_header.rqs_entry_count-1, seg, 1577 (long long) dm_segs[segcnt].ds_addr, 1578 (long long) dm_segs[segcnt].ds_len); 1579 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1580 cto->ct_seg_count++; 1581 } 1582 MEMORYBARRIER(isp, SYNC_REQUEST, curip, QENTRY_LEN); 1583 isp_put_cont_req(isp, crq, qep); 1584 ISP_TDQE(isp, "cont entry", curi, qep); 1585 } 1586 1587 /* 1588 * No do final twiddling for the CTIO itself. 1589 */ 1590 cto->ct_header.rqs_seqno = 1; 1591 isp_prt(isp, ISP_LOGTDEBUG1, 1592 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x resid %d", 1593 cto->ct_rxid, csio->ccb_h.target_lun, (int) cto->ct_iid, 1594 cto->ct_flags, cto->ct_status, cto->rsp.m1.ct_scsi_status, 1595 cto->ct_resid); 1596 isp_put_ctio2(isp, cto, qe); 1597 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe); 1598 *mp->nxtip = nxti; 1599 } 1600 #endif 1601 1602 static void dma2(void *, bus_dma_segment_t *, int, int); 1603 1604 static void 1605 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1606 { 1607 mush_t *mp; 1608 struct ispsoftc *isp; 1609 struct ccb_scsiio *csio; 1610 struct isp_pcisoftc *pcs; 1611 bus_dmamap_t *dp; 1612 bus_dma_segment_t *eseg; 1613 ispreq_t *rq; 1614 int seglim, datalen; 1615 u_int16_t nxti; 1616 1617 mp = (mush_t *) arg; 1618 if (error) { 1619 mp->error = error; 1620 return; 1621 } 1622 1623 if (nseg < 1) { 1624 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1625 mp->error = EFAULT; 1626 return; 1627 } 1628 csio = mp->cmd_token; 1629 isp = mp->isp; 1630 rq = mp->rq; 1631 pcs = (struct isp_pcisoftc *)mp->isp; 1632 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1633 nxti = *mp->nxtip; 1634 1635 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1636 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1637 } else { 1638 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1639 } 1640 1641 datalen = XS_XFRLEN(csio); 1642 1643 /* 1644 * We're passed an initial partially filled in entry that 1645 * has most fields filled in except for data transfer 1646 * related values. 1647 * 1648 * Our job is to fill in the initial request queue entry and 1649 * then to start allocating and filling in continuation entries 1650 * until we've covered the entire transfer. 1651 */ 1652 1653 if (IS_FC(isp)) { 1654 seglim = ISP_RQDSEG_T2; 1655 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1656 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1657 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1658 } else { 1659 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1660 } 1661 } else { 1662 if (csio->cdb_len > 12) { 1663 seglim = 0; 1664 } else { 1665 seglim = ISP_RQDSEG; 1666 } 1667 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1668 rq->req_flags |= REQFLAG_DATA_IN; 1669 } else { 1670 rq->req_flags |= REQFLAG_DATA_OUT; 1671 } 1672 } 1673 1674 eseg = dm_segs + nseg; 1675 1676 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1677 if (IS_FC(isp)) { 1678 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1679 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1680 dm_segs->ds_addr; 1681 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1682 dm_segs->ds_len; 1683 } else { 1684 rq->req_dataseg[rq->req_seg_count].ds_base = 1685 dm_segs->ds_addr; 1686 rq->req_dataseg[rq->req_seg_count].ds_count = 1687 dm_segs->ds_len; 1688 } 1689 datalen -= dm_segs->ds_len; 1690 rq->req_seg_count++; 1691 dm_segs++; 1692 } 1693 1694 while (datalen > 0 && dm_segs != eseg) { 1695 u_int16_t onxti; 1696 ispcontreq_t local, *crq = &local, *cqe; 1697 1698 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1699 onxti = nxti; 1700 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1701 if (nxti == mp->optr) { 1702 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1703 mp->error = MUSHERR_NOQENTRIES; 1704 return; 1705 } 1706 rq->req_header.rqs_entry_count++; 1707 MEMZERO((void *)crq, sizeof (*crq)); 1708 crq->req_header.rqs_entry_count = 1; 1709 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1710 1711 seglim = 0; 1712 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1713 crq->req_dataseg[seglim].ds_base = 1714 dm_segs->ds_addr; 1715 crq->req_dataseg[seglim].ds_count = 1716 dm_segs->ds_len; 1717 rq->req_seg_count++; 1718 dm_segs++; 1719 seglim++; 1720 datalen -= dm_segs->ds_len; 1721 } 1722 isp_put_cont_req(isp, crq, cqe); 1723 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1724 } 1725 *mp->nxtip = nxti; 1726 } 1727 1728 static int 1729 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1730 u_int16_t *nxtip, u_int16_t optr) 1731 { 1732 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1733 ispreq_t *qep; 1734 bus_dmamap_t *dp = NULL; 1735 mush_t mush, *mp; 1736 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1737 1738 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); 1739 #ifdef ISP_TARGET_MODE 1740 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1741 if (IS_FC(isp)) { 1742 eptr = tdma_mkfc; 1743 } else { 1744 eptr = tdma_mk; 1745 } 1746 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1747 (csio->dxfer_len == 0)) { 1748 mp = &mush; 1749 mp->isp = isp; 1750 mp->cmd_token = csio; 1751 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 1752 mp->nxtip = nxtip; 1753 mp->optr = optr; 1754 mp->error = 0; 1755 (*eptr)(mp, NULL, 0, 0); 1756 goto mbxsync; 1757 } 1758 } else 1759 #endif 1760 eptr = dma2; 1761 1762 1763 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1764 (csio->dxfer_len == 0)) { 1765 rq->req_seg_count = 1; 1766 goto mbxsync; 1767 } 1768 1769 /* 1770 * Do a virtual grapevine step to collect info for 1771 * the callback dma allocation that we have to use... 1772 */ 1773 mp = &mush; 1774 mp->isp = isp; 1775 mp->cmd_token = csio; 1776 mp->rq = rq; 1777 mp->nxtip = nxtip; 1778 mp->optr = optr; 1779 mp->error = 0; 1780 1781 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1782 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1783 int error, s; 1784 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1785 s = splsoftvm(); 1786 error = bus_dmamap_load(pcs->dmat, *dp, 1787 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1788 if (error == EINPROGRESS) { 1789 bus_dmamap_unload(pcs->dmat, *dp); 1790 mp->error = EINVAL; 1791 isp_prt(isp, ISP_LOGERR, 1792 "deferred dma allocation not supported"); 1793 } else if (error && mp->error == 0) { 1794 #ifdef DIAGNOSTIC 1795 isp_prt(isp, ISP_LOGERR, 1796 "error %d in dma mapping code", error); 1797 #endif 1798 mp->error = error; 1799 } 1800 splx(s); 1801 } else { 1802 /* Pointer to physical buffer */ 1803 struct bus_dma_segment seg; 1804 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1805 seg.ds_len = csio->dxfer_len; 1806 (*eptr)(mp, &seg, 1, 0); 1807 } 1808 } else { 1809 struct bus_dma_segment *segs; 1810 1811 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1812 isp_prt(isp, ISP_LOGERR, 1813 "Physical segment pointers unsupported"); 1814 mp->error = EINVAL; 1815 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1816 isp_prt(isp, ISP_LOGERR, 1817 "Virtual segment addresses unsupported"); 1818 mp->error = EINVAL; 1819 } else { 1820 /* Just use the segments provided */ 1821 segs = (struct bus_dma_segment *) csio->data_ptr; 1822 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1823 } 1824 } 1825 if (mp->error) { 1826 int retval = CMD_COMPLETE; 1827 if (mp->error == MUSHERR_NOQENTRIES) { 1828 retval = CMD_EAGAIN; 1829 } else if (mp->error == EFBIG) { 1830 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1831 } else if (mp->error == EINVAL) { 1832 XS_SETERR(csio, CAM_REQ_INVALID); 1833 } else { 1834 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1835 } 1836 return (retval); 1837 } 1838 mbxsync: 1839 switch (rq->req_header.rqs_entry_type) { 1840 case RQSTYPE_REQUEST: 1841 isp_put_request(isp, rq, qep); 1842 break; 1843 case RQSTYPE_CMDONLY: 1844 isp_put_extended_request(isp, (ispextreq_t *)rq, 1845 (ispextreq_t *)qep); 1846 break; 1847 case RQSTYPE_T2RQS: 1848 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1849 break; 1850 } 1851 return (CMD_QUEUED); 1852 } 1853 1854 static void 1855 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1856 { 1857 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1858 bus_dmamap_t *dp = &pcs->dmaps[isp_handle_index(handle)]; 1859 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1860 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTREAD); 1861 } else { 1862 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTWRITE); 1863 } 1864 bus_dmamap_unload(pcs->dmat, *dp); 1865 } 1866 1867 1868 static void 1869 isp_pci_reset1(struct ispsoftc *isp) 1870 { 1871 /* Make sure the BIOS is disabled */ 1872 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1873 /* and enable interrupts */ 1874 ENABLE_INTS(isp); 1875 } 1876 1877 static void 1878 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1879 { 1880 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1881 if (msg) 1882 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1883 else 1884 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1885 if (IS_SCSI(isp)) 1886 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1887 else 1888 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1889 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1890 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1891 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1892 1893 1894 if (IS_SCSI(isp)) { 1895 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1896 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1897 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1898 ISP_READ(isp, CDMA_FIFO_STS)); 1899 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1900 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1901 ISP_READ(isp, DDMA_FIFO_STS)); 1902 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1903 ISP_READ(isp, SXP_INTERRUPT), 1904 ISP_READ(isp, SXP_GROSS_ERR), 1905 ISP_READ(isp, SXP_PINS_CTRL)); 1906 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1907 } 1908 printf(" mbox regs: %x %x %x %x %x\n", 1909 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1910 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1911 ISP_READ(isp, OUTMAILBOX4)); 1912 printf(" PCI Status Command/Status=%x\n", 1913 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1914 } 1915