1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997-2008 by Matthew Jacob 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice immediately at the beginning of the file, without modification, 12 * this list of conditions, and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 /* 29 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 30 * FreeBSD Version. 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/linker.h> 40 #include <sys/firmware.h> 41 #include <sys/bus.h> 42 #include <sys/stdint.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <sys/rman.h> 48 #include <sys/malloc.h> 49 #include <sys/uio.h> 50 51 #ifdef __sparc64__ 52 #include <dev/ofw/openfirm.h> 53 #include <machine/ofw_machdep.h> 54 #endif 55 56 #include <dev/isp/isp_freebsd.h> 57 58 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 59 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 60 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 61 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 62 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 63 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 64 static uint32_t isp_pci_rd_reg_2600(ispsoftc_t *, int); 65 static void isp_pci_wr_reg_2600(ispsoftc_t *, int, uint32_t); 66 static void isp_pci_run_isr(ispsoftc_t *); 67 static void isp_pci_run_isr_2300(ispsoftc_t *); 68 static void isp_pci_run_isr_2400(ispsoftc_t *); 69 static int isp_pci_mbxdma(ispsoftc_t *); 70 static void isp_pci_mbxdmafree(ispsoftc_t *); 71 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 72 static int isp_pci_irqsetup(ispsoftc_t *); 73 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 74 75 static struct ispmdvec mdvec = { 76 isp_pci_run_isr, 77 isp_pci_rd_reg, 78 isp_pci_wr_reg, 79 isp_pci_mbxdma, 80 isp_pci_dmasetup, 81 isp_common_dmateardown, 82 isp_pci_irqsetup, 83 isp_pci_dumpregs, 84 NULL, 85 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 86 }; 87 88 static struct ispmdvec mdvec_1080 = { 89 isp_pci_run_isr, 90 isp_pci_rd_reg_1080, 91 isp_pci_wr_reg_1080, 92 isp_pci_mbxdma, 93 isp_pci_dmasetup, 94 isp_common_dmateardown, 95 isp_pci_irqsetup, 96 isp_pci_dumpregs, 97 NULL, 98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 99 }; 100 101 static struct ispmdvec mdvec_12160 = { 102 isp_pci_run_isr, 103 isp_pci_rd_reg_1080, 104 isp_pci_wr_reg_1080, 105 isp_pci_mbxdma, 106 isp_pci_dmasetup, 107 isp_common_dmateardown, 108 isp_pci_irqsetup, 109 isp_pci_dumpregs, 110 NULL, 111 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 112 }; 113 114 static struct ispmdvec mdvec_2100 = { 115 isp_pci_run_isr, 116 isp_pci_rd_reg, 117 isp_pci_wr_reg, 118 isp_pci_mbxdma, 119 isp_pci_dmasetup, 120 isp_common_dmateardown, 121 isp_pci_irqsetup, 122 isp_pci_dumpregs 123 }; 124 125 static struct ispmdvec mdvec_2200 = { 126 isp_pci_run_isr, 127 isp_pci_rd_reg, 128 isp_pci_wr_reg, 129 isp_pci_mbxdma, 130 isp_pci_dmasetup, 131 isp_common_dmateardown, 132 isp_pci_irqsetup, 133 isp_pci_dumpregs 134 }; 135 136 static struct ispmdvec mdvec_2300 = { 137 isp_pci_run_isr_2300, 138 isp_pci_rd_reg, 139 isp_pci_wr_reg, 140 isp_pci_mbxdma, 141 isp_pci_dmasetup, 142 isp_common_dmateardown, 143 isp_pci_irqsetup, 144 isp_pci_dumpregs 145 }; 146 147 static struct ispmdvec mdvec_2400 = { 148 isp_pci_run_isr_2400, 149 isp_pci_rd_reg_2400, 150 isp_pci_wr_reg_2400, 151 isp_pci_mbxdma, 152 isp_pci_dmasetup, 153 isp_common_dmateardown, 154 isp_pci_irqsetup, 155 NULL 156 }; 157 158 static struct ispmdvec mdvec_2500 = { 159 isp_pci_run_isr_2400, 160 isp_pci_rd_reg_2400, 161 isp_pci_wr_reg_2400, 162 isp_pci_mbxdma, 163 isp_pci_dmasetup, 164 isp_common_dmateardown, 165 isp_pci_irqsetup, 166 NULL 167 }; 168 169 static struct ispmdvec mdvec_2600 = { 170 isp_pci_run_isr_2400, 171 isp_pci_rd_reg_2600, 172 isp_pci_wr_reg_2600, 173 isp_pci_mbxdma, 174 isp_pci_dmasetup, 175 isp_common_dmateardown, 176 isp_pci_irqsetup, 177 NULL 178 }; 179 180 #ifndef PCIM_CMD_INVEN 181 #define PCIM_CMD_INVEN 0x10 182 #endif 183 #ifndef PCIM_CMD_BUSMASTEREN 184 #define PCIM_CMD_BUSMASTEREN 0x0004 185 #endif 186 #ifndef PCIM_CMD_PERRESPEN 187 #define PCIM_CMD_PERRESPEN 0x0040 188 #endif 189 #ifndef PCIM_CMD_SEREN 190 #define PCIM_CMD_SEREN 0x0100 191 #endif 192 #ifndef PCIM_CMD_INTX_DISABLE 193 #define PCIM_CMD_INTX_DISABLE 0x0400 194 #endif 195 196 #ifndef PCIR_COMMAND 197 #define PCIR_COMMAND 0x04 198 #endif 199 200 #ifndef PCIR_CACHELNSZ 201 #define PCIR_CACHELNSZ 0x0c 202 #endif 203 204 #ifndef PCIR_LATTIMER 205 #define PCIR_LATTIMER 0x0d 206 #endif 207 208 #ifndef PCIR_ROMADDR 209 #define PCIR_ROMADDR 0x30 210 #endif 211 212 #ifndef PCI_VENDOR_QLOGIC 213 #define PCI_VENDOR_QLOGIC 0x1077 214 #endif 215 216 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 217 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 218 #endif 219 220 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 221 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 222 #endif 223 224 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 225 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 226 #endif 227 228 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 229 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 230 #endif 231 232 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 233 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 234 #endif 235 236 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 237 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 238 #endif 239 240 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 241 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 242 #endif 243 244 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 245 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 246 #endif 247 248 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 249 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 250 #endif 251 252 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 253 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 254 #endif 255 256 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 257 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 258 #endif 259 260 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 261 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 262 #endif 263 264 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 265 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 266 #endif 267 268 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 269 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 270 #endif 271 272 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 273 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 274 #endif 275 276 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 277 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 278 #endif 279 280 #ifndef PCI_PRODUCT_QLOGIC_ISP5432 281 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 282 #endif 283 284 #ifndef PCI_PRODUCT_QLOGIC_ISP2031 285 #define PCI_PRODUCT_QLOGIC_ISP2031 0x2031 286 #endif 287 288 #ifndef PCI_PRODUCT_QLOGIC_ISP8031 289 #define PCI_PRODUCT_QLOGIC_ISP8031 0x8031 290 #endif 291 292 #define PCI_QLOGIC_ISP5432 \ 293 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 294 295 #define PCI_QLOGIC_ISP1020 \ 296 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 297 298 #define PCI_QLOGIC_ISP1080 \ 299 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 300 301 #define PCI_QLOGIC_ISP10160 \ 302 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 303 304 #define PCI_QLOGIC_ISP12160 \ 305 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 306 307 #define PCI_QLOGIC_ISP1240 \ 308 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 309 310 #define PCI_QLOGIC_ISP1280 \ 311 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 312 313 #define PCI_QLOGIC_ISP2100 \ 314 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 315 316 #define PCI_QLOGIC_ISP2200 \ 317 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 318 319 #define PCI_QLOGIC_ISP2300 \ 320 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 321 322 #define PCI_QLOGIC_ISP2312 \ 323 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 324 325 #define PCI_QLOGIC_ISP2322 \ 326 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 327 328 #define PCI_QLOGIC_ISP2422 \ 329 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 330 331 #define PCI_QLOGIC_ISP2432 \ 332 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 333 334 #define PCI_QLOGIC_ISP2532 \ 335 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 336 337 #define PCI_QLOGIC_ISP6312 \ 338 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 339 340 #define PCI_QLOGIC_ISP6322 \ 341 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 342 343 #define PCI_QLOGIC_ISP2031 \ 344 ((PCI_PRODUCT_QLOGIC_ISP2031 << 16) | PCI_VENDOR_QLOGIC) 345 346 #define PCI_QLOGIC_ISP8031 \ 347 ((PCI_PRODUCT_QLOGIC_ISP8031 << 16) | PCI_VENDOR_QLOGIC) 348 349 /* 350 * Odd case for some AMI raid cards... We need to *not* attach to this. 351 */ 352 #define AMI_RAID_SUBVENDOR_ID 0x101e 353 354 #define PCI_DFLT_LTNCY 0x40 355 #define PCI_DFLT_LNSZ 0x10 356 357 static int isp_pci_probe (device_t); 358 static int isp_pci_attach (device_t); 359 static int isp_pci_detach (device_t); 360 361 362 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 363 struct isp_pcisoftc { 364 ispsoftc_t pci_isp; 365 device_t pci_dev; 366 struct resource * regs; 367 struct resource * regs1; 368 struct resource * regs2; 369 struct { 370 int iqd; 371 struct resource * irq; 372 void * ih; 373 } irq[ISP_MAX_IRQS]; 374 int rtp; 375 int rgd; 376 int rtp1; 377 int rgd1; 378 int rtp2; 379 int rgd2; 380 int16_t pci_poff[_NREG_BLKS]; 381 bus_dma_tag_t dmat; 382 int msicount; 383 }; 384 385 386 static device_method_t isp_pci_methods[] = { 387 /* Device interface */ 388 DEVMETHOD(device_probe, isp_pci_probe), 389 DEVMETHOD(device_attach, isp_pci_attach), 390 DEVMETHOD(device_detach, isp_pci_detach), 391 { 0, 0 } 392 }; 393 394 static driver_t isp_pci_driver = { 395 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 396 }; 397 static devclass_t isp_devclass; 398 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 399 MODULE_DEPEND(isp, cam, 1, 1, 1); 400 MODULE_DEPEND(isp, firmware, 1, 1, 1); 401 static int isp_nvports = 0; 402 403 static int 404 isp_pci_probe(device_t dev) 405 { 406 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 407 case PCI_QLOGIC_ISP1020: 408 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 409 break; 410 case PCI_QLOGIC_ISP1080: 411 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 412 break; 413 case PCI_QLOGIC_ISP1240: 414 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 415 break; 416 case PCI_QLOGIC_ISP1280: 417 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 418 break; 419 case PCI_QLOGIC_ISP10160: 420 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 421 break; 422 case PCI_QLOGIC_ISP12160: 423 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 424 return (ENXIO); 425 } 426 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 427 break; 428 case PCI_QLOGIC_ISP2100: 429 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 430 break; 431 case PCI_QLOGIC_ISP2200: 432 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 433 break; 434 case PCI_QLOGIC_ISP2300: 435 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 436 break; 437 case PCI_QLOGIC_ISP2312: 438 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 439 break; 440 case PCI_QLOGIC_ISP2322: 441 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 442 break; 443 case PCI_QLOGIC_ISP2422: 444 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 445 break; 446 case PCI_QLOGIC_ISP2432: 447 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 448 break; 449 case PCI_QLOGIC_ISP2532: 450 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 451 break; 452 case PCI_QLOGIC_ISP5432: 453 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 454 break; 455 case PCI_QLOGIC_ISP6312: 456 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 457 break; 458 case PCI_QLOGIC_ISP6322: 459 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 460 break; 461 case PCI_QLOGIC_ISP2031: 462 device_set_desc(dev, "Qlogic ISP 2031 PCI FC-AL Adapter"); 463 break; 464 case PCI_QLOGIC_ISP8031: 465 device_set_desc(dev, "Qlogic ISP 8031 PCI FCoE Adapter"); 466 break; 467 default: 468 return (ENXIO); 469 } 470 if (isp_announced == 0 && bootverbose) { 471 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 472 "Core Version %d.%d\n", 473 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 474 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 475 isp_announced++; 476 } 477 /* 478 * XXXX: Here is where we might load the f/w module 479 * XXXX: (or increase a reference count to it). 480 */ 481 return (BUS_PROBE_DEFAULT); 482 } 483 484 static void 485 isp_get_generic_options(device_t dev, ispsoftc_t *isp) 486 { 487 int tval; 488 489 tval = 0; 490 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 491 isp->isp_confopts |= ISP_CFG_NORELOAD; 492 } 493 tval = 0; 494 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 495 isp->isp_confopts |= ISP_CFG_NONVRAM; 496 } 497 tval = 0; 498 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 499 if (tval) { 500 isp->isp_dblev = tval; 501 } else { 502 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 503 } 504 if (bootverbose) { 505 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 506 } 507 tval = -1; 508 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 509 if (tval > 0 && tval <= 254) { 510 isp_nvports = tval; 511 } 512 tval = 7; 513 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 514 isp_quickboot_time = tval; 515 } 516 517 static void 518 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 519 { 520 const char *sptr; 521 int tval = 0; 522 char prefix[12], name[16]; 523 524 if (chan == 0) 525 prefix[0] = 0; 526 else 527 snprintf(prefix, sizeof(prefix), "chan%d.", chan); 528 snprintf(name, sizeof(name), "%siid", prefix); 529 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 530 name, &tval)) { 531 if (IS_FC(isp)) { 532 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 533 } else { 534 #ifdef __sparc64__ 535 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 536 #else 537 ISP_SPI_PC(isp, chan)->iid = 7; 538 #endif 539 } 540 } else { 541 if (IS_FC(isp)) { 542 ISP_FC_PC(isp, chan)->default_id = tval - chan; 543 } else { 544 ISP_SPI_PC(isp, chan)->iid = tval; 545 } 546 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 547 } 548 549 if (IS_SCSI(isp)) 550 return; 551 552 tval = -1; 553 snprintf(name, sizeof(name), "%srole", prefix); 554 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 555 name, &tval) == 0) { 556 switch (tval) { 557 case ISP_ROLE_NONE: 558 case ISP_ROLE_INITIATOR: 559 case ISP_ROLE_TARGET: 560 case ISP_ROLE_BOTH: 561 device_printf(dev, "Chan %d setting role to 0x%x\n", chan, tval); 562 break; 563 default: 564 tval = -1; 565 break; 566 } 567 } 568 if (tval == -1) { 569 tval = ISP_DEFAULT_ROLES; 570 } 571 ISP_FC_PC(isp, chan)->def_role = tval; 572 573 tval = 0; 574 snprintf(name, sizeof(name), "%sfullduplex", prefix); 575 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 576 name, &tval) == 0 && tval != 0) { 577 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 578 } 579 sptr = NULL; 580 snprintf(name, sizeof(name), "%stopology", prefix); 581 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 582 name, (const char **) &sptr) == 0 && sptr != NULL) { 583 if (strcmp(sptr, "lport") == 0) { 584 isp->isp_confopts |= ISP_CFG_LPORT; 585 } else if (strcmp(sptr, "nport") == 0) { 586 isp->isp_confopts |= ISP_CFG_NPORT; 587 } else if (strcmp(sptr, "lport-only") == 0) { 588 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 589 } else if (strcmp(sptr, "nport-only") == 0) { 590 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 591 } 592 } 593 594 #ifdef ISP_FCTAPE_OFF 595 isp->isp_confopts |= ISP_CFG_NOFCTAPE; 596 #else 597 isp->isp_confopts |= ISP_CFG_FCTAPE; 598 #endif 599 600 tval = 0; 601 snprintf(name, sizeof(name), "%snofctape", prefix); 602 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 603 name, &tval); 604 if (tval) { 605 isp->isp_confopts &= ~ISP_CFG_FCTAPE; 606 isp->isp_confopts |= ISP_CFG_NOFCTAPE; 607 } 608 609 tval = 0; 610 snprintf(name, sizeof(name), "%sfctape", prefix); 611 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 612 name, &tval); 613 if (tval) { 614 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE; 615 isp->isp_confopts |= ISP_CFG_FCTAPE; 616 } 617 618 619 /* 620 * Because the resource_*_value functions can neither return 621 * 64 bit integer values, nor can they be directly coerced 622 * to interpret the right hand side of the assignment as 623 * you want them to interpret it, we have to force WWN 624 * hint replacement to specify WWN strings with a leading 625 * 'w' (e..g w50000000aaaa0001). Sigh. 626 */ 627 sptr = NULL; 628 snprintf(name, sizeof(name), "%sportwwn", prefix); 629 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 630 name, (const char **) &sptr); 631 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 632 char *eptr = NULL; 633 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 634 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 635 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 636 ISP_FC_PC(isp, chan)->def_wwpn = 0; 637 } 638 } 639 640 sptr = NULL; 641 snprintf(name, sizeof(name), "%snodewwn", prefix); 642 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 643 name, (const char **) &sptr); 644 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 645 char *eptr = NULL; 646 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 647 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 648 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 649 ISP_FC_PC(isp, chan)->def_wwnn = 0; 650 } 651 } 652 653 tval = -1; 654 snprintf(name, sizeof(name), "%sloop_down_limit", prefix); 655 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 656 name, &tval); 657 if (tval >= 0 && tval < 0xffff) { 658 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 659 } else { 660 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 661 } 662 663 tval = -1; 664 snprintf(name, sizeof(name), "%sgone_device_time", prefix); 665 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 666 name, &tval); 667 if (tval >= 0 && tval < 0xffff) { 668 ISP_FC_PC(isp, chan)->gone_device_time = tval; 669 } else { 670 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 671 } 672 } 673 674 static int 675 isp_pci_attach(device_t dev) 676 { 677 struct isp_pcisoftc *pcs = device_get_softc(dev); 678 ispsoftc_t *isp = &pcs->pci_isp; 679 int i; 680 uint32_t data, cmd, linesz, did; 681 size_t psize, xsize; 682 char fwname[32]; 683 684 pcs->pci_dev = dev; 685 isp->isp_dev = dev; 686 isp->isp_nchan = 1; 687 mtx_init(&isp->isp_lock, "isp", NULL, MTX_DEF); 688 689 /* 690 * Get Generic Options 691 */ 692 isp_nvports = 0; 693 isp_get_generic_options(dev, isp); 694 695 linesz = PCI_DFLT_LNSZ; 696 pcs->regs = pcs->regs2 = NULL; 697 pcs->rgd = pcs->rtp = 0; 698 699 pcs->pci_dev = dev; 700 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 701 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 702 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 703 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 704 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 705 706 switch (pci_get_devid(dev)) { 707 case PCI_QLOGIC_ISP1020: 708 did = 0x1040; 709 isp->isp_mdvec = &mdvec; 710 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 711 break; 712 case PCI_QLOGIC_ISP1080: 713 did = 0x1080; 714 isp->isp_mdvec = &mdvec_1080; 715 isp->isp_type = ISP_HA_SCSI_1080; 716 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 717 break; 718 case PCI_QLOGIC_ISP1240: 719 did = 0x1080; 720 isp->isp_mdvec = &mdvec_1080; 721 isp->isp_type = ISP_HA_SCSI_1240; 722 isp->isp_nchan = 2; 723 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 724 break; 725 case PCI_QLOGIC_ISP1280: 726 did = 0x1080; 727 isp->isp_mdvec = &mdvec_1080; 728 isp->isp_type = ISP_HA_SCSI_1280; 729 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 730 break; 731 case PCI_QLOGIC_ISP10160: 732 did = 0x12160; 733 isp->isp_mdvec = &mdvec_12160; 734 isp->isp_type = ISP_HA_SCSI_10160; 735 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 736 break; 737 case PCI_QLOGIC_ISP12160: 738 did = 0x12160; 739 isp->isp_nchan = 2; 740 isp->isp_mdvec = &mdvec_12160; 741 isp->isp_type = ISP_HA_SCSI_12160; 742 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 743 break; 744 case PCI_QLOGIC_ISP2100: 745 did = 0x2100; 746 isp->isp_mdvec = &mdvec_2100; 747 isp->isp_type = ISP_HA_FC_2100; 748 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 749 if (pci_get_revid(dev) < 3) { 750 /* 751 * XXX: Need to get the actual revision 752 * XXX: number of the 2100 FB. At any rate, 753 * XXX: lower cache line size for early revision 754 * XXX; boards. 755 */ 756 linesz = 1; 757 } 758 break; 759 case PCI_QLOGIC_ISP2200: 760 did = 0x2200; 761 isp->isp_mdvec = &mdvec_2200; 762 isp->isp_type = ISP_HA_FC_2200; 763 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 764 break; 765 case PCI_QLOGIC_ISP2300: 766 did = 0x2300; 767 isp->isp_mdvec = &mdvec_2300; 768 isp->isp_type = ISP_HA_FC_2300; 769 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 770 break; 771 case PCI_QLOGIC_ISP2312: 772 case PCI_QLOGIC_ISP6312: 773 did = 0x2300; 774 isp->isp_mdvec = &mdvec_2300; 775 isp->isp_type = ISP_HA_FC_2312; 776 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 777 break; 778 case PCI_QLOGIC_ISP2322: 779 case PCI_QLOGIC_ISP6322: 780 did = 0x2322; 781 isp->isp_mdvec = &mdvec_2300; 782 isp->isp_type = ISP_HA_FC_2322; 783 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 784 break; 785 case PCI_QLOGIC_ISP2422: 786 case PCI_QLOGIC_ISP2432: 787 did = 0x2400; 788 isp->isp_nchan += isp_nvports; 789 isp->isp_mdvec = &mdvec_2400; 790 isp->isp_type = ISP_HA_FC_2400; 791 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 792 break; 793 case PCI_QLOGIC_ISP2532: 794 did = 0x2500; 795 isp->isp_nchan += isp_nvports; 796 isp->isp_mdvec = &mdvec_2500; 797 isp->isp_type = ISP_HA_FC_2500; 798 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 799 break; 800 case PCI_QLOGIC_ISP5432: 801 did = 0x2500; 802 isp->isp_mdvec = &mdvec_2500; 803 isp->isp_type = ISP_HA_FC_2500; 804 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 805 break; 806 case PCI_QLOGIC_ISP2031: 807 case PCI_QLOGIC_ISP8031: 808 did = 0x2600; 809 isp->isp_nchan += isp_nvports; 810 isp->isp_mdvec = &mdvec_2600; 811 isp->isp_type = ISP_HA_FC_2600; 812 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 813 break; 814 default: 815 device_printf(dev, "unknown device type\n"); 816 goto bad; 817 break; 818 } 819 isp->isp_revision = pci_get_revid(dev); 820 821 if (IS_26XX(isp)) { 822 pcs->rtp = SYS_RES_MEMORY; 823 pcs->rgd = PCIR_BAR(0); 824 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, 825 RF_ACTIVE); 826 pcs->rtp1 = SYS_RES_MEMORY; 827 pcs->rgd1 = PCIR_BAR(2); 828 pcs->regs1 = bus_alloc_resource_any(dev, pcs->rtp1, &pcs->rgd1, 829 RF_ACTIVE); 830 pcs->rtp2 = SYS_RES_MEMORY; 831 pcs->rgd2 = PCIR_BAR(4); 832 pcs->regs2 = bus_alloc_resource_any(dev, pcs->rtp2, &pcs->rgd2, 833 RF_ACTIVE); 834 } else { 835 pcs->rtp = SYS_RES_MEMORY; 836 pcs->rgd = PCIR_BAR(1); 837 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, 838 RF_ACTIVE); 839 if (pcs->regs == NULL) { 840 pcs->rtp = SYS_RES_IOPORT; 841 pcs->rgd = PCIR_BAR(0); 842 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, 843 &pcs->rgd, RF_ACTIVE); 844 } 845 } 846 if (pcs->regs == NULL) { 847 device_printf(dev, "Unable to map any ports\n"); 848 goto bad; 849 } 850 if (bootverbose) { 851 device_printf(dev, "Using %s space register mapping\n", 852 (pcs->rtp == SYS_RES_IOPORT)? "I/O" : "Memory"); 853 } 854 isp->isp_regs = pcs->regs; 855 isp->isp_regs2 = pcs->regs2; 856 857 if (IS_FC(isp)) { 858 psize = sizeof (fcparam); 859 xsize = sizeof (struct isp_fc); 860 } else { 861 psize = sizeof (sdparam); 862 xsize = sizeof (struct isp_spi); 863 } 864 psize *= isp->isp_nchan; 865 xsize *= isp->isp_nchan; 866 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 867 if (isp->isp_param == NULL) { 868 device_printf(dev, "cannot allocate parameter data\n"); 869 goto bad; 870 } 871 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 872 if (isp->isp_osinfo.pc.ptr == NULL) { 873 device_printf(dev, "cannot allocate parameter data\n"); 874 goto bad; 875 } 876 877 /* 878 * Now that we know who we are (roughly) get/set specific options 879 */ 880 for (i = 0; i < isp->isp_nchan; i++) { 881 isp_get_specific_options(dev, i, isp); 882 } 883 884 isp->isp_osinfo.fw = NULL; 885 if (isp->isp_osinfo.fw == NULL) { 886 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 887 isp->isp_osinfo.fw = firmware_get(fwname); 888 } 889 if (isp->isp_osinfo.fw != NULL) { 890 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname); 891 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 892 } 893 894 /* 895 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 896 */ 897 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 898 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 899 if (IS_2300(isp)) { /* per QLogic errata */ 900 cmd &= ~PCIM_CMD_INVEN; 901 } 902 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 903 cmd &= ~PCIM_CMD_INTX_DISABLE; 904 } 905 if (IS_24XX(isp)) { 906 cmd &= ~PCIM_CMD_INTX_DISABLE; 907 } 908 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 909 910 /* 911 * Make sure the Cache Line Size register is set sensibly. 912 */ 913 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 914 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 915 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data); 916 data = linesz; 917 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 918 } 919 920 /* 921 * Make sure the Latency Timer is sane. 922 */ 923 data = pci_read_config(dev, PCIR_LATTIMER, 1); 924 if (data < PCI_DFLT_LTNCY) { 925 data = PCI_DFLT_LTNCY; 926 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data); 927 pci_write_config(dev, PCIR_LATTIMER, data, 1); 928 } 929 930 /* 931 * Make sure we've disabled the ROM. 932 */ 933 data = pci_read_config(dev, PCIR_ROMADDR, 4); 934 data &= ~1; 935 pci_write_config(dev, PCIR_ROMADDR, data, 4); 936 937 /* 938 * Last minute checks... 939 */ 940 if (IS_23XX(isp) || IS_24XX(isp)) { 941 isp->isp_port = pci_get_function(dev); 942 } 943 944 /* 945 * Make sure we're in reset state. 946 */ 947 ISP_LOCK(isp); 948 if (isp_reinit(isp, 1) != 0) { 949 ISP_UNLOCK(isp); 950 goto bad; 951 } 952 ISP_UNLOCK(isp); 953 if (isp_attach(isp)) { 954 ISP_LOCK(isp); 955 isp_shutdown(isp); 956 ISP_UNLOCK(isp); 957 goto bad; 958 } 959 return (0); 960 961 bad: 962 for (i = 0; i < isp->isp_nirq; i++) { 963 (void) bus_teardown_intr(dev, pcs->irq[i].irq, pcs->irq[i].ih); 964 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->irq[i].iqd, 965 pcs->irq[0].irq); 966 } 967 if (pcs->msicount) { 968 pci_release_msi(dev); 969 } 970 if (pcs->regs) 971 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 972 if (pcs->regs1) 973 (void) bus_release_resource(dev, pcs->rtp1, pcs->rgd1, pcs->regs1); 974 if (pcs->regs2) 975 (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2); 976 if (pcs->pci_isp.isp_param) { 977 free(pcs->pci_isp.isp_param, M_DEVBUF); 978 pcs->pci_isp.isp_param = NULL; 979 } 980 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 981 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 982 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 983 } 984 mtx_destroy(&isp->isp_lock); 985 return (ENXIO); 986 } 987 988 static int 989 isp_pci_detach(device_t dev) 990 { 991 struct isp_pcisoftc *pcs = device_get_softc(dev); 992 ispsoftc_t *isp = &pcs->pci_isp; 993 int i, status; 994 995 status = isp_detach(isp); 996 if (status) 997 return (status); 998 ISP_LOCK(isp); 999 isp_shutdown(isp); 1000 ISP_UNLOCK(isp); 1001 for (i = 0; i < isp->isp_nirq; i++) { 1002 (void) bus_teardown_intr(dev, pcs->irq[i].irq, pcs->irq[i].ih); 1003 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->irq[i].iqd, 1004 pcs->irq[i].irq); 1005 } 1006 if (pcs->msicount) 1007 pci_release_msi(dev); 1008 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1009 if (pcs->regs1) 1010 (void) bus_release_resource(dev, pcs->rtp1, pcs->rgd1, pcs->regs1); 1011 if (pcs->regs2) 1012 (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2); 1013 isp_pci_mbxdmafree(isp); 1014 if (pcs->pci_isp.isp_param) { 1015 free(pcs->pci_isp.isp_param, M_DEVBUF); 1016 pcs->pci_isp.isp_param = NULL; 1017 } 1018 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1019 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1020 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1021 } 1022 mtx_destroy(&isp->isp_lock); 1023 return (0); 1024 } 1025 1026 #define IspVirt2Off(a, x) \ 1027 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1028 _BLK_REG_SHFT] + ((x) & 0xfff)) 1029 1030 #define BXR2(isp, off) bus_read_2((isp)->isp_regs, (off)) 1031 #define BXW2(isp, off, v) bus_write_2((isp)->isp_regs, (off), (v)) 1032 #define BXR4(isp, off) bus_read_4((isp)->isp_regs, (off)) 1033 #define BXW4(isp, off, v) bus_write_4((isp)->isp_regs, (off), (v)) 1034 #define B2R4(isp, off) bus_read_4((isp)->isp_regs2, (off)) 1035 #define B2W4(isp, off, v) bus_write_4((isp)->isp_regs2, (off), (v)) 1036 1037 static ISP_INLINE uint16_t 1038 isp_pci_rd_debounced(ispsoftc_t *isp, int off) 1039 { 1040 uint16_t val, prev; 1041 1042 val = BXR2(isp, IspVirt2Off(isp, off)); 1043 do { 1044 prev = val; 1045 val = BXR2(isp, IspVirt2Off(isp, off)); 1046 } while (val != prev); 1047 return (val); 1048 } 1049 1050 static void 1051 isp_pci_run_isr(ispsoftc_t *isp) 1052 { 1053 uint16_t isr, sema, info; 1054 1055 if (IS_2100(isp)) { 1056 isr = isp_pci_rd_debounced(isp, BIU_ISR); 1057 sema = isp_pci_rd_debounced(isp, BIU_SEMA); 1058 } else { 1059 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1060 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1061 } 1062 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1063 isr &= INT_PENDING_MASK(isp); 1064 sema &= BIU_SEMA_LOCK; 1065 if (isr == 0 && sema == 0) 1066 return; 1067 if (sema != 0) { 1068 if (IS_2100(isp)) 1069 info = isp_pci_rd_debounced(isp, OUTMAILBOX0); 1070 else 1071 info = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1072 if (info & MBOX_COMMAND_COMPLETE) 1073 isp_intr_mbox(isp, info); 1074 else 1075 isp_intr_async(isp, info); 1076 if (!IS_FC(isp) && isp->isp_state == ISP_RUNSTATE) 1077 isp_intr_respq(isp); 1078 } else 1079 isp_intr_respq(isp); 1080 ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); 1081 if (sema) 1082 ISP_WRITE(isp, BIU_SEMA, 0); 1083 } 1084 1085 static void 1086 isp_pci_run_isr_2300(ispsoftc_t *isp) 1087 { 1088 uint32_t hccr, r2hisr; 1089 uint16_t isr, info; 1090 1091 if ((BXR2(isp, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT) == 0) 1092 return; 1093 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1094 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1095 if ((r2hisr & BIU_R2HST_INTR) == 0) 1096 return; 1097 isr = r2hisr & BIU_R2HST_ISTAT_MASK; 1098 info = r2hisr >> 16; 1099 switch (isr) { 1100 case ISPR2HST_ROM_MBX_OK: 1101 case ISPR2HST_ROM_MBX_FAIL: 1102 case ISPR2HST_MBX_OK: 1103 case ISPR2HST_MBX_FAIL: 1104 isp_intr_mbox(isp, info); 1105 break; 1106 case ISPR2HST_ASYNC_EVENT: 1107 isp_intr_async(isp, info); 1108 break; 1109 case ISPR2HST_RIO_16: 1110 isp_intr_async(isp, ASYNC_RIO16_1); 1111 break; 1112 case ISPR2HST_FPOST: 1113 isp_intr_async(isp, ASYNC_CMD_CMPLT); 1114 break; 1115 case ISPR2HST_FPOST_CTIO: 1116 isp_intr_async(isp, ASYNC_CTIO_DONE); 1117 break; 1118 case ISPR2HST_RSPQ_UPDATE: 1119 isp_intr_respq(isp); 1120 break; 1121 default: 1122 hccr = ISP_READ(isp, HCCR); 1123 if (hccr & HCCR_PAUSE) { 1124 ISP_WRITE(isp, HCCR, HCCR_RESET); 1125 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1126 ISP_WRITE(isp, BIU_ICR, 0); 1127 } else { 1128 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1129 } 1130 } 1131 ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); 1132 ISP_WRITE(isp, BIU_SEMA, 0); 1133 } 1134 1135 static void 1136 isp_pci_run_isr_2400(ispsoftc_t *isp) 1137 { 1138 uint32_t r2hisr; 1139 uint16_t isr, info; 1140 1141 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1142 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1143 if ((r2hisr & BIU_R2HST_INTR) == 0) 1144 return; 1145 isr = r2hisr & BIU_R2HST_ISTAT_MASK; 1146 info = (r2hisr >> 16); 1147 switch (isr) { 1148 case ISPR2HST_ROM_MBX_OK: 1149 case ISPR2HST_ROM_MBX_FAIL: 1150 case ISPR2HST_MBX_OK: 1151 case ISPR2HST_MBX_FAIL: 1152 isp_intr_mbox(isp, info); 1153 break; 1154 case ISPR2HST_ASYNC_EVENT: 1155 isp_intr_async(isp, info); 1156 break; 1157 case ISPR2HST_RSPQ_UPDATE: 1158 isp_intr_respq(isp); 1159 break; 1160 case ISPR2HST_RSPQ_UPDATE2: 1161 #ifdef ISP_TARGET_MODE 1162 case ISPR2HST_ATIO_RSPQ_UPDATE: 1163 #endif 1164 isp_intr_respq(isp); 1165 /* FALLTHROUGH */ 1166 #ifdef ISP_TARGET_MODE 1167 case ISPR2HST_ATIO_UPDATE: 1168 case ISPR2HST_ATIO_UPDATE2: 1169 isp_intr_atioq(isp); 1170 #endif 1171 break; 1172 default: 1173 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1174 } 1175 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1176 } 1177 1178 static uint32_t 1179 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1180 { 1181 uint16_t rv; 1182 int oldconf = 0; 1183 1184 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1185 /* 1186 * We will assume that someone has paused the RISC processor. 1187 */ 1188 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1189 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1190 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1191 } 1192 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1193 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1194 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1195 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1196 } 1197 return (rv); 1198 } 1199 1200 static void 1201 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1202 { 1203 int oldconf = 0; 1204 1205 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1206 /* 1207 * We will assume that someone has paused the RISC processor. 1208 */ 1209 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1210 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1211 oldconf | BIU_PCI_CONF1_SXP); 1212 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1213 } 1214 BXW2(isp, IspVirt2Off(isp, regoff), val); 1215 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1216 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1217 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1218 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1219 } 1220 1221 } 1222 1223 static uint32_t 1224 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1225 { 1226 uint32_t rv, oc = 0; 1227 1228 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1229 uint32_t tc; 1230 /* 1231 * We will assume that someone has paused the RISC processor. 1232 */ 1233 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1234 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1235 if (regoff & SXP_BANK1_SELECT) 1236 tc |= BIU_PCI1080_CONF1_SXP1; 1237 else 1238 tc |= BIU_PCI1080_CONF1_SXP0; 1239 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1240 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1241 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1242 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1243 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1244 oc | BIU_PCI1080_CONF1_DMA); 1245 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1246 } 1247 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1248 if (oc) { 1249 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1250 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1251 } 1252 return (rv); 1253 } 1254 1255 static void 1256 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1257 { 1258 int oc = 0; 1259 1260 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1261 uint32_t tc; 1262 /* 1263 * We will assume that someone has paused the RISC processor. 1264 */ 1265 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1266 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1267 if (regoff & SXP_BANK1_SELECT) 1268 tc |= BIU_PCI1080_CONF1_SXP1; 1269 else 1270 tc |= BIU_PCI1080_CONF1_SXP0; 1271 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1272 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1273 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1274 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1275 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1276 oc | BIU_PCI1080_CONF1_DMA); 1277 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1278 } 1279 BXW2(isp, IspVirt2Off(isp, regoff), val); 1280 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1281 if (oc) { 1282 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1283 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1284 } 1285 } 1286 1287 static uint32_t 1288 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1289 { 1290 uint32_t rv; 1291 int block = regoff & _BLK_REG_MASK; 1292 1293 switch (block) { 1294 case BIU_BLOCK: 1295 break; 1296 case MBOX_BLOCK: 1297 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1298 case SXP_BLOCK: 1299 isp_prt(isp, ISP_LOGERR, "SXP_BLOCK read at 0x%x", regoff); 1300 return (0xffffffff); 1301 case RISC_BLOCK: 1302 isp_prt(isp, ISP_LOGERR, "RISC_BLOCK read at 0x%x", regoff); 1303 return (0xffffffff); 1304 case DMA_BLOCK: 1305 isp_prt(isp, ISP_LOGERR, "DMA_BLOCK read at 0x%x", regoff); 1306 return (0xffffffff); 1307 default: 1308 isp_prt(isp, ISP_LOGERR, "unknown block read at 0x%x", regoff); 1309 return (0xffffffff); 1310 } 1311 1312 switch (regoff) { 1313 case BIU2400_FLASH_ADDR: 1314 case BIU2400_FLASH_DATA: 1315 case BIU2400_ICR: 1316 case BIU2400_ISR: 1317 case BIU2400_CSR: 1318 case BIU2400_REQINP: 1319 case BIU2400_REQOUTP: 1320 case BIU2400_RSPINP: 1321 case BIU2400_RSPOUTP: 1322 case BIU2400_PRI_REQINP: 1323 case BIU2400_PRI_REQOUTP: 1324 case BIU2400_ATIO_RSPINP: 1325 case BIU2400_ATIO_RSPOUTP: 1326 case BIU2400_HCCR: 1327 case BIU2400_GPIOD: 1328 case BIU2400_GPIOE: 1329 case BIU2400_HSEMA: 1330 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1331 break; 1332 case BIU2400_R2HSTSLO: 1333 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1334 break; 1335 case BIU2400_R2HSTSHI: 1336 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1337 break; 1338 default: 1339 isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x", 1340 regoff); 1341 rv = 0xffffffff; 1342 break; 1343 } 1344 return (rv); 1345 } 1346 1347 static void 1348 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1349 { 1350 int block = regoff & _BLK_REG_MASK; 1351 1352 switch (block) { 1353 case BIU_BLOCK: 1354 break; 1355 case MBOX_BLOCK: 1356 BXW2(isp, IspVirt2Off(isp, regoff), val); 1357 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1358 return; 1359 case SXP_BLOCK: 1360 isp_prt(isp, ISP_LOGERR, "SXP_BLOCK write at 0x%x", regoff); 1361 return; 1362 case RISC_BLOCK: 1363 isp_prt(isp, ISP_LOGERR, "RISC_BLOCK write at 0x%x", regoff); 1364 return; 1365 case DMA_BLOCK: 1366 isp_prt(isp, ISP_LOGERR, "DMA_BLOCK write at 0x%x", regoff); 1367 return; 1368 default: 1369 isp_prt(isp, ISP_LOGERR, "unknown block write at 0x%x", regoff); 1370 break; 1371 } 1372 1373 switch (regoff) { 1374 case BIU2400_FLASH_ADDR: 1375 case BIU2400_FLASH_DATA: 1376 case BIU2400_ICR: 1377 case BIU2400_ISR: 1378 case BIU2400_CSR: 1379 case BIU2400_REQINP: 1380 case BIU2400_REQOUTP: 1381 case BIU2400_RSPINP: 1382 case BIU2400_RSPOUTP: 1383 case BIU2400_PRI_REQINP: 1384 case BIU2400_PRI_REQOUTP: 1385 case BIU2400_ATIO_RSPINP: 1386 case BIU2400_ATIO_RSPOUTP: 1387 case BIU2400_HCCR: 1388 case BIU2400_GPIOD: 1389 case BIU2400_GPIOE: 1390 case BIU2400_HSEMA: 1391 BXW4(isp, IspVirt2Off(isp, regoff), val); 1392 #ifdef MEMORYBARRIERW 1393 if (regoff == BIU2400_REQINP || 1394 regoff == BIU2400_RSPOUTP || 1395 regoff == BIU2400_PRI_REQINP || 1396 regoff == BIU2400_ATIO_RSPOUTP) 1397 MEMORYBARRIERW(isp, SYNC_REG, 1398 IspVirt2Off(isp, regoff), 4, -1) 1399 else 1400 #endif 1401 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1402 break; 1403 default: 1404 isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x", 1405 regoff); 1406 break; 1407 } 1408 } 1409 1410 static uint32_t 1411 isp_pci_rd_reg_2600(ispsoftc_t *isp, int regoff) 1412 { 1413 uint32_t rv; 1414 1415 switch (regoff) { 1416 case BIU2400_PRI_REQINP: 1417 case BIU2400_PRI_REQOUTP: 1418 isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x", 1419 regoff); 1420 rv = 0xffffffff; 1421 break; 1422 case BIU2400_REQINP: 1423 rv = B2R4(isp, 0x00); 1424 break; 1425 case BIU2400_REQOUTP: 1426 rv = B2R4(isp, 0x04); 1427 break; 1428 case BIU2400_RSPINP: 1429 rv = B2R4(isp, 0x08); 1430 break; 1431 case BIU2400_RSPOUTP: 1432 rv = B2R4(isp, 0x0c); 1433 break; 1434 case BIU2400_ATIO_RSPINP: 1435 rv = B2R4(isp, 0x10); 1436 break; 1437 case BIU2400_ATIO_RSPOUTP: 1438 rv = B2R4(isp, 0x14); 1439 break; 1440 default: 1441 rv = isp_pci_rd_reg_2400(isp, regoff); 1442 break; 1443 } 1444 return (rv); 1445 } 1446 1447 static void 1448 isp_pci_wr_reg_2600(ispsoftc_t *isp, int regoff, uint32_t val) 1449 { 1450 int off; 1451 1452 switch (regoff) { 1453 case BIU2400_PRI_REQINP: 1454 case BIU2400_PRI_REQOUTP: 1455 isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x", 1456 regoff); 1457 return; 1458 case BIU2400_REQINP: 1459 off = 0x00; 1460 break; 1461 case BIU2400_REQOUTP: 1462 off = 0x04; 1463 break; 1464 case BIU2400_RSPINP: 1465 off = 0x08; 1466 break; 1467 case BIU2400_RSPOUTP: 1468 off = 0x0c; 1469 break; 1470 case BIU2400_ATIO_RSPINP: 1471 off = 0x10; 1472 break; 1473 case BIU2400_ATIO_RSPOUTP: 1474 off = 0x14; 1475 break; 1476 default: 1477 isp_pci_wr_reg_2400(isp, regoff, val); 1478 return; 1479 } 1480 B2W4(isp, off, val); 1481 } 1482 1483 1484 struct imush { 1485 bus_addr_t maddr; 1486 int error; 1487 }; 1488 1489 static void 1490 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1491 { 1492 struct imush *imushp = (struct imush *) arg; 1493 1494 if (!(imushp->error = error)) 1495 imushp->maddr = segs[0].ds_addr; 1496 } 1497 1498 static int 1499 isp_pci_mbxdma(ispsoftc_t *isp) 1500 { 1501 caddr_t base; 1502 uint32_t len, nsegs; 1503 int i, error, cmap = 0; 1504 bus_size_t slim; /* segment size */ 1505 bus_addr_t llim; /* low limit of unavailable dma */ 1506 bus_addr_t hlim; /* high limit of unavailable dma */ 1507 struct imush im; 1508 isp_ecmd_t *ecmd; 1509 1510 /* Already been here? If so, leave... */ 1511 if (isp->isp_xflist != NULL) 1512 return (0); 1513 if (isp->isp_rquest != NULL && isp->isp_maxcmds == 0) 1514 return (0); 1515 ISP_UNLOCK(isp); 1516 if (isp->isp_rquest != NULL) 1517 goto gotmaxcmds; 1518 1519 hlim = BUS_SPACE_MAXADDR; 1520 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1521 if (sizeof (bus_size_t) > 4) 1522 slim = (bus_size_t) (1ULL << 32); 1523 else 1524 slim = (bus_size_t) (1UL << 31); 1525 llim = BUS_SPACE_MAXADDR; 1526 } else { 1527 slim = (1UL << 24); 1528 llim = BUS_SPACE_MAXADDR_32BIT; 1529 } 1530 if (sizeof (bus_size_t) > 4) 1531 nsegs = ISP_NSEG64_MAX; 1532 else 1533 nsegs = ISP_NSEG_MAX; 1534 1535 if (bus_dma_tag_create(bus_get_dma_tag(ISP_PCD(isp)), 1, 1536 slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, 1537 busdma_lock_mutex, &isp->isp_lock, &isp->isp_osinfo.dmat)) { 1538 ISP_LOCK(isp); 1539 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1540 return (1); 1541 } 1542 1543 /* 1544 * Allocate and map the request queue and a region for external 1545 * DMA addressable command/status structures (22XX and later). 1546 */ 1547 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1548 if (isp->isp_type >= ISP_HA_FC_2200) 1549 len += (N_XCMDS * XCMD_SIZE); 1550 if (bus_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, 1551 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1552 len, 1, len, 0, busdma_lock_mutex, &isp->isp_lock, 1553 &isp->isp_osinfo.reqdmat)) { 1554 isp_prt(isp, ISP_LOGERR, "cannot create request DMA tag"); 1555 goto bad; 1556 } 1557 if (bus_dmamem_alloc(isp->isp_osinfo.reqdmat, (void **)&base, 1558 BUS_DMA_COHERENT, &isp->isp_osinfo.reqmap) != 0) { 1559 isp_prt(isp, ISP_LOGERR, "cannot allocate request DMA memory"); 1560 bus_dma_tag_destroy(isp->isp_osinfo.reqdmat); 1561 goto bad; 1562 } 1563 isp->isp_rquest = base; 1564 im.error = 0; 1565 if (bus_dmamap_load(isp->isp_osinfo.reqdmat, isp->isp_osinfo.reqmap, 1566 base, len, imc, &im, 0) || im.error) { 1567 isp_prt(isp, ISP_LOGERR, "error loading request DMA map %d", im.error); 1568 goto bad; 1569 } 1570 isp_prt(isp, ISP_LOGDEBUG0, "request area @ 0x%jx/0x%jx", 1571 (uintmax_t)im.maddr, (uintmax_t)len); 1572 isp->isp_rquest_dma = im.maddr; 1573 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1574 im.maddr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1575 if (isp->isp_type >= ISP_HA_FC_2200) { 1576 isp->isp_osinfo.ecmd_dma = im.maddr; 1577 isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)base; 1578 isp->isp_osinfo.ecmd_base = isp->isp_osinfo.ecmd_free; 1579 for (ecmd = isp->isp_osinfo.ecmd_free; 1580 ecmd < &isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) { 1581 if (ecmd == &isp->isp_osinfo.ecmd_free[N_XCMDS - 1]) 1582 ecmd->next = NULL; 1583 else 1584 ecmd->next = ecmd + 1; 1585 } 1586 } 1587 1588 /* 1589 * Allocate and map the result queue. 1590 */ 1591 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1592 if (bus_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, 1593 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1594 len, 1, len, 0, busdma_lock_mutex, &isp->isp_lock, 1595 &isp->isp_osinfo.respdmat)) { 1596 isp_prt(isp, ISP_LOGERR, "cannot create response DMA tag"); 1597 goto bad; 1598 } 1599 if (bus_dmamem_alloc(isp->isp_osinfo.respdmat, (void **)&base, 1600 BUS_DMA_COHERENT, &isp->isp_osinfo.respmap) != 0) { 1601 isp_prt(isp, ISP_LOGERR, "cannot allocate response DMA memory"); 1602 bus_dma_tag_destroy(isp->isp_osinfo.respdmat); 1603 goto bad; 1604 } 1605 isp->isp_result = base; 1606 im.error = 0; 1607 if (bus_dmamap_load(isp->isp_osinfo.respdmat, isp->isp_osinfo.respmap, 1608 base, len, imc, &im, 0) || im.error) { 1609 isp_prt(isp, ISP_LOGERR, "error loading response DMA map %d", im.error); 1610 goto bad; 1611 } 1612 isp_prt(isp, ISP_LOGDEBUG0, "response area @ 0x%jx/0x%jx", 1613 (uintmax_t)im.maddr, (uintmax_t)len); 1614 isp->isp_result_dma = im.maddr; 1615 1616 #ifdef ISP_TARGET_MODE 1617 /* 1618 * Allocate and map ATIO queue on 24xx with target mode. 1619 */ 1620 if (IS_24XX(isp)) { 1621 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1622 if (bus_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, 1623 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1624 len, 1, len, 0, busdma_lock_mutex, &isp->isp_lock, 1625 &isp->isp_osinfo.atiodmat)) { 1626 isp_prt(isp, ISP_LOGERR, "cannot create ATIO DMA tag"); 1627 goto bad; 1628 } 1629 if (bus_dmamem_alloc(isp->isp_osinfo.atiodmat, (void **)&base, 1630 BUS_DMA_COHERENT, &isp->isp_osinfo.atiomap) != 0) { 1631 isp_prt(isp, ISP_LOGERR, "cannot allocate ATIO DMA memory"); 1632 bus_dma_tag_destroy(isp->isp_osinfo.atiodmat); 1633 goto bad; 1634 } 1635 isp->isp_atioq = base; 1636 im.error = 0; 1637 if (bus_dmamap_load(isp->isp_osinfo.atiodmat, isp->isp_osinfo.atiomap, 1638 base, len, imc, &im, 0) || im.error) { 1639 isp_prt(isp, ISP_LOGERR, "error loading ATIO DMA map %d", im.error); 1640 goto bad; 1641 } 1642 isp_prt(isp, ISP_LOGDEBUG0, "ATIO area @ 0x%jx/0x%jx", 1643 (uintmax_t)im.maddr, (uintmax_t)len); 1644 isp->isp_atioq_dma = im.maddr; 1645 } 1646 #endif 1647 1648 if (IS_FC(isp)) { 1649 if (bus_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, 1650 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1651 2*QENTRY_LEN, 1, 2*QENTRY_LEN, 0, busdma_lock_mutex, 1652 &isp->isp_lock, &isp->isp_osinfo.iocbdmat)) { 1653 goto bad; 1654 } 1655 if (bus_dmamem_alloc(isp->isp_osinfo.iocbdmat, 1656 (void **)&base, BUS_DMA_COHERENT, &isp->isp_osinfo.iocbmap) != 0) 1657 goto bad; 1658 isp->isp_iocb = base; 1659 im.error = 0; 1660 if (bus_dmamap_load(isp->isp_osinfo.iocbdmat, isp->isp_osinfo.iocbmap, 1661 base, 2*QENTRY_LEN, imc, &im, 0) || im.error) 1662 goto bad; 1663 isp->isp_iocb_dma = im.maddr; 1664 1665 if (bus_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, 1666 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1667 ISP_FC_SCRLEN, 1, ISP_FC_SCRLEN, 0, busdma_lock_mutex, 1668 &isp->isp_lock, &isp->isp_osinfo.scdmat)) 1669 goto bad; 1670 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1671 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1672 if (bus_dmamem_alloc(isp->isp_osinfo.scdmat, 1673 (void **)&base, BUS_DMA_COHERENT, &fc->scmap) != 0) 1674 goto bad; 1675 FCPARAM(isp, cmap)->isp_scratch = base; 1676 im.error = 0; 1677 if (bus_dmamap_load(isp->isp_osinfo.scdmat, fc->scmap, 1678 base, ISP_FC_SCRLEN, imc, &im, 0) || im.error) { 1679 bus_dmamem_free(isp->isp_osinfo.scdmat, 1680 base, fc->scmap); 1681 FCPARAM(isp, cmap)->isp_scratch = NULL; 1682 goto bad; 1683 } 1684 FCPARAM(isp, cmap)->isp_scdma = im.maddr; 1685 if (!IS_2100(isp)) { 1686 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) { 1687 struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO); 1688 if (n == NULL) { 1689 while (fc->nexus_free_list) { 1690 n = fc->nexus_free_list; 1691 fc->nexus_free_list = n->next; 1692 free(n, M_DEVBUF); 1693 } 1694 goto bad; 1695 } 1696 n->next = fc->nexus_free_list; 1697 fc->nexus_free_list = n; 1698 } 1699 } 1700 } 1701 } 1702 1703 if (isp->isp_maxcmds == 0) { 1704 ISP_LOCK(isp); 1705 return (0); 1706 } 1707 1708 gotmaxcmds: 1709 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1710 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) 1711 malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1712 for (i = 0; i < isp->isp_maxcmds; i++) { 1713 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1714 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1715 if (error) { 1716 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1717 while (--i >= 0) { 1718 bus_dmamap_destroy(isp->isp_osinfo.dmat, 1719 isp->isp_osinfo.pcmd_pool[i].dmap); 1720 } 1721 goto bad; 1722 } 1723 callout_init_mtx(&pcmd->wdog, &isp->isp_lock, 0); 1724 if (i == isp->isp_maxcmds-1) 1725 pcmd->next = NULL; 1726 else 1727 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1728 } 1729 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1730 1731 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1732 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1733 for (len = 0; len < isp->isp_maxcmds - 1; len++) 1734 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1735 isp->isp_xffree = isp->isp_xflist; 1736 1737 ISP_LOCK(isp); 1738 return (0); 1739 1740 bad: 1741 isp_pci_mbxdmafree(isp); 1742 ISP_LOCK(isp); 1743 return (1); 1744 } 1745 1746 static void 1747 isp_pci_mbxdmafree(ispsoftc_t *isp) 1748 { 1749 int i; 1750 1751 if (isp->isp_xflist != NULL) { 1752 free(isp->isp_xflist, M_DEVBUF); 1753 isp->isp_xflist = NULL; 1754 } 1755 if (isp->isp_osinfo.pcmd_pool != NULL) { 1756 for (i = 0; i < isp->isp_maxcmds; i++) { 1757 bus_dmamap_destroy(isp->isp_osinfo.dmat, 1758 isp->isp_osinfo.pcmd_pool[i].dmap); 1759 } 1760 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1761 isp->isp_osinfo.pcmd_pool = NULL; 1762 } 1763 if (IS_FC(isp)) { 1764 for (i = 0; i < isp->isp_nchan; i++) { 1765 struct isp_fc *fc = ISP_FC_PC(isp, i); 1766 if (FCPARAM(isp, i)->isp_scdma != 0) { 1767 bus_dmamap_unload(isp->isp_osinfo.scdmat, 1768 fc->scmap); 1769 FCPARAM(isp, i)->isp_scdma = 0; 1770 } 1771 if (FCPARAM(isp, i)->isp_scratch != NULL) { 1772 bus_dmamem_free(isp->isp_osinfo.scdmat, 1773 FCPARAM(isp, i)->isp_scratch, fc->scmap); 1774 FCPARAM(isp, i)->isp_scratch = NULL; 1775 } 1776 while (fc->nexus_free_list) { 1777 struct isp_nexus *n = fc->nexus_free_list; 1778 fc->nexus_free_list = n->next; 1779 free(n, M_DEVBUF); 1780 } 1781 } 1782 if (isp->isp_iocb_dma != 0) { 1783 bus_dma_tag_destroy(isp->isp_osinfo.scdmat); 1784 bus_dmamap_unload(isp->isp_osinfo.iocbdmat, 1785 isp->isp_osinfo.iocbmap); 1786 isp->isp_iocb_dma = 0; 1787 } 1788 if (isp->isp_iocb != NULL) { 1789 bus_dmamem_free(isp->isp_osinfo.iocbdmat, 1790 isp->isp_iocb, isp->isp_osinfo.iocbmap); 1791 bus_dma_tag_destroy(isp->isp_osinfo.iocbdmat); 1792 } 1793 } 1794 #ifdef ISP_TARGET_MODE 1795 if (IS_24XX(isp)) { 1796 if (isp->isp_atioq_dma != 0) { 1797 bus_dmamap_unload(isp->isp_osinfo.atiodmat, 1798 isp->isp_osinfo.atiomap); 1799 isp->isp_atioq_dma = 0; 1800 } 1801 if (isp->isp_atioq != NULL) { 1802 bus_dmamem_free(isp->isp_osinfo.atiodmat, isp->isp_atioq, 1803 isp->isp_osinfo.atiomap); 1804 bus_dma_tag_destroy(isp->isp_osinfo.atiodmat); 1805 isp->isp_atioq = NULL; 1806 } 1807 } 1808 #endif 1809 if (isp->isp_result_dma != 0) { 1810 bus_dmamap_unload(isp->isp_osinfo.respdmat, 1811 isp->isp_osinfo.respmap); 1812 isp->isp_result_dma = 0; 1813 } 1814 if (isp->isp_result != NULL) { 1815 bus_dmamem_free(isp->isp_osinfo.respdmat, isp->isp_result, 1816 isp->isp_osinfo.respmap); 1817 bus_dma_tag_destroy(isp->isp_osinfo.respdmat); 1818 isp->isp_result = NULL; 1819 } 1820 if (isp->isp_rquest_dma != 0) { 1821 bus_dmamap_unload(isp->isp_osinfo.reqdmat, 1822 isp->isp_osinfo.reqmap); 1823 isp->isp_rquest_dma = 0; 1824 } 1825 if (isp->isp_rquest != NULL) { 1826 bus_dmamem_free(isp->isp_osinfo.reqdmat, isp->isp_rquest, 1827 isp->isp_osinfo.reqmap); 1828 bus_dma_tag_destroy(isp->isp_osinfo.reqdmat); 1829 isp->isp_rquest = NULL; 1830 } 1831 } 1832 1833 typedef struct { 1834 ispsoftc_t *isp; 1835 void *cmd_token; 1836 void *rq; /* original request */ 1837 int error; 1838 } mush_t; 1839 1840 #define MUSHERR_NOQENTRIES -2 1841 1842 static void 1843 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1844 { 1845 mush_t *mp = (mush_t *) arg; 1846 ispsoftc_t *isp= mp->isp; 1847 struct ccb_scsiio *csio = mp->cmd_token; 1848 isp_ddir_t ddir; 1849 int sdir; 1850 1851 if (error) { 1852 mp->error = error; 1853 return; 1854 } 1855 if (nseg == 0) { 1856 ddir = ISP_NOXFR; 1857 } else { 1858 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1859 ddir = ISP_FROM_DEVICE; 1860 } else { 1861 ddir = ISP_TO_DEVICE; 1862 } 1863 if ((csio->ccb_h.func_code == XPT_CONT_TARGET_IO) ^ 1864 ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)) { 1865 sdir = BUS_DMASYNC_PREREAD; 1866 } else { 1867 sdir = BUS_DMASYNC_PREWRITE; 1868 } 1869 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, 1870 sdir); 1871 } 1872 1873 error = isp_send_cmd(isp, mp->rq, dm_segs, nseg, XS_XFRLEN(csio), 1874 ddir, (ispds64_t *)csio->req_map); 1875 switch (error) { 1876 case CMD_EAGAIN: 1877 mp->error = MUSHERR_NOQENTRIES; 1878 break; 1879 case CMD_QUEUED: 1880 break; 1881 default: 1882 mp->error = EIO; 1883 break; 1884 } 1885 } 1886 1887 static int 1888 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1889 { 1890 mush_t mush, *mp; 1891 int error; 1892 1893 mp = &mush; 1894 mp->isp = isp; 1895 mp->cmd_token = csio; 1896 mp->rq = ff; 1897 mp->error = 0; 1898 1899 error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, 1900 (union ccb *)csio, dma2, mp, 0); 1901 if (error == EINPROGRESS) { 1902 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1903 mp->error = EINVAL; 1904 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1905 } else if (error && mp->error == 0) { 1906 #ifdef DIAGNOSTIC 1907 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1908 #endif 1909 mp->error = error; 1910 } 1911 if (mp->error) { 1912 int retval = CMD_COMPLETE; 1913 if (mp->error == MUSHERR_NOQENTRIES) { 1914 retval = CMD_EAGAIN; 1915 } else if (mp->error == EFBIG) { 1916 csio->ccb_h.status = CAM_REQ_TOO_BIG; 1917 } else if (mp->error == EINVAL) { 1918 csio->ccb_h.status = CAM_REQ_INVALID; 1919 } else { 1920 csio->ccb_h.status = CAM_UNREC_HBA_ERROR; 1921 } 1922 return (retval); 1923 } 1924 return (CMD_QUEUED); 1925 } 1926 1927 static int 1928 isp_pci_irqsetup(ispsoftc_t *isp) 1929 { 1930 device_t dev = isp->isp_osinfo.dev; 1931 struct isp_pcisoftc *pcs = device_get_softc(dev); 1932 driver_intr_t *f; 1933 int i, max_irq; 1934 1935 /* Allocate IRQs only once. */ 1936 if (isp->isp_nirq > 0) 1937 return (0); 1938 1939 ISP_UNLOCK(isp); 1940 if (ISP_CAP_MSIX(isp)) { 1941 max_irq = min(ISP_MAX_IRQS, IS_26XX(isp) ? 3 : 2); 1942 pcs->msicount = imin(pci_msix_count(dev), max_irq); 1943 if (pcs->msicount > 0 && 1944 pci_alloc_msix(dev, &pcs->msicount) != 0) 1945 pcs->msicount = 0; 1946 } 1947 if (pcs->msicount == 0) { 1948 pcs->msicount = imin(pci_msi_count(dev), 1); 1949 if (pcs->msicount > 0 && 1950 pci_alloc_msi(dev, &pcs->msicount) != 0) 1951 pcs->msicount = 0; 1952 } 1953 for (i = 0; i < MAX(1, pcs->msicount); i++) { 1954 pcs->irq[i].iqd = i + (pcs->msicount > 0); 1955 pcs->irq[i].irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1956 &pcs->irq[i].iqd, RF_ACTIVE | RF_SHAREABLE); 1957 if (pcs->irq[i].irq == NULL) { 1958 device_printf(dev, "could not allocate interrupt\n"); 1959 break; 1960 } 1961 if (i == 0) 1962 f = isp_platform_intr; 1963 else if (i == 1) 1964 f = isp_platform_intr_resp; 1965 else 1966 f = isp_platform_intr_atio; 1967 if (bus_setup_intr(dev, pcs->irq[i].irq, ISP_IFLAGS, NULL, 1968 f, isp, &pcs->irq[i].ih)) { 1969 device_printf(dev, "could not setup interrupt\n"); 1970 (void) bus_release_resource(dev, SYS_RES_IRQ, 1971 pcs->irq[i].iqd, pcs->irq[i].irq); 1972 break; 1973 } 1974 if (pcs->msicount > 1) { 1975 bus_describe_intr(dev, pcs->irq[i].irq, pcs->irq[i].ih, 1976 "%d", i); 1977 } 1978 isp->isp_nirq = i + 1; 1979 } 1980 ISP_LOCK(isp); 1981 1982 return (isp->isp_nirq == 0); 1983 } 1984 1985 static void 1986 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1987 { 1988 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1989 if (msg) 1990 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1991 else 1992 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1993 if (IS_SCSI(isp)) 1994 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1995 else 1996 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1997 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1998 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1999 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 2000 2001 2002 if (IS_SCSI(isp)) { 2003 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 2004 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 2005 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 2006 ISP_READ(isp, CDMA_FIFO_STS)); 2007 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 2008 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 2009 ISP_READ(isp, DDMA_FIFO_STS)); 2010 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 2011 ISP_READ(isp, SXP_INTERRUPT), 2012 ISP_READ(isp, SXP_GROSS_ERR), 2013 ISP_READ(isp, SXP_PINS_CTRL)); 2014 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2015 } 2016 printf(" mbox regs: %x %x %x %x %x\n", 2017 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2018 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2019 ISP_READ(isp, OUTMAILBOX4)); 2020 printf(" PCI Status Command/Status=%x\n", 2021 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2022 } 2023