1 /* $FreeBSD$ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * FreeBSD Version. 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 36 #include <pci/pcireg.h> 37 #include <pci/pcivar.h> 38 39 #include <machine/bus_memio.h> 40 #include <machine/bus_pio.h> 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 46 #include <dev/isp/isp_freebsd.h> 47 48 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int)); 49 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t)); 50 static u_int16_t isp_pci_rd_reg_1080 __P((struct ispsoftc *, int)); 51 static void isp_pci_wr_reg_1080 __P((struct ispsoftc *, int, u_int16_t)); 52 static int isp_pci_mbxdma __P((struct ispsoftc *)); 53 static int isp_pci_dmasetup __P((struct ispsoftc *, XS_T *, 54 ispreq_t *, u_int16_t *, u_int16_t)); 55 static void 56 isp_pci_dmateardown __P((struct ispsoftc *, XS_T *, u_int32_t)); 57 58 static void isp_pci_reset1 __P((struct ispsoftc *)); 59 static void isp_pci_dumpregs __P((struct ispsoftc *, const char *)); 60 61 #ifndef ISP_CODE_ORG 62 #define ISP_CODE_ORG 0x1000 63 #endif 64 65 static struct ispmdvec mdvec = { 66 isp_pci_rd_reg, 67 isp_pci_wr_reg, 68 isp_pci_mbxdma, 69 isp_pci_dmasetup, 70 isp_pci_dmateardown, 71 NULL, 72 isp_pci_reset1, 73 isp_pci_dumpregs, 74 NULL, 75 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 76 }; 77 78 static struct ispmdvec mdvec_1080 = { 79 isp_pci_rd_reg_1080, 80 isp_pci_wr_reg_1080, 81 isp_pci_mbxdma, 82 isp_pci_dmasetup, 83 isp_pci_dmateardown, 84 NULL, 85 isp_pci_reset1, 86 isp_pci_dumpregs, 87 NULL, 88 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 89 }; 90 91 static struct ispmdvec mdvec_12160 = { 92 isp_pci_rd_reg_1080, 93 isp_pci_wr_reg_1080, 94 isp_pci_mbxdma, 95 isp_pci_dmasetup, 96 isp_pci_dmateardown, 97 NULL, 98 isp_pci_reset1, 99 isp_pci_dumpregs, 100 NULL, 101 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 102 }; 103 104 static struct ispmdvec mdvec_2100 = { 105 isp_pci_rd_reg, 106 isp_pci_wr_reg, 107 isp_pci_mbxdma, 108 isp_pci_dmasetup, 109 isp_pci_dmateardown, 110 NULL, 111 isp_pci_reset1, 112 isp_pci_dumpregs 113 }; 114 115 static struct ispmdvec mdvec_2200 = { 116 isp_pci_rd_reg, 117 isp_pci_wr_reg, 118 isp_pci_mbxdma, 119 isp_pci_dmasetup, 120 isp_pci_dmateardown, 121 NULL, 122 isp_pci_reset1, 123 isp_pci_dumpregs 124 }; 125 126 #ifndef PCIM_CMD_INVEN 127 #define PCIM_CMD_INVEN 0x10 128 #endif 129 #ifndef PCIM_CMD_BUSMASTEREN 130 #define PCIM_CMD_BUSMASTEREN 0x0004 131 #endif 132 #ifndef PCIM_CMD_PERRESPEN 133 #define PCIM_CMD_PERRESPEN 0x0040 134 #endif 135 #ifndef PCIM_CMD_SEREN 136 #define PCIM_CMD_SEREN 0x0100 137 #endif 138 139 #ifndef PCIR_COMMAND 140 #define PCIR_COMMAND 0x04 141 #endif 142 143 #ifndef PCIR_CACHELNSZ 144 #define PCIR_CACHELNSZ 0x0c 145 #endif 146 147 #ifndef PCIR_LATTIMER 148 #define PCIR_LATTIMER 0x0d 149 #endif 150 151 #ifndef PCIR_ROMADDR 152 #define PCIR_ROMADDR 0x30 153 #endif 154 155 #ifndef PCI_VENDOR_QLOGIC 156 #define PCI_VENDOR_QLOGIC 0x1077 157 #endif 158 159 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 160 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 161 #endif 162 163 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 164 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 165 #endif 166 167 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 168 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 169 #endif 170 171 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 172 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 173 #endif 174 175 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 176 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 177 #endif 178 179 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 180 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 181 #endif 182 183 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 184 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 185 #endif 186 187 #define PCI_QLOGIC_ISP1020 \ 188 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 189 190 #define PCI_QLOGIC_ISP1080 \ 191 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 192 193 #define PCI_QLOGIC_ISP12160 \ 194 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 195 196 #define PCI_QLOGIC_ISP1240 \ 197 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 198 199 #define PCI_QLOGIC_ISP1280 \ 200 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 201 202 #define PCI_QLOGIC_ISP2100 \ 203 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 204 205 #define PCI_QLOGIC_ISP2200 \ 206 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 207 208 /* 209 * Odd case for some AMI raid cards... We need to *not* attach to this. 210 */ 211 #define AMI_RAID_SUBVENDOR_ID 0x101e 212 213 #define IO_MAP_REG 0x10 214 #define MEM_MAP_REG 0x14 215 216 #define PCI_DFLT_LTNCY 0x40 217 #define PCI_DFLT_LNSZ 0x10 218 219 static int isp_pci_probe (device_t); 220 static int isp_pci_attach (device_t); 221 222 struct isp_pcisoftc { 223 struct ispsoftc pci_isp; 224 device_t pci_dev; 225 struct resource * pci_reg; 226 bus_space_tag_t pci_st; 227 bus_space_handle_t pci_sh; 228 void * ih; 229 int16_t pci_poff[_NREG_BLKS]; 230 bus_dma_tag_t parent_dmat; 231 bus_dma_tag_t cntrol_dmat; 232 bus_dmamap_t cntrol_dmap; 233 bus_dmamap_t *dmaps; 234 }; 235 ispfwfunc *isp_get_firmware_p = NULL; 236 237 static device_method_t isp_pci_methods[] = { 238 /* Device interface */ 239 DEVMETHOD(device_probe, isp_pci_probe), 240 DEVMETHOD(device_attach, isp_pci_attach), 241 { 0, 0 } 242 }; 243 static void isp_pci_intr __P((void *)); 244 245 static driver_t isp_pci_driver = { 246 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 247 }; 248 static devclass_t isp_devclass; 249 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 250 MODULE_VERSION(isp, 1); 251 252 static int 253 isp_pci_probe(device_t dev) 254 { 255 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 256 case PCI_QLOGIC_ISP1020: 257 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 258 break; 259 case PCI_QLOGIC_ISP1080: 260 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 261 break; 262 case PCI_QLOGIC_ISP1240: 263 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 264 break; 265 case PCI_QLOGIC_ISP1280: 266 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 267 break; 268 case PCI_QLOGIC_ISP12160: 269 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 270 return (ENXIO); 271 } 272 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 273 break; 274 case PCI_QLOGIC_ISP2100: 275 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 276 break; 277 case PCI_QLOGIC_ISP2200: 278 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 279 break; 280 default: 281 return (ENXIO); 282 } 283 if (device_get_unit(dev) == 0 && bootverbose) { 284 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 285 "Core Version %d.%d\n", 286 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 287 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 288 } 289 /* 290 * XXXX: Here is where we might load the f/w module 291 * XXXX: (or increase a reference count to it). 292 */ 293 return (0); 294 } 295 296 static int 297 isp_pci_attach(device_t dev) 298 { 299 struct resource *regs, *irq; 300 int unit, bitmap, rtp, rgd, iqd, m1, m2, isp_debug; 301 u_int32_t data, cmd, linesz, psize, basetype; 302 struct isp_pcisoftc *pcs; 303 struct ispsoftc *isp = NULL; 304 struct ispmdvec *mdvp; 305 bus_size_t lim; 306 #ifdef ISP_SMPLOCK 307 int locksetup = 0; 308 #endif 309 310 /* 311 * Figure out if we're supposed to skip this one. 312 */ 313 unit = device_get_unit(dev); 314 if (getenv_int("isp_disable", &bitmap)) { 315 if (bitmap & (1 << unit)) { 316 device_printf(dev, "not configuring\n"); 317 return (ENODEV); 318 } 319 } 320 321 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT | M_ZERO); 322 if (pcs == NULL) { 323 device_printf(dev, "cannot allocate softc\n"); 324 return (ENOMEM); 325 } 326 327 /* 328 * Figure out which we should try first - memory mapping or i/o mapping? 329 */ 330 #ifdef __alpha__ 331 m1 = PCIM_CMD_MEMEN; 332 m2 = PCIM_CMD_PORTEN; 333 #else 334 m1 = PCIM_CMD_PORTEN; 335 m2 = PCIM_CMD_MEMEN; 336 #endif 337 bitmap = 0; 338 if (getenv_int("isp_mem_map", &bitmap)) { 339 if (bitmap & (1 << unit)) { 340 m1 = PCIM_CMD_MEMEN; 341 m2 = PCIM_CMD_PORTEN; 342 } 343 } 344 bitmap = 0; 345 if (getenv_int("isp_io_map", &bitmap)) { 346 if (bitmap & (1 << unit)) { 347 m1 = PCIM_CMD_PORTEN; 348 m2 = PCIM_CMD_MEMEN; 349 } 350 } 351 352 linesz = PCI_DFLT_LNSZ; 353 irq = regs = NULL; 354 rgd = rtp = iqd = 0; 355 356 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 357 if (cmd & m1) { 358 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 359 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 360 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 361 } 362 if (regs == NULL && (cmd & m2)) { 363 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 364 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 365 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 366 } 367 if (regs == NULL) { 368 device_printf(dev, "unable to map any ports\n"); 369 goto bad; 370 } 371 if (bootverbose) 372 device_printf(dev, "using %s space register mapping\n", 373 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 374 pcs->pci_dev = dev; 375 pcs->pci_reg = regs; 376 pcs->pci_st = rman_get_bustag(regs); 377 pcs->pci_sh = rman_get_bushandle(regs); 378 379 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 380 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 381 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 382 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 383 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 384 mdvp = &mdvec; 385 basetype = ISP_HA_SCSI_UNKNOWN; 386 psize = sizeof (sdparam); 387 lim = BUS_SPACE_MAXSIZE_32BIT; 388 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 389 mdvp = &mdvec; 390 basetype = ISP_HA_SCSI_UNKNOWN; 391 psize = sizeof (sdparam); 392 lim = BUS_SPACE_MAXSIZE_24BIT; 393 } 394 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 395 mdvp = &mdvec_1080; 396 basetype = ISP_HA_SCSI_1080; 397 psize = sizeof (sdparam); 398 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 399 ISP1080_DMA_REGS_OFF; 400 } 401 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 402 mdvp = &mdvec_1080; 403 basetype = ISP_HA_SCSI_1240; 404 psize = 2 * sizeof (sdparam); 405 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 406 ISP1080_DMA_REGS_OFF; 407 } 408 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 409 mdvp = &mdvec_1080; 410 basetype = ISP_HA_SCSI_1280; 411 psize = 2 * sizeof (sdparam); 412 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 413 ISP1080_DMA_REGS_OFF; 414 } 415 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 416 mdvp = &mdvec_12160; 417 basetype = ISP_HA_SCSI_12160; 418 psize = 2 * sizeof (sdparam); 419 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 420 ISP1080_DMA_REGS_OFF; 421 } 422 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 423 mdvp = &mdvec_2100; 424 basetype = ISP_HA_FC_2100; 425 psize = sizeof (fcparam); 426 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 427 PCI_MBOX_REGS2100_OFF; 428 if (pci_get_revid(dev) < 3) { 429 /* 430 * XXX: Need to get the actual revision 431 * XXX: number of the 2100 FB. At any rate, 432 * XXX: lower cache line size for early revision 433 * XXX; boards. 434 */ 435 linesz = 1; 436 } 437 } 438 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 439 mdvp = &mdvec_2200; 440 basetype = ISP_HA_FC_2200; 441 psize = sizeof (fcparam); 442 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 443 PCI_MBOX_REGS2100_OFF; 444 } 445 isp = &pcs->pci_isp; 446 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 447 if (isp->isp_param == NULL) { 448 device_printf(dev, "cannot allocate parameter data\n"); 449 goto bad; 450 } 451 isp->isp_mdvec = mdvp; 452 isp->isp_type = basetype; 453 isp->isp_revision = pci_get_revid(dev); 454 (void) snprintf(isp->isp_name, sizeof (isp->isp_name), "isp%d", unit); 455 isp->isp_osinfo.unit = unit; 456 isp->isp_role = ISP_DEFAULT_ROLES; 457 458 /* 459 * Try and find firmware for this device. 460 */ 461 462 if (isp_get_firmware_p) { 463 int device = (int) pci_get_device(dev); 464 #ifdef ISP_TARGET_MODE 465 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 466 #else 467 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 468 #endif 469 } 470 471 /* 472 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 473 * are set. 474 */ 475 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 476 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 477 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 478 479 /* 480 * Make sure the Cache Line Size register is set sensibly. 481 */ 482 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 483 if (data != linesz) { 484 data = PCI_DFLT_LNSZ; 485 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 486 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 487 } 488 489 /* 490 * Make sure the Latency Timer is sane. 491 */ 492 data = pci_read_config(dev, PCIR_LATTIMER, 1); 493 if (data < PCI_DFLT_LTNCY) { 494 data = PCI_DFLT_LTNCY; 495 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 496 pci_write_config(dev, PCIR_LATTIMER, data, 1); 497 } 498 499 /* 500 * Make sure we've disabled the ROM. 501 */ 502 data = pci_read_config(dev, PCIR_ROMADDR, 4); 503 data &= ~1; 504 pci_write_config(dev, PCIR_ROMADDR, data, 4); 505 506 507 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 508 BUS_SPACE_MAXADDR, NULL, NULL, lim + 1, 509 255, lim, 0, &pcs->parent_dmat) != 0) { 510 device_printf(dev, "could not create master dma tag\n"); 511 free(isp->isp_param, M_DEVBUF); 512 free(pcs, M_DEVBUF); 513 return (ENXIO); 514 } 515 516 iqd = 0; 517 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 518 1, RF_ACTIVE | RF_SHAREABLE); 519 if (irq == NULL) { 520 device_printf(dev, "could not allocate interrupt\n"); 521 goto bad; 522 } 523 524 if (getenv_int("isp_no_fwload", &bitmap)) { 525 if (bitmap & (1 << unit)) 526 isp->isp_confopts |= ISP_CFG_NORELOAD; 527 } 528 if (getenv_int("isp_fwload", &bitmap)) { 529 if (bitmap & (1 << unit)) 530 isp->isp_confopts &= ~ISP_CFG_NORELOAD; 531 } 532 if (getenv_int("isp_no_nvram", &bitmap)) { 533 if (bitmap & (1 << unit)) 534 isp->isp_confopts |= ISP_CFG_NONVRAM; 535 } 536 if (getenv_int("isp_nvram", &bitmap)) { 537 if (bitmap & (1 << unit)) 538 isp->isp_confopts &= ~ISP_CFG_NONVRAM; 539 } 540 if (getenv_int("isp_fcduplex", &bitmap)) { 541 if (bitmap & (1 << unit)) 542 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 543 } 544 if (getenv_int("isp_no_fcduplex", &bitmap)) { 545 if (bitmap & (1 << unit)) 546 isp->isp_confopts &= ~ISP_CFG_FULL_DUPLEX; 547 } 548 if (getenv_int("isp_nport", &bitmap)) { 549 if (bitmap & (1 << unit)) 550 isp->isp_confopts |= ISP_CFG_NPORT; 551 } 552 /* 553 * Look for overriding WWN. This is a Node WWN so it binds to 554 * all FC instances. A Port WWN will be constructed from it 555 * as appropriate. 556 */ 557 if (!getenv_quad("isp_wwn", (quad_t *) &isp->isp_osinfo.default_wwn)) { 558 int i; 559 u_int64_t seed = (u_int64_t) (intptr_t) isp; 560 561 seed <<= 16; 562 seed &= ((1LL << 48) - 1LL); 563 /* 564 * This isn't very random, but it's the best we can do for 565 * the real edge case of cards that don't have WWNs. If 566 * you recompile a new vers.c, you'll get a different WWN. 567 */ 568 for (i = 0; version[i] != 0; i++) { 569 seed += version[i]; 570 } 571 /* 572 * Make sure the top nibble has something vaguely sensible 573 * (NAA == Locally Administered) 574 */ 575 isp->isp_osinfo.default_wwn |= (3LL << 60) | seed; 576 } else { 577 isp->isp_confopts |= ISP_CFG_OWNWWN; 578 } 579 isp_debug = 0; 580 (void) getenv_int("isp_debug", &isp_debug); 581 582 #ifdef ISP_SMPLOCK 583 /* Make sure the lock is set up. */ 584 mtx_init(&isp->isp_osinfo.lock, "isp", MTX_DEF); 585 locksetup++; 586 #endif 587 588 #ifdef ISP_SMPLOCK 589 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM | INTR_MPSAFE, 590 isp_pci_intr, isp, &pcs->ih)) { 591 device_printf(dev, "could not setup interrupt\n"); 592 goto bad; 593 } 594 #else 595 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM, 596 isp_pci_intr, isp, &pcs->ih)) { 597 device_printf(dev, "could not setup interrupt\n"); 598 goto bad; 599 } 600 #endif 601 602 /* 603 * Set up logging levels. 604 */ 605 if (isp_debug) { 606 isp->isp_dblev = isp_debug; 607 } else { 608 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 609 } 610 if (bootverbose) 611 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 612 613 /* 614 * Make sure we're in reset state. 615 */ 616 ISP_LOCK(isp); 617 isp_reset(isp); 618 619 if (isp->isp_state != ISP_RESETSTATE) { 620 ISP_UNLOCK(isp); 621 goto bad; 622 } 623 isp_init(isp); 624 if (isp->isp_state != ISP_INITSTATE) { 625 /* If we're a Fibre Channel Card, we allow deferred attach */ 626 if (IS_SCSI(isp)) { 627 isp_uninit(isp); 628 ISP_UNLOCK(isp); 629 goto bad; 630 } 631 } 632 isp_attach(isp); 633 if (isp->isp_state != ISP_RUNSTATE) { 634 /* If we're a Fibre Channel Card, we allow deferred attach */ 635 if (IS_SCSI(isp)) { 636 isp_uninit(isp); 637 ISP_UNLOCK(isp); 638 goto bad; 639 } 640 } 641 /* 642 * XXXX: Here is where we might unload the f/w module 643 * XXXX: (or decrease the reference count to it). 644 */ 645 ISP_UNLOCK(isp); 646 return (0); 647 648 bad: 649 650 if (pcs && pcs->ih) { 651 (void) bus_teardown_intr(dev, irq, pcs->ih); 652 } 653 654 #ifdef ISP_SMPLOCK 655 if (locksetup && isp) { 656 mtx_destroy(&isp->isp_osinfo.lock); 657 } 658 #endif 659 660 if (irq) { 661 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 662 } 663 664 665 if (regs) { 666 (void) bus_release_resource(dev, rtp, rgd, regs); 667 } 668 669 if (pcs) { 670 if (pcs->pci_isp.isp_param) 671 free(pcs->pci_isp.isp_param, M_DEVBUF); 672 free(pcs, M_DEVBUF); 673 } 674 675 /* 676 * XXXX: Here is where we might unload the f/w module 677 * XXXX: (or decrease the reference count to it). 678 */ 679 return (ENXIO); 680 } 681 682 static void 683 isp_pci_intr(void *arg) 684 { 685 struct ispsoftc *isp = arg; 686 ISP_LOCK(isp); 687 (void) isp_intr(isp); 688 ISP_UNLOCK(isp); 689 } 690 691 static u_int16_t 692 isp_pci_rd_reg(isp, regoff) 693 struct ispsoftc *isp; 694 int regoff; 695 { 696 u_int16_t rv; 697 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 698 int offset, oldconf = 0; 699 700 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 701 /* 702 * We will assume that someone has paused the RISC processor. 703 */ 704 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 705 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 706 } 707 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 708 offset += (regoff & 0xff); 709 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 710 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 711 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 712 } 713 return (rv); 714 } 715 716 static void 717 isp_pci_wr_reg(isp, regoff, val) 718 struct ispsoftc *isp; 719 int regoff; 720 u_int16_t val; 721 { 722 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 723 int offset, oldconf = 0; 724 725 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 726 /* 727 * We will assume that someone has paused the RISC processor. 728 */ 729 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 730 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 731 } 732 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 733 offset += (regoff & 0xff); 734 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 735 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 736 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 737 } 738 } 739 740 static u_int16_t 741 isp_pci_rd_reg_1080(isp, regoff) 742 struct ispsoftc *isp; 743 int regoff; 744 { 745 u_int16_t rv, oc = 0; 746 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 747 int offset; 748 749 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 750 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 751 u_int16_t tc; 752 /* 753 * We will assume that someone has paused the RISC processor. 754 */ 755 oc = isp_pci_rd_reg(isp, BIU_CONF1); 756 tc = oc & ~BIU_PCI1080_CONF1_DMA; 757 if (regoff & SXP_BANK1_SELECT) 758 tc |= BIU_PCI1080_CONF1_SXP1; 759 else 760 tc |= BIU_PCI1080_CONF1_SXP0; 761 isp_pci_wr_reg(isp, BIU_CONF1, tc); 762 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 763 oc = isp_pci_rd_reg(isp, BIU_CONF1); 764 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 765 } 766 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 767 offset += (regoff & 0xff); 768 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 769 if (oc) { 770 isp_pci_wr_reg(isp, BIU_CONF1, oc); 771 } 772 return (rv); 773 } 774 775 static void 776 isp_pci_wr_reg_1080(isp, regoff, val) 777 struct ispsoftc *isp; 778 int regoff; 779 u_int16_t val; 780 { 781 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 782 int offset, oc = 0; 783 784 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 785 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 786 u_int16_t tc; 787 /* 788 * We will assume that someone has paused the RISC processor. 789 */ 790 oc = isp_pci_rd_reg(isp, BIU_CONF1); 791 tc = oc & ~BIU_PCI1080_CONF1_DMA; 792 if (regoff & SXP_BANK1_SELECT) 793 tc |= BIU_PCI1080_CONF1_SXP1; 794 else 795 tc |= BIU_PCI1080_CONF1_SXP0; 796 isp_pci_wr_reg(isp, BIU_CONF1, tc); 797 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 798 oc = isp_pci_rd_reg(isp, BIU_CONF1); 799 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 800 } 801 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 802 offset += (regoff & 0xff); 803 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 804 if (oc) { 805 isp_pci_wr_reg(isp, BIU_CONF1, oc); 806 } 807 } 808 809 static void isp_map_rquest __P((void *, bus_dma_segment_t *, int, int)); 810 static void isp_map_result __P((void *, bus_dma_segment_t *, int, int)); 811 static void isp_map_fcscrt __P((void *, bus_dma_segment_t *, int, int)); 812 813 struct imush { 814 struct ispsoftc *isp; 815 int error; 816 }; 817 818 static void 819 isp_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) 820 { 821 struct imush *imushp = (struct imush *) arg; 822 if (error) { 823 imushp->error = error; 824 } else { 825 imushp->isp->isp_rquest_dma = segs->ds_addr; 826 } 827 } 828 829 static void 830 isp_map_result(void *arg, bus_dma_segment_t *segs, int nseg, int error) 831 { 832 struct imush *imushp = (struct imush *) arg; 833 if (error) { 834 imushp->error = error; 835 } else { 836 imushp->isp->isp_result_dma = segs->ds_addr; 837 } 838 } 839 840 static void 841 isp_map_fcscrt(void *arg, bus_dma_segment_t *segs, int nseg, int error) 842 { 843 struct imush *imushp = (struct imush *) arg; 844 if (error) { 845 imushp->error = error; 846 } else { 847 fcparam *fcp = imushp->isp->isp_param; 848 fcp->isp_scdma = segs->ds_addr; 849 } 850 } 851 852 static int 853 isp_pci_mbxdma(struct ispsoftc *isp) 854 { 855 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 856 caddr_t base; 857 u_int32_t len; 858 int i, error; 859 bus_size_t lim; 860 struct imush im; 861 862 863 /* 864 * Already been here? If so, leave... 865 */ 866 if (isp->isp_rquest) { 867 return (0); 868 } 869 870 len = sizeof (XS_T **) * isp->isp_maxcmds; 871 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 872 if (isp->isp_xflist == NULL) { 873 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 874 return (1); 875 } 876 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 877 pci->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 878 if (pci->dmaps == NULL) { 879 isp_prt(isp, ISP_LOGERR, "can't alloc dma maps"); 880 free(isp->isp_xflist, M_DEVBUF); 881 return (1); 882 } 883 884 if (IS_FC(isp) || IS_ULTRA2(isp)) 885 lim = BUS_SPACE_MAXADDR + 1; 886 else 887 lim = BUS_SPACE_MAXADDR_24BIT + 1; 888 889 /* 890 * Allocate and map the request, result queues, plus FC scratch area. 891 */ 892 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 893 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 894 if (IS_FC(isp)) { 895 len += ISP2100_SCRLEN; 896 } 897 if (bus_dma_tag_create(pci->parent_dmat, PAGE_SIZE, lim, 898 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, 899 BUS_SPACE_MAXSIZE_32BIT, 0, &pci->cntrol_dmat) != 0) { 900 isp_prt(isp, ISP_LOGERR, 901 "cannot create a dma tag for control spaces"); 902 free(isp->isp_xflist, M_DEVBUF); 903 free(pci->dmaps, M_DEVBUF); 904 return (1); 905 } 906 if (bus_dmamem_alloc(pci->cntrol_dmat, (void **)&base, 907 BUS_DMA_NOWAIT, &pci->cntrol_dmap) != 0) { 908 isp_prt(isp, ISP_LOGERR, 909 "cannot allocate %d bytes of CCB memory", len); 910 free(isp->isp_xflist, M_DEVBUF); 911 free(pci->dmaps, M_DEVBUF); 912 return (1); 913 } 914 915 isp->isp_rquest = base; 916 im.isp = isp; 917 im.error = 0; 918 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_rquest, 919 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)), isp_map_rquest, &im, 0); 920 if (im.error) { 921 isp_prt(isp, ISP_LOGERR, 922 "error %d loading dma map for DMA request queue", im.error); 923 free(isp->isp_xflist, M_DEVBUF); 924 free(pci->dmaps, M_DEVBUF); 925 isp->isp_rquest = NULL; 926 return (1); 927 } 928 isp->isp_result = base + ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 929 im.error = 0; 930 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_result, 931 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)), isp_map_result, &im, 0); 932 if (im.error) { 933 isp_prt(isp, ISP_LOGERR, 934 "error %d loading dma map for DMA result queue", im.error); 935 free(isp->isp_xflist, M_DEVBUF); 936 free(pci->dmaps, M_DEVBUF); 937 isp->isp_rquest = NULL; 938 return (1); 939 } 940 941 for (i = 0; i < isp->isp_maxcmds; i++) { 942 error = bus_dmamap_create(pci->parent_dmat, 0, &pci->dmaps[i]); 943 if (error) { 944 isp_prt(isp, ISP_LOGERR, 945 "error %d creating per-cmd DMA maps", error); 946 free(isp->isp_xflist, M_DEVBUF); 947 free(pci->dmaps, M_DEVBUF); 948 isp->isp_rquest = NULL; 949 return (1); 950 } 951 } 952 953 if (IS_FC(isp)) { 954 fcparam *fcp = (fcparam *) isp->isp_param; 955 fcp->isp_scratch = base + 956 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)) + 957 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 958 im.error = 0; 959 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, 960 fcp->isp_scratch, ISP2100_SCRLEN, isp_map_fcscrt, &im, 0); 961 if (im.error) { 962 isp_prt(isp, ISP_LOGERR, 963 "error %d loading FC scratch area", im.error); 964 free(isp->isp_xflist, M_DEVBUF); 965 free(pci->dmaps, M_DEVBUF); 966 isp->isp_rquest = NULL; 967 return (1); 968 } 969 } 970 return (0); 971 } 972 973 typedef struct { 974 struct ispsoftc *isp; 975 void *cmd_token; 976 void *rq; 977 u_int16_t *iptrp; 978 u_int16_t optr; 979 u_int error; 980 } mush_t; 981 982 #define MUSHERR_NOQENTRIES -2 983 984 #ifdef ISP_TARGET_MODE 985 /* 986 * We need to handle DMA for target mode differently from initiator mode. 987 * 988 * DMA mapping and construction and submission of CTIO Request Entries 989 * and rendevous for completion are very tightly coupled because we start 990 * out by knowing (per platform) how much data we have to move, but we 991 * don't know, up front, how many DMA mapping segments will have to be used 992 * cover that data, so we don't know how many CTIO Request Entries we 993 * will end up using. Further, for performance reasons we may want to 994 * (on the last CTIO for Fibre Channel), send status too (if all went well). 995 * 996 * The standard vector still goes through isp_pci_dmasetup, but the callback 997 * for the DMA mapping routines comes here instead with the whole transfer 998 * mapped and a pointer to a partially filled in already allocated request 999 * queue entry. We finish the job. 1000 */ 1001 static void tdma_mk __P((void *, bus_dma_segment_t *, int, int)); 1002 static void tdma_mkfc __P((void *, bus_dma_segment_t *, int, int)); 1003 1004 static void 1005 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1006 { 1007 mush_t *mp; 1008 struct ccb_scsiio *csio; 1009 struct isp_pcisoftc *pci; 1010 bus_dmamap_t *dp; 1011 u_int8_t scsi_status; 1012 ct_entry_t *cto; 1013 u_int32_t handle, totxfr, sflags; 1014 int nctios, send_status; 1015 int32_t resid; 1016 1017 mp = (mush_t *) arg; 1018 if (error) { 1019 mp->error = error; 1020 return; 1021 } 1022 csio = mp->cmd_token; 1023 cto = mp->rq; 1024 1025 cto->ct_xfrlen = 0; 1026 cto->ct_seg_count = 0; 1027 cto->ct_header.rqs_entry_count = 1; 1028 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1029 1030 if (nseg == 0) { 1031 cto->ct_header.rqs_seqno = 1; 1032 ISP_TDQE(mp->isp, "tdma_mk[no data]", *mp->iptrp, cto); 1033 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1034 "CTIO lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x res %d", 1035 csio->ccb_h.target_lun, cto->ct_iid, cto->ct_flags, 1036 cto->ct_status, cto->ct_scsi_status, cto->ct_resid); 1037 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1038 return; 1039 } 1040 1041 nctios = nseg / ISP_RQDSEG; 1042 if (nseg % ISP_RQDSEG) { 1043 nctios++; 1044 } 1045 1046 /* 1047 * Save handle, and potentially any SCSI status, which we'll reinsert 1048 * on the last CTIO we're going to send. 1049 */ 1050 handle = cto->ct_reserved; 1051 cto->ct_reserved = 0; 1052 cto->ct_header.rqs_seqno = 0; 1053 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1054 1055 if (send_status) { 1056 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1057 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1058 /* 1059 * Preserve residual. 1060 */ 1061 resid = cto->ct_resid; 1062 1063 /* 1064 * Save actual SCSI status. 1065 */ 1066 scsi_status = cto->ct_scsi_status; 1067 1068 /* 1069 * We can't do a status at the same time as a data CTIO, so 1070 * we need to synthesize an extra CTIO at this level. 1071 */ 1072 nctios++; 1073 } else { 1074 sflags = scsi_status = resid = 0; 1075 } 1076 1077 totxfr = cto->ct_resid = 0; 1078 cto->ct_scsi_status = 0; 1079 1080 pci = (struct isp_pcisoftc *)mp->isp; 1081 dp = &pci->dmaps[isp_handle_index(handle)]; 1082 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1083 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1084 } else { 1085 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1086 } 1087 1088 1089 while (nctios--) { 1090 int seglim; 1091 1092 seglim = nseg; 1093 if (seglim) { 1094 int seg; 1095 1096 if (seglim > ISP_RQDSEG) 1097 seglim = ISP_RQDSEG; 1098 1099 for (seg = 0; seg < seglim; seg++, nseg--) { 1100 /* 1101 * Unlike normal initiator commands, we don't 1102 * do any swizzling here. 1103 */ 1104 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1105 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1106 cto->ct_xfrlen += dm_segs->ds_len; 1107 totxfr += dm_segs->ds_len; 1108 dm_segs++; 1109 } 1110 cto->ct_seg_count = seg; 1111 } else { 1112 /* 1113 * This case should only happen when we're sending an 1114 * extra CTIO with final status. 1115 */ 1116 if (send_status == 0) { 1117 isp_prt(mp->isp, ISP_LOGWARN, 1118 "tdma_mk ran out of segments"); 1119 mp->error = EINVAL; 1120 return; 1121 } 1122 } 1123 1124 /* 1125 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1126 * ct_tagtype, and ct_timeout have been carried over 1127 * unchanged from what our caller had set. 1128 * 1129 * The dataseg fields and the seg_count fields we just got 1130 * through setting. The data direction we've preserved all 1131 * along and only clear it if we're now sending status. 1132 */ 1133 1134 if (nctios == 0) { 1135 /* 1136 * We're the last in a sequence of CTIOs, so mark 1137 * this CTIO and save the handle to the CCB such that 1138 * when this CTIO completes we can free dma resources 1139 * and do whatever else we need to do to finish the 1140 * rest of the command. 1141 */ 1142 cto->ct_reserved = handle; 1143 cto->ct_header.rqs_seqno = 1; 1144 1145 if (send_status) { 1146 cto->ct_scsi_status = scsi_status; 1147 cto->ct_flags |= sflags | CT_NO_DATA;; 1148 cto->ct_resid = resid; 1149 } 1150 if (send_status) { 1151 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1152 "CTIO lun%d for ID %d ct_flags 0x%x scsi " 1153 "status %x resid %d", 1154 csio->ccb_h.target_lun, 1155 cto->ct_iid, cto->ct_flags, 1156 cto->ct_scsi_status, cto->ct_resid); 1157 } else { 1158 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1159 "CTIO lun%d for ID%d ct_flags 0x%x", 1160 csio->ccb_h.target_lun, 1161 cto->ct_iid, cto->ct_flags); 1162 } 1163 ISP_TDQE(mp->isp, "last tdma_mk", *mp->iptrp, cto); 1164 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1165 } else { 1166 ct_entry_t *octo = cto; 1167 1168 /* 1169 * Make sure handle fields are clean 1170 */ 1171 cto->ct_reserved = 0; 1172 cto->ct_header.rqs_seqno = 0; 1173 1174 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1175 "CTIO lun%d for ID%d ct_flags 0x%x", 1176 csio->ccb_h.target_lun, cto->ct_iid, cto->ct_flags); 1177 ISP_TDQE(mp->isp, "tdma_mk", *mp->iptrp, cto); 1178 1179 /* 1180 * Get a new CTIO 1181 */ 1182 cto = (ct_entry_t *) 1183 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1184 *mp->iptrp = 1185 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1186 if (*mp->iptrp == mp->optr) { 1187 isp_prt(mp->isp, ISP_LOGWARN, 1188 "Queue Overflow in tdma_mk"); 1189 mp->error = MUSHERR_NOQENTRIES; 1190 return; 1191 } 1192 /* 1193 * Fill in the new CTIO with info from the old one. 1194 */ 1195 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1196 cto->ct_header.rqs_entry_count = 1; 1197 cto->ct_header.rqs_flags = 0; 1198 cto->ct_lun = octo->ct_lun; 1199 cto->ct_iid = octo->ct_iid; 1200 cto->ct_reserved2 = octo->ct_reserved2; 1201 cto->ct_tgt = octo->ct_tgt; 1202 cto->ct_flags = octo->ct_flags; 1203 cto->ct_status = 0; 1204 cto->ct_scsi_status = 0; 1205 cto->ct_tag_val = octo->ct_tag_val; 1206 cto->ct_tag_type = octo->ct_tag_type; 1207 cto->ct_xfrlen = 0; 1208 cto->ct_resid = 0; 1209 cto->ct_timeout = octo->ct_timeout; 1210 cto->ct_seg_count = 0; 1211 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1212 /* 1213 * Now swizzle the old one for the consumption of the 1214 * chip. 1215 */ 1216 ISP_SWIZ_CTIO(mp->isp, octo, octo); 1217 } 1218 } 1219 } 1220 1221 static void 1222 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1223 { 1224 mush_t *mp; 1225 struct ccb_scsiio *csio; 1226 struct isp_pcisoftc *pci; 1227 bus_dmamap_t *dp; 1228 ct2_entry_t *cto; 1229 u_int16_t scsi_status, send_status, send_sense; 1230 u_int32_t handle, totxfr, datalen; 1231 u_int8_t sense[QLTM_SENSELEN]; 1232 int nctios; 1233 1234 mp = (mush_t *) arg; 1235 if (error) { 1236 mp->error = error; 1237 return; 1238 } 1239 1240 csio = mp->cmd_token; 1241 cto = mp->rq; 1242 1243 if (nseg == 0) { 1244 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1245 isp_prt(mp->isp, ISP_LOGWARN, 1246 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1247 "set (0x%x)", cto->ct_flags); 1248 mp->error = EINVAL; 1249 return; 1250 } 1251 cto->ct_header.rqs_entry_count = 1; 1252 cto->ct_header.rqs_seqno = 1; 1253 /* ct_reserved contains the handle set by caller */ 1254 /* 1255 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1256 * flags to NO DATA and clear relative offset flags. 1257 * We preserve the ct_resid and the response area. 1258 */ 1259 cto->ct_flags |= CT2_NO_DATA; 1260 if (cto->ct_resid > 0) 1261 cto->ct_flags |= CT2_DATA_UNDER; 1262 else if (cto->ct_resid < 0) 1263 cto->ct_flags |= CT2_DATA_OVER; 1264 cto->ct_seg_count = 0; 1265 cto->ct_reloff = 0; 1266 ISP_TDQE(mp->isp, "dma2_tgt_fc[no data]", *mp->iptrp, cto); 1267 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1268 "CTIO2 RX_ID 0x%x lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1269 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1270 cto->ct_iid, cto->ct_flags, cto->ct_status, 1271 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1272 ISP_SWIZ_CTIO2(isp, cto, cto); 1273 return; 1274 } 1275 1276 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1277 isp_prt(mp->isp, ISP_LOGWARN, 1278 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1279 "(0x%x)", cto->ct_flags); 1280 mp->error = EINVAL; 1281 return; 1282 } 1283 1284 1285 nctios = nseg / ISP_RQDSEG_T2; 1286 if (nseg % ISP_RQDSEG_T2) { 1287 nctios++; 1288 } 1289 1290 /* 1291 * Save the handle, status, reloff, and residual. We'll reinsert the 1292 * handle into the last CTIO2 we're going to send, and reinsert status 1293 * and residual (and possibly sense data) if that's to be sent as well. 1294 * 1295 * We preserve ct_reloff and adjust it for each data CTIO2 we send past 1296 * the first one. This is needed so that the FCP DATA IUs being sent 1297 * out have the correct offset (they can arrive at the other end out 1298 * of order). 1299 */ 1300 1301 handle = cto->ct_reserved; 1302 cto->ct_reserved = 0; 1303 1304 if ((send_status = (cto->ct_flags & CT2_SENDSTATUS)) != 0) { 1305 cto->ct_flags &= ~CT2_SENDSTATUS; 1306 1307 /* 1308 * Preserve residual, which is actually the total count. 1309 */ 1310 datalen = cto->ct_resid; 1311 1312 /* 1313 * Save actual SCSI status. We'll reinsert the 1314 * CT2_SNSLEN_VALID later if appropriate. 1315 */ 1316 scsi_status = cto->rsp.m0.ct_scsi_status & 0xff; 1317 send_sense = cto->rsp.m0.ct_scsi_status & CT2_SNSLEN_VALID; 1318 1319 /* 1320 * If we're sending status and have a CHECK CONDTION and 1321 * have sense data, we send one more CTIO2 with just the 1322 * status and sense data. The upper layers have stashed 1323 * the sense data in the dataseg structure for us. 1324 */ 1325 1326 if ((scsi_status & 0xf) == SCSI_STATUS_CHECK_COND && 1327 send_sense) { 1328 bcopy(cto->rsp.m0.ct_dataseg, sense, QLTM_SENSELEN); 1329 nctios++; 1330 } 1331 } else { 1332 scsi_status = send_sense = datalen = 0; 1333 } 1334 1335 totxfr = cto->ct_resid = 0; 1336 cto->rsp.m0.ct_scsi_status = 0; 1337 bzero(&cto->rsp, sizeof (cto->rsp)); 1338 1339 pci = (struct isp_pcisoftc *)mp->isp; 1340 dp = &pci->dmaps[isp_handle_index(handle)]; 1341 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1342 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1343 } else { 1344 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1345 } 1346 1347 while (nctios--) { 1348 int seg, seglim; 1349 1350 seglim = nseg; 1351 if (seglim) { 1352 if (seglim > ISP_RQDSEG_T2) 1353 seglim = ISP_RQDSEG_T2; 1354 1355 for (seg = 0; seg < seglim; seg++) { 1356 cto->rsp.m0.ct_dataseg[seg].ds_base = 1357 dm_segs->ds_addr; 1358 cto->rsp.m0.ct_dataseg[seg].ds_count = 1359 dm_segs->ds_len; 1360 cto->rsp.m0.ct_xfrlen += dm_segs->ds_len; 1361 totxfr += dm_segs->ds_len; 1362 dm_segs++; 1363 } 1364 cto->ct_seg_count = seg; 1365 } else { 1366 /* 1367 * This case should only happen when we're sending a 1368 * synthesized MODE1 final status with sense data. 1369 */ 1370 if (send_sense == 0) { 1371 isp_prt(mp->isp, ISP_LOGWARN, 1372 "dma2_tgt_fc ran out of segments, " 1373 "no SENSE DATA"); 1374 mp->error = EINVAL; 1375 return; 1376 } 1377 } 1378 1379 /* 1380 * At this point, the fields ct_lun, ct_iid, ct_rxid, 1381 * ct_timeout have been carried over unchanged from what 1382 * our caller had set. 1383 * 1384 * The field ct_reloff is either what the caller set, or 1385 * what we've added to below. 1386 * 1387 * The dataseg fields and the seg_count fields we just got 1388 * through setting. The data direction we've preserved all 1389 * along and only clear it if we're sending a MODE1 status 1390 * as the last CTIO. 1391 * 1392 */ 1393 1394 if (nctios == 0) { 1395 1396 /* 1397 * We're the last in a sequence of CTIO2s, so mark this 1398 * CTIO2 and save the handle to the CCB such that when 1399 * this CTIO2 completes we can free dma resources and 1400 * do whatever else we need to do to finish the rest 1401 * of the command. 1402 */ 1403 1404 cto->ct_reserved = handle; 1405 cto->ct_header.rqs_seqno = 1; 1406 1407 if (send_status) { 1408 if (send_sense) { 1409 bcopy(sense, cto->rsp.m1.ct_resp, 1410 QLTM_SENSELEN); 1411 cto->rsp.m1.ct_senselen = 1412 QLTM_SENSELEN; 1413 scsi_status |= CT2_SNSLEN_VALID; 1414 cto->rsp.m1.ct_scsi_status = 1415 scsi_status; 1416 cto->ct_flags &= CT2_FLAG_MMASK; 1417 cto->ct_flags |= CT2_FLAG_MODE1 | 1418 CT2_NO_DATA| CT2_SENDSTATUS; 1419 } else { 1420 cto->rsp.m0.ct_scsi_status = 1421 scsi_status; 1422 cto->ct_flags |= CT2_SENDSTATUS; 1423 } 1424 /* 1425 * Get 'real' residual and set flags based 1426 * on it. 1427 */ 1428 cto->ct_resid = datalen - totxfr; 1429 if (cto->ct_resid > 0) 1430 cto->ct_flags |= CT2_DATA_UNDER; 1431 else if (cto->ct_resid < 0) 1432 cto->ct_flags |= CT2_DATA_OVER; 1433 } 1434 ISP_TDQE(mp->isp, "last dma2_tgt_fc", *mp->iptrp, cto); 1435 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1436 "CTIO2 RX_ID 0x%x lun %d->iid%d flgs 0x%x sts 0x%x" 1437 " ssts 0x%x res %d", cto->ct_rxid, 1438 csio->ccb_h.target_lun, (int) cto->ct_iid, 1439 cto->ct_flags, cto->ct_status, 1440 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1441 ISP_SWIZ_CTIO2(isp, cto, cto); 1442 } else { 1443 ct2_entry_t *octo = cto; 1444 1445 /* 1446 * Make sure handle fields are clean 1447 */ 1448 cto->ct_reserved = 0; 1449 cto->ct_header.rqs_seqno = 0; 1450 1451 ISP_TDQE(mp->isp, "dma2_tgt_fc", *mp->iptrp, cto); 1452 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1453 "CTIO2 RX_ID 0x%x lun %d->iid%d flgs 0x%x", 1454 cto->ct_rxid, csio->ccb_h.target_lun, 1455 (int) cto->ct_iid, cto->ct_flags); 1456 /* 1457 * Get a new CTIO2 1458 */ 1459 cto = (ct2_entry_t *) 1460 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1461 *mp->iptrp = 1462 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1463 if (*mp->iptrp == mp->optr) { 1464 isp_prt(mp->isp, ISP_LOGWARN, 1465 "Queue Overflow in dma2_tgt_fc"); 1466 mp->error = MUSHERR_NOQENTRIES; 1467 return; 1468 } 1469 1470 /* 1471 * Fill in the new CTIO2 with info from the old one. 1472 */ 1473 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO2; 1474 cto->ct_header.rqs_entry_count = 1; 1475 cto->ct_header.rqs_flags = 0; 1476 /* ct_header.rqs_seqno && ct_reserved done later */ 1477 cto->ct_lun = octo->ct_lun; 1478 cto->ct_iid = octo->ct_iid; 1479 cto->ct_rxid = octo->ct_rxid; 1480 cto->ct_flags = octo->ct_flags; 1481 cto->ct_status = 0; 1482 cto->ct_resid = 0; 1483 cto->ct_timeout = octo->ct_timeout; 1484 cto->ct_seg_count = 0; 1485 /* 1486 * Adjust the new relative offset by the amount which 1487 * is recorded in the data segment of the old CTIO2 we 1488 * just finished filling out. 1489 */ 1490 cto->ct_reloff += octo->rsp.m0.ct_xfrlen; 1491 bzero(&cto->rsp, sizeof (cto->rsp)); 1492 ISP_SWIZ_CTIO2(isp, cto, cto); 1493 } 1494 } 1495 } 1496 #endif 1497 1498 static void dma2 __P((void *, bus_dma_segment_t *, int, int)); 1499 1500 static void 1501 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1502 { 1503 mush_t *mp; 1504 struct ccb_scsiio *csio; 1505 struct isp_pcisoftc *pci; 1506 bus_dmamap_t *dp; 1507 bus_dma_segment_t *eseg; 1508 ispreq_t *rq; 1509 ispcontreq_t *crq; 1510 int seglim, datalen; 1511 1512 mp = (mush_t *) arg; 1513 if (error) { 1514 mp->error = error; 1515 return; 1516 } 1517 1518 if (nseg < 1) { 1519 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1520 mp->error = EFAULT; 1521 return; 1522 } 1523 csio = mp->cmd_token; 1524 rq = mp->rq; 1525 pci = (struct isp_pcisoftc *)mp->isp; 1526 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1527 1528 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1529 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1530 } else { 1531 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1532 } 1533 1534 datalen = XS_XFRLEN(csio); 1535 1536 /* 1537 * We're passed an initial partially filled in entry that 1538 * has most fields filled in except for data transfer 1539 * related values. 1540 * 1541 * Our job is to fill in the initial request queue entry and 1542 * then to start allocating and filling in continuation entries 1543 * until we've covered the entire transfer. 1544 */ 1545 1546 if (IS_FC(mp->isp)) { 1547 seglim = ISP_RQDSEG_T2; 1548 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1549 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1550 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1551 } else { 1552 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1553 } 1554 } else { 1555 if (csio->cdb_len > 12) { 1556 seglim = 0; 1557 } else { 1558 seglim = ISP_RQDSEG; 1559 } 1560 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1561 rq->req_flags |= REQFLAG_DATA_IN; 1562 } else { 1563 rq->req_flags |= REQFLAG_DATA_OUT; 1564 } 1565 } 1566 1567 eseg = dm_segs + nseg; 1568 1569 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1570 if (IS_FC(mp->isp)) { 1571 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1572 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1573 dm_segs->ds_addr; 1574 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1575 dm_segs->ds_len; 1576 } else { 1577 rq->req_dataseg[rq->req_seg_count].ds_base = 1578 dm_segs->ds_addr; 1579 rq->req_dataseg[rq->req_seg_count].ds_count = 1580 dm_segs->ds_len; 1581 } 1582 datalen -= dm_segs->ds_len; 1583 #if 0 1584 if (IS_FC(mp->isp)) { 1585 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1586 printf("%s: seg0[%d] cnt 0x%x paddr 0x%08x\n", 1587 mp->isp->isp_name, rq->req_seg_count, 1588 rq2->req_dataseg[rq2->req_seg_count].ds_count, 1589 rq2->req_dataseg[rq2->req_seg_count].ds_base); 1590 } else { 1591 printf("%s: seg0[%d] cnt 0x%x paddr 0x%08x\n", 1592 mp->isp->isp_name, rq->req_seg_count, 1593 rq->req_dataseg[rq->req_seg_count].ds_count, 1594 rq->req_dataseg[rq->req_seg_count].ds_base); 1595 } 1596 #endif 1597 rq->req_seg_count++; 1598 dm_segs++; 1599 } 1600 1601 while (datalen > 0 && dm_segs != eseg) { 1602 crq = (ispcontreq_t *) 1603 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1604 *mp->iptrp = ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1605 if (*mp->iptrp == mp->optr) { 1606 #if 0 1607 printf("%s: Request Queue Overflow++\n", 1608 mp->isp->isp_name); 1609 #endif 1610 mp->error = MUSHERR_NOQENTRIES; 1611 return; 1612 } 1613 rq->req_header.rqs_entry_count++; 1614 bzero((void *)crq, sizeof (*crq)); 1615 crq->req_header.rqs_entry_count = 1; 1616 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1617 1618 seglim = 0; 1619 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1620 crq->req_dataseg[seglim].ds_base = 1621 dm_segs->ds_addr; 1622 crq->req_dataseg[seglim].ds_count = 1623 dm_segs->ds_len; 1624 #if 0 1625 printf("%s: seg%d[%d] cnt 0x%x paddr 0x%08x\n", 1626 mp->isp->isp_name, rq->req_header.rqs_entry_count-1, 1627 seglim, crq->req_dataseg[seglim].ds_count, 1628 crq->req_dataseg[seglim].ds_base); 1629 #endif 1630 rq->req_seg_count++; 1631 dm_segs++; 1632 seglim++; 1633 datalen -= dm_segs->ds_len; 1634 } 1635 } 1636 } 1637 1638 static int 1639 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1640 u_int16_t *iptrp, u_int16_t optr) 1641 { 1642 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1643 bus_dmamap_t *dp = NULL; 1644 mush_t mush, *mp; 1645 void (*eptr) __P((void *, bus_dma_segment_t *, int, int)); 1646 1647 #ifdef ISP_TARGET_MODE 1648 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1649 if (IS_FC(isp)) { 1650 eptr = tdma_mkfc; 1651 } else { 1652 eptr = tdma_mk; 1653 } 1654 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1655 (csio->dxfer_len == 0)) { 1656 rq->req_seg_count = 1; 1657 mp = &mush; 1658 mp->isp = isp; 1659 mp->cmd_token = csio; 1660 mp->rq = rq; 1661 mp->iptrp = iptrp; 1662 mp->optr = optr; 1663 mp->error = 0; 1664 (*eptr)(mp, NULL, 0, 0); 1665 goto exit; 1666 } 1667 } else 1668 #endif 1669 eptr = dma2; 1670 1671 /* 1672 * NB: if we need to do request queue entry swizzling, 1673 * NB: this is where it would need to be done for cmds 1674 * NB: that move no data. For commands that move data, 1675 * NB: swizzling would take place in those functions. 1676 */ 1677 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1678 (csio->dxfer_len == 0)) { 1679 rq->req_seg_count = 1; 1680 return (CMD_QUEUED); 1681 } 1682 1683 /* 1684 * Do a virtual grapevine step to collect info for 1685 * the callback dma allocation that we have to use... 1686 */ 1687 mp = &mush; 1688 mp->isp = isp; 1689 mp->cmd_token = csio; 1690 mp->rq = rq; 1691 mp->iptrp = iptrp; 1692 mp->optr = optr; 1693 mp->error = 0; 1694 1695 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1696 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1697 int error, s; 1698 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1699 s = splsoftvm(); 1700 error = bus_dmamap_load(pci->parent_dmat, *dp, 1701 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1702 if (error == EINPROGRESS) { 1703 bus_dmamap_unload(pci->parent_dmat, *dp); 1704 mp->error = EINVAL; 1705 isp_prt(isp, ISP_LOGERR, 1706 "deferred dma allocation not supported"); 1707 } else if (error && mp->error == 0) { 1708 #ifdef DIAGNOSTIC 1709 printf("%s: error %d in dma mapping code\n", 1710 isp->isp_name, error); 1711 #endif 1712 mp->error = error; 1713 } 1714 splx(s); 1715 } else { 1716 /* Pointer to physical buffer */ 1717 struct bus_dma_segment seg; 1718 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1719 seg.ds_len = csio->dxfer_len; 1720 (*eptr)(mp, &seg, 1, 0); 1721 } 1722 } else { 1723 struct bus_dma_segment *segs; 1724 1725 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1726 isp_prt(isp, ISP_LOGERR, 1727 "Physical segment pointers unsupported"); 1728 mp->error = EINVAL; 1729 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1730 isp_prt(isp, ISP_LOGERR, 1731 "Virtual segment addresses unsupported"); 1732 mp->error = EINVAL; 1733 } else { 1734 /* Just use the segments provided */ 1735 segs = (struct bus_dma_segment *) csio->data_ptr; 1736 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1737 } 1738 } 1739 #ifdef ISP_TARGET_MODE 1740 exit: 1741 #endif 1742 if (mp->error) { 1743 int retval = CMD_COMPLETE; 1744 if (mp->error == MUSHERR_NOQENTRIES) { 1745 retval = CMD_EAGAIN; 1746 } else if (mp->error == EFBIG) { 1747 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1748 } else if (mp->error == EINVAL) { 1749 XS_SETERR(csio, CAM_REQ_INVALID); 1750 } else { 1751 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1752 } 1753 return (retval); 1754 } else { 1755 /* 1756 * Check to see if we weren't cancelled while sleeping on 1757 * getting DMA resources... 1758 */ 1759 if ((csio->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 1760 if (dp) { 1761 bus_dmamap_unload(pci->parent_dmat, *dp); 1762 } 1763 return (CMD_COMPLETE); 1764 } 1765 return (CMD_QUEUED); 1766 } 1767 } 1768 1769 static void 1770 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int32_t handle) 1771 { 1772 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1773 bus_dmamap_t *dp = &pci->dmaps[isp_handle_index(handle)]; 1774 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1775 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTREAD); 1776 } else { 1777 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTWRITE); 1778 } 1779 bus_dmamap_unload(pci->parent_dmat, *dp); 1780 } 1781 1782 1783 static void 1784 isp_pci_reset1(struct ispsoftc *isp) 1785 { 1786 /* Make sure the BIOS is disabled */ 1787 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1788 /* and enable interrupts */ 1789 ENABLE_INTS(isp); 1790 } 1791 1792 static void 1793 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1794 { 1795 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1796 if (msg) 1797 printf("%s: %s\n", isp->isp_name, msg); 1798 if (IS_SCSI(isp)) 1799 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1800 else 1801 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1802 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1803 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1804 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1805 1806 1807 if (IS_SCSI(isp)) { 1808 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1809 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1810 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1811 ISP_READ(isp, CDMA_FIFO_STS)); 1812 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1813 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1814 ISP_READ(isp, DDMA_FIFO_STS)); 1815 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1816 ISP_READ(isp, SXP_INTERRUPT), 1817 ISP_READ(isp, SXP_GROSS_ERR), 1818 ISP_READ(isp, SXP_PINS_CTRL)); 1819 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1820 } 1821 printf(" mbox regs: %x %x %x %x %x\n", 1822 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1823 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1824 ISP_READ(isp, OUTMAILBOX4)); 1825 printf(" PCI Status Command/Status=%x\n", 1826 pci_read_config(pci->pci_dev, PCIR_COMMAND, 1)); 1827 } 1828