1 /* $FreeBSD$ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * FreeBSD Version. 5 * 6 *--------------------------------------- 7 * Copyright (c) 1997, 1998, 1999 by Matthew Jacob 8 * NASA/Ames Research Center 9 * All rights reserved. 10 *--------------------------------------- 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice immediately at the beginning of the file, without modification, 17 * this list of conditions, and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/bus.h> 42 43 #include <pci/pcireg.h> 44 #include <pci/pcivar.h> 45 46 #include <machine/bus_memio.h> 47 #include <machine/bus_pio.h> 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/clock.h> 51 #include <sys/rman.h> 52 #include <sys/malloc.h> 53 54 #include <dev/isp/isp_freebsd.h> 55 56 static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int)); 57 static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t)); 58 static u_int16_t isp_pci_rd_reg_1080 __P((struct ispsoftc *, int)); 59 static void isp_pci_wr_reg_1080 __P((struct ispsoftc *, int, u_int16_t)); 60 static int isp_pci_mbxdma __P((struct ispsoftc *)); 61 static int isp_pci_dmasetup __P((struct ispsoftc *, XS_T *, 62 ispreq_t *, u_int16_t *, u_int16_t)); 63 static void 64 isp_pci_dmateardown __P((struct ispsoftc *, XS_T *, u_int32_t)); 65 66 static void isp_pci_reset1 __P((struct ispsoftc *)); 67 static void isp_pci_dumpregs __P((struct ispsoftc *, const char *)); 68 69 #ifndef ISP_CODE_ORG 70 #define ISP_CODE_ORG 0x1000 71 #endif 72 73 static struct ispmdvec mdvec = { 74 isp_pci_rd_reg, 75 isp_pci_wr_reg, 76 isp_pci_mbxdma, 77 isp_pci_dmasetup, 78 isp_pci_dmateardown, 79 NULL, 80 isp_pci_reset1, 81 isp_pci_dumpregs, 82 NULL, 83 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 84 }; 85 86 static struct ispmdvec mdvec_1080 = { 87 isp_pci_rd_reg_1080, 88 isp_pci_wr_reg_1080, 89 isp_pci_mbxdma, 90 isp_pci_dmasetup, 91 isp_pci_dmateardown, 92 NULL, 93 isp_pci_reset1, 94 isp_pci_dumpregs, 95 NULL, 96 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 97 }; 98 99 static struct ispmdvec mdvec_12160 = { 100 isp_pci_rd_reg_1080, 101 isp_pci_wr_reg_1080, 102 isp_pci_mbxdma, 103 isp_pci_dmasetup, 104 isp_pci_dmateardown, 105 NULL, 106 isp_pci_reset1, 107 isp_pci_dumpregs, 108 NULL, 109 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 110 }; 111 112 static struct ispmdvec mdvec_2100 = { 113 isp_pci_rd_reg, 114 isp_pci_wr_reg, 115 isp_pci_mbxdma, 116 isp_pci_dmasetup, 117 isp_pci_dmateardown, 118 NULL, 119 isp_pci_reset1, 120 isp_pci_dumpregs 121 }; 122 123 static struct ispmdvec mdvec_2200 = { 124 isp_pci_rd_reg, 125 isp_pci_wr_reg, 126 isp_pci_mbxdma, 127 isp_pci_dmasetup, 128 isp_pci_dmateardown, 129 NULL, 130 isp_pci_reset1, 131 isp_pci_dumpregs 132 }; 133 134 #ifndef PCIM_CMD_INVEN 135 #define PCIM_CMD_INVEN 0x10 136 #endif 137 #ifndef PCIM_CMD_BUSMASTEREN 138 #define PCIM_CMD_BUSMASTEREN 0x0004 139 #endif 140 #ifndef PCIM_CMD_PERRESPEN 141 #define PCIM_CMD_PERRESPEN 0x0040 142 #endif 143 #ifndef PCIM_CMD_SEREN 144 #define PCIM_CMD_SEREN 0x0100 145 #endif 146 147 #ifndef PCIR_COMMAND 148 #define PCIR_COMMAND 0x04 149 #endif 150 151 #ifndef PCIR_CACHELNSZ 152 #define PCIR_CACHELNSZ 0x0c 153 #endif 154 155 #ifndef PCIR_LATTIMER 156 #define PCIR_LATTIMER 0x0d 157 #endif 158 159 #ifndef PCIR_ROMADDR 160 #define PCIR_ROMADDR 0x30 161 #endif 162 163 #ifndef PCI_VENDOR_QLOGIC 164 #define PCI_VENDOR_QLOGIC 0x1077 165 #endif 166 167 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 168 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 169 #endif 170 171 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 172 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 173 #endif 174 175 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 176 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 177 #endif 178 179 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 180 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 181 #endif 182 183 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 184 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 185 #endif 186 187 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 188 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 189 #endif 190 191 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 192 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 193 #endif 194 195 #define PCI_QLOGIC_ISP1020 \ 196 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 197 198 #define PCI_QLOGIC_ISP1080 \ 199 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 200 201 #define PCI_QLOGIC_ISP12160 \ 202 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 203 204 #define PCI_QLOGIC_ISP1240 \ 205 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 206 207 #define PCI_QLOGIC_ISP1280 \ 208 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 209 210 #define PCI_QLOGIC_ISP2100 \ 211 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 212 213 #define PCI_QLOGIC_ISP2200 \ 214 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 215 216 #define IO_MAP_REG 0x10 217 #define MEM_MAP_REG 0x14 218 219 #define PCI_DFLT_LTNCY 0x40 220 #define PCI_DFLT_LNSZ 0x10 221 222 static int isp_pci_probe (device_t); 223 static int isp_pci_attach (device_t); 224 225 /* This distinguishing define is not right, but it does work */ 226 #ifdef __alpha__ 227 #define IO_SPACE_MAPPING ALPHA_BUS_SPACE_IO 228 #define MEM_SPACE_MAPPING ALPHA_BUS_SPACE_MEM 229 #else 230 #define IO_SPACE_MAPPING I386_BUS_SPACE_IO 231 #define MEM_SPACE_MAPPING I386_BUS_SPACE_MEM 232 #endif 233 234 struct isp_pcisoftc { 235 struct ispsoftc pci_isp; 236 device_t pci_dev; 237 struct resource * pci_reg; 238 bus_space_tag_t pci_st; 239 bus_space_handle_t pci_sh; 240 void * ih; 241 int16_t pci_poff[_NREG_BLKS]; 242 bus_dma_tag_t parent_dmat; 243 bus_dma_tag_t cntrol_dmat; 244 bus_dmamap_t cntrol_dmap; 245 bus_dmamap_t *dmaps; 246 }; 247 ispfwfunc *isp_get_firmware_p = NULL; 248 249 static device_method_t isp_pci_methods[] = { 250 /* Device interface */ 251 DEVMETHOD(device_probe, isp_pci_probe), 252 DEVMETHOD(device_attach, isp_pci_attach), 253 { 0, 0 } 254 }; 255 256 static driver_t isp_pci_driver = { 257 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 258 }; 259 static devclass_t isp_devclass; 260 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 261 MODULE_VERSION(isp, 1); 262 263 static int 264 isp_pci_probe(device_t dev) 265 { 266 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 267 case PCI_QLOGIC_ISP1020: 268 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 269 break; 270 case PCI_QLOGIC_ISP1080: 271 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 272 break; 273 case PCI_QLOGIC_ISP1240: 274 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 275 break; 276 case PCI_QLOGIC_ISP1280: 277 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 278 break; 279 case PCI_QLOGIC_ISP12160: 280 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 281 break; 282 case PCI_QLOGIC_ISP2100: 283 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 284 break; 285 case PCI_QLOGIC_ISP2200: 286 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 287 break; 288 default: 289 return (ENXIO); 290 } 291 if (device_get_unit(dev) == 0 && bootverbose) { 292 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 293 "Core Version %d.%d\n", 294 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 295 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 296 } 297 /* 298 * XXXX: Here is where we might load the f/w module 299 * XXXX: (or increase a reference count to it). 300 */ 301 return (0); 302 } 303 304 static int 305 isp_pci_attach(device_t dev) 306 { 307 struct resource *regs, *irq; 308 int unit, bitmap, rtp, rgd, iqd, m1, m2, s, isp_debug; 309 u_int32_t data, cmd, linesz, psize, basetype; 310 struct isp_pcisoftc *pcs; 311 struct ispsoftc *isp; 312 struct ispmdvec *mdvp; 313 bus_size_t lim; 314 315 /* 316 * Figure out if we're supposed to skip this one. 317 */ 318 unit = device_get_unit(dev); 319 if (getenv_int("isp_disable", &bitmap)) { 320 if (bitmap & (1 << unit)) { 321 device_printf(dev, "not configuring\n"); 322 return (ENODEV); 323 } 324 } 325 326 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT); 327 if (pcs == NULL) { 328 device_printf(dev, "cannot allocate softc\n"); 329 return (ENOMEM); 330 } 331 bzero(pcs, sizeof (struct isp_pcisoftc)); 332 333 /* 334 * Figure out which we should try first - memory mapping or i/o mapping? 335 */ 336 #ifdef __alpha__ 337 m1 = PCIM_CMD_MEMEN; 338 m2 = PCIM_CMD_PORTEN; 339 #else 340 m1 = PCIM_CMD_PORTEN; 341 m2 = PCIM_CMD_MEMEN; 342 #endif 343 bitmap = 0; 344 if (getenv_int("isp_mem_map", &bitmap)) { 345 if (bitmap & (1 << unit)) { 346 m1 = PCIM_CMD_MEMEN; 347 m2 = PCIM_CMD_PORTEN; 348 } 349 } 350 bitmap = 0; 351 if (getenv_int("isp_io_map", &bitmap)) { 352 if (bitmap & (1 << unit)) { 353 m1 = PCIM_CMD_PORTEN; 354 m2 = PCIM_CMD_MEMEN; 355 } 356 } 357 358 linesz = PCI_DFLT_LNSZ; 359 irq = regs = NULL; 360 rgd = rtp = iqd = 0; 361 362 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 363 if (cmd & m1) { 364 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 365 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 366 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 367 } 368 if (regs == NULL && (cmd & m2)) { 369 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 370 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 371 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 372 } 373 if (regs == NULL) { 374 device_printf(dev, "unable to map any ports\n"); 375 goto bad; 376 } 377 if (bootverbose) 378 printf("isp%d: using %s space register mapping\n", unit, 379 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 380 pcs->pci_dev = dev; 381 pcs->pci_reg = regs; 382 pcs->pci_st = rman_get_bustag(regs); 383 pcs->pci_sh = rman_get_bushandle(regs); 384 385 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 386 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 387 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 388 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 389 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 390 mdvp = &mdvec; 391 basetype = ISP_HA_SCSI_UNKNOWN; 392 psize = sizeof (sdparam); 393 lim = BUS_SPACE_MAXSIZE_32BIT; 394 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 395 mdvp = &mdvec; 396 basetype = ISP_HA_SCSI_UNKNOWN; 397 psize = sizeof (sdparam); 398 lim = BUS_SPACE_MAXSIZE_24BIT; 399 } 400 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 401 mdvp = &mdvec_1080; 402 basetype = ISP_HA_SCSI_1080; 403 psize = sizeof (sdparam); 404 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 405 ISP1080_DMA_REGS_OFF; 406 } 407 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 408 mdvp = &mdvec_1080; 409 basetype = ISP_HA_SCSI_1240; 410 psize = 2 * sizeof (sdparam); 411 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 412 ISP1080_DMA_REGS_OFF; 413 } 414 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 415 mdvp = &mdvec_1080; 416 basetype = ISP_HA_SCSI_1280; 417 psize = 2 * sizeof (sdparam); 418 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 419 ISP1080_DMA_REGS_OFF; 420 } 421 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 422 mdvp = &mdvec_12160; 423 basetype = ISP_HA_SCSI_12160; 424 psize = 2 * sizeof (sdparam); 425 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 426 ISP1080_DMA_REGS_OFF; 427 } 428 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 429 mdvp = &mdvec_2100; 430 basetype = ISP_HA_FC_2100; 431 psize = sizeof (fcparam); 432 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 433 PCI_MBOX_REGS2100_OFF; 434 if (pci_get_revid(dev) < 3) { 435 /* 436 * XXX: Need to get the actual revision 437 * XXX: number of the 2100 FB. At any rate, 438 * XXX: lower cache line size for early revision 439 * XXX; boards. 440 */ 441 linesz = 1; 442 } 443 } 444 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 445 mdvp = &mdvec_2200; 446 basetype = ISP_HA_FC_2200; 447 psize = sizeof (fcparam); 448 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 449 PCI_MBOX_REGS2100_OFF; 450 } 451 isp = &pcs->pci_isp; 452 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT); 453 if (isp->isp_param == NULL) { 454 device_printf(dev, "cannot allocate parameter data\n"); 455 goto bad; 456 } 457 bzero(isp->isp_param, psize); 458 isp->isp_mdvec = mdvp; 459 isp->isp_type = basetype; 460 isp->isp_revision = pci_get_revid(dev); 461 (void) snprintf(isp->isp_name, sizeof (isp->isp_name), "isp%d", unit); 462 isp->isp_osinfo.unit = unit; 463 464 /* 465 * Try and find firmware for this device. 466 */ 467 468 if (isp_get_firmware_p) { 469 int device = (int) pci_get_device(dev); 470 #ifdef ISP_TARGET_MODE 471 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 472 #else 473 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 474 #endif 475 } 476 477 /* 478 * 479 */ 480 481 s = splbio(); 482 /* 483 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 484 * are set. 485 */ 486 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 487 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 488 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 489 490 /* 491 * Make sure the Cache Line Size register is set sensibly. 492 */ 493 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 494 if (data != linesz) { 495 data = PCI_DFLT_LNSZ; 496 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 497 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 498 } 499 500 /* 501 * Make sure the Latency Timer is sane. 502 */ 503 data = pci_read_config(dev, PCIR_LATTIMER, 1); 504 if (data < PCI_DFLT_LTNCY) { 505 data = PCI_DFLT_LTNCY; 506 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 507 pci_write_config(dev, PCIR_LATTIMER, data, 1); 508 } 509 510 /* 511 * Make sure we've disabled the ROM. 512 */ 513 data = pci_read_config(dev, PCIR_ROMADDR, 4); 514 data &= ~1; 515 pci_write_config(dev, PCIR_ROMADDR, data, 4); 516 517 518 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 519 BUS_SPACE_MAXADDR, NULL, NULL, lim + 1, 520 255, lim, 0, &pcs->parent_dmat) != 0) { 521 splx(s); 522 printf("%s: could not create master dma tag\n", isp->isp_name); 523 free(isp->isp_param, M_DEVBUF); 524 free(pcs, M_DEVBUF); 525 return (ENXIO); 526 } 527 528 iqd = 0; 529 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 530 1, RF_ACTIVE | RF_SHAREABLE); 531 if (irq == NULL) { 532 device_printf(dev, "could not allocate interrupt\n"); 533 goto bad; 534 } 535 536 if (getenv_int("isp_no_fwload", &bitmap)) { 537 if (bitmap & (1 << unit)) 538 isp->isp_confopts |= ISP_CFG_NORELOAD; 539 } 540 if (getenv_int("isp_fwload", &bitmap)) { 541 if (bitmap & (1 << unit)) 542 isp->isp_confopts &= ~ISP_CFG_NORELOAD; 543 } 544 if (getenv_int("isp_no_nvram", &bitmap)) { 545 if (bitmap & (1 << unit)) 546 isp->isp_confopts |= ISP_CFG_NONVRAM; 547 } 548 if (getenv_int("isp_nvram", &bitmap)) { 549 if (bitmap & (1 << unit)) 550 isp->isp_confopts &= ~ISP_CFG_NONVRAM; 551 } 552 if (getenv_int("isp_fcduplex", &bitmap)) { 553 if (bitmap & (1 << unit)) 554 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 555 } 556 if (getenv_int("isp_no_fcduplex", &bitmap)) { 557 if (bitmap & (1 << unit)) 558 isp->isp_confopts &= ~ISP_CFG_FULL_DUPLEX; 559 } 560 if (getenv_int("isp_nport", &bitmap)) { 561 if (bitmap & (1 << unit)) 562 isp->isp_confopts |= ISP_CFG_NPORT; 563 } 564 /* 565 * Look for overriding WWN. This is a Node WWN so it binds to 566 * all FC instances. A Port WWN will be constructed from it 567 * as appropriate. 568 */ 569 if (!getenv_quad("isp_wwn", (quad_t *) &isp->isp_osinfo.default_wwn)) { 570 int i; 571 u_int64_t seed = (u_int64_t) (intptr_t) isp; 572 573 seed <<= 16; 574 seed &= ((1LL << 48) - 1LL); 575 /* 576 * This isn't very random, but it's the best we can do for 577 * the real edge case of cards that don't have WWNs. If 578 * you recompile a new vers.c, you'll get a different WWN. 579 */ 580 for (i = 0; version[i] != 0; i++) { 581 seed += version[i]; 582 } 583 /* 584 * Make sure the top nibble has something vaguely sensible 585 * (NAA == Locally Administered) 586 */ 587 isp->isp_osinfo.default_wwn |= (3LL << 60) | seed; 588 } else { 589 isp->isp_confopts |= ISP_CFG_OWNWWN; 590 } 591 isp_debug = 0; 592 (void) getenv_int("isp_debug", &isp_debug); 593 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM, (void (*)(void *))isp_intr, 594 isp, &pcs->ih)) { 595 splx(s); 596 device_printf(dev, "could not setup interrupt\n"); 597 goto bad; 598 } 599 600 /* 601 * Set up logging levels. 602 */ 603 if (isp_debug) { 604 isp->isp_dblev = isp_debug; 605 } else { 606 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 607 } 608 if (bootverbose) 609 isp->isp_dblev |= ISP_LOGCONFIG; 610 611 /* 612 * Make sure we're in reset state. 613 */ 614 isp_reset(isp); 615 616 if (isp->isp_state != ISP_RESETSTATE) { 617 splx(s); 618 goto bad; 619 } 620 isp_init(isp); 621 if (isp->isp_state != ISP_INITSTATE) { 622 /* If we're a Fibre Channel Card, we allow deferred attach */ 623 if (IS_SCSI(isp)) { 624 isp_uninit(isp); 625 splx(s); 626 goto bad; 627 } 628 } 629 isp_attach(isp); 630 if (isp->isp_state != ISP_RUNSTATE) { 631 /* If we're a Fibre Channel Card, we allow deferred attach */ 632 if (IS_SCSI(isp)) { 633 isp_uninit(isp); 634 splx(s); 635 goto bad; 636 } 637 } 638 splx(s); 639 /* 640 * XXXX: Here is where we might unload the f/w module 641 * XXXX: (or decrease the reference count to it). 642 */ 643 return (0); 644 645 bad: 646 647 if (pcs && pcs->ih) { 648 (void) bus_teardown_intr(dev, irq, pcs->ih); 649 } 650 651 if (irq) { 652 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 653 } 654 if (regs) { 655 (void) bus_release_resource(dev, rtp, rgd, regs); 656 } 657 if (pcs) { 658 if (pcs->pci_isp.isp_param) 659 free(pcs->pci_isp.isp_param, M_DEVBUF); 660 free(pcs, M_DEVBUF); 661 } 662 /* 663 * XXXX: Here is where we might unload the f/w module 664 * XXXX: (or decrease the reference count to it). 665 */ 666 return (ENXIO); 667 } 668 669 static u_int16_t 670 isp_pci_rd_reg(isp, regoff) 671 struct ispsoftc *isp; 672 int regoff; 673 { 674 u_int16_t rv; 675 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 676 int offset, oldconf = 0; 677 678 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 679 /* 680 * We will assume that someone has paused the RISC processor. 681 */ 682 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 683 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 684 } 685 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 686 offset += (regoff & 0xff); 687 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 688 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 689 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 690 } 691 return (rv); 692 } 693 694 static void 695 isp_pci_wr_reg(isp, regoff, val) 696 struct ispsoftc *isp; 697 int regoff; 698 u_int16_t val; 699 { 700 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 701 int offset, oldconf = 0; 702 703 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 704 /* 705 * We will assume that someone has paused the RISC processor. 706 */ 707 oldconf = isp_pci_rd_reg(isp, BIU_CONF1); 708 isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); 709 } 710 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 711 offset += (regoff & 0xff); 712 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 713 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 714 isp_pci_wr_reg(isp, BIU_CONF1, oldconf); 715 } 716 } 717 718 static u_int16_t 719 isp_pci_rd_reg_1080(isp, regoff) 720 struct ispsoftc *isp; 721 int regoff; 722 { 723 u_int16_t rv, oc = 0; 724 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 725 int offset; 726 727 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 728 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 729 u_int16_t tc; 730 /* 731 * We will assume that someone has paused the RISC processor. 732 */ 733 oc = isp_pci_rd_reg(isp, BIU_CONF1); 734 tc = oc & ~BIU_PCI1080_CONF1_DMA; 735 if (regoff & SXP_BANK1_SELECT) 736 tc |= BIU_PCI1080_CONF1_SXP1; 737 else 738 tc |= BIU_PCI1080_CONF1_SXP0; 739 isp_pci_wr_reg(isp, BIU_CONF1, tc); 740 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 741 oc = isp_pci_rd_reg(isp, BIU_CONF1); 742 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 743 } 744 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 745 offset += (regoff & 0xff); 746 rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); 747 if (oc) { 748 isp_pci_wr_reg(isp, BIU_CONF1, oc); 749 } 750 return (rv); 751 } 752 753 static void 754 isp_pci_wr_reg_1080(isp, regoff, val) 755 struct ispsoftc *isp; 756 int regoff; 757 u_int16_t val; 758 { 759 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 760 int offset, oc = 0; 761 762 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 763 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 764 u_int16_t tc; 765 /* 766 * We will assume that someone has paused the RISC processor. 767 */ 768 oc = isp_pci_rd_reg(isp, BIU_CONF1); 769 tc = oc & ~BIU_PCI1080_CONF1_DMA; 770 if (regoff & SXP_BANK1_SELECT) 771 tc |= BIU_PCI1080_CONF1_SXP1; 772 else 773 tc |= BIU_PCI1080_CONF1_SXP0; 774 isp_pci_wr_reg(isp, BIU_CONF1, tc); 775 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 776 oc = isp_pci_rd_reg(isp, BIU_CONF1); 777 isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); 778 } 779 offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; 780 offset += (regoff & 0xff); 781 bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); 782 if (oc) { 783 isp_pci_wr_reg(isp, BIU_CONF1, oc); 784 } 785 } 786 787 static void isp_map_rquest __P((void *, bus_dma_segment_t *, int, int)); 788 static void isp_map_result __P((void *, bus_dma_segment_t *, int, int)); 789 static void isp_map_fcscrt __P((void *, bus_dma_segment_t *, int, int)); 790 791 struct imush { 792 struct ispsoftc *isp; 793 int error; 794 }; 795 796 static void 797 isp_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) 798 { 799 struct imush *imushp = (struct imush *) arg; 800 if (error) { 801 imushp->error = error; 802 } else { 803 imushp->isp->isp_rquest_dma = segs->ds_addr; 804 } 805 } 806 807 static void 808 isp_map_result(void *arg, bus_dma_segment_t *segs, int nseg, int error) 809 { 810 struct imush *imushp = (struct imush *) arg; 811 if (error) { 812 imushp->error = error; 813 } else { 814 imushp->isp->isp_result_dma = segs->ds_addr; 815 } 816 } 817 818 static void 819 isp_map_fcscrt(void *arg, bus_dma_segment_t *segs, int nseg, int error) 820 { 821 struct imush *imushp = (struct imush *) arg; 822 if (error) { 823 imushp->error = error; 824 } else { 825 fcparam *fcp = imushp->isp->isp_param; 826 fcp->isp_scdma = segs->ds_addr; 827 } 828 } 829 830 static int 831 isp_pci_mbxdma(struct ispsoftc *isp) 832 { 833 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 834 caddr_t base; 835 u_int32_t len; 836 int i, error; 837 bus_size_t lim; 838 struct imush im; 839 840 841 /* 842 * Already been here? If so, leave... 843 */ 844 if (isp->isp_rquest) { 845 return (0); 846 } 847 848 len = sizeof (XS_T **) * isp->isp_maxcmds; 849 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 850 if (isp->isp_xflist == NULL) { 851 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 852 return (1); 853 } 854 bzero(isp->isp_xflist, len); 855 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 856 pci->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 857 if (pci->dmaps == NULL) { 858 isp_prt(isp, ISP_LOGERR, "can't alloc dma maps"); 859 free(isp->isp_xflist, M_DEVBUF); 860 return (1); 861 } 862 863 if (IS_FC(isp) || IS_ULTRA2(isp)) 864 lim = BUS_SPACE_MAXADDR + 1; 865 else 866 lim = BUS_SPACE_MAXADDR_24BIT + 1; 867 868 /* 869 * Allocate and map the request, result queues, plus FC scratch area. 870 */ 871 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 872 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 873 if (IS_FC(isp)) { 874 len += ISP2100_SCRLEN; 875 } 876 if (bus_dma_tag_create(pci->parent_dmat, PAGE_SIZE, lim, 877 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, 878 BUS_SPACE_MAXSIZE_32BIT, 0, &pci->cntrol_dmat) != 0) { 879 printf("%s: cannot create a dma tag for control spaces\n", 880 isp->isp_name); 881 free(isp->isp_xflist, M_DEVBUF); 882 free(pci->dmaps, M_DEVBUF); 883 return (1); 884 } 885 if (bus_dmamem_alloc(pci->cntrol_dmat, (void **)&base, 886 BUS_DMA_NOWAIT, &pci->cntrol_dmap) != 0) { 887 printf("%s: cannot allocate %d bytes of CCB memory\n", 888 isp->isp_name, len); 889 free(isp->isp_xflist, M_DEVBUF); 890 free(pci->dmaps, M_DEVBUF); 891 return (1); 892 } 893 894 isp->isp_rquest = base; 895 im.isp = isp; 896 im.error = 0; 897 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_rquest, 898 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)), isp_map_rquest, &im, 0); 899 if (im.error) { 900 printf("%s: error %d loading dma map for DMA request queue\n", 901 isp->isp_name, im.error); 902 free(isp->isp_xflist, M_DEVBUF); 903 free(pci->dmaps, M_DEVBUF); 904 isp->isp_rquest = NULL; 905 return (1); 906 } 907 isp->isp_result = base + ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 908 im.error = 0; 909 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_result, 910 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)), isp_map_result, &im, 0); 911 if (im.error) { 912 printf("%s: error %d loading dma map for DMA result queue\n", 913 isp->isp_name, im.error); 914 free(isp->isp_xflist, M_DEVBUF); 915 free(pci->dmaps, M_DEVBUF); 916 isp->isp_rquest = NULL; 917 return (1); 918 } 919 920 for (i = 0; i < isp->isp_maxcmds; i++) { 921 error = bus_dmamap_create(pci->parent_dmat, 0, &pci->dmaps[i]); 922 if (error) { 923 printf("%s: error %d creating per-cmd DMA maps\n", 924 isp->isp_name, error); 925 free(isp->isp_xflist, M_DEVBUF); 926 free(pci->dmaps, M_DEVBUF); 927 isp->isp_rquest = NULL; 928 return (1); 929 } 930 } 931 932 if (IS_FC(isp)) { 933 fcparam *fcp = (fcparam *) isp->isp_param; 934 fcp->isp_scratch = base + 935 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)) + 936 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 937 im.error = 0; 938 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, 939 fcp->isp_scratch, ISP2100_SCRLEN, isp_map_fcscrt, &im, 0); 940 if (im.error) { 941 printf("%s: error %d loading FC scratch area\n", 942 isp->isp_name, im.error); 943 free(isp->isp_xflist, M_DEVBUF); 944 free(pci->dmaps, M_DEVBUF); 945 isp->isp_rquest = NULL; 946 return (1); 947 } 948 } 949 return (0); 950 } 951 952 typedef struct { 953 struct ispsoftc *isp; 954 void *cmd_token; 955 void *rq; 956 u_int16_t *iptrp; 957 u_int16_t optr; 958 u_int error; 959 } mush_t; 960 961 #define MUSHERR_NOQENTRIES -2 962 963 #ifdef ISP_TARGET_MODE 964 /* 965 * We need to handle DMA for target mode differently from initiator mode. 966 * 967 * DMA mapping and construction and submission of CTIO Request Entries 968 * and rendevous for completion are very tightly coupled because we start 969 * out by knowing (per platform) how much data we have to move, but we 970 * don't know, up front, how many DMA mapping segments will have to be used 971 * cover that data, so we don't know how many CTIO Request Entries we 972 * will end up using. Further, for performance reasons we may want to 973 * (on the last CTIO for Fibre Channel), send status too (if all went well). 974 * 975 * The standard vector still goes through isp_pci_dmasetup, but the callback 976 * for the DMA mapping routines comes here instead with the whole transfer 977 * mapped and a pointer to a partially filled in already allocated request 978 * queue entry. We finish the job. 979 */ 980 static void tdma_mk __P((void *, bus_dma_segment_t *, int, int)); 981 static void tdma_mkfc __P((void *, bus_dma_segment_t *, int, int)); 982 983 static void 984 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 985 { 986 mush_t *mp; 987 struct ccb_scsiio *csio; 988 struct isp_pcisoftc *pci; 989 bus_dmamap_t *dp; 990 u_int8_t scsi_status; 991 ct_entry_t *cto; 992 u_int32_t handle, totxfr, sflags; 993 int nctios, send_status; 994 int32_t resid; 995 996 mp = (mush_t *) arg; 997 if (error) { 998 mp->error = error; 999 return; 1000 } 1001 csio = mp->cmd_token; 1002 cto = mp->rq; 1003 1004 cto->ct_xfrlen = 0; 1005 cto->ct_seg_count = 0; 1006 cto->ct_header.rqs_entry_count = 1; 1007 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1008 1009 if (nseg == 0) { 1010 cto->ct_header.rqs_seqno = 1; 1011 ISP_TDQE(mp->isp, "tdma_mk[no data]", *mp->iptrp, cto); 1012 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1013 "CTIO lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x res %d", 1014 csio->ccb_h.target_lun, cto->ct_iid, cto->ct_flags, 1015 cto->ct_status, cto->ct_scsi_status, cto->ct_resid); 1016 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1017 return; 1018 } 1019 1020 nctios = nseg / ISP_RQDSEG; 1021 if (nseg % ISP_RQDSEG) { 1022 nctios++; 1023 } 1024 1025 /* 1026 * Save handle, and potentially any SCSI status, which we'll reinsert 1027 * on the last CTIO we're going to send. 1028 */ 1029 handle = cto->ct_reserved; 1030 cto->ct_reserved = 0; 1031 cto->ct_header.rqs_seqno = 0; 1032 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1033 1034 if (send_status) { 1035 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1036 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1037 /* 1038 * Preserve residual. 1039 */ 1040 resid = cto->ct_resid; 1041 1042 /* 1043 * Save actual SCSI status. 1044 */ 1045 scsi_status = cto->ct_scsi_status; 1046 1047 /* 1048 * We can't do a status at the same time as a data CTIO, so 1049 * we need to synthesize an extra CTIO at this level. 1050 */ 1051 nctios++; 1052 } else { 1053 sflags = scsi_status = resid = 0; 1054 } 1055 1056 totxfr = cto->ct_resid = 0; 1057 cto->ct_scsi_status = 0; 1058 1059 pci = (struct isp_pcisoftc *)mp->isp; 1060 dp = &pci->dmaps[isp_handle_index(handle)]; 1061 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1062 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1063 } else { 1064 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1065 } 1066 1067 1068 while (nctios--) { 1069 int seglim; 1070 1071 seglim = nseg; 1072 if (seglim) { 1073 int seg; 1074 1075 if (seglim > ISP_RQDSEG) 1076 seglim = ISP_RQDSEG; 1077 1078 for (seg = 0; seg < seglim; seg++, nseg--) { 1079 /* 1080 * Unlike normal initiator commands, we don't 1081 * do any swizzling here. 1082 */ 1083 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1084 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1085 cto->ct_xfrlen += dm_segs->ds_len; 1086 totxfr += dm_segs->ds_len; 1087 dm_segs++; 1088 } 1089 cto->ct_seg_count = seg; 1090 } else { 1091 /* 1092 * This case should only happen when we're sending an 1093 * extra CTIO with final status. 1094 */ 1095 if (send_status == 0) { 1096 printf("%s: tdma_mk ran out of segments\n", 1097 mp->isp->isp_name); 1098 mp->error = EINVAL; 1099 return; 1100 } 1101 } 1102 1103 /* 1104 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1105 * ct_tagtype, and ct_timeout have been carried over 1106 * unchanged from what our caller had set. 1107 * 1108 * The dataseg fields and the seg_count fields we just got 1109 * through setting. The data direction we've preserved all 1110 * along and only clear it if we're now sending status. 1111 */ 1112 1113 if (nctios == 0) { 1114 /* 1115 * We're the last in a sequence of CTIOs, so mark 1116 * this CTIO and save the handle to the CCB such that 1117 * when this CTIO completes we can free dma resources 1118 * and do whatever else we need to do to finish the 1119 * rest of the command. 1120 */ 1121 cto->ct_reserved = handle; 1122 cto->ct_header.rqs_seqno = 1; 1123 1124 if (send_status) { 1125 cto->ct_scsi_status = scsi_status; 1126 cto->ct_flags |= sflags | CT_NO_DATA;; 1127 cto->ct_resid = resid; 1128 } 1129 if (send_status) { 1130 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1131 "CTIO lun%d for ID %d ct_flags 0x%x scsi " 1132 "status %x resid %d", 1133 csio->ccb_h.target_lun, 1134 cto->ct_iid, cto->ct_flags, 1135 cto->ct_scsi_status, cto->ct_resid); 1136 } else { 1137 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1138 "CTIO lun%d for ID%d ct_flags 0x%x", 1139 csio->ccb_h.target_lun, 1140 cto->ct_iid, cto->ct_flags); 1141 } 1142 ISP_TDQE(mp->isp, "last tdma_mk", *mp->iptrp, cto); 1143 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1144 } else { 1145 ct_entry_t *octo = cto; 1146 1147 /* 1148 * Make sure handle fields are clean 1149 */ 1150 cto->ct_reserved = 0; 1151 cto->ct_header.rqs_seqno = 0; 1152 1153 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1154 "CTIO lun%d for ID%d ct_flags 0x%x", 1155 csio->ccb_h.target_lun, cto->ct_iid, cto->ct_flags); 1156 ISP_TDQE(mp->isp, "tdma_mk", *mp->iptrp, cto); 1157 1158 /* 1159 * Get a new CTIO 1160 */ 1161 cto = (ct_entry_t *) 1162 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1163 *mp->iptrp = 1164 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1165 if (*mp->iptrp == mp->optr) { 1166 printf("%s: Queue Overflow in tdma_mk\n", 1167 mp->isp->isp_name); 1168 mp->error = MUSHERR_NOQENTRIES; 1169 return; 1170 } 1171 /* 1172 * Fill in the new CTIO with info from the old one. 1173 */ 1174 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1175 cto->ct_header.rqs_entry_count = 1; 1176 cto->ct_header.rqs_flags = 0; 1177 cto->ct_lun = octo->ct_lun; 1178 cto->ct_iid = octo->ct_iid; 1179 cto->ct_reserved2 = octo->ct_reserved2; 1180 cto->ct_tgt = octo->ct_tgt; 1181 cto->ct_flags = octo->ct_flags; 1182 cto->ct_status = 0; 1183 cto->ct_scsi_status = 0; 1184 cto->ct_tag_val = octo->ct_tag_val; 1185 cto->ct_tag_type = octo->ct_tag_type; 1186 cto->ct_xfrlen = 0; 1187 cto->ct_resid = 0; 1188 cto->ct_timeout = octo->ct_timeout; 1189 cto->ct_seg_count = 0; 1190 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1191 /* 1192 * Now swizzle the old one for the consumption of the 1193 * chip. 1194 */ 1195 ISP_SWIZ_CTIO(mp->isp, octo, octo); 1196 } 1197 } 1198 } 1199 1200 static void 1201 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1202 { 1203 mush_t *mp; 1204 struct ccb_scsiio *csio; 1205 struct isp_pcisoftc *pci; 1206 bus_dmamap_t *dp; 1207 ct2_entry_t *cto; 1208 u_int16_t scsi_status, send_status, send_sense; 1209 u_int32_t handle, totxfr, datalen; 1210 u_int8_t sense[QLTM_SENSELEN]; 1211 int nctios; 1212 1213 mp = (mush_t *) arg; 1214 if (error) { 1215 mp->error = error; 1216 return; 1217 } 1218 1219 csio = mp->cmd_token; 1220 cto = mp->rq; 1221 1222 if (nseg == 0) { 1223 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1224 printf("%s: dma2_tgt_fc, a status CTIO2 without MODE1 " 1225 "set (0x%x)\n", mp->isp->isp_name, cto->ct_flags); 1226 mp->error = EINVAL; 1227 return; 1228 } 1229 cto->ct_header.rqs_entry_count = 1; 1230 cto->ct_header.rqs_seqno = 1; 1231 /* ct_reserved contains the handle set by caller */ 1232 /* 1233 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1234 * flags to NO DATA and clear relative offset flags. 1235 * We preserve the ct_resid and the response area. 1236 */ 1237 cto->ct_flags |= CT2_NO_DATA; 1238 if (cto->ct_resid > 0) 1239 cto->ct_flags |= CT2_DATA_UNDER; 1240 else if (cto->ct_resid < 0) 1241 cto->ct_flags |= CT2_DATA_OVER; 1242 cto->ct_seg_count = 0; 1243 cto->ct_reloff = 0; 1244 ISP_TDQE(mp->isp, "dma2_tgt_fc[no data]", *mp->iptrp, cto); 1245 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1246 "CTIO2 RX_ID 0x%x lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1247 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1248 cto->ct_iid, cto->ct_flags, cto->ct_status, 1249 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1250 ISP_SWIZ_CTIO2(isp, cto, cto); 1251 return; 1252 } 1253 1254 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1255 printf("%s: dma2_tgt_fc, a data CTIO2 without MODE0 set " 1256 "(0x%x)\n\n", mp->isp->isp_name, cto->ct_flags); 1257 mp->error = EINVAL; 1258 return; 1259 } 1260 1261 1262 nctios = nseg / ISP_RQDSEG_T2; 1263 if (nseg % ISP_RQDSEG_T2) { 1264 nctios++; 1265 } 1266 1267 /* 1268 * Save the handle, status, reloff, and residual. We'll reinsert the 1269 * handle into the last CTIO2 we're going to send, and reinsert status 1270 * and residual (and possibly sense data) if that's to be sent as well. 1271 * 1272 * We preserve ct_reloff and adjust it for each data CTIO2 we send past 1273 * the first one. This is needed so that the FCP DATA IUs being sent 1274 * out have the correct offset (they can arrive at the other end out 1275 * of order). 1276 */ 1277 1278 handle = cto->ct_reserved; 1279 cto->ct_reserved = 0; 1280 1281 if ((send_status = (cto->ct_flags & CT2_SENDSTATUS)) != 0) { 1282 cto->ct_flags &= ~CT2_SENDSTATUS; 1283 1284 /* 1285 * Preserve residual, which is actually the total count. 1286 */ 1287 datalen = cto->ct_resid; 1288 1289 /* 1290 * Save actual SCSI status. We'll reinsert the 1291 * CT2_SNSLEN_VALID later if appropriate. 1292 */ 1293 scsi_status = cto->rsp.m0.ct_scsi_status & 0xff; 1294 send_sense = cto->rsp.m0.ct_scsi_status & CT2_SNSLEN_VALID; 1295 1296 /* 1297 * If we're sending status and have a CHECK CONDTION and 1298 * have sense data, we send one more CTIO2 with just the 1299 * status and sense data. The upper layers have stashed 1300 * the sense data in the dataseg structure for us. 1301 */ 1302 1303 if ((scsi_status & 0xf) == SCSI_STATUS_CHECK_COND && 1304 send_sense) { 1305 bcopy(cto->rsp.m0.ct_dataseg, sense, QLTM_SENSELEN); 1306 nctios++; 1307 } 1308 } else { 1309 scsi_status = send_sense = datalen = 0; 1310 } 1311 1312 totxfr = cto->ct_resid = 0; 1313 cto->rsp.m0.ct_scsi_status = 0; 1314 bzero(&cto->rsp, sizeof (cto->rsp)); 1315 1316 pci = (struct isp_pcisoftc *)mp->isp; 1317 dp = &pci->dmaps[isp_handle_index(handle)]; 1318 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1319 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1320 } else { 1321 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1322 } 1323 1324 while (nctios--) { 1325 int seg, seglim; 1326 1327 seglim = nseg; 1328 if (seglim) { 1329 if (seglim > ISP_RQDSEG_T2) 1330 seglim = ISP_RQDSEG_T2; 1331 1332 for (seg = 0; seg < seglim; seg++) { 1333 cto->rsp.m0.ct_dataseg[seg].ds_base = 1334 dm_segs->ds_addr; 1335 cto->rsp.m0.ct_dataseg[seg].ds_count = 1336 dm_segs->ds_len; 1337 cto->rsp.m0.ct_xfrlen += dm_segs->ds_len; 1338 totxfr += dm_segs->ds_len; 1339 dm_segs++; 1340 } 1341 cto->ct_seg_count = seg; 1342 } else { 1343 /* 1344 * This case should only happen when we're sending a 1345 * synthesized MODE1 final status with sense data. 1346 */ 1347 if (send_sense == 0) { 1348 printf("%s: dma2_tgt_fc ran out of segments, " 1349 "no SENSE DATA\n", mp->isp->isp_name); 1350 mp->error = EINVAL; 1351 return; 1352 } 1353 } 1354 1355 /* 1356 * At this point, the fields ct_lun, ct_iid, ct_rxid, 1357 * ct_timeout have been carried over unchanged from what 1358 * our caller had set. 1359 * 1360 * The field ct_reloff is either what the caller set, or 1361 * what we've added to below. 1362 * 1363 * The dataseg fields and the seg_count fields we just got 1364 * through setting. The data direction we've preserved all 1365 * along and only clear it if we're sending a MODE1 status 1366 * as the last CTIO. 1367 * 1368 */ 1369 1370 if (nctios == 0) { 1371 1372 /* 1373 * We're the last in a sequence of CTIO2s, so mark this 1374 * CTIO2 and save the handle to the CCB such that when 1375 * this CTIO2 completes we can free dma resources and 1376 * do whatever else we need to do to finish the rest 1377 * of the command. 1378 */ 1379 1380 cto->ct_reserved = handle; 1381 cto->ct_header.rqs_seqno = 1; 1382 1383 if (send_status) { 1384 if (send_sense) { 1385 bcopy(sense, cto->rsp.m1.ct_resp, 1386 QLTM_SENSELEN); 1387 cto->rsp.m1.ct_senselen = 1388 QLTM_SENSELEN; 1389 scsi_status |= CT2_SNSLEN_VALID; 1390 cto->rsp.m1.ct_scsi_status = 1391 scsi_status; 1392 cto->ct_flags &= CT2_FLAG_MMASK; 1393 cto->ct_flags |= CT2_FLAG_MODE1 | 1394 CT2_NO_DATA| CT2_SENDSTATUS; 1395 } else { 1396 cto->rsp.m0.ct_scsi_status = 1397 scsi_status; 1398 cto->ct_flags |= CT2_SENDSTATUS; 1399 } 1400 /* 1401 * Get 'real' residual and set flags based 1402 * on it. 1403 */ 1404 cto->ct_resid = datalen - totxfr; 1405 if (cto->ct_resid > 0) 1406 cto->ct_flags |= CT2_DATA_UNDER; 1407 else if (cto->ct_resid < 0) 1408 cto->ct_flags |= CT2_DATA_OVER; 1409 } 1410 ISP_TDQE(mp->isp, "last dma2_tgt_fc", *mp->iptrp, cto); 1411 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1412 "CTIO2 RX_ID 0x%x lun %d->iid%d flgs 0x%x sts 0x%x" 1413 " ssts 0x%x res %d", cto->ct_rxid, 1414 csio->ccb_h.target_lun, (int) cto->ct_iid, 1415 cto->ct_flags, cto->ct_status, 1416 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1417 ISP_SWIZ_CTIO2(isp, cto, cto); 1418 } else { 1419 ct2_entry_t *octo = cto; 1420 1421 /* 1422 * Make sure handle fields are clean 1423 */ 1424 cto->ct_reserved = 0; 1425 cto->ct_header.rqs_seqno = 0; 1426 1427 ISP_TDQE(mp->isp, "dma2_tgt_fc", *mp->iptrp, cto); 1428 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1429 "CTIO2 RX_ID 0x%x lun %d->iid%d flgs 0x%x", 1430 cto->ct_rxid, csio->ccb_h.target_lun, 1431 (int) cto->ct_iid, cto->ct_flags); 1432 /* 1433 * Get a new CTIO2 1434 */ 1435 cto = (ct2_entry_t *) 1436 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1437 *mp->iptrp = 1438 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1439 if (*mp->iptrp == mp->optr) { 1440 printf("%s: Queue Overflow in dma2_tgt_fc\n", 1441 mp->isp->isp_name); 1442 mp->error = MUSHERR_NOQENTRIES; 1443 return; 1444 } 1445 1446 /* 1447 * Fill in the new CTIO2 with info from the old one. 1448 */ 1449 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO2; 1450 cto->ct_header.rqs_entry_count = 1; 1451 cto->ct_header.rqs_flags = 0; 1452 /* ct_header.rqs_seqno && ct_reserved done later */ 1453 cto->ct_lun = octo->ct_lun; 1454 cto->ct_iid = octo->ct_iid; 1455 cto->ct_rxid = octo->ct_rxid; 1456 cto->ct_flags = octo->ct_flags; 1457 cto->ct_status = 0; 1458 cto->ct_resid = 0; 1459 cto->ct_timeout = octo->ct_timeout; 1460 cto->ct_seg_count = 0; 1461 /* 1462 * Adjust the new relative offset by the amount which 1463 * is recorded in the data segment of the old CTIO2 we 1464 * just finished filling out. 1465 */ 1466 cto->ct_reloff += octo->rsp.m0.ct_xfrlen; 1467 bzero(&cto->rsp, sizeof (cto->rsp)); 1468 ISP_SWIZ_CTIO2(isp, cto, cto); 1469 } 1470 } 1471 } 1472 #endif 1473 1474 static void dma2 __P((void *, bus_dma_segment_t *, int, int)); 1475 1476 static void 1477 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1478 { 1479 mush_t *mp; 1480 struct ccb_scsiio *csio; 1481 struct isp_pcisoftc *pci; 1482 bus_dmamap_t *dp; 1483 bus_dma_segment_t *eseg; 1484 ispreq_t *rq; 1485 ispcontreq_t *crq; 1486 int seglim, datalen; 1487 1488 mp = (mush_t *) arg; 1489 if (error) { 1490 mp->error = error; 1491 return; 1492 } 1493 1494 if (nseg < 1) { 1495 printf("%s: bad segment count (%d)\n", mp->isp->isp_name, nseg); 1496 mp->error = EFAULT; 1497 return; 1498 } 1499 csio = mp->cmd_token; 1500 rq = mp->rq; 1501 pci = (struct isp_pcisoftc *)mp->isp; 1502 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1503 1504 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1505 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1506 } else { 1507 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1508 } 1509 1510 datalen = XS_XFRLEN(csio); 1511 1512 /* 1513 * We're passed an initial partially filled in entry that 1514 * has most fields filled in except for data transfer 1515 * related values. 1516 * 1517 * Our job is to fill in the initial request queue entry and 1518 * then to start allocating and filling in continuation entries 1519 * until we've covered the entire transfer. 1520 */ 1521 1522 if (IS_FC(mp->isp)) { 1523 seglim = ISP_RQDSEG_T2; 1524 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1525 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1526 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1527 } else { 1528 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1529 } 1530 } else { 1531 if (csio->cdb_len > 12) { 1532 seglim = 0; 1533 } else { 1534 seglim = ISP_RQDSEG; 1535 } 1536 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1537 rq->req_flags |= REQFLAG_DATA_IN; 1538 } else { 1539 rq->req_flags |= REQFLAG_DATA_OUT; 1540 } 1541 } 1542 1543 eseg = dm_segs + nseg; 1544 1545 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1546 if (IS_FC(mp->isp)) { 1547 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1548 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1549 dm_segs->ds_addr; 1550 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1551 dm_segs->ds_len; 1552 } else { 1553 rq->req_dataseg[rq->req_seg_count].ds_base = 1554 dm_segs->ds_addr; 1555 rq->req_dataseg[rq->req_seg_count].ds_count = 1556 dm_segs->ds_len; 1557 } 1558 datalen -= dm_segs->ds_len; 1559 #if 0 1560 if (IS_FC(mp->isp)) { 1561 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1562 printf("%s: seg0[%d] cnt 0x%x paddr 0x%08x\n", 1563 mp->isp->isp_name, rq->req_seg_count, 1564 rq2->req_dataseg[rq2->req_seg_count].ds_count, 1565 rq2->req_dataseg[rq2->req_seg_count].ds_base); 1566 } else { 1567 printf("%s: seg0[%d] cnt 0x%x paddr 0x%08x\n", 1568 mp->isp->isp_name, rq->req_seg_count, 1569 rq->req_dataseg[rq->req_seg_count].ds_count, 1570 rq->req_dataseg[rq->req_seg_count].ds_base); 1571 } 1572 #endif 1573 rq->req_seg_count++; 1574 dm_segs++; 1575 } 1576 1577 while (datalen > 0 && dm_segs != eseg) { 1578 crq = (ispcontreq_t *) 1579 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1580 *mp->iptrp = ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1581 if (*mp->iptrp == mp->optr) { 1582 #if 0 1583 printf("%s: Request Queue Overflow++\n", 1584 mp->isp->isp_name); 1585 #endif 1586 mp->error = MUSHERR_NOQENTRIES; 1587 return; 1588 } 1589 rq->req_header.rqs_entry_count++; 1590 bzero((void *)crq, sizeof (*crq)); 1591 crq->req_header.rqs_entry_count = 1; 1592 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1593 1594 seglim = 0; 1595 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1596 crq->req_dataseg[seglim].ds_base = 1597 dm_segs->ds_addr; 1598 crq->req_dataseg[seglim].ds_count = 1599 dm_segs->ds_len; 1600 #if 0 1601 printf("%s: seg%d[%d] cnt 0x%x paddr 0x%08x\n", 1602 mp->isp->isp_name, rq->req_header.rqs_entry_count-1, 1603 seglim, crq->req_dataseg[seglim].ds_count, 1604 crq->req_dataseg[seglim].ds_base); 1605 #endif 1606 rq->req_seg_count++; 1607 dm_segs++; 1608 seglim++; 1609 datalen -= dm_segs->ds_len; 1610 } 1611 } 1612 } 1613 1614 static int 1615 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1616 u_int16_t *iptrp, u_int16_t optr) 1617 { 1618 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1619 bus_dmamap_t *dp = NULL; 1620 mush_t mush, *mp; 1621 void (*eptr) __P((void *, bus_dma_segment_t *, int, int)); 1622 1623 #ifdef ISP_TARGET_MODE 1624 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1625 if (IS_FC(isp)) { 1626 eptr = tdma_mkfc; 1627 } else { 1628 eptr = tdma_mk; 1629 } 1630 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1631 (csio->dxfer_len == 0)) { 1632 rq->req_seg_count = 1; 1633 mp = &mush; 1634 mp->isp = isp; 1635 mp->cmd_token = csio; 1636 mp->rq = rq; 1637 mp->iptrp = iptrp; 1638 mp->optr = optr; 1639 mp->error = 0; 1640 (*eptr)(mp, NULL, 0, 0); 1641 goto exit; 1642 } 1643 } else 1644 #endif 1645 eptr = dma2; 1646 1647 /* 1648 * NB: if we need to do request queue entry swizzling, 1649 * NB: this is where it would need to be done for cmds 1650 * NB: that move no data. For commands that move data, 1651 * NB: swizzling would take place in those functions. 1652 */ 1653 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1654 (csio->dxfer_len == 0)) { 1655 rq->req_seg_count = 1; 1656 return (CMD_QUEUED); 1657 } 1658 1659 /* 1660 * Do a virtual grapevine step to collect info for 1661 * the callback dma allocation that we have to use... 1662 */ 1663 mp = &mush; 1664 mp->isp = isp; 1665 mp->cmd_token = csio; 1666 mp->rq = rq; 1667 mp->iptrp = iptrp; 1668 mp->optr = optr; 1669 mp->error = 0; 1670 1671 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1672 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1673 int error, s; 1674 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1675 s = splsoftvm(); 1676 error = bus_dmamap_load(pci->parent_dmat, *dp, 1677 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1678 if (error == EINPROGRESS) { 1679 bus_dmamap_unload(pci->parent_dmat, *dp); 1680 mp->error = EINVAL; 1681 printf("%s: deferred dma allocation not " 1682 "supported\n", isp->isp_name); 1683 } else if (error && mp->error == 0) { 1684 #ifdef DIAGNOSTIC 1685 printf("%s: error %d in dma mapping code\n", 1686 isp->isp_name, error); 1687 #endif 1688 mp->error = error; 1689 } 1690 splx(s); 1691 } else { 1692 /* Pointer to physical buffer */ 1693 struct bus_dma_segment seg; 1694 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1695 seg.ds_len = csio->dxfer_len; 1696 (*eptr)(mp, &seg, 1, 0); 1697 } 1698 } else { 1699 struct bus_dma_segment *segs; 1700 1701 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1702 printf("%s: Physical segment pointers unsupported", 1703 isp->isp_name); 1704 mp->error = EINVAL; 1705 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1706 printf("%s: Virtual segment addresses unsupported", 1707 isp->isp_name); 1708 mp->error = EINVAL; 1709 } else { 1710 /* Just use the segments provided */ 1711 segs = (struct bus_dma_segment *) csio->data_ptr; 1712 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1713 } 1714 } 1715 #ifdef ISP_TARGET_MODE 1716 exit: 1717 #endif 1718 if (mp->error) { 1719 int retval = CMD_COMPLETE; 1720 if (mp->error == MUSHERR_NOQENTRIES) { 1721 retval = CMD_EAGAIN; 1722 } else if (mp->error == EFBIG) { 1723 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1724 } else if (mp->error == EINVAL) { 1725 XS_SETERR(csio, CAM_REQ_INVALID); 1726 } else { 1727 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1728 } 1729 return (retval); 1730 } else { 1731 /* 1732 * Check to see if we weren't cancelled while sleeping on 1733 * getting DMA resources... 1734 */ 1735 if ((csio->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 1736 if (dp) { 1737 bus_dmamap_unload(pci->parent_dmat, *dp); 1738 } 1739 return (CMD_COMPLETE); 1740 } 1741 return (CMD_QUEUED); 1742 } 1743 } 1744 1745 static void 1746 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int32_t handle) 1747 { 1748 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1749 bus_dmamap_t *dp = &pci->dmaps[isp_handle_index(handle)]; 1750 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1751 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTREAD); 1752 } else { 1753 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTWRITE); 1754 } 1755 bus_dmamap_unload(pci->parent_dmat, *dp); 1756 } 1757 1758 1759 static void 1760 isp_pci_reset1(struct ispsoftc *isp) 1761 { 1762 /* Make sure the BIOS is disabled */ 1763 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1764 /* and enable interrupts */ 1765 ENABLE_INTS(isp); 1766 } 1767 1768 static void 1769 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1770 { 1771 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1772 if (msg) 1773 printf("%s: %s\n", isp->isp_name, msg); 1774 if (IS_SCSI(isp)) 1775 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1776 else 1777 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1778 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1779 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1780 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1781 1782 1783 if (IS_SCSI(isp)) { 1784 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1785 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1786 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1787 ISP_READ(isp, CDMA_FIFO_STS)); 1788 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1789 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1790 ISP_READ(isp, DDMA_FIFO_STS)); 1791 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1792 ISP_READ(isp, SXP_INTERRUPT), 1793 ISP_READ(isp, SXP_GROSS_ERR), 1794 ISP_READ(isp, SXP_PINS_CTRL)); 1795 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1796 } 1797 printf(" mbox regs: %x %x %x %x %x\n", 1798 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1799 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1800 ISP_READ(isp, OUTMAILBOX4)); 1801 printf(" PCI Status Command/Status=%x\n", 1802 pci_read_config(pci->pci_dev, PCIR_COMMAND, 1)); 1803 } 1804