1 /*- 2 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 3 * FreeBSD Version. 4 * 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 by Matthew Jacob 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice immediately at the beginning of the file, without modification, 12 * this list of conditions, and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <machine/bus_memio.h> 42 #include <machine/bus_pio.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 #include <sys/malloc.h> 47 48 #include <dev/isp/isp_freebsd.h> 49 50 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 51 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 52 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 53 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 54 static int 55 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 56 static int 57 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 58 static int isp_pci_mbxdma(struct ispsoftc *); 59 static int 60 isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, u_int16_t *, u_int16_t); 61 static void 62 isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 63 64 static void isp_pci_reset1(struct ispsoftc *); 65 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 66 67 static struct ispmdvec mdvec = { 68 isp_pci_rd_isr, 69 isp_pci_rd_reg, 70 isp_pci_wr_reg, 71 isp_pci_mbxdma, 72 isp_pci_dmasetup, 73 isp_pci_dmateardown, 74 NULL, 75 isp_pci_reset1, 76 isp_pci_dumpregs, 77 NULL, 78 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 79 }; 80 81 static struct ispmdvec mdvec_1080 = { 82 isp_pci_rd_isr, 83 isp_pci_rd_reg_1080, 84 isp_pci_wr_reg_1080, 85 isp_pci_mbxdma, 86 isp_pci_dmasetup, 87 isp_pci_dmateardown, 88 NULL, 89 isp_pci_reset1, 90 isp_pci_dumpregs, 91 NULL, 92 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 93 }; 94 95 static struct ispmdvec mdvec_12160 = { 96 isp_pci_rd_isr, 97 isp_pci_rd_reg_1080, 98 isp_pci_wr_reg_1080, 99 isp_pci_mbxdma, 100 isp_pci_dmasetup, 101 isp_pci_dmateardown, 102 NULL, 103 isp_pci_reset1, 104 isp_pci_dumpregs, 105 NULL, 106 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 107 }; 108 109 static struct ispmdvec mdvec_2100 = { 110 isp_pci_rd_isr, 111 isp_pci_rd_reg, 112 isp_pci_wr_reg, 113 isp_pci_mbxdma, 114 isp_pci_dmasetup, 115 isp_pci_dmateardown, 116 NULL, 117 isp_pci_reset1, 118 isp_pci_dumpregs 119 }; 120 121 static struct ispmdvec mdvec_2200 = { 122 isp_pci_rd_isr, 123 isp_pci_rd_reg, 124 isp_pci_wr_reg, 125 isp_pci_mbxdma, 126 isp_pci_dmasetup, 127 isp_pci_dmateardown, 128 NULL, 129 isp_pci_reset1, 130 isp_pci_dumpregs 131 }; 132 133 static struct ispmdvec mdvec_2300 = { 134 isp_pci_rd_isr_2300, 135 isp_pci_rd_reg, 136 isp_pci_wr_reg, 137 isp_pci_mbxdma, 138 isp_pci_dmasetup, 139 isp_pci_dmateardown, 140 NULL, 141 isp_pci_reset1, 142 isp_pci_dumpregs 143 }; 144 145 #ifndef PCIM_CMD_INVEN 146 #define PCIM_CMD_INVEN 0x10 147 #endif 148 #ifndef PCIM_CMD_BUSMASTEREN 149 #define PCIM_CMD_BUSMASTEREN 0x0004 150 #endif 151 #ifndef PCIM_CMD_PERRESPEN 152 #define PCIM_CMD_PERRESPEN 0x0040 153 #endif 154 #ifndef PCIM_CMD_SEREN 155 #define PCIM_CMD_SEREN 0x0100 156 #endif 157 158 #ifndef PCIR_COMMAND 159 #define PCIR_COMMAND 0x04 160 #endif 161 162 #ifndef PCIR_CACHELNSZ 163 #define PCIR_CACHELNSZ 0x0c 164 #endif 165 166 #ifndef PCIR_LATTIMER 167 #define PCIR_LATTIMER 0x0d 168 #endif 169 170 #ifndef PCIR_ROMADDR 171 #define PCIR_ROMADDR 0x30 172 #endif 173 174 #ifndef PCI_VENDOR_QLOGIC 175 #define PCI_VENDOR_QLOGIC 0x1077 176 #endif 177 178 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 179 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 180 #endif 181 182 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 183 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 184 #endif 185 186 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 187 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 188 #endif 189 190 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 191 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 192 #endif 193 194 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 195 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 196 #endif 197 198 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 199 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 200 #endif 201 202 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 203 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 204 #endif 205 206 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 207 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 208 #endif 209 210 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 211 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 212 #endif 213 214 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 215 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 216 #endif 217 218 #define PCI_QLOGIC_ISP1020 \ 219 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 220 221 #define PCI_QLOGIC_ISP1080 \ 222 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 223 224 #define PCI_QLOGIC_ISP10160 \ 225 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 226 227 #define PCI_QLOGIC_ISP12160 \ 228 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 229 230 #define PCI_QLOGIC_ISP1240 \ 231 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 232 233 #define PCI_QLOGIC_ISP1280 \ 234 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 235 236 #define PCI_QLOGIC_ISP2100 \ 237 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 238 239 #define PCI_QLOGIC_ISP2200 \ 240 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 241 242 #define PCI_QLOGIC_ISP2300 \ 243 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 244 245 #define PCI_QLOGIC_ISP2312 \ 246 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 247 248 /* 249 * Odd case for some AMI raid cards... We need to *not* attach to this. 250 */ 251 #define AMI_RAID_SUBVENDOR_ID 0x101e 252 253 #define IO_MAP_REG 0x10 254 #define MEM_MAP_REG 0x14 255 256 #define PCI_DFLT_LTNCY 0x40 257 #define PCI_DFLT_LNSZ 0x10 258 259 static int isp_pci_probe (device_t); 260 static int isp_pci_attach (device_t); 261 262 263 struct isp_pcisoftc { 264 struct ispsoftc pci_isp; 265 device_t pci_dev; 266 struct resource * pci_reg; 267 bus_space_tag_t pci_st; 268 bus_space_handle_t pci_sh; 269 void * ih; 270 int16_t pci_poff[_NREG_BLKS]; 271 bus_dma_tag_t dmat; 272 bus_dmamap_t *dmaps; 273 }; 274 extern ispfwfunc *isp_get_firmware_p; 275 276 static device_method_t isp_pci_methods[] = { 277 /* Device interface */ 278 DEVMETHOD(device_probe, isp_pci_probe), 279 DEVMETHOD(device_attach, isp_pci_attach), 280 { 0, 0 } 281 }; 282 static void isp_pci_intr(void *); 283 284 static driver_t isp_pci_driver = { 285 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 286 }; 287 static devclass_t isp_devclass; 288 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 289 290 static int 291 isp_pci_probe(device_t dev) 292 { 293 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 294 case PCI_QLOGIC_ISP1020: 295 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 296 break; 297 case PCI_QLOGIC_ISP1080: 298 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 299 break; 300 case PCI_QLOGIC_ISP1240: 301 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 302 break; 303 case PCI_QLOGIC_ISP1280: 304 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 305 break; 306 case PCI_QLOGIC_ISP10160: 307 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 308 break; 309 case PCI_QLOGIC_ISP12160: 310 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 311 return (ENXIO); 312 } 313 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 314 break; 315 case PCI_QLOGIC_ISP2100: 316 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 317 break; 318 case PCI_QLOGIC_ISP2200: 319 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 320 break; 321 case PCI_QLOGIC_ISP2300: 322 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 323 break; 324 case PCI_QLOGIC_ISP2312: 325 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 326 break; 327 default: 328 return (ENXIO); 329 } 330 if (isp_announced == 0 && bootverbose) { 331 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 332 "Core Version %d.%d\n", 333 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 334 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 335 isp_announced++; 336 } 337 /* 338 * XXXX: Here is where we might load the f/w module 339 * XXXX: (or increase a reference count to it). 340 */ 341 return (0); 342 } 343 344 static int 345 isp_pci_attach(device_t dev) 346 { 347 struct resource *regs, *irq; 348 int tval, rtp, rgd, iqd, m1, m2, isp_debug, role; 349 u_int32_t data, cmd, linesz, psize, basetype; 350 struct isp_pcisoftc *pcs; 351 struct ispsoftc *isp = NULL; 352 struct ispmdvec *mdvp; 353 const char *sptr; 354 int locksetup = 0; 355 356 /* 357 * Figure out if we're supposed to skip this one. 358 */ 359 360 tval = 0; 361 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 362 "disable", &tval) == 0 && tval) { 363 device_printf(dev, "device is disabled\n"); 364 /* but return 0 so the !$)$)*!$*) unit isn't reused */ 365 return (0); 366 } 367 368 role = -1; 369 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 370 "role", &role) == 0 && role != -1) { 371 role &= (ISP_ROLE_INITIATOR|ISP_ROLE_TARGET); 372 device_printf(dev, "setting role to 0x%x\n", role); 373 } else { 374 #ifdef ISP_TARGET_MODE 375 role = ISP_ROLE_TARGET; 376 #else 377 role = ISP_DEFAULT_ROLES; 378 #endif 379 } 380 381 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT | M_ZERO); 382 if (pcs == NULL) { 383 device_printf(dev, "cannot allocate softc\n"); 384 return (ENOMEM); 385 } 386 387 /* 388 * Figure out which we should try first - memory mapping or i/o mapping? 389 */ 390 #ifdef __alpha__ 391 m1 = PCIM_CMD_MEMEN; 392 m2 = PCIM_CMD_PORTEN; 393 #else 394 m1 = PCIM_CMD_PORTEN; 395 m2 = PCIM_CMD_MEMEN; 396 #endif 397 398 tval = 0; 399 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 400 "prefer_iomap", &tval) == 0 && tval != 0) { 401 m1 = PCIM_CMD_PORTEN; 402 m2 = PCIM_CMD_MEMEN; 403 } 404 tval = 0; 405 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 406 "prefer_memmap", &tval) == 0 && tval != 0) { 407 m1 = PCIM_CMD_MEMEN; 408 m2 = PCIM_CMD_PORTEN; 409 } 410 411 linesz = PCI_DFLT_LNSZ; 412 irq = regs = NULL; 413 rgd = rtp = iqd = 0; 414 415 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 416 if (cmd & m1) { 417 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 418 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 419 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 420 } 421 if (regs == NULL && (cmd & m2)) { 422 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 423 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 424 regs = bus_alloc_resource_any(dev, rtp, &rgd, RF_ACTIVE); 425 } 426 if (regs == NULL) { 427 device_printf(dev, "unable to map any ports\n"); 428 goto bad; 429 } 430 if (bootverbose) 431 device_printf(dev, "using %s space register mapping\n", 432 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 433 pcs->pci_dev = dev; 434 pcs->pci_reg = regs; 435 pcs->pci_st = rman_get_bustag(regs); 436 pcs->pci_sh = rman_get_bushandle(regs); 437 438 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 439 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 440 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 441 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 442 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 443 mdvp = &mdvec; 444 basetype = ISP_HA_SCSI_UNKNOWN; 445 psize = sizeof (sdparam); 446 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 447 mdvp = &mdvec; 448 basetype = ISP_HA_SCSI_UNKNOWN; 449 psize = sizeof (sdparam); 450 } 451 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 452 mdvp = &mdvec_1080; 453 basetype = ISP_HA_SCSI_1080; 454 psize = sizeof (sdparam); 455 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 456 ISP1080_DMA_REGS_OFF; 457 } 458 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 459 mdvp = &mdvec_1080; 460 basetype = ISP_HA_SCSI_1240; 461 psize = 2 * sizeof (sdparam); 462 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 463 ISP1080_DMA_REGS_OFF; 464 } 465 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 466 mdvp = &mdvec_1080; 467 basetype = ISP_HA_SCSI_1280; 468 psize = 2 * sizeof (sdparam); 469 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 470 ISP1080_DMA_REGS_OFF; 471 } 472 if (pci_get_devid(dev) == PCI_QLOGIC_ISP10160) { 473 mdvp = &mdvec_12160; 474 basetype = ISP_HA_SCSI_10160; 475 psize = sizeof (sdparam); 476 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 477 ISP1080_DMA_REGS_OFF; 478 } 479 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 480 mdvp = &mdvec_12160; 481 basetype = ISP_HA_SCSI_12160; 482 psize = 2 * sizeof (sdparam); 483 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 484 ISP1080_DMA_REGS_OFF; 485 } 486 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 487 mdvp = &mdvec_2100; 488 basetype = ISP_HA_FC_2100; 489 psize = sizeof (fcparam); 490 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 491 PCI_MBOX_REGS2100_OFF; 492 if (pci_get_revid(dev) < 3) { 493 /* 494 * XXX: Need to get the actual revision 495 * XXX: number of the 2100 FB. At any rate, 496 * XXX: lower cache line size for early revision 497 * XXX; boards. 498 */ 499 linesz = 1; 500 } 501 } 502 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 503 mdvp = &mdvec_2200; 504 basetype = ISP_HA_FC_2200; 505 psize = sizeof (fcparam); 506 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 507 PCI_MBOX_REGS2100_OFF; 508 } 509 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2300) { 510 mdvp = &mdvec_2300; 511 basetype = ISP_HA_FC_2300; 512 psize = sizeof (fcparam); 513 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 514 PCI_MBOX_REGS2300_OFF; 515 } 516 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2312) { 517 mdvp = &mdvec_2300; 518 basetype = ISP_HA_FC_2312; 519 psize = sizeof (fcparam); 520 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 521 PCI_MBOX_REGS2300_OFF; 522 } 523 isp = &pcs->pci_isp; 524 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 525 if (isp->isp_param == NULL) { 526 device_printf(dev, "cannot allocate parameter data\n"); 527 goto bad; 528 } 529 isp->isp_mdvec = mdvp; 530 isp->isp_type = basetype; 531 isp->isp_revision = pci_get_revid(dev); 532 isp->isp_role = role; 533 isp->isp_dev = dev; 534 535 /* 536 * Try and find firmware for this device. 537 */ 538 539 if (isp_get_firmware_p) { 540 int device = (int) pci_get_device(dev); 541 #ifdef ISP_TARGET_MODE 542 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 543 #else 544 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 545 #endif 546 } 547 548 /* 549 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 550 * are set. 551 */ 552 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 553 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 554 if (IS_2300(isp)) { /* per QLogic errata */ 555 cmd &= ~PCIM_CMD_INVEN; 556 } 557 if (IS_23XX(isp)) { 558 /* 559 * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command. 560 */ 561 isp->isp_touched = 1; 562 563 } 564 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 565 566 /* 567 * Make sure the Cache Line Size register is set sensibly. 568 */ 569 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 570 if (data != linesz) { 571 data = PCI_DFLT_LNSZ; 572 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 573 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 574 } 575 576 /* 577 * Make sure the Latency Timer is sane. 578 */ 579 data = pci_read_config(dev, PCIR_LATTIMER, 1); 580 if (data < PCI_DFLT_LTNCY) { 581 data = PCI_DFLT_LTNCY; 582 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 583 pci_write_config(dev, PCIR_LATTIMER, data, 1); 584 } 585 586 /* 587 * Make sure we've disabled the ROM. 588 */ 589 data = pci_read_config(dev, PCIR_ROMADDR, 4); 590 data &= ~1; 591 pci_write_config(dev, PCIR_ROMADDR, data, 4); 592 593 iqd = 0; 594 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd, 595 RF_ACTIVE | RF_SHAREABLE); 596 if (irq == NULL) { 597 device_printf(dev, "could not allocate interrupt\n"); 598 goto bad; 599 } 600 601 tval = 0; 602 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 603 "fwload_disable", &tval) == 0 && tval != 0) { 604 isp->isp_confopts |= ISP_CFG_NORELOAD; 605 } 606 tval = 0; 607 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 608 "ignore_nvram", &tval) == 0 && tval != 0) { 609 isp->isp_confopts |= ISP_CFG_NONVRAM; 610 } 611 tval = 0; 612 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 613 "fullduplex", &tval) == 0 && tval != 0) { 614 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 615 } 616 #ifdef ISP_FW_CRASH_DUMP 617 tval = 0; 618 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 619 "fw_dump_enable", &tval) == 0 && tval != 0) { 620 size_t amt = 0; 621 if (IS_2200(isp)) { 622 amt = QLA2200_RISC_IMAGE_DUMP_SIZE; 623 } else if (IS_23XX(isp)) { 624 amt = QLA2300_RISC_IMAGE_DUMP_SIZE; 625 } 626 if (amt) { 627 FCPARAM(isp)->isp_dump_data = 628 malloc(amt, M_DEVBUF, M_WAITOK | M_ZERO); 629 } else { 630 device_printf(dev, 631 "f/w crash dumps not supported for this model\n"); 632 } 633 } 634 #endif 635 636 sptr = 0; 637 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 638 "topology", (const char **) &sptr) == 0 && sptr != 0) { 639 if (strcmp(sptr, "lport") == 0) { 640 isp->isp_confopts |= ISP_CFG_LPORT; 641 } else if (strcmp(sptr, "nport") == 0) { 642 isp->isp_confopts |= ISP_CFG_NPORT; 643 } else if (strcmp(sptr, "lport-only") == 0) { 644 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 645 } else if (strcmp(sptr, "nport-only") == 0) { 646 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 647 } 648 } 649 650 /* 651 * Because the resource_*_value functions can neither return 652 * 64 bit integer values, nor can they be directly coerced 653 * to interpret the right hand side of the assignment as 654 * you want them to interpret it, we have to force WWN 655 * hint replacement to specify WWN strings with a leading 656 * 'w' (e..g w50000000aaaa0001). Sigh. 657 */ 658 sptr = 0; 659 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 660 "portwwn", (const char **) &sptr); 661 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 662 char *eptr = 0; 663 isp->isp_osinfo.default_port_wwn = strtouq(sptr, &eptr, 16); 664 if (eptr < sptr + 16 || isp->isp_osinfo.default_port_wwn == 0) { 665 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 666 isp->isp_osinfo.default_port_wwn = 0; 667 } else { 668 isp->isp_confopts |= ISP_CFG_OWNWWPN; 669 } 670 } 671 if (isp->isp_osinfo.default_port_wwn == 0) { 672 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 673 } 674 675 sptr = 0; 676 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 677 "nodewwn", (const char **) &sptr); 678 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 679 char *eptr = 0; 680 isp->isp_osinfo.default_node_wwn = strtouq(sptr, &eptr, 16); 681 if (eptr < sptr + 16 || isp->isp_osinfo.default_node_wwn == 0) { 682 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 683 isp->isp_osinfo.default_node_wwn = 0; 684 } else { 685 isp->isp_confopts |= ISP_CFG_OWNWWNN; 686 } 687 } 688 if (isp->isp_osinfo.default_node_wwn == 0) { 689 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 690 } 691 692 isp->isp_osinfo.default_id = -1; 693 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 694 "iid", &tval) == 0) { 695 isp->isp_osinfo.default_id = tval; 696 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 697 } 698 if (isp->isp_osinfo.default_id == -1) { 699 if (IS_FC(isp)) { 700 isp->isp_osinfo.default_id = 109; 701 } else { 702 isp->isp_osinfo.default_id = 7; 703 } 704 } 705 706 isp_debug = 0; 707 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 708 "debug", &isp_debug); 709 710 /* Make sure the lock is set up. */ 711 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 712 locksetup++; 713 714 if (bus_setup_intr(dev, irq, ISP_IFLAGS, isp_pci_intr, isp, &pcs->ih)) { 715 device_printf(dev, "could not setup interrupt\n"); 716 goto bad; 717 } 718 719 /* 720 * Set up logging levels. 721 */ 722 if (isp_debug) { 723 isp->isp_dblev = isp_debug; 724 } else { 725 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 726 } 727 if (bootverbose) 728 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 729 730 /* 731 * Last minute checks... 732 */ 733 if (IS_2312(isp)) { 734 isp->isp_port = pci_get_function(dev); 735 } 736 737 /* 738 * Make sure we're in reset state. 739 */ 740 ISP_LOCK(isp); 741 isp_reset(isp); 742 if (isp->isp_state != ISP_RESETSTATE) { 743 ISP_UNLOCK(isp); 744 goto bad; 745 } 746 isp_init(isp); 747 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_INITSTATE) { 748 isp_uninit(isp); 749 ISP_UNLOCK(isp); 750 goto bad; 751 } 752 isp_attach(isp); 753 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_RUNSTATE) { 754 isp_uninit(isp); 755 ISP_UNLOCK(isp); 756 goto bad; 757 } 758 /* 759 * XXXX: Here is where we might unload the f/w module 760 * XXXX: (or decrease the reference count to it). 761 */ 762 ISP_UNLOCK(isp); 763 return (0); 764 765 bad: 766 767 if (pcs && pcs->ih) { 768 (void) bus_teardown_intr(dev, irq, pcs->ih); 769 } 770 771 if (locksetup && isp) { 772 mtx_destroy(&isp->isp_osinfo.lock); 773 } 774 775 if (irq) { 776 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 777 } 778 779 780 if (regs) { 781 (void) bus_release_resource(dev, rtp, rgd, regs); 782 } 783 784 if (pcs) { 785 if (pcs->pci_isp.isp_param) 786 free(pcs->pci_isp.isp_param, M_DEVBUF); 787 free(pcs, M_DEVBUF); 788 } 789 790 /* 791 * XXXX: Here is where we might unload the f/w module 792 * XXXX: (or decrease the reference count to it). 793 */ 794 return (ENXIO); 795 } 796 797 static void 798 isp_pci_intr(void *arg) 799 { 800 struct ispsoftc *isp = arg; 801 u_int16_t isr, sema, mbox; 802 803 ISP_LOCK(isp); 804 isp->isp_intcnt++; 805 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 806 isp->isp_intbogus++; 807 } else { 808 int iok = isp->isp_osinfo.intsok; 809 isp->isp_osinfo.intsok = 0; 810 isp_intr(isp, isr, sema, mbox); 811 isp->isp_osinfo.intsok = iok; 812 } 813 ISP_UNLOCK(isp); 814 } 815 816 817 #define IspVirt2Off(a, x) \ 818 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 819 _BLK_REG_SHFT] + ((x) & 0xff)) 820 821 #define BXR2(pcs, off) \ 822 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 823 #define BXW2(pcs, off, v) \ 824 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 825 826 827 static INLINE int 828 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 829 { 830 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 831 u_int16_t val0, val1; 832 int i = 0; 833 834 do { 835 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 836 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 837 } while (val0 != val1 && ++i < 1000); 838 if (val0 != val1) { 839 return (1); 840 } 841 *rp = val0; 842 return (0); 843 } 844 845 static int 846 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 847 u_int16_t *semap, u_int16_t *mbp) 848 { 849 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 850 u_int16_t isr, sema; 851 852 if (IS_2100(isp)) { 853 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 854 return (0); 855 } 856 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 857 return (0); 858 } 859 } else { 860 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 861 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 862 } 863 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 864 isr &= INT_PENDING_MASK(isp); 865 sema &= BIU_SEMA_LOCK; 866 if (isr == 0 && sema == 0) { 867 return (0); 868 } 869 *isrp = isr; 870 if ((*semap = sema) != 0) { 871 if (IS_2100(isp)) { 872 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 873 return (0); 874 } 875 } else { 876 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 877 } 878 } 879 return (1); 880 } 881 882 static int 883 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 884 u_int16_t *semap, u_int16_t *mbox0p) 885 { 886 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 887 u_int32_t r2hisr; 888 889 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 890 *isrp = 0; 891 return (0); 892 } 893 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 894 IspVirt2Off(pcs, BIU_R2HSTSLO)); 895 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 896 if ((r2hisr & BIU_R2HST_INTR) == 0) { 897 *isrp = 0; 898 return (0); 899 } 900 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 901 case ISPR2HST_ROM_MBX_OK: 902 case ISPR2HST_ROM_MBX_FAIL: 903 case ISPR2HST_MBX_OK: 904 case ISPR2HST_MBX_FAIL: 905 case ISPR2HST_ASYNC_EVENT: 906 *isrp = r2hisr & 0xffff; 907 *mbox0p = (r2hisr >> 16); 908 *semap = 1; 909 return (1); 910 case ISPR2HST_RIO_16: 911 *isrp = r2hisr & 0xffff; 912 *mbox0p = ASYNC_RIO1; 913 *semap = 1; 914 return (1); 915 case ISPR2HST_FPOST: 916 *isrp = r2hisr & 0xffff; 917 *mbox0p = ASYNC_CMD_CMPLT; 918 *semap = 1; 919 return (1); 920 case ISPR2HST_FPOST_CTIO: 921 *isrp = r2hisr & 0xffff; 922 *mbox0p = ASYNC_CTIO_DONE; 923 *semap = 1; 924 return (1); 925 case ISPR2HST_RSPQ_UPDATE: 926 *isrp = r2hisr & 0xffff; 927 *mbox0p = 0; 928 *semap = 0; 929 return (1); 930 default: 931 return (0); 932 } 933 } 934 935 static u_int16_t 936 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 937 { 938 u_int16_t rv; 939 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 940 int oldconf = 0; 941 942 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 943 /* 944 * We will assume that someone has paused the RISC processor. 945 */ 946 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 947 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 948 oldconf | BIU_PCI_CONF1_SXP); 949 } 950 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 951 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 952 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 953 } 954 return (rv); 955 } 956 957 static void 958 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 959 { 960 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 961 int oldconf = 0; 962 963 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 964 /* 965 * We will assume that someone has paused the RISC processor. 966 */ 967 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 968 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 969 oldconf | BIU_PCI_CONF1_SXP); 970 } 971 BXW2(pcs, IspVirt2Off(isp, regoff), val); 972 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 973 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 974 } 975 } 976 977 static u_int16_t 978 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 979 { 980 u_int16_t rv, oc = 0; 981 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 982 983 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 984 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 985 u_int16_t tc; 986 /* 987 * We will assume that someone has paused the RISC processor. 988 */ 989 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 990 tc = oc & ~BIU_PCI1080_CONF1_DMA; 991 if (regoff & SXP_BANK1_SELECT) 992 tc |= BIU_PCI1080_CONF1_SXP1; 993 else 994 tc |= BIU_PCI1080_CONF1_SXP0; 995 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 996 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 997 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 998 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 999 oc | BIU_PCI1080_CONF1_DMA); 1000 } 1001 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1002 if (oc) { 1003 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1004 } 1005 return (rv); 1006 } 1007 1008 static void 1009 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 1010 { 1011 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1012 int oc = 0; 1013 1014 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1015 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1016 u_int16_t tc; 1017 /* 1018 * We will assume that someone has paused the RISC processor. 1019 */ 1020 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1021 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1022 if (regoff & SXP_BANK1_SELECT) 1023 tc |= BIU_PCI1080_CONF1_SXP1; 1024 else 1025 tc |= BIU_PCI1080_CONF1_SXP0; 1026 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1027 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1028 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1029 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1030 oc | BIU_PCI1080_CONF1_DMA); 1031 } 1032 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1033 if (oc) { 1034 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1035 } 1036 } 1037 1038 1039 struct imush { 1040 struct ispsoftc *isp; 1041 int error; 1042 }; 1043 1044 static void imc(void *, bus_dma_segment_t *, int, int); 1045 1046 static void 1047 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1048 { 1049 struct imush *imushp = (struct imush *) arg; 1050 if (error) { 1051 imushp->error = error; 1052 } else { 1053 struct ispsoftc *isp =imushp->isp; 1054 bus_addr_t addr = segs->ds_addr; 1055 1056 isp->isp_rquest_dma = addr; 1057 addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1058 isp->isp_result_dma = addr; 1059 if (IS_FC(isp)) { 1060 addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1061 FCPARAM(isp)->isp_scdma = addr; 1062 } 1063 } 1064 } 1065 1066 /* 1067 * Should be BUS_SPACE_MAXSIZE, but MAXPHYS is larger than BUS_SPACE_MAXSIZE 1068 */ 1069 #define ISP_NSEGS ((MAXPHYS / PAGE_SIZE) + 1) 1070 1071 static int 1072 isp_pci_mbxdma(struct ispsoftc *isp) 1073 { 1074 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1075 caddr_t base; 1076 u_int32_t len; 1077 int i, error, ns; 1078 bus_size_t alim, slim; 1079 struct imush im; 1080 1081 /* 1082 * Already been here? If so, leave... 1083 */ 1084 if (isp->isp_rquest) { 1085 return (0); 1086 } 1087 1088 #ifdef ISP_DAC_SUPPORTED 1089 alim = BUS_SPACE_UNRESTRICTED; 1090 #else 1091 alim = BUS_SPACE_MAXADDR_32BIT; 1092 #endif 1093 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1094 slim = BUS_SPACE_MAXADDR_32BIT; 1095 } else { 1096 slim = BUS_SPACE_MAXADDR_24BIT; 1097 } 1098 1099 ISP_UNLOCK(isp); 1100 if (bus_dma_tag_create(NULL, 1, slim+1, alim, alim, 1101 NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, 1102 busdma_lock_mutex, &Giant, &pcs->dmat)) { 1103 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1104 ISP_LOCK(isp); 1105 return(1); 1106 } 1107 1108 1109 len = sizeof (XS_T **) * isp->isp_maxcmds; 1110 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1111 if (isp->isp_xflist == NULL) { 1112 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1113 ISP_LOCK(isp); 1114 return (1); 1115 } 1116 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 1117 pcs->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1118 if (pcs->dmaps == NULL) { 1119 isp_prt(isp, ISP_LOGERR, "can't alloc dma map storage"); 1120 free(isp->isp_xflist, M_DEVBUF); 1121 ISP_LOCK(isp); 1122 return (1); 1123 } 1124 1125 /* 1126 * Allocate and map the request, result queues, plus FC scratch area. 1127 */ 1128 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1129 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1130 if (IS_FC(isp)) { 1131 len += ISP2100_SCRLEN; 1132 } 1133 1134 ns = (len / PAGE_SIZE) + 1; 1135 if (bus_dma_tag_create(pcs->dmat, QENTRY_LEN, slim+1, alim, alim, 1136 NULL, NULL, len, ns, slim, 0, busdma_lock_mutex, &Giant, 1137 &isp->isp_cdmat)) { 1138 isp_prt(isp, ISP_LOGERR, 1139 "cannot create a dma tag for control spaces"); 1140 free(pcs->dmaps, M_DEVBUF); 1141 free(isp->isp_xflist, M_DEVBUF); 1142 ISP_LOCK(isp); 1143 return (1); 1144 } 1145 1146 if (bus_dmamem_alloc(isp->isp_cdmat, (void **)&base, BUS_DMA_NOWAIT, 1147 &isp->isp_cdmap) != 0) { 1148 isp_prt(isp, ISP_LOGERR, 1149 "cannot allocate %d bytes of CCB memory", len); 1150 bus_dma_tag_destroy(isp->isp_cdmat); 1151 free(isp->isp_xflist, M_DEVBUF); 1152 free(pcs->dmaps, M_DEVBUF); 1153 ISP_LOCK(isp); 1154 return (1); 1155 } 1156 1157 for (i = 0; i < isp->isp_maxcmds; i++) { 1158 error = bus_dmamap_create(pcs->dmat, 0, &pcs->dmaps[i]); 1159 if (error) { 1160 isp_prt(isp, ISP_LOGERR, 1161 "error %d creating per-cmd DMA maps", error); 1162 while (--i >= 0) { 1163 bus_dmamap_destroy(pcs->dmat, pcs->dmaps[i]); 1164 } 1165 goto bad; 1166 } 1167 } 1168 1169 im.isp = isp; 1170 im.error = 0; 1171 bus_dmamap_load(isp->isp_cdmat, isp->isp_cdmap, base, len, imc, &im, 0); 1172 if (im.error) { 1173 isp_prt(isp, ISP_LOGERR, 1174 "error %d loading dma map for control areas", im.error); 1175 goto bad; 1176 } 1177 1178 isp->isp_rquest = base; 1179 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1180 isp->isp_result = base; 1181 if (IS_FC(isp)) { 1182 base += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1183 FCPARAM(isp)->isp_scratch = base; 1184 } 1185 ISP_LOCK(isp); 1186 return (0); 1187 1188 bad: 1189 bus_dmamem_free(isp->isp_cdmat, base, isp->isp_cdmap); 1190 bus_dma_tag_destroy(isp->isp_cdmat); 1191 free(isp->isp_xflist, M_DEVBUF); 1192 free(pcs->dmaps, M_DEVBUF); 1193 ISP_LOCK(isp); 1194 isp->isp_rquest = NULL; 1195 return (1); 1196 } 1197 1198 typedef struct { 1199 struct ispsoftc *isp; 1200 void *cmd_token; 1201 void *rq; 1202 u_int16_t *nxtip; 1203 u_int16_t optr; 1204 u_int error; 1205 } mush_t; 1206 1207 #define MUSHERR_NOQENTRIES -2 1208 1209 #ifdef ISP_TARGET_MODE 1210 /* 1211 * We need to handle DMA for target mode differently from initiator mode. 1212 * 1213 * DMA mapping and construction and submission of CTIO Request Entries 1214 * and rendevous for completion are very tightly coupled because we start 1215 * out by knowing (per platform) how much data we have to move, but we 1216 * don't know, up front, how many DMA mapping segments will have to be used 1217 * cover that data, so we don't know how many CTIO Request Entries we 1218 * will end up using. Further, for performance reasons we may want to 1219 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1220 * 1221 * The standard vector still goes through isp_pci_dmasetup, but the callback 1222 * for the DMA mapping routines comes here instead with the whole transfer 1223 * mapped and a pointer to a partially filled in already allocated request 1224 * queue entry. We finish the job. 1225 */ 1226 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1227 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1228 1229 #define STATUS_WITH_DATA 1 1230 1231 static void 1232 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1233 { 1234 mush_t *mp; 1235 struct ccb_scsiio *csio; 1236 struct ispsoftc *isp; 1237 struct isp_pcisoftc *pcs; 1238 bus_dmamap_t *dp; 1239 ct_entry_t *cto, *qe; 1240 u_int8_t scsi_status; 1241 u_int16_t curi, nxti, handle; 1242 u_int32_t sflags; 1243 int32_t resid; 1244 int nth_ctio, nctios, send_status; 1245 1246 mp = (mush_t *) arg; 1247 if (error) { 1248 mp->error = error; 1249 return; 1250 } 1251 1252 isp = mp->isp; 1253 csio = mp->cmd_token; 1254 cto = mp->rq; 1255 curi = isp->isp_reqidx; 1256 qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1257 1258 cto->ct_xfrlen = 0; 1259 cto->ct_seg_count = 0; 1260 cto->ct_header.rqs_entry_count = 1; 1261 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1262 1263 if (nseg == 0) { 1264 cto->ct_header.rqs_seqno = 1; 1265 isp_prt(isp, ISP_LOGTDEBUG1, 1266 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1267 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1268 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1269 cto->ct_scsi_status, cto->ct_resid); 1270 ISP_TDQE(isp, "tdma_mk[no data]", curi, cto); 1271 isp_put_ctio(isp, cto, qe); 1272 return; 1273 } 1274 1275 nctios = nseg / ISP_RQDSEG; 1276 if (nseg % ISP_RQDSEG) { 1277 nctios++; 1278 } 1279 1280 /* 1281 * Save syshandle, and potentially any SCSI status, which we'll 1282 * reinsert on the last CTIO we're going to send. 1283 */ 1284 1285 handle = cto->ct_syshandle; 1286 cto->ct_syshandle = 0; 1287 cto->ct_header.rqs_seqno = 0; 1288 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1289 1290 if (send_status) { 1291 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1292 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1293 /* 1294 * Preserve residual. 1295 */ 1296 resid = cto->ct_resid; 1297 1298 /* 1299 * Save actual SCSI status. 1300 */ 1301 scsi_status = cto->ct_scsi_status; 1302 1303 #ifndef STATUS_WITH_DATA 1304 sflags |= CT_NO_DATA; 1305 /* 1306 * We can't do a status at the same time as a data CTIO, so 1307 * we need to synthesize an extra CTIO at this level. 1308 */ 1309 nctios++; 1310 #endif 1311 } else { 1312 sflags = scsi_status = resid = 0; 1313 } 1314 1315 cto->ct_resid = 0; 1316 cto->ct_scsi_status = 0; 1317 1318 pcs = (struct isp_pcisoftc *)isp; 1319 dp = &pcs->dmaps[isp_handle_index(handle)]; 1320 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1321 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1322 } else { 1323 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1324 } 1325 1326 nxti = *mp->nxtip; 1327 1328 for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { 1329 int seglim; 1330 1331 seglim = nseg; 1332 if (seglim) { 1333 int seg; 1334 1335 if (seglim > ISP_RQDSEG) 1336 seglim = ISP_RQDSEG; 1337 1338 for (seg = 0; seg < seglim; seg++, nseg--) { 1339 /* 1340 * Unlike normal initiator commands, we don't 1341 * do any swizzling here. 1342 */ 1343 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1344 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1345 cto->ct_xfrlen += dm_segs->ds_len; 1346 dm_segs++; 1347 } 1348 cto->ct_seg_count = seg; 1349 } else { 1350 /* 1351 * This case should only happen when we're sending an 1352 * extra CTIO with final status. 1353 */ 1354 if (send_status == 0) { 1355 isp_prt(isp, ISP_LOGWARN, 1356 "tdma_mk ran out of segments"); 1357 mp->error = EINVAL; 1358 return; 1359 } 1360 } 1361 1362 /* 1363 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1364 * ct_tagtype, and ct_timeout have been carried over 1365 * unchanged from what our caller had set. 1366 * 1367 * The dataseg fields and the seg_count fields we just got 1368 * through setting. The data direction we've preserved all 1369 * along and only clear it if we're now sending status. 1370 */ 1371 1372 if (nth_ctio == nctios - 1) { 1373 /* 1374 * We're the last in a sequence of CTIOs, so mark 1375 * this CTIO and save the handle to the CCB such that 1376 * when this CTIO completes we can free dma resources 1377 * and do whatever else we need to do to finish the 1378 * rest of the command. We *don't* give this to the 1379 * firmware to work on- the caller will do that. 1380 */ 1381 1382 cto->ct_syshandle = handle; 1383 cto->ct_header.rqs_seqno = 1; 1384 1385 if (send_status) { 1386 cto->ct_scsi_status = scsi_status; 1387 cto->ct_flags |= sflags; 1388 cto->ct_resid = resid; 1389 } 1390 if (send_status) { 1391 isp_prt(isp, ISP_LOGTDEBUG1, 1392 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 1393 "scsi status %x resid %d", 1394 cto->ct_fwhandle, csio->ccb_h.target_lun, 1395 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 1396 cto->ct_scsi_status, cto->ct_resid); 1397 } else { 1398 isp_prt(isp, ISP_LOGTDEBUG1, 1399 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 1400 cto->ct_fwhandle, csio->ccb_h.target_lun, 1401 cto->ct_iid, cto->ct_tag_val, 1402 cto->ct_flags); 1403 } 1404 isp_put_ctio(isp, cto, qe); 1405 ISP_TDQE(isp, "last tdma_mk", curi, cto); 1406 if (nctios > 1) { 1407 MEMORYBARRIER(isp, SYNC_REQUEST, 1408 curi, QENTRY_LEN); 1409 } 1410 } else { 1411 ct_entry_t *oqe = qe; 1412 1413 /* 1414 * Make sure syshandle fields are clean 1415 */ 1416 cto->ct_syshandle = 0; 1417 cto->ct_header.rqs_seqno = 0; 1418 1419 isp_prt(isp, ISP_LOGTDEBUG1, 1420 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 1421 cto->ct_fwhandle, csio->ccb_h.target_lun, 1422 cto->ct_iid, cto->ct_flags); 1423 1424 /* 1425 * Get a new CTIO 1426 */ 1427 qe = (ct_entry_t *) 1428 ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1429 nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); 1430 if (nxti == mp->optr) { 1431 isp_prt(isp, ISP_LOGTDEBUG0, 1432 "Queue Overflow in tdma_mk"); 1433 mp->error = MUSHERR_NOQENTRIES; 1434 return; 1435 } 1436 1437 /* 1438 * Now that we're done with the old CTIO, 1439 * flush it out to the request queue. 1440 */ 1441 ISP_TDQE(isp, "dma_tgt_fc", curi, cto); 1442 isp_put_ctio(isp, cto, oqe); 1443 if (nth_ctio != 0) { 1444 MEMORYBARRIER(isp, SYNC_REQUEST, curi, 1445 QENTRY_LEN); 1446 } 1447 curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); 1448 1449 /* 1450 * Reset some fields in the CTIO so we can reuse 1451 * for the next one we'll flush to the request 1452 * queue. 1453 */ 1454 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1455 cto->ct_header.rqs_entry_count = 1; 1456 cto->ct_header.rqs_flags = 0; 1457 cto->ct_status = 0; 1458 cto->ct_scsi_status = 0; 1459 cto->ct_xfrlen = 0; 1460 cto->ct_resid = 0; 1461 cto->ct_seg_count = 0; 1462 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1463 } 1464 } 1465 *mp->nxtip = nxti; 1466 } 1467 1468 /* 1469 * We don't have to do multiple CTIOs here. Instead, we can just do 1470 * continuation segments as needed. This greatly simplifies the code 1471 * improves performance. 1472 */ 1473 1474 static void 1475 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1476 { 1477 mush_t *mp; 1478 struct ccb_scsiio *csio; 1479 struct ispsoftc *isp; 1480 ct2_entry_t *cto, *qe; 1481 u_int16_t curi, nxti; 1482 int segcnt; 1483 1484 mp = (mush_t *) arg; 1485 if (error) { 1486 mp->error = error; 1487 return; 1488 } 1489 1490 isp = mp->isp; 1491 csio = mp->cmd_token; 1492 cto = mp->rq; 1493 1494 curi = isp->isp_reqidx; 1495 qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1496 1497 if (nseg == 0) { 1498 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1499 isp_prt(isp, ISP_LOGWARN, 1500 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1501 "set (0x%x)", cto->ct_flags); 1502 mp->error = EINVAL; 1503 return; 1504 } 1505 /* 1506 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1507 * flags to NO DATA and clear relative offset flags. 1508 * We preserve the ct_resid and the response area. 1509 */ 1510 cto->ct_header.rqs_seqno = 1; 1511 cto->ct_seg_count = 0; 1512 cto->ct_reloff = 0; 1513 isp_prt(isp, ISP_LOGTDEBUG1, 1514 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1515 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1516 cto->ct_iid, cto->ct_flags, cto->ct_status, 1517 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1518 isp_put_ctio2(isp, cto, qe); 1519 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe); 1520 return; 1521 } 1522 1523 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1524 isp_prt(isp, ISP_LOGERR, 1525 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1526 "(0x%x)", cto->ct_flags); 1527 mp->error = EINVAL; 1528 return; 1529 } 1530 1531 1532 nxti = *mp->nxtip; 1533 1534 /* 1535 * Set up the CTIO2 data segments. 1536 */ 1537 for (segcnt = 0; cto->ct_seg_count < ISP_RQDSEG_T2 && segcnt < nseg; 1538 cto->ct_seg_count++, segcnt++) { 1539 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_base = 1540 dm_segs[segcnt].ds_addr; 1541 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_count = 1542 dm_segs[segcnt].ds_len; 1543 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1544 isp_prt(isp, ISP_LOGTDEBUG1, 1545 "isp_send_ctio2: ent0[%d]0x%llx:%lld", 1546 cto->ct_seg_count, (long long)dm_segs[segcnt].ds_addr, 1547 (long long)dm_segs[segcnt].ds_len); 1548 } 1549 1550 while (segcnt < nseg) { 1551 u_int16_t curip; 1552 int seg; 1553 ispcontreq_t local, *crq = &local, *qep; 1554 1555 qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1556 curip = nxti; 1557 nxti = ISP_NXT_QENTRY(curip, RQUEST_QUEUE_LEN(isp)); 1558 if (nxti == mp->optr) { 1559 ISP_UNLOCK(isp); 1560 isp_prt(isp, ISP_LOGTDEBUG0, 1561 "tdma_mkfc: request queue overflow"); 1562 mp->error = MUSHERR_NOQENTRIES; 1563 return; 1564 } 1565 cto->ct_header.rqs_entry_count++; 1566 MEMZERO((void *)crq, sizeof (*crq)); 1567 crq->req_header.rqs_entry_count = 1; 1568 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1569 for (seg = 0; segcnt < nseg && seg < ISP_CDSEG; 1570 segcnt++, seg++) { 1571 crq->req_dataseg[seg].ds_base = dm_segs[segcnt].ds_addr; 1572 crq->req_dataseg[seg].ds_count = dm_segs[segcnt].ds_len; 1573 isp_prt(isp, ISP_LOGTDEBUG1, 1574 "isp_send_ctio2: ent%d[%d]0x%llx:%lld", 1575 cto->ct_header.rqs_entry_count-1, seg, 1576 (long long) dm_segs[segcnt].ds_addr, 1577 (long long) dm_segs[segcnt].ds_len); 1578 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1579 cto->ct_seg_count++; 1580 } 1581 MEMORYBARRIER(isp, SYNC_REQUEST, curip, QENTRY_LEN); 1582 isp_put_cont_req(isp, crq, qep); 1583 ISP_TDQE(isp, "cont entry", curi, qep); 1584 } 1585 1586 /* 1587 * No do final twiddling for the CTIO itself. 1588 */ 1589 cto->ct_header.rqs_seqno = 1; 1590 isp_prt(isp, ISP_LOGTDEBUG1, 1591 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x resid %d", 1592 cto->ct_rxid, csio->ccb_h.target_lun, (int) cto->ct_iid, 1593 cto->ct_flags, cto->ct_status, cto->rsp.m1.ct_scsi_status, 1594 cto->ct_resid); 1595 isp_put_ctio2(isp, cto, qe); 1596 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe); 1597 *mp->nxtip = nxti; 1598 } 1599 #endif 1600 1601 static void dma2(void *, bus_dma_segment_t *, int, int); 1602 1603 static void 1604 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1605 { 1606 mush_t *mp; 1607 struct ispsoftc *isp; 1608 struct ccb_scsiio *csio; 1609 struct isp_pcisoftc *pcs; 1610 bus_dmamap_t *dp; 1611 bus_dma_segment_t *eseg; 1612 ispreq_t *rq; 1613 int seglim, datalen; 1614 u_int16_t nxti; 1615 1616 mp = (mush_t *) arg; 1617 if (error) { 1618 mp->error = error; 1619 return; 1620 } 1621 1622 if (nseg < 1) { 1623 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1624 mp->error = EFAULT; 1625 return; 1626 } 1627 csio = mp->cmd_token; 1628 isp = mp->isp; 1629 rq = mp->rq; 1630 pcs = (struct isp_pcisoftc *)mp->isp; 1631 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1632 nxti = *mp->nxtip; 1633 1634 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1635 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1636 } else { 1637 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1638 } 1639 1640 datalen = XS_XFRLEN(csio); 1641 1642 /* 1643 * We're passed an initial partially filled in entry that 1644 * has most fields filled in except for data transfer 1645 * related values. 1646 * 1647 * Our job is to fill in the initial request queue entry and 1648 * then to start allocating and filling in continuation entries 1649 * until we've covered the entire transfer. 1650 */ 1651 1652 if (IS_FC(isp)) { 1653 seglim = ISP_RQDSEG_T2; 1654 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1655 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1656 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1657 } else { 1658 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1659 } 1660 } else { 1661 if (csio->cdb_len > 12) { 1662 seglim = 0; 1663 } else { 1664 seglim = ISP_RQDSEG; 1665 } 1666 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1667 rq->req_flags |= REQFLAG_DATA_IN; 1668 } else { 1669 rq->req_flags |= REQFLAG_DATA_OUT; 1670 } 1671 } 1672 1673 eseg = dm_segs + nseg; 1674 1675 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1676 if (IS_FC(isp)) { 1677 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1678 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1679 dm_segs->ds_addr; 1680 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1681 dm_segs->ds_len; 1682 } else { 1683 rq->req_dataseg[rq->req_seg_count].ds_base = 1684 dm_segs->ds_addr; 1685 rq->req_dataseg[rq->req_seg_count].ds_count = 1686 dm_segs->ds_len; 1687 } 1688 datalen -= dm_segs->ds_len; 1689 rq->req_seg_count++; 1690 dm_segs++; 1691 } 1692 1693 while (datalen > 0 && dm_segs != eseg) { 1694 u_int16_t onxti; 1695 ispcontreq_t local, *crq = &local, *cqe; 1696 1697 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1698 onxti = nxti; 1699 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1700 if (nxti == mp->optr) { 1701 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1702 mp->error = MUSHERR_NOQENTRIES; 1703 return; 1704 } 1705 rq->req_header.rqs_entry_count++; 1706 MEMZERO((void *)crq, sizeof (*crq)); 1707 crq->req_header.rqs_entry_count = 1; 1708 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1709 1710 seglim = 0; 1711 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1712 crq->req_dataseg[seglim].ds_base = 1713 dm_segs->ds_addr; 1714 crq->req_dataseg[seglim].ds_count = 1715 dm_segs->ds_len; 1716 rq->req_seg_count++; 1717 dm_segs++; 1718 seglim++; 1719 datalen -= dm_segs->ds_len; 1720 } 1721 isp_put_cont_req(isp, crq, cqe); 1722 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1723 } 1724 *mp->nxtip = nxti; 1725 } 1726 1727 static int 1728 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1729 u_int16_t *nxtip, u_int16_t optr) 1730 { 1731 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1732 ispreq_t *qep; 1733 bus_dmamap_t *dp = NULL; 1734 mush_t mush, *mp; 1735 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1736 1737 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); 1738 #ifdef ISP_TARGET_MODE 1739 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1740 if (IS_FC(isp)) { 1741 eptr = tdma_mkfc; 1742 } else { 1743 eptr = tdma_mk; 1744 } 1745 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1746 (csio->dxfer_len == 0)) { 1747 mp = &mush; 1748 mp->isp = isp; 1749 mp->cmd_token = csio; 1750 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 1751 mp->nxtip = nxtip; 1752 mp->optr = optr; 1753 mp->error = 0; 1754 (*eptr)(mp, NULL, 0, 0); 1755 goto mbxsync; 1756 } 1757 } else 1758 #endif 1759 eptr = dma2; 1760 1761 1762 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1763 (csio->dxfer_len == 0)) { 1764 rq->req_seg_count = 1; 1765 goto mbxsync; 1766 } 1767 1768 /* 1769 * Do a virtual grapevine step to collect info for 1770 * the callback dma allocation that we have to use... 1771 */ 1772 mp = &mush; 1773 mp->isp = isp; 1774 mp->cmd_token = csio; 1775 mp->rq = rq; 1776 mp->nxtip = nxtip; 1777 mp->optr = optr; 1778 mp->error = 0; 1779 1780 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1781 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1782 int error, s; 1783 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1784 s = splsoftvm(); 1785 error = bus_dmamap_load(pcs->dmat, *dp, 1786 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1787 if (error == EINPROGRESS) { 1788 bus_dmamap_unload(pcs->dmat, *dp); 1789 mp->error = EINVAL; 1790 isp_prt(isp, ISP_LOGERR, 1791 "deferred dma allocation not supported"); 1792 } else if (error && mp->error == 0) { 1793 #ifdef DIAGNOSTIC 1794 isp_prt(isp, ISP_LOGERR, 1795 "error %d in dma mapping code", error); 1796 #endif 1797 mp->error = error; 1798 } 1799 splx(s); 1800 } else { 1801 /* Pointer to physical buffer */ 1802 struct bus_dma_segment seg; 1803 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1804 seg.ds_len = csio->dxfer_len; 1805 (*eptr)(mp, &seg, 1, 0); 1806 } 1807 } else { 1808 struct bus_dma_segment *segs; 1809 1810 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1811 isp_prt(isp, ISP_LOGERR, 1812 "Physical segment pointers unsupported"); 1813 mp->error = EINVAL; 1814 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1815 isp_prt(isp, ISP_LOGERR, 1816 "Virtual segment addresses unsupported"); 1817 mp->error = EINVAL; 1818 } else { 1819 /* Just use the segments provided */ 1820 segs = (struct bus_dma_segment *) csio->data_ptr; 1821 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1822 } 1823 } 1824 if (mp->error) { 1825 int retval = CMD_COMPLETE; 1826 if (mp->error == MUSHERR_NOQENTRIES) { 1827 retval = CMD_EAGAIN; 1828 } else if (mp->error == EFBIG) { 1829 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1830 } else if (mp->error == EINVAL) { 1831 XS_SETERR(csio, CAM_REQ_INVALID); 1832 } else { 1833 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1834 } 1835 return (retval); 1836 } 1837 mbxsync: 1838 switch (rq->req_header.rqs_entry_type) { 1839 case RQSTYPE_REQUEST: 1840 isp_put_request(isp, rq, qep); 1841 break; 1842 case RQSTYPE_CMDONLY: 1843 isp_put_extended_request(isp, (ispextreq_t *)rq, 1844 (ispextreq_t *)qep); 1845 break; 1846 case RQSTYPE_T2RQS: 1847 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1848 break; 1849 } 1850 return (CMD_QUEUED); 1851 } 1852 1853 static void 1854 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1855 { 1856 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1857 bus_dmamap_t *dp = &pcs->dmaps[isp_handle_index(handle)]; 1858 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1859 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTREAD); 1860 } else { 1861 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTWRITE); 1862 } 1863 bus_dmamap_unload(pcs->dmat, *dp); 1864 } 1865 1866 1867 static void 1868 isp_pci_reset1(struct ispsoftc *isp) 1869 { 1870 /* Make sure the BIOS is disabled */ 1871 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1872 /* and enable interrupts */ 1873 ENABLE_INTS(isp); 1874 } 1875 1876 static void 1877 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1878 { 1879 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1880 if (msg) 1881 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1882 else 1883 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1884 if (IS_SCSI(isp)) 1885 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1886 else 1887 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1888 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1889 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1890 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1891 1892 1893 if (IS_SCSI(isp)) { 1894 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1895 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1896 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1897 ISP_READ(isp, CDMA_FIFO_STS)); 1898 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1899 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1900 ISP_READ(isp, DDMA_FIFO_STS)); 1901 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1902 ISP_READ(isp, SXP_INTERRUPT), 1903 ISP_READ(isp, SXP_GROSS_ERR), 1904 ISP_READ(isp, SXP_PINS_CTRL)); 1905 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1906 } 1907 printf(" mbox regs: %x %x %x %x %x\n", 1908 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1909 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1910 ISP_READ(isp, OUTMAILBOX4)); 1911 printf(" PCI Status Command/Status=%x\n", 1912 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1913 } 1914