1 /* $FreeBSD$ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * FreeBSD Version. 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000, 2001 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 36 #include <pci/pcireg.h> 37 #include <pci/pcivar.h> 38 39 #include <machine/bus_memio.h> 40 #include <machine/bus_pio.h> 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 46 #include <dev/isp/isp_freebsd.h> 47 48 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 49 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 50 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 51 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 52 static int 53 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 54 static int 55 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 56 static int isp_pci_mbxdma(struct ispsoftc *); 57 static int 58 isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, u_int16_t *, u_int16_t); 59 static void 60 isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 61 62 static void isp_pci_reset1(struct ispsoftc *); 63 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 64 65 static struct ispmdvec mdvec = { 66 isp_pci_rd_isr, 67 isp_pci_rd_reg, 68 isp_pci_wr_reg, 69 isp_pci_mbxdma, 70 isp_pci_dmasetup, 71 isp_pci_dmateardown, 72 NULL, 73 isp_pci_reset1, 74 isp_pci_dumpregs, 75 NULL, 76 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 77 }; 78 79 static struct ispmdvec mdvec_1080 = { 80 isp_pci_rd_isr, 81 isp_pci_rd_reg_1080, 82 isp_pci_wr_reg_1080, 83 isp_pci_mbxdma, 84 isp_pci_dmasetup, 85 isp_pci_dmateardown, 86 NULL, 87 isp_pci_reset1, 88 isp_pci_dumpregs, 89 NULL, 90 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 91 }; 92 93 static struct ispmdvec mdvec_12160 = { 94 isp_pci_rd_isr, 95 isp_pci_rd_reg_1080, 96 isp_pci_wr_reg_1080, 97 isp_pci_mbxdma, 98 isp_pci_dmasetup, 99 isp_pci_dmateardown, 100 NULL, 101 isp_pci_reset1, 102 isp_pci_dumpregs, 103 NULL, 104 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 105 }; 106 107 static struct ispmdvec mdvec_2100 = { 108 isp_pci_rd_isr, 109 isp_pci_rd_reg, 110 isp_pci_wr_reg, 111 isp_pci_mbxdma, 112 isp_pci_dmasetup, 113 isp_pci_dmateardown, 114 NULL, 115 isp_pci_reset1, 116 isp_pci_dumpregs 117 }; 118 119 static struct ispmdvec mdvec_2200 = { 120 isp_pci_rd_isr, 121 isp_pci_rd_reg, 122 isp_pci_wr_reg, 123 isp_pci_mbxdma, 124 isp_pci_dmasetup, 125 isp_pci_dmateardown, 126 NULL, 127 isp_pci_reset1, 128 isp_pci_dumpregs 129 }; 130 131 static struct ispmdvec mdvec_2300 = { 132 isp_pci_rd_isr_2300, 133 isp_pci_rd_reg, 134 isp_pci_wr_reg, 135 isp_pci_mbxdma, 136 isp_pci_dmasetup, 137 isp_pci_dmateardown, 138 NULL, 139 isp_pci_reset1, 140 isp_pci_dumpregs 141 }; 142 143 #ifndef PCIM_CMD_INVEN 144 #define PCIM_CMD_INVEN 0x10 145 #endif 146 #ifndef PCIM_CMD_BUSMASTEREN 147 #define PCIM_CMD_BUSMASTEREN 0x0004 148 #endif 149 #ifndef PCIM_CMD_PERRESPEN 150 #define PCIM_CMD_PERRESPEN 0x0040 151 #endif 152 #ifndef PCIM_CMD_SEREN 153 #define PCIM_CMD_SEREN 0x0100 154 #endif 155 156 #ifndef PCIR_COMMAND 157 #define PCIR_COMMAND 0x04 158 #endif 159 160 #ifndef PCIR_CACHELNSZ 161 #define PCIR_CACHELNSZ 0x0c 162 #endif 163 164 #ifndef PCIR_LATTIMER 165 #define PCIR_LATTIMER 0x0d 166 #endif 167 168 #ifndef PCIR_ROMADDR 169 #define PCIR_ROMADDR 0x30 170 #endif 171 172 #ifndef PCI_VENDOR_QLOGIC 173 #define PCI_VENDOR_QLOGIC 0x1077 174 #endif 175 176 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 177 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 178 #endif 179 180 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 181 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 182 #endif 183 184 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 185 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 186 #endif 187 188 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 189 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 190 #endif 191 192 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 193 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 194 #endif 195 196 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 197 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 198 #endif 199 200 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 201 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 202 #endif 203 204 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 205 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 206 #endif 207 208 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 209 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 210 #endif 211 212 #define PCI_QLOGIC_ISP1020 \ 213 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 214 215 #define PCI_QLOGIC_ISP1080 \ 216 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 217 218 #define PCI_QLOGIC_ISP12160 \ 219 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 220 221 #define PCI_QLOGIC_ISP1240 \ 222 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 223 224 #define PCI_QLOGIC_ISP1280 \ 225 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 226 227 #define PCI_QLOGIC_ISP2100 \ 228 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 229 230 #define PCI_QLOGIC_ISP2200 \ 231 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 232 233 #define PCI_QLOGIC_ISP2300 \ 234 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 235 236 #define PCI_QLOGIC_ISP2312 \ 237 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 238 239 /* 240 * Odd case for some AMI raid cards... We need to *not* attach to this. 241 */ 242 #define AMI_RAID_SUBVENDOR_ID 0x101e 243 244 #define IO_MAP_REG 0x10 245 #define MEM_MAP_REG 0x14 246 247 #define PCI_DFLT_LTNCY 0x40 248 #define PCI_DFLT_LNSZ 0x10 249 250 static int isp_pci_probe (device_t); 251 static int isp_pci_attach (device_t); 252 253 254 struct isp_pcisoftc { 255 struct ispsoftc pci_isp; 256 device_t pci_dev; 257 struct resource * pci_reg; 258 bus_space_tag_t pci_st; 259 bus_space_handle_t pci_sh; 260 void * ih; 261 int16_t pci_poff[_NREG_BLKS]; 262 bus_dma_tag_t dmat; 263 bus_dmamap_t *dmaps; 264 }; 265 extern ispfwfunc *isp_get_firmware_p; 266 267 static device_method_t isp_pci_methods[] = { 268 /* Device interface */ 269 DEVMETHOD(device_probe, isp_pci_probe), 270 DEVMETHOD(device_attach, isp_pci_attach), 271 { 0, 0 } 272 }; 273 static void isp_pci_intr(void *); 274 275 static driver_t isp_pci_driver = { 276 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 277 }; 278 static devclass_t isp_devclass; 279 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 280 281 static int 282 isp_pci_probe(device_t dev) 283 { 284 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 285 case PCI_QLOGIC_ISP1020: 286 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 287 break; 288 case PCI_QLOGIC_ISP1080: 289 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 290 break; 291 case PCI_QLOGIC_ISP1240: 292 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 293 break; 294 case PCI_QLOGIC_ISP1280: 295 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 296 break; 297 case PCI_QLOGIC_ISP12160: 298 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 299 return (ENXIO); 300 } 301 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 302 break; 303 case PCI_QLOGIC_ISP2100: 304 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 305 break; 306 case PCI_QLOGIC_ISP2200: 307 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 308 break; 309 case PCI_QLOGIC_ISP2300: 310 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 311 break; 312 case PCI_QLOGIC_ISP2312: 313 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 314 break; 315 default: 316 return (ENXIO); 317 } 318 if (isp_announced == 0 && bootverbose) { 319 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 320 "Core Version %d.%d\n", 321 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 322 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 323 isp_announced++; 324 } 325 /* 326 * XXXX: Here is where we might load the f/w module 327 * XXXX: (or increase a reference count to it). 328 */ 329 return (0); 330 } 331 332 static int 333 isp_pci_attach(device_t dev) 334 { 335 struct resource *regs, *irq; 336 int tval, rtp, rgd, iqd, m1, m2, isp_debug, role; 337 u_int32_t data, cmd, linesz, psize, basetype; 338 struct isp_pcisoftc *pcs; 339 struct ispsoftc *isp = NULL; 340 struct ispmdvec *mdvp; 341 const char *sptr; 342 int locksetup = 0; 343 344 /* 345 * Figure out if we're supposed to skip this one. 346 * If we are, we actually go to ISP_ROLE_NONE. 347 */ 348 349 tval = 0; 350 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 351 "disable", &tval) == 0 && tval) { 352 device_printf(dev, "device is disabled\n"); 353 /* but return 0 so the !$)$)*!$*) unit isn't reused */ 354 return (0); 355 } 356 357 role = 0; 358 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 359 "role", &role) == 0 && 360 ((role & ~(ISP_ROLE_INITIATOR|ISP_ROLE_TARGET)) == 0)) { 361 device_printf(dev, "setting role to 0x%x\n", role); 362 } else { 363 #ifdef ISP_TARGET_MODE 364 role = ISP_ROLE_INITIATOR|ISP_ROLE_TARGET; 365 #else 366 role = ISP_DEFAULT_ROLES; 367 #endif 368 } 369 370 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT | M_ZERO); 371 if (pcs == NULL) { 372 device_printf(dev, "cannot allocate softc\n"); 373 return (ENOMEM); 374 } 375 376 /* 377 * Figure out which we should try first - memory mapping or i/o mapping? 378 */ 379 #ifdef __alpha__ 380 m1 = PCIM_CMD_MEMEN; 381 m2 = PCIM_CMD_PORTEN; 382 #else 383 m1 = PCIM_CMD_PORTEN; 384 m2 = PCIM_CMD_MEMEN; 385 #endif 386 387 tval = 0; 388 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 389 "prefer_iomap", &tval) == 0 && tval != 0) { 390 m1 = PCIM_CMD_PORTEN; 391 m2 = PCIM_CMD_MEMEN; 392 } 393 tval = 0; 394 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 395 "prefer_memmap", &tval) == 0 && tval != 0) { 396 m1 = PCIM_CMD_MEMEN; 397 m2 = PCIM_CMD_PORTEN; 398 } 399 400 linesz = PCI_DFLT_LNSZ; 401 irq = regs = NULL; 402 rgd = rtp = iqd = 0; 403 404 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 405 if (cmd & m1) { 406 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 407 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 408 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 409 } 410 if (regs == NULL && (cmd & m2)) { 411 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 412 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 413 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 414 } 415 if (regs == NULL) { 416 device_printf(dev, "unable to map any ports\n"); 417 goto bad; 418 } 419 if (bootverbose) 420 device_printf(dev, "using %s space register mapping\n", 421 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 422 pcs->pci_dev = dev; 423 pcs->pci_reg = regs; 424 pcs->pci_st = rman_get_bustag(regs); 425 pcs->pci_sh = rman_get_bushandle(regs); 426 427 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 428 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 429 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 430 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 431 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 432 mdvp = &mdvec; 433 basetype = ISP_HA_SCSI_UNKNOWN; 434 psize = sizeof (sdparam); 435 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 436 mdvp = &mdvec; 437 basetype = ISP_HA_SCSI_UNKNOWN; 438 psize = sizeof (sdparam); 439 } 440 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 441 mdvp = &mdvec_1080; 442 basetype = ISP_HA_SCSI_1080; 443 psize = sizeof (sdparam); 444 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 445 ISP1080_DMA_REGS_OFF; 446 } 447 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 448 mdvp = &mdvec_1080; 449 basetype = ISP_HA_SCSI_1240; 450 psize = 2 * sizeof (sdparam); 451 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 452 ISP1080_DMA_REGS_OFF; 453 } 454 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 455 mdvp = &mdvec_1080; 456 basetype = ISP_HA_SCSI_1280; 457 psize = 2 * sizeof (sdparam); 458 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 459 ISP1080_DMA_REGS_OFF; 460 } 461 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 462 mdvp = &mdvec_12160; 463 basetype = ISP_HA_SCSI_12160; 464 psize = 2 * sizeof (sdparam); 465 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 466 ISP1080_DMA_REGS_OFF; 467 } 468 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 469 mdvp = &mdvec_2100; 470 basetype = ISP_HA_FC_2100; 471 psize = sizeof (fcparam); 472 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 473 PCI_MBOX_REGS2100_OFF; 474 if (pci_get_revid(dev) < 3) { 475 /* 476 * XXX: Need to get the actual revision 477 * XXX: number of the 2100 FB. At any rate, 478 * XXX: lower cache line size for early revision 479 * XXX; boards. 480 */ 481 linesz = 1; 482 } 483 } 484 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 485 mdvp = &mdvec_2200; 486 basetype = ISP_HA_FC_2200; 487 psize = sizeof (fcparam); 488 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 489 PCI_MBOX_REGS2100_OFF; 490 } 491 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2300) { 492 mdvp = &mdvec_2300; 493 basetype = ISP_HA_FC_2300; 494 psize = sizeof (fcparam); 495 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 496 PCI_MBOX_REGS2300_OFF; 497 } 498 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2312) { 499 mdvp = &mdvec_2300; 500 basetype = ISP_HA_FC_2312; 501 psize = sizeof (fcparam); 502 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 503 PCI_MBOX_REGS2300_OFF; 504 } 505 isp = &pcs->pci_isp; 506 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 507 if (isp->isp_param == NULL) { 508 device_printf(dev, "cannot allocate parameter data\n"); 509 goto bad; 510 } 511 isp->isp_mdvec = mdvp; 512 isp->isp_type = basetype; 513 isp->isp_revision = pci_get_revid(dev); 514 isp->isp_role = role; 515 isp->isp_dev = dev; 516 517 /* 518 * Try and find firmware for this device. 519 */ 520 521 if (isp_get_firmware_p) { 522 int device = (int) pci_get_device(dev); 523 #ifdef ISP_TARGET_MODE 524 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 525 #else 526 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 527 #endif 528 } 529 530 /* 531 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 532 * are set. 533 */ 534 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 535 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 536 if (IS_2300(isp)) { /* per QLogic errata */ 537 cmd &= ~PCIM_CMD_INVEN; 538 } 539 if (IS_23XX(isp)) { 540 /* 541 * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command. 542 */ 543 isp->isp_touched = 1; 544 545 } 546 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 547 548 /* 549 * Make sure the Cache Line Size register is set sensibly. 550 */ 551 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 552 if (data != linesz) { 553 data = PCI_DFLT_LNSZ; 554 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 555 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 556 } 557 558 /* 559 * Make sure the Latency Timer is sane. 560 */ 561 data = pci_read_config(dev, PCIR_LATTIMER, 1); 562 if (data < PCI_DFLT_LTNCY) { 563 data = PCI_DFLT_LTNCY; 564 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 565 pci_write_config(dev, PCIR_LATTIMER, data, 1); 566 } 567 568 /* 569 * Make sure we've disabled the ROM. 570 */ 571 data = pci_read_config(dev, PCIR_ROMADDR, 4); 572 data &= ~1; 573 pci_write_config(dev, PCIR_ROMADDR, data, 4); 574 575 iqd = 0; 576 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 577 1, RF_ACTIVE | RF_SHAREABLE); 578 if (irq == NULL) { 579 device_printf(dev, "could not allocate interrupt\n"); 580 goto bad; 581 } 582 583 tval = 0; 584 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 585 "fwload_disable", &tval) == 0 && tval != 0) { 586 isp->isp_confopts |= ISP_CFG_NORELOAD; 587 } 588 tval = 0; 589 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 590 "ignore_nvram", &tval) == 0 && tval != 0) { 591 isp->isp_confopts |= ISP_CFG_NONVRAM; 592 } 593 tval = 0; 594 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 595 "fullduplex", &tval) == 0 && tval != 0) { 596 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 597 } 598 #ifdef ISP_FW_CRASH_DUMP 599 tval = 0; 600 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 601 "fw_dump_enable", &tval) == 0 && tval != 0) { 602 size_t amt = 0; 603 if (IS_2200(isp)) { 604 amt = QLA2200_RISC_IMAGE_DUMP_SIZE; 605 } else if (IS_23XX(isp)) { 606 amt = QLA2300_RISC_IMAGE_DUMP_SIZE; 607 } 608 if (amt) { 609 FCPARAM(isp)->isp_dump_data = 610 malloc(amt, M_DEVBUF, M_WAITOK | M_ZERO); 611 } else { 612 device_printf(dev, 613 "f/w crash dumps not supported for this model\n"); 614 } 615 } 616 #endif 617 618 sptr = 0; 619 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 620 "topology", (const char **) &sptr) == 0 && sptr != 0) { 621 if (strcmp(sptr, "lport") == 0) { 622 isp->isp_confopts |= ISP_CFG_LPORT; 623 } else if (strcmp(sptr, "nport") == 0) { 624 isp->isp_confopts |= ISP_CFG_NPORT; 625 } else if (strcmp(sptr, "lport-only") == 0) { 626 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 627 } else if (strcmp(sptr, "nport-only") == 0) { 628 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 629 } 630 } 631 632 /* 633 * Because the resource_*_value functions can neither return 634 * 64 bit integer values, nor can they be directly coerced 635 * to interpret the right hand side of the assignment as 636 * you want them to interpret it, we have to force WWN 637 * hint replacement to specify WWN strings with a leading 638 * 'w' (e..g w50000000aaaa0001). Sigh. 639 */ 640 sptr = 0; 641 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 642 "portwwn", (const char **) &sptr); 643 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 644 char *eptr = 0; 645 isp->isp_osinfo.default_port_wwn = strtouq(sptr, &eptr, 16); 646 if (eptr < sptr + 16 || isp->isp_osinfo.default_port_wwn == 0) { 647 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 648 isp->isp_osinfo.default_port_wwn = 0; 649 } else { 650 isp->isp_confopts |= ISP_CFG_OWNWWPN; 651 } 652 } 653 if (isp->isp_osinfo.default_port_wwn == 0) { 654 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 655 } 656 657 sptr = 0; 658 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 659 "nodewwn", (const char **) &sptr); 660 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 661 char *eptr = 0; 662 isp->isp_osinfo.default_node_wwn = strtouq(sptr, &eptr, 16); 663 if (eptr < sptr + 16 || isp->isp_osinfo.default_node_wwn == 0) { 664 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 665 isp->isp_osinfo.default_node_wwn = 0; 666 } else { 667 isp->isp_confopts |= ISP_CFG_OWNWWNN; 668 } 669 } 670 if (isp->isp_osinfo.default_node_wwn == 0) { 671 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 672 } 673 674 isp->isp_osinfo.default_id = -1; 675 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 676 "iid", &tval) == 0) { 677 isp->isp_osinfo.default_id = tval; 678 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 679 } 680 if (isp->isp_osinfo.default_id == -1) { 681 if (IS_FC(isp)) { 682 isp->isp_osinfo.default_id = 109; 683 } else { 684 isp->isp_osinfo.default_id = 7; 685 } 686 } 687 688 isp_debug = 0; 689 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 690 "debug", &isp_debug); 691 692 /* Make sure the lock is set up. */ 693 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 694 locksetup++; 695 696 if (bus_setup_intr(dev, irq, ISP_IFLAGS, isp_pci_intr, isp, &pcs->ih)) { 697 device_printf(dev, "could not setup interrupt\n"); 698 goto bad; 699 } 700 701 /* 702 * Set up logging levels. 703 */ 704 if (isp_debug) { 705 isp->isp_dblev = isp_debug; 706 } else { 707 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 708 } 709 if (bootverbose) 710 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 711 712 /* 713 * Last minute checks... 714 */ 715 if (IS_2312(isp)) { 716 isp->isp_port = pci_get_function(dev); 717 } 718 719 /* 720 * Make sure we're in reset state. 721 */ 722 ISP_LOCK(isp); 723 isp_reset(isp); 724 if (isp->isp_state != ISP_RESETSTATE) { 725 ISP_UNLOCK(isp); 726 goto bad; 727 } 728 isp_init(isp); 729 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_INITSTATE) { 730 isp_uninit(isp); 731 ISP_UNLOCK(isp); 732 goto bad; 733 } 734 isp_attach(isp); 735 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_RUNSTATE) { 736 isp_uninit(isp); 737 ISP_UNLOCK(isp); 738 goto bad; 739 } 740 /* 741 * XXXX: Here is where we might unload the f/w module 742 * XXXX: (or decrease the reference count to it). 743 */ 744 ISP_UNLOCK(isp); 745 return (0); 746 747 bad: 748 749 if (pcs && pcs->ih) { 750 (void) bus_teardown_intr(dev, irq, pcs->ih); 751 } 752 753 if (locksetup && isp) { 754 mtx_destroy(&isp->isp_osinfo.lock); 755 } 756 757 if (irq) { 758 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 759 } 760 761 762 if (regs) { 763 (void) bus_release_resource(dev, rtp, rgd, regs); 764 } 765 766 if (pcs) { 767 if (pcs->pci_isp.isp_param) 768 free(pcs->pci_isp.isp_param, M_DEVBUF); 769 free(pcs, M_DEVBUF); 770 } 771 772 /* 773 * XXXX: Here is where we might unload the f/w module 774 * XXXX: (or decrease the reference count to it). 775 */ 776 return (ENXIO); 777 } 778 779 static void 780 isp_pci_intr(void *arg) 781 { 782 struct ispsoftc *isp = arg; 783 u_int16_t isr, sema, mbox; 784 785 ISP_LOCK(isp); 786 isp->isp_intcnt++; 787 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 788 isp->isp_intbogus++; 789 } else { 790 int iok = isp->isp_osinfo.intsok; 791 isp->isp_osinfo.intsok = 0; 792 isp_intr(isp, isr, sema, mbox); 793 isp->isp_osinfo.intsok = iok; 794 } 795 ISP_UNLOCK(isp); 796 } 797 798 799 #define IspVirt2Off(a, x) \ 800 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 801 _BLK_REG_SHFT] + ((x) & 0xff)) 802 803 #define BXR2(pcs, off) \ 804 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 805 #define BXW2(pcs, off, v) \ 806 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 807 808 809 static INLINE int 810 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 811 { 812 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 813 u_int16_t val0, val1; 814 int i = 0; 815 816 do { 817 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 818 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 819 } while (val0 != val1 && ++i < 1000); 820 if (val0 != val1) { 821 return (1); 822 } 823 *rp = val0; 824 return (0); 825 } 826 827 static int 828 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 829 u_int16_t *semap, u_int16_t *mbp) 830 { 831 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 832 u_int16_t isr, sema; 833 834 if (IS_2100(isp)) { 835 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 836 return (0); 837 } 838 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 839 return (0); 840 } 841 } else { 842 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 843 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 844 } 845 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 846 isr &= INT_PENDING_MASK(isp); 847 sema &= BIU_SEMA_LOCK; 848 if (isr == 0 && sema == 0) { 849 return (0); 850 } 851 *isrp = isr; 852 if ((*semap = sema) != 0) { 853 if (IS_2100(isp)) { 854 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 855 return (0); 856 } 857 } else { 858 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 859 } 860 } 861 return (1); 862 } 863 864 static int 865 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 866 u_int16_t *semap, u_int16_t *mbox0p) 867 { 868 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 869 u_int32_t r2hisr; 870 871 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 872 *isrp = 0; 873 return (0); 874 } 875 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 876 IspVirt2Off(pcs, BIU_R2HSTSLO)); 877 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 878 if ((r2hisr & BIU_R2HST_INTR) == 0) { 879 *isrp = 0; 880 return (0); 881 } 882 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 883 case ISPR2HST_ROM_MBX_OK: 884 case ISPR2HST_ROM_MBX_FAIL: 885 case ISPR2HST_MBX_OK: 886 case ISPR2HST_MBX_FAIL: 887 case ISPR2HST_ASYNC_EVENT: 888 *isrp = r2hisr & 0xffff; 889 *mbox0p = (r2hisr >> 16); 890 *semap = 1; 891 return (1); 892 case ISPR2HST_RIO_16: 893 *isrp = r2hisr & 0xffff; 894 *mbox0p = ASYNC_RIO1; 895 *semap = 1; 896 return (1); 897 case ISPR2HST_FPOST: 898 *isrp = r2hisr & 0xffff; 899 *mbox0p = ASYNC_CMD_CMPLT; 900 *semap = 1; 901 return (1); 902 case ISPR2HST_FPOST_CTIO: 903 *isrp = r2hisr & 0xffff; 904 *mbox0p = ASYNC_CTIO_DONE; 905 *semap = 1; 906 return (1); 907 case ISPR2HST_RSPQ_UPDATE: 908 *isrp = r2hisr & 0xffff; 909 *mbox0p = 0; 910 *semap = 0; 911 return (1); 912 default: 913 return (0); 914 } 915 } 916 917 static u_int16_t 918 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 919 { 920 u_int16_t rv; 921 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 922 int oldconf = 0; 923 924 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 925 /* 926 * We will assume that someone has paused the RISC processor. 927 */ 928 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 929 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 930 oldconf | BIU_PCI_CONF1_SXP); 931 } 932 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 933 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 934 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 935 } 936 return (rv); 937 } 938 939 static void 940 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 941 { 942 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 943 int oldconf = 0; 944 945 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 946 /* 947 * We will assume that someone has paused the RISC processor. 948 */ 949 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 950 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 951 oldconf | BIU_PCI_CONF1_SXP); 952 } 953 BXW2(pcs, IspVirt2Off(isp, regoff), val); 954 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 955 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 956 } 957 } 958 959 static u_int16_t 960 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 961 { 962 u_int16_t rv, oc = 0; 963 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 964 965 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 966 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 967 u_int16_t tc; 968 /* 969 * We will assume that someone has paused the RISC processor. 970 */ 971 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 972 tc = oc & ~BIU_PCI1080_CONF1_DMA; 973 if (regoff & SXP_BANK1_SELECT) 974 tc |= BIU_PCI1080_CONF1_SXP1; 975 else 976 tc |= BIU_PCI1080_CONF1_SXP0; 977 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 978 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 979 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 980 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 981 oc | BIU_PCI1080_CONF1_DMA); 982 } 983 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 984 if (oc) { 985 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 986 } 987 return (rv); 988 } 989 990 static void 991 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 992 { 993 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 994 int oc = 0; 995 996 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 997 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 998 u_int16_t tc; 999 /* 1000 * We will assume that someone has paused the RISC processor. 1001 */ 1002 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1003 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1004 if (regoff & SXP_BANK1_SELECT) 1005 tc |= BIU_PCI1080_CONF1_SXP1; 1006 else 1007 tc |= BIU_PCI1080_CONF1_SXP0; 1008 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1009 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1010 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1011 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1012 oc | BIU_PCI1080_CONF1_DMA); 1013 } 1014 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1015 if (oc) { 1016 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1017 } 1018 } 1019 1020 1021 struct imush { 1022 struct ispsoftc *isp; 1023 int error; 1024 }; 1025 1026 static void imc(void *, bus_dma_segment_t *, int, int); 1027 1028 static void 1029 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1030 { 1031 struct imush *imushp = (struct imush *) arg; 1032 if (error) { 1033 imushp->error = error; 1034 } else { 1035 struct ispsoftc *isp =imushp->isp; 1036 bus_addr_t addr = segs->ds_addr; 1037 1038 isp->isp_rquest_dma = addr; 1039 addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1040 isp->isp_result_dma = addr; 1041 if (IS_FC(isp)) { 1042 addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1043 FCPARAM(isp)->isp_scdma = addr; 1044 } 1045 } 1046 } 1047 1048 /* 1049 * Should be BUS_SPACE_MAXSIZE, but MAXPHYS is larger than BUS_SPACE_MAXSIZE 1050 */ 1051 #define ISP_NSEGS ((MAXPHYS / PAGE_SIZE) + 1) 1052 1053 static int 1054 isp_pci_mbxdma(struct ispsoftc *isp) 1055 { 1056 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1057 caddr_t base; 1058 u_int32_t len; 1059 int i, error, ns; 1060 bus_size_t alim, slim; 1061 struct imush im; 1062 1063 /* 1064 * Already been here? If so, leave... 1065 */ 1066 if (isp->isp_rquest) { 1067 return (0); 1068 } 1069 1070 #ifdef ISP_DAC_SUPPORTED 1071 alim = BUS_SPACE_UNRESTRICTED; 1072 #else 1073 alim = BUS_SPACE_MAXADDR_32BIT; 1074 #endif 1075 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1076 slim = BUS_SPACE_MAXADDR_32BIT; 1077 } else { 1078 slim = BUS_SPACE_MAXADDR_24BIT; 1079 } 1080 1081 ISP_UNLOCK(isp); 1082 if (bus_dma_tag_create(NULL, 1, slim+1, alim, alim, 1083 NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &pcs->dmat)) { 1084 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1085 ISP_LOCK(isp); 1086 return(1); 1087 } 1088 1089 1090 len = sizeof (XS_T **) * isp->isp_maxcmds; 1091 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1092 if (isp->isp_xflist == NULL) { 1093 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1094 ISP_LOCK(isp); 1095 return (1); 1096 } 1097 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 1098 pcs->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1099 if (pcs->dmaps == NULL) { 1100 isp_prt(isp, ISP_LOGERR, "can't alloc dma map storage"); 1101 free(isp->isp_xflist, M_DEVBUF); 1102 ISP_LOCK(isp); 1103 return (1); 1104 } 1105 1106 /* 1107 * Allocate and map the request, result queues, plus FC scratch area. 1108 */ 1109 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1110 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1111 if (IS_FC(isp)) { 1112 len += ISP2100_SCRLEN; 1113 } 1114 1115 ns = (len / PAGE_SIZE) + 1; 1116 if (bus_dma_tag_create(pcs->dmat, QENTRY_LEN, slim+1, alim, alim, 1117 NULL, NULL, len, ns, slim, 0, &isp->isp_cdmat)) { 1118 isp_prt(isp, ISP_LOGERR, 1119 "cannot create a dma tag for control spaces"); 1120 free(pcs->dmaps, M_DEVBUF); 1121 free(isp->isp_xflist, M_DEVBUF); 1122 ISP_LOCK(isp); 1123 return (1); 1124 } 1125 1126 if (bus_dmamem_alloc(isp->isp_cdmat, (void **)&base, BUS_DMA_NOWAIT, 1127 &isp->isp_cdmap) != 0) { 1128 isp_prt(isp, ISP_LOGERR, 1129 "cannot allocate %d bytes of CCB memory", len); 1130 bus_dma_tag_destroy(isp->isp_cdmat); 1131 free(isp->isp_xflist, M_DEVBUF); 1132 free(pcs->dmaps, M_DEVBUF); 1133 ISP_LOCK(isp); 1134 return (1); 1135 } 1136 1137 for (i = 0; i < isp->isp_maxcmds; i++) { 1138 error = bus_dmamap_create(pcs->dmat, 0, &pcs->dmaps[i]); 1139 if (error) { 1140 isp_prt(isp, ISP_LOGERR, 1141 "error %d creating per-cmd DMA maps", error); 1142 while (--i >= 0) { 1143 bus_dmamap_destroy(pcs->dmat, pcs->dmaps[i]); 1144 } 1145 goto bad; 1146 } 1147 } 1148 1149 im.isp = isp; 1150 im.error = 0; 1151 bus_dmamap_load(isp->isp_cdmat, isp->isp_cdmap, base, len, imc, &im, 0); 1152 if (im.error) { 1153 isp_prt(isp, ISP_LOGERR, 1154 "error %d loading dma map for control areas", im.error); 1155 goto bad; 1156 } 1157 1158 isp->isp_rquest = base; 1159 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1160 isp->isp_result = base; 1161 if (IS_FC(isp)) { 1162 base += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1163 FCPARAM(isp)->isp_scratch = base; 1164 } 1165 ISP_LOCK(isp); 1166 return (0); 1167 1168 bad: 1169 bus_dmamem_free(isp->isp_cdmat, base, isp->isp_cdmap); 1170 bus_dma_tag_destroy(isp->isp_cdmat); 1171 free(isp->isp_xflist, M_DEVBUF); 1172 free(pcs->dmaps, M_DEVBUF); 1173 ISP_LOCK(isp); 1174 isp->isp_rquest = NULL; 1175 return (1); 1176 } 1177 1178 typedef struct { 1179 struct ispsoftc *isp; 1180 void *cmd_token; 1181 void *rq; 1182 u_int16_t *nxtip; 1183 u_int16_t optr; 1184 u_int error; 1185 } mush_t; 1186 1187 #define MUSHERR_NOQENTRIES -2 1188 1189 #ifdef ISP_TARGET_MODE 1190 /* 1191 * We need to handle DMA for target mode differently from initiator mode. 1192 * 1193 * DMA mapping and construction and submission of CTIO Request Entries 1194 * and rendevous for completion are very tightly coupled because we start 1195 * out by knowing (per platform) how much data we have to move, but we 1196 * don't know, up front, how many DMA mapping segments will have to be used 1197 * cover that data, so we don't know how many CTIO Request Entries we 1198 * will end up using. Further, for performance reasons we may want to 1199 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1200 * 1201 * The standard vector still goes through isp_pci_dmasetup, but the callback 1202 * for the DMA mapping routines comes here instead with the whole transfer 1203 * mapped and a pointer to a partially filled in already allocated request 1204 * queue entry. We finish the job. 1205 */ 1206 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1207 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1208 1209 #define STATUS_WITH_DATA 1 1210 1211 static void 1212 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1213 { 1214 mush_t *mp; 1215 struct ccb_scsiio *csio; 1216 struct ispsoftc *isp; 1217 struct isp_pcisoftc *pcs; 1218 bus_dmamap_t *dp; 1219 ct_entry_t *cto, *qe; 1220 u_int8_t scsi_status; 1221 u_int16_t curi, nxti, handle; 1222 u_int32_t sflags; 1223 int32_t resid; 1224 int nth_ctio, nctios, send_status; 1225 1226 mp = (mush_t *) arg; 1227 if (error) { 1228 mp->error = error; 1229 return; 1230 } 1231 1232 isp = mp->isp; 1233 csio = mp->cmd_token; 1234 cto = mp->rq; 1235 curi = isp->isp_reqidx; 1236 qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1237 1238 cto->ct_xfrlen = 0; 1239 cto->ct_seg_count = 0; 1240 cto->ct_header.rqs_entry_count = 1; 1241 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1242 1243 if (nseg == 0) { 1244 cto->ct_header.rqs_seqno = 1; 1245 isp_prt(isp, ISP_LOGTDEBUG1, 1246 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1247 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1248 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1249 cto->ct_scsi_status, cto->ct_resid); 1250 ISP_TDQE(isp, "tdma_mk[no data]", curi, cto); 1251 isp_put_ctio(isp, cto, qe); 1252 return; 1253 } 1254 1255 nctios = nseg / ISP_RQDSEG; 1256 if (nseg % ISP_RQDSEG) { 1257 nctios++; 1258 } 1259 1260 /* 1261 * Save syshandle, and potentially any SCSI status, which we'll 1262 * reinsert on the last CTIO we're going to send. 1263 */ 1264 1265 handle = cto->ct_syshandle; 1266 cto->ct_syshandle = 0; 1267 cto->ct_header.rqs_seqno = 0; 1268 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1269 1270 if (send_status) { 1271 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1272 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1273 /* 1274 * Preserve residual. 1275 */ 1276 resid = cto->ct_resid; 1277 1278 /* 1279 * Save actual SCSI status. 1280 */ 1281 scsi_status = cto->ct_scsi_status; 1282 1283 #ifndef STATUS_WITH_DATA 1284 sflags |= CT_NO_DATA; 1285 /* 1286 * We can't do a status at the same time as a data CTIO, so 1287 * we need to synthesize an extra CTIO at this level. 1288 */ 1289 nctios++; 1290 #endif 1291 } else { 1292 sflags = scsi_status = resid = 0; 1293 } 1294 1295 cto->ct_resid = 0; 1296 cto->ct_scsi_status = 0; 1297 1298 pcs = (struct isp_pcisoftc *)isp; 1299 dp = &pcs->dmaps[isp_handle_index(handle)]; 1300 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1301 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1302 } else { 1303 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1304 } 1305 1306 nxti = *mp->nxtip; 1307 1308 for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { 1309 int seglim; 1310 1311 seglim = nseg; 1312 if (seglim) { 1313 int seg; 1314 1315 if (seglim > ISP_RQDSEG) 1316 seglim = ISP_RQDSEG; 1317 1318 for (seg = 0; seg < seglim; seg++, nseg--) { 1319 /* 1320 * Unlike normal initiator commands, we don't 1321 * do any swizzling here. 1322 */ 1323 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1324 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1325 cto->ct_xfrlen += dm_segs->ds_len; 1326 dm_segs++; 1327 } 1328 cto->ct_seg_count = seg; 1329 } else { 1330 /* 1331 * This case should only happen when we're sending an 1332 * extra CTIO with final status. 1333 */ 1334 if (send_status == 0) { 1335 isp_prt(isp, ISP_LOGWARN, 1336 "tdma_mk ran out of segments"); 1337 mp->error = EINVAL; 1338 return; 1339 } 1340 } 1341 1342 /* 1343 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1344 * ct_tagtype, and ct_timeout have been carried over 1345 * unchanged from what our caller had set. 1346 * 1347 * The dataseg fields and the seg_count fields we just got 1348 * through setting. The data direction we've preserved all 1349 * along and only clear it if we're now sending status. 1350 */ 1351 1352 if (nth_ctio == nctios - 1) { 1353 /* 1354 * We're the last in a sequence of CTIOs, so mark 1355 * this CTIO and save the handle to the CCB such that 1356 * when this CTIO completes we can free dma resources 1357 * and do whatever else we need to do to finish the 1358 * rest of the command. We *don't* give this to the 1359 * firmware to work on- the caller will do that. 1360 */ 1361 1362 cto->ct_syshandle = handle; 1363 cto->ct_header.rqs_seqno = 1; 1364 1365 if (send_status) { 1366 cto->ct_scsi_status = scsi_status; 1367 cto->ct_flags |= sflags; 1368 cto->ct_resid = resid; 1369 } 1370 if (send_status) { 1371 isp_prt(isp, ISP_LOGTDEBUG1, 1372 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 1373 "scsi status %x resid %d", 1374 cto->ct_fwhandle, csio->ccb_h.target_lun, 1375 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 1376 cto->ct_scsi_status, cto->ct_resid); 1377 } else { 1378 isp_prt(isp, ISP_LOGTDEBUG1, 1379 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 1380 cto->ct_fwhandle, csio->ccb_h.target_lun, 1381 cto->ct_iid, cto->ct_tag_val, 1382 cto->ct_flags); 1383 } 1384 isp_put_ctio(isp, cto, qe); 1385 ISP_TDQE(isp, "last tdma_mk", curi, cto); 1386 if (nctios > 1) { 1387 MEMORYBARRIER(isp, SYNC_REQUEST, 1388 curi, QENTRY_LEN); 1389 } 1390 } else { 1391 ct_entry_t *oqe = qe; 1392 1393 /* 1394 * Make sure syshandle fields are clean 1395 */ 1396 cto->ct_syshandle = 0; 1397 cto->ct_header.rqs_seqno = 0; 1398 1399 isp_prt(isp, ISP_LOGTDEBUG1, 1400 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 1401 cto->ct_fwhandle, csio->ccb_h.target_lun, 1402 cto->ct_iid, cto->ct_flags); 1403 1404 /* 1405 * Get a new CTIO 1406 */ 1407 qe = (ct_entry_t *) 1408 ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1409 nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); 1410 if (nxti == mp->optr) { 1411 isp_prt(isp, ISP_LOGTDEBUG0, 1412 "Queue Overflow in tdma_mk"); 1413 mp->error = MUSHERR_NOQENTRIES; 1414 return; 1415 } 1416 1417 /* 1418 * Now that we're done with the old CTIO, 1419 * flush it out to the request queue. 1420 */ 1421 ISP_TDQE(isp, "dma_tgt_fc", curi, cto); 1422 isp_put_ctio(isp, cto, oqe); 1423 if (nth_ctio != 0) { 1424 MEMORYBARRIER(isp, SYNC_REQUEST, curi, 1425 QENTRY_LEN); 1426 } 1427 curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); 1428 1429 /* 1430 * Reset some fields in the CTIO so we can reuse 1431 * for the next one we'll flush to the request 1432 * queue. 1433 */ 1434 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1435 cto->ct_header.rqs_entry_count = 1; 1436 cto->ct_header.rqs_flags = 0; 1437 cto->ct_status = 0; 1438 cto->ct_scsi_status = 0; 1439 cto->ct_xfrlen = 0; 1440 cto->ct_resid = 0; 1441 cto->ct_seg_count = 0; 1442 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1443 } 1444 } 1445 *mp->nxtip = nxti; 1446 } 1447 1448 /* 1449 * We don't have to do multiple CTIOs here. Instead, we can just do 1450 * continuation segments as needed. This greatly simplifies the code 1451 * improves performance. 1452 */ 1453 1454 static void 1455 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1456 { 1457 mush_t *mp; 1458 struct ccb_scsiio *csio; 1459 struct ispsoftc *isp; 1460 ct2_entry_t *cto, *qe; 1461 u_int16_t curi, nxti; 1462 int segcnt; 1463 1464 mp = (mush_t *) arg; 1465 if (error) { 1466 mp->error = error; 1467 return; 1468 } 1469 1470 isp = mp->isp; 1471 csio = mp->cmd_token; 1472 cto = mp->rq; 1473 1474 curi = isp->isp_reqidx; 1475 qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1476 1477 if (nseg == 0) { 1478 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1479 isp_prt(isp, ISP_LOGWARN, 1480 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1481 "set (0x%x)", cto->ct_flags); 1482 mp->error = EINVAL; 1483 return; 1484 } 1485 /* 1486 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1487 * flags to NO DATA and clear relative offset flags. 1488 * We preserve the ct_resid and the response area. 1489 */ 1490 cto->ct_header.rqs_seqno = 1; 1491 cto->ct_seg_count = 0; 1492 cto->ct_reloff = 0; 1493 isp_prt(isp, ISP_LOGTDEBUG1, 1494 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1495 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1496 cto->ct_iid, cto->ct_flags, cto->ct_status, 1497 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1498 isp_put_ctio2(isp, cto, qe); 1499 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe); 1500 return; 1501 } 1502 1503 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1504 isp_prt(isp, ISP_LOGERR, 1505 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1506 "(0x%x)", cto->ct_flags); 1507 mp->error = EINVAL; 1508 return; 1509 } 1510 1511 1512 nxti = *mp->nxtip; 1513 1514 /* 1515 * Set up the CTIO2 data segments. 1516 */ 1517 for (segcnt = 0; cto->ct_seg_count < ISP_RQDSEG_T2 && segcnt < nseg; 1518 cto->ct_seg_count++, segcnt++) { 1519 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_base = 1520 dm_segs[segcnt].ds_addr; 1521 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_count = 1522 dm_segs[segcnt].ds_len; 1523 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1524 isp_prt(isp, ISP_LOGTDEBUG1, "isp_send_ctio2: ent0[%d]0x%x:%d", 1525 cto->ct_seg_count, dm_segs[segcnt].ds_addr, 1526 dm_segs[segcnt].ds_len); 1527 } 1528 1529 while (segcnt < nseg) { 1530 u_int16_t curip; 1531 int seg; 1532 ispcontreq_t local, *crq = &local, *qep; 1533 1534 qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1535 curip = nxti; 1536 nxti = ISP_NXT_QENTRY(curip, RQUEST_QUEUE_LEN(isp)); 1537 if (nxti == mp->optr) { 1538 ISP_UNLOCK(isp); 1539 isp_prt(isp, ISP_LOGTDEBUG0, 1540 "tdma_mkfc: request queue overflow"); 1541 mp->error = MUSHERR_NOQENTRIES; 1542 return; 1543 } 1544 cto->ct_header.rqs_entry_count++; 1545 MEMZERO((void *)crq, sizeof (*crq)); 1546 crq->req_header.rqs_entry_count = 1; 1547 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1548 for (seg = 0; segcnt < nseg && seg < ISP_CDSEG; 1549 segcnt++, seg++) { 1550 crq->req_dataseg[seg].ds_base = dm_segs[segcnt].ds_addr; 1551 crq->req_dataseg[seg].ds_count = dm_segs[segcnt].ds_len; 1552 isp_prt(isp, ISP_LOGTDEBUG1, 1553 "isp_send_ctio2: ent%d[%d]%x:%u", 1554 cto->ct_header.rqs_entry_count-1, seg, 1555 dm_segs[segcnt].ds_addr, dm_segs[segcnt].ds_len); 1556 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1557 cto->ct_seg_count++; 1558 } 1559 MEMORYBARRIER(isp, SYNC_REQUEST, curip, QENTRY_LEN); 1560 isp_put_cont_req(isp, crq, qep); 1561 ISP_TDQE(isp, "cont entry", curi, qep); 1562 } 1563 1564 /* 1565 * No do final twiddling for the CTIO itself. 1566 */ 1567 cto->ct_header.rqs_seqno = 1; 1568 isp_prt(isp, ISP_LOGTDEBUG1, 1569 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x resid %d", 1570 cto->ct_rxid, csio->ccb_h.target_lun, (int) cto->ct_iid, 1571 cto->ct_flags, cto->ct_status, cto->rsp.m1.ct_scsi_status, 1572 cto->ct_resid); 1573 isp_put_ctio2(isp, cto, qe); 1574 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe); 1575 *mp->nxtip = nxti; 1576 } 1577 #endif 1578 1579 static void dma2(void *, bus_dma_segment_t *, int, int); 1580 1581 static void 1582 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1583 { 1584 mush_t *mp; 1585 struct ispsoftc *isp; 1586 struct ccb_scsiio *csio; 1587 struct isp_pcisoftc *pcs; 1588 bus_dmamap_t *dp; 1589 bus_dma_segment_t *eseg; 1590 ispreq_t *rq; 1591 int seglim, datalen; 1592 u_int16_t nxti; 1593 1594 mp = (mush_t *) arg; 1595 if (error) { 1596 mp->error = error; 1597 return; 1598 } 1599 1600 if (nseg < 1) { 1601 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1602 mp->error = EFAULT; 1603 return; 1604 } 1605 csio = mp->cmd_token; 1606 isp = mp->isp; 1607 rq = mp->rq; 1608 pcs = (struct isp_pcisoftc *)mp->isp; 1609 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1610 nxti = *mp->nxtip; 1611 1612 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1613 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1614 } else { 1615 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1616 } 1617 1618 datalen = XS_XFRLEN(csio); 1619 1620 /* 1621 * We're passed an initial partially filled in entry that 1622 * has most fields filled in except for data transfer 1623 * related values. 1624 * 1625 * Our job is to fill in the initial request queue entry and 1626 * then to start allocating and filling in continuation entries 1627 * until we've covered the entire transfer. 1628 */ 1629 1630 if (IS_FC(isp)) { 1631 seglim = ISP_RQDSEG_T2; 1632 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1633 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1634 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1635 } else { 1636 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1637 } 1638 } else { 1639 if (csio->cdb_len > 12) { 1640 seglim = 0; 1641 } else { 1642 seglim = ISP_RQDSEG; 1643 } 1644 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1645 rq->req_flags |= REQFLAG_DATA_IN; 1646 } else { 1647 rq->req_flags |= REQFLAG_DATA_OUT; 1648 } 1649 } 1650 1651 eseg = dm_segs + nseg; 1652 1653 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1654 if (IS_FC(isp)) { 1655 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1656 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1657 dm_segs->ds_addr; 1658 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1659 dm_segs->ds_len; 1660 } else { 1661 rq->req_dataseg[rq->req_seg_count].ds_base = 1662 dm_segs->ds_addr; 1663 rq->req_dataseg[rq->req_seg_count].ds_count = 1664 dm_segs->ds_len; 1665 } 1666 datalen -= dm_segs->ds_len; 1667 rq->req_seg_count++; 1668 dm_segs++; 1669 } 1670 1671 while (datalen > 0 && dm_segs != eseg) { 1672 u_int16_t onxti; 1673 ispcontreq_t local, *crq = &local, *cqe; 1674 1675 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1676 onxti = nxti; 1677 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1678 if (nxti == mp->optr) { 1679 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1680 mp->error = MUSHERR_NOQENTRIES; 1681 return; 1682 } 1683 rq->req_header.rqs_entry_count++; 1684 MEMZERO((void *)crq, sizeof (*crq)); 1685 crq->req_header.rqs_entry_count = 1; 1686 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1687 1688 seglim = 0; 1689 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1690 crq->req_dataseg[seglim].ds_base = 1691 dm_segs->ds_addr; 1692 crq->req_dataseg[seglim].ds_count = 1693 dm_segs->ds_len; 1694 rq->req_seg_count++; 1695 dm_segs++; 1696 seglim++; 1697 datalen -= dm_segs->ds_len; 1698 } 1699 isp_put_cont_req(isp, crq, cqe); 1700 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1701 } 1702 *mp->nxtip = nxti; 1703 } 1704 1705 static int 1706 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1707 u_int16_t *nxtip, u_int16_t optr) 1708 { 1709 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1710 ispreq_t *qep; 1711 bus_dmamap_t *dp = NULL; 1712 mush_t mush, *mp; 1713 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1714 1715 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); 1716 #ifdef ISP_TARGET_MODE 1717 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1718 if (IS_FC(isp)) { 1719 eptr = tdma_mkfc; 1720 } else { 1721 eptr = tdma_mk; 1722 } 1723 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1724 (csio->dxfer_len == 0)) { 1725 mp = &mush; 1726 mp->isp = isp; 1727 mp->cmd_token = csio; 1728 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 1729 mp->nxtip = nxtip; 1730 mp->optr = optr; 1731 mp->error = 0; 1732 (*eptr)(mp, NULL, 0, 0); 1733 goto mbxsync; 1734 } 1735 } else 1736 #endif 1737 eptr = dma2; 1738 1739 1740 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1741 (csio->dxfer_len == 0)) { 1742 rq->req_seg_count = 1; 1743 goto mbxsync; 1744 } 1745 1746 /* 1747 * Do a virtual grapevine step to collect info for 1748 * the callback dma allocation that we have to use... 1749 */ 1750 mp = &mush; 1751 mp->isp = isp; 1752 mp->cmd_token = csio; 1753 mp->rq = rq; 1754 mp->nxtip = nxtip; 1755 mp->optr = optr; 1756 mp->error = 0; 1757 1758 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1759 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1760 int error, s; 1761 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1762 s = splsoftvm(); 1763 error = bus_dmamap_load(pcs->dmat, *dp, 1764 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1765 if (error == EINPROGRESS) { 1766 bus_dmamap_unload(pcs->dmat, *dp); 1767 mp->error = EINVAL; 1768 isp_prt(isp, ISP_LOGERR, 1769 "deferred dma allocation not supported"); 1770 } else if (error && mp->error == 0) { 1771 #ifdef DIAGNOSTIC 1772 isp_prt(isp, ISP_LOGERR, 1773 "error %d in dma mapping code", error); 1774 #endif 1775 mp->error = error; 1776 } 1777 splx(s); 1778 } else { 1779 /* Pointer to physical buffer */ 1780 struct bus_dma_segment seg; 1781 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1782 seg.ds_len = csio->dxfer_len; 1783 (*eptr)(mp, &seg, 1, 0); 1784 } 1785 } else { 1786 struct bus_dma_segment *segs; 1787 1788 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1789 isp_prt(isp, ISP_LOGERR, 1790 "Physical segment pointers unsupported"); 1791 mp->error = EINVAL; 1792 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1793 isp_prt(isp, ISP_LOGERR, 1794 "Virtual segment addresses unsupported"); 1795 mp->error = EINVAL; 1796 } else { 1797 /* Just use the segments provided */ 1798 segs = (struct bus_dma_segment *) csio->data_ptr; 1799 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1800 } 1801 } 1802 if (mp->error) { 1803 int retval = CMD_COMPLETE; 1804 if (mp->error == MUSHERR_NOQENTRIES) { 1805 retval = CMD_EAGAIN; 1806 } else if (mp->error == EFBIG) { 1807 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1808 } else if (mp->error == EINVAL) { 1809 XS_SETERR(csio, CAM_REQ_INVALID); 1810 } else { 1811 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1812 } 1813 return (retval); 1814 } 1815 mbxsync: 1816 switch (rq->req_header.rqs_entry_type) { 1817 case RQSTYPE_REQUEST: 1818 isp_put_request(isp, rq, qep); 1819 break; 1820 case RQSTYPE_CMDONLY: 1821 isp_put_extended_request(isp, (ispextreq_t *)rq, 1822 (ispextreq_t *)qep); 1823 break; 1824 case RQSTYPE_T2RQS: 1825 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1826 break; 1827 } 1828 return (CMD_QUEUED); 1829 } 1830 1831 static void 1832 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1833 { 1834 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1835 bus_dmamap_t *dp = &pcs->dmaps[isp_handle_index(handle)]; 1836 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1837 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTREAD); 1838 } else { 1839 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTWRITE); 1840 } 1841 bus_dmamap_unload(pcs->dmat, *dp); 1842 } 1843 1844 1845 static void 1846 isp_pci_reset1(struct ispsoftc *isp) 1847 { 1848 /* Make sure the BIOS is disabled */ 1849 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1850 /* and enable interrupts */ 1851 ENABLE_INTS(isp); 1852 } 1853 1854 static void 1855 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1856 { 1857 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1858 if (msg) 1859 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1860 else 1861 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1862 if (IS_SCSI(isp)) 1863 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1864 else 1865 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1866 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1867 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1868 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1869 1870 1871 if (IS_SCSI(isp)) { 1872 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1873 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1874 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1875 ISP_READ(isp, CDMA_FIFO_STS)); 1876 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1877 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1878 ISP_READ(isp, DDMA_FIFO_STS)); 1879 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1880 ISP_READ(isp, SXP_INTERRUPT), 1881 ISP_READ(isp, SXP_GROSS_ERR), 1882 ISP_READ(isp, SXP_PINS_CTRL)); 1883 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1884 } 1885 printf(" mbox regs: %x %x %x %x %x\n", 1886 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1887 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1888 ISP_READ(isp, OUTMAILBOX4)); 1889 printf(" PCI Status Command/Status=%x\n", 1890 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1891 } 1892