1 /* $FreeBSD$ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * FreeBSD Version. 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000, 2001 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 36 #include <pci/pcireg.h> 37 #include <pci/pcivar.h> 38 39 #include <machine/bus_memio.h> 40 #include <machine/bus_pio.h> 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 46 #include <dev/isp/isp_freebsd.h> 47 48 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 49 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 50 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 51 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 52 static int 53 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 54 static int 55 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 56 static int isp_pci_mbxdma(struct ispsoftc *); 57 static int 58 isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, u_int16_t *, u_int16_t); 59 static void 60 isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 61 62 static void isp_pci_reset1(struct ispsoftc *); 63 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 64 65 #ifndef ISP_CODE_ORG 66 #define ISP_CODE_ORG 0x1000 67 #endif 68 69 static struct ispmdvec mdvec = { 70 isp_pci_rd_isr, 71 isp_pci_rd_reg, 72 isp_pci_wr_reg, 73 isp_pci_mbxdma, 74 isp_pci_dmasetup, 75 isp_pci_dmateardown, 76 NULL, 77 isp_pci_reset1, 78 isp_pci_dumpregs, 79 NULL, 80 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 81 }; 82 83 static struct ispmdvec mdvec_1080 = { 84 isp_pci_rd_isr, 85 isp_pci_rd_reg_1080, 86 isp_pci_wr_reg_1080, 87 isp_pci_mbxdma, 88 isp_pci_dmasetup, 89 isp_pci_dmateardown, 90 NULL, 91 isp_pci_reset1, 92 isp_pci_dumpregs, 93 NULL, 94 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 95 }; 96 97 static struct ispmdvec mdvec_12160 = { 98 isp_pci_rd_isr, 99 isp_pci_rd_reg_1080, 100 isp_pci_wr_reg_1080, 101 isp_pci_mbxdma, 102 isp_pci_dmasetup, 103 isp_pci_dmateardown, 104 NULL, 105 isp_pci_reset1, 106 isp_pci_dumpregs, 107 NULL, 108 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 109 }; 110 111 static struct ispmdvec mdvec_2100 = { 112 isp_pci_rd_isr, 113 isp_pci_rd_reg, 114 isp_pci_wr_reg, 115 isp_pci_mbxdma, 116 isp_pci_dmasetup, 117 isp_pci_dmateardown, 118 NULL, 119 isp_pci_reset1, 120 isp_pci_dumpregs 121 }; 122 123 static struct ispmdvec mdvec_2200 = { 124 isp_pci_rd_isr, 125 isp_pci_rd_reg, 126 isp_pci_wr_reg, 127 isp_pci_mbxdma, 128 isp_pci_dmasetup, 129 isp_pci_dmateardown, 130 NULL, 131 isp_pci_reset1, 132 isp_pci_dumpregs 133 }; 134 135 static struct ispmdvec mdvec_2300 = { 136 isp_pci_rd_isr_2300, 137 isp_pci_rd_reg, 138 isp_pci_wr_reg, 139 isp_pci_mbxdma, 140 isp_pci_dmasetup, 141 isp_pci_dmateardown, 142 NULL, 143 isp_pci_reset1, 144 isp_pci_dumpregs 145 }; 146 147 #ifndef PCIM_CMD_INVEN 148 #define PCIM_CMD_INVEN 0x10 149 #endif 150 #ifndef PCIM_CMD_BUSMASTEREN 151 #define PCIM_CMD_BUSMASTEREN 0x0004 152 #endif 153 #ifndef PCIM_CMD_PERRESPEN 154 #define PCIM_CMD_PERRESPEN 0x0040 155 #endif 156 #ifndef PCIM_CMD_SEREN 157 #define PCIM_CMD_SEREN 0x0100 158 #endif 159 160 #ifndef PCIR_COMMAND 161 #define PCIR_COMMAND 0x04 162 #endif 163 164 #ifndef PCIR_CACHELNSZ 165 #define PCIR_CACHELNSZ 0x0c 166 #endif 167 168 #ifndef PCIR_LATTIMER 169 #define PCIR_LATTIMER 0x0d 170 #endif 171 172 #ifndef PCIR_ROMADDR 173 #define PCIR_ROMADDR 0x30 174 #endif 175 176 #ifndef PCI_VENDOR_QLOGIC 177 #define PCI_VENDOR_QLOGIC 0x1077 178 #endif 179 180 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 181 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 182 #endif 183 184 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 185 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 186 #endif 187 188 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 189 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 190 #endif 191 192 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 193 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 194 #endif 195 196 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 197 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 198 #endif 199 200 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 201 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 202 #endif 203 204 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 205 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 206 #endif 207 208 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 209 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 210 #endif 211 212 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 213 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 214 #endif 215 216 #define PCI_QLOGIC_ISP1020 \ 217 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 218 219 #define PCI_QLOGIC_ISP1080 \ 220 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 221 222 #define PCI_QLOGIC_ISP12160 \ 223 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 224 225 #define PCI_QLOGIC_ISP1240 \ 226 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 227 228 #define PCI_QLOGIC_ISP1280 \ 229 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 230 231 #define PCI_QLOGIC_ISP2100 \ 232 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 233 234 #define PCI_QLOGIC_ISP2200 \ 235 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 236 237 #define PCI_QLOGIC_ISP2300 \ 238 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 239 240 #define PCI_QLOGIC_ISP2312 \ 241 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 242 243 /* 244 * Odd case for some AMI raid cards... We need to *not* attach to this. 245 */ 246 #define AMI_RAID_SUBVENDOR_ID 0x101e 247 248 #define IO_MAP_REG 0x10 249 #define MEM_MAP_REG 0x14 250 251 #define PCI_DFLT_LTNCY 0x40 252 #define PCI_DFLT_LNSZ 0x10 253 254 static int isp_pci_probe (device_t); 255 static int isp_pci_attach (device_t); 256 257 struct isp_pcisoftc { 258 struct ispsoftc pci_isp; 259 device_t pci_dev; 260 struct resource * pci_reg; 261 bus_space_tag_t pci_st; 262 bus_space_handle_t pci_sh; 263 void * ih; 264 int16_t pci_poff[_NREG_BLKS]; 265 bus_dma_tag_t parent_dmat; 266 bus_dma_tag_t cntrol_dmat; 267 bus_dmamap_t cntrol_dmap; 268 bus_dmamap_t *dmaps; 269 }; 270 ispfwfunc *isp_get_firmware_p = NULL; 271 272 static device_method_t isp_pci_methods[] = { 273 /* Device interface */ 274 DEVMETHOD(device_probe, isp_pci_probe), 275 DEVMETHOD(device_attach, isp_pci_attach), 276 { 0, 0 } 277 }; 278 static void isp_pci_intr(void *); 279 280 static driver_t isp_pci_driver = { 281 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 282 }; 283 static devclass_t isp_devclass; 284 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 285 MODULE_VERSION(isp, 1); 286 287 static int 288 isp_pci_probe(device_t dev) 289 { 290 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 291 case PCI_QLOGIC_ISP1020: 292 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 293 break; 294 case PCI_QLOGIC_ISP1080: 295 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 296 break; 297 case PCI_QLOGIC_ISP1240: 298 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 299 break; 300 case PCI_QLOGIC_ISP1280: 301 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 302 break; 303 case PCI_QLOGIC_ISP12160: 304 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 305 return (ENXIO); 306 } 307 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 308 break; 309 case PCI_QLOGIC_ISP2100: 310 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 311 break; 312 case PCI_QLOGIC_ISP2200: 313 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 314 break; 315 case PCI_QLOGIC_ISP2300: 316 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 317 break; 318 case PCI_QLOGIC_ISP2312: 319 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 320 break; 321 default: 322 return (ENXIO); 323 } 324 if (device_get_unit(dev) == 0 && bootverbose) { 325 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 326 "Core Version %d.%d\n", 327 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 328 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 329 } 330 /* 331 * XXXX: Here is where we might load the f/w module 332 * XXXX: (or increase a reference count to it). 333 */ 334 return (0); 335 } 336 337 static int 338 isp_pci_attach(device_t dev) 339 { 340 struct resource *regs, *irq; 341 int tval, rtp, rgd, iqd, m1, m2, isp_debug, role; 342 u_int32_t data, cmd, linesz, psize, basetype; 343 struct isp_pcisoftc *pcs; 344 struct ispsoftc *isp = NULL; 345 struct ispmdvec *mdvp; 346 bus_size_t lim; 347 const char *sptr; 348 int locksetup = 0; 349 350 /* 351 * Figure out if we're supposed to skip this one. 352 * If we are, we actually go to ISP_ROLE_NONE. 353 */ 354 355 tval = 0; 356 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 357 "disable", &tval) == 0 && tval) { 358 device_printf(dev, "device is disabled\n"); 359 /* but return 0 so the !$)$)*!$*) unit isn't reused */ 360 return (0); 361 } 362 363 role = 0; 364 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 365 "role", &role) == 0 && 366 ((role & ~(ISP_ROLE_INITIATOR|ISP_ROLE_TARGET)) == 0)) { 367 device_printf(dev, "setting role to 0x%x\n", role); 368 } else { 369 #ifdef ISP_TARGET_MODE 370 role = ISP_ROLE_INITIATOR|ISP_ROLE_TARGET; 371 #else 372 role = ISP_DEFAULT_ROLES; 373 #endif 374 } 375 376 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT | M_ZERO); 377 if (pcs == NULL) { 378 device_printf(dev, "cannot allocate softc\n"); 379 return (ENOMEM); 380 } 381 382 /* 383 * Figure out which we should try first - memory mapping or i/o mapping? 384 */ 385 #ifdef __alpha__ 386 m1 = PCIM_CMD_MEMEN; 387 m2 = PCIM_CMD_PORTEN; 388 #else 389 m1 = PCIM_CMD_PORTEN; 390 m2 = PCIM_CMD_MEMEN; 391 #endif 392 393 tval = 0; 394 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 395 "prefer_iomap", &tval) == 0 && tval != 0) { 396 m1 = PCIM_CMD_PORTEN; 397 m2 = PCIM_CMD_MEMEN; 398 } 399 tval = 0; 400 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 401 "prefer_memmap", &tval) == 0 && tval != 0) { 402 m1 = PCIM_CMD_MEMEN; 403 m2 = PCIM_CMD_PORTEN; 404 } 405 406 linesz = PCI_DFLT_LNSZ; 407 irq = regs = NULL; 408 rgd = rtp = iqd = 0; 409 410 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 411 if (cmd & m1) { 412 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 413 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 414 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 415 } 416 if (regs == NULL && (cmd & m2)) { 417 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 418 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 419 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 420 } 421 if (regs == NULL) { 422 device_printf(dev, "unable to map any ports\n"); 423 goto bad; 424 } 425 if (bootverbose) 426 device_printf(dev, "using %s space register mapping\n", 427 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 428 pcs->pci_dev = dev; 429 pcs->pci_reg = regs; 430 pcs->pci_st = rman_get_bustag(regs); 431 pcs->pci_sh = rman_get_bushandle(regs); 432 433 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 434 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 435 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 436 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 437 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 438 mdvp = &mdvec; 439 basetype = ISP_HA_SCSI_UNKNOWN; 440 psize = sizeof (sdparam); 441 lim = BUS_SPACE_MAXSIZE_32BIT; 442 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 443 mdvp = &mdvec; 444 basetype = ISP_HA_SCSI_UNKNOWN; 445 psize = sizeof (sdparam); 446 lim = BUS_SPACE_MAXSIZE_24BIT; 447 } 448 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 449 mdvp = &mdvec_1080; 450 basetype = ISP_HA_SCSI_1080; 451 psize = sizeof (sdparam); 452 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 453 ISP1080_DMA_REGS_OFF; 454 } 455 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 456 mdvp = &mdvec_1080; 457 basetype = ISP_HA_SCSI_1240; 458 psize = 2 * sizeof (sdparam); 459 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 460 ISP1080_DMA_REGS_OFF; 461 } 462 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 463 mdvp = &mdvec_1080; 464 basetype = ISP_HA_SCSI_1280; 465 psize = 2 * sizeof (sdparam); 466 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 467 ISP1080_DMA_REGS_OFF; 468 } 469 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 470 mdvp = &mdvec_12160; 471 basetype = ISP_HA_SCSI_12160; 472 psize = 2 * sizeof (sdparam); 473 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 474 ISP1080_DMA_REGS_OFF; 475 } 476 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 477 mdvp = &mdvec_2100; 478 basetype = ISP_HA_FC_2100; 479 psize = sizeof (fcparam); 480 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 481 PCI_MBOX_REGS2100_OFF; 482 if (pci_get_revid(dev) < 3) { 483 /* 484 * XXX: Need to get the actual revision 485 * XXX: number of the 2100 FB. At any rate, 486 * XXX: lower cache line size for early revision 487 * XXX; boards. 488 */ 489 linesz = 1; 490 } 491 } 492 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 493 mdvp = &mdvec_2200; 494 basetype = ISP_HA_FC_2200; 495 psize = sizeof (fcparam); 496 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 497 PCI_MBOX_REGS2100_OFF; 498 } 499 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2300 || 500 pci_get_devid(dev) == PCI_QLOGIC_ISP2312) { 501 mdvp = &mdvec_2300; 502 basetype = ISP_HA_FC_2300; 503 psize = sizeof (fcparam); 504 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 505 PCI_MBOX_REGS2300_OFF; 506 } 507 isp = &pcs->pci_isp; 508 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 509 if (isp->isp_param == NULL) { 510 device_printf(dev, "cannot allocate parameter data\n"); 511 goto bad; 512 } 513 isp->isp_mdvec = mdvp; 514 isp->isp_type = basetype; 515 isp->isp_revision = pci_get_revid(dev); 516 isp->isp_role = role; 517 isp->isp_dev = dev; 518 519 /* 520 * Try and find firmware for this device. 521 */ 522 523 if (isp_get_firmware_p) { 524 int device = (int) pci_get_device(dev); 525 #ifdef ISP_TARGET_MODE 526 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 527 #else 528 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 529 #endif 530 } 531 532 /* 533 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 534 * are set. 535 */ 536 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 537 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 538 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 539 540 /* 541 * Make sure the Cache Line Size register is set sensibly. 542 */ 543 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 544 if (data != linesz) { 545 data = PCI_DFLT_LNSZ; 546 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 547 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 548 } 549 550 /* 551 * Make sure the Latency Timer is sane. 552 */ 553 data = pci_read_config(dev, PCIR_LATTIMER, 1); 554 if (data < PCI_DFLT_LTNCY) { 555 data = PCI_DFLT_LTNCY; 556 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 557 pci_write_config(dev, PCIR_LATTIMER, data, 1); 558 } 559 560 /* 561 * Make sure we've disabled the ROM. 562 */ 563 data = pci_read_config(dev, PCIR_ROMADDR, 4); 564 data &= ~1; 565 pci_write_config(dev, PCIR_ROMADDR, data, 4); 566 567 568 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 569 BUS_SPACE_MAXADDR, NULL, NULL, lim + 1, 570 255, lim, 0, &pcs->parent_dmat) != 0) { 571 device_printf(dev, "could not create master dma tag\n"); 572 free(isp->isp_param, M_DEVBUF); 573 free(pcs, M_DEVBUF); 574 return (ENXIO); 575 } 576 577 iqd = 0; 578 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 579 1, RF_ACTIVE | RF_SHAREABLE); 580 if (irq == NULL) { 581 device_printf(dev, "could not allocate interrupt\n"); 582 goto bad; 583 } 584 585 tval = 0; 586 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 587 "fwload_disable", &tval) == 0 && tval != 0) { 588 isp->isp_confopts |= ISP_CFG_NORELOAD; 589 } 590 tval = 0; 591 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 592 "ignore_nvram", &tval) == 0 && tval != 0) { 593 isp->isp_confopts |= ISP_CFG_NONVRAM; 594 } 595 tval = 0; 596 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 597 "fullduplex", &tval) == 0 && tval != 0) { 598 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 599 } 600 601 sptr = 0; 602 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 603 "topology", (const char **) &sptr) == 0 && sptr != 0) { 604 if (strcmp(sptr, "lport") == 0) { 605 isp->isp_confopts |= ISP_CFG_LPORT; 606 } else if (strcmp(sptr, "nport") == 0) { 607 isp->isp_confopts |= ISP_CFG_NPORT; 608 } else if (strcmp(sptr, "lport-only") == 0) { 609 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 610 } else if (strcmp(sptr, "nport-only") == 0) { 611 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 612 } 613 } 614 615 /* 616 * Because the resource_*_value functions can neither return 617 * 64 bit integer values, nor can they be directly coerced 618 * to interpret the right hand side of the assignment as 619 * you want them to interpret it, we have to force WWN 620 * hint replacement to specify WWN strings with a leading 621 * 'w' (e..g w50000000aaaa0001). Sigh. 622 */ 623 sptr = 0; 624 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 625 "portwwn", (const char **) &sptr); 626 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 627 char *eptr = 0; 628 isp->isp_osinfo.default_port_wwn = strtouq(sptr, &eptr, 16); 629 if (eptr < sptr + 16 || isp->isp_osinfo.default_port_wwn == 0) { 630 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 631 isp->isp_osinfo.default_port_wwn = 0; 632 } else { 633 isp->isp_confopts |= ISP_CFG_OWNWWN; 634 } 635 } 636 if (isp->isp_osinfo.default_port_wwn == 0) { 637 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 638 } 639 640 sptr = 0; 641 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 642 "nodewwn", (const char **) &sptr); 643 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 644 char *eptr = 0; 645 isp->isp_osinfo.default_node_wwn = strtouq(sptr, &eptr, 16); 646 if (eptr < sptr + 16 || isp->isp_osinfo.default_node_wwn == 0) { 647 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 648 isp->isp_osinfo.default_node_wwn = 0; 649 } else { 650 isp->isp_confopts |= ISP_CFG_OWNWWN; 651 } 652 } 653 if (isp->isp_osinfo.default_node_wwn == 0) { 654 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 655 } 656 657 isp_debug = 0; 658 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 659 "debug", &isp_debug); 660 661 /* Make sure the lock is set up. */ 662 mtx_init(&isp->isp_osinfo.lock, "isp", MTX_DEF); 663 locksetup++; 664 665 #ifdef ISP_SMPLOCK 666 #define INTR_FLAGS INTR_TYPE_CAM | INTR_MPSAFE | INTR_ENTROPY 667 #else 668 #define INTR_FLAGS INTR_TYPE_CAM | INTR_ENTROPY 669 #endif 670 if (bus_setup_intr(dev, irq, INTR_FLAGS, isp_pci_intr, isp, &pcs->ih)) { 671 device_printf(dev, "could not setup interrupt\n"); 672 goto bad; 673 } 674 675 /* 676 * Set up logging levels. 677 */ 678 if (isp_debug) { 679 isp->isp_dblev = isp_debug; 680 } else { 681 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 682 } 683 if (bootverbose) 684 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 685 686 /* 687 * Make sure we're in reset state. 688 */ 689 ISP_LOCK(isp); 690 isp_reset(isp); 691 if (isp->isp_state != ISP_RESETSTATE) { 692 ISP_UNLOCK(isp); 693 goto bad; 694 } 695 isp_init(isp); 696 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_INITSTATE) { 697 isp_uninit(isp); 698 ISP_UNLOCK(isp); 699 goto bad; 700 } 701 isp_attach(isp); 702 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_RUNSTATE) { 703 isp_uninit(isp); 704 ISP_UNLOCK(isp); 705 goto bad; 706 } 707 /* 708 * XXXX: Here is where we might unload the f/w module 709 * XXXX: (or decrease the reference count to it). 710 */ 711 ISP_UNLOCK(isp); 712 return (0); 713 714 bad: 715 716 if (pcs && pcs->ih) { 717 (void) bus_teardown_intr(dev, irq, pcs->ih); 718 } 719 720 if (locksetup && isp) { 721 mtx_destroy(&isp->isp_osinfo.lock); 722 } 723 724 if (irq) { 725 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 726 } 727 728 729 if (regs) { 730 (void) bus_release_resource(dev, rtp, rgd, regs); 731 } 732 733 if (pcs) { 734 if (pcs->pci_isp.isp_param) 735 free(pcs->pci_isp.isp_param, M_DEVBUF); 736 free(pcs, M_DEVBUF); 737 } 738 739 /* 740 * XXXX: Here is where we might unload the f/w module 741 * XXXX: (or decrease the reference count to it). 742 */ 743 return (ENXIO); 744 } 745 746 static void 747 isp_pci_intr(void *arg) 748 { 749 struct ispsoftc *isp = arg; 750 u_int16_t isr, sema, mbox; 751 752 ISP_LOCK(isp); 753 isp->isp_intcnt++; 754 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 755 isp->isp_intbogus++; 756 } else { 757 int iok = isp->isp_osinfo.intsok; 758 isp->isp_osinfo.intsok = 0; 759 isp_intr(isp, isr, sema, mbox); 760 isp->isp_osinfo.intsok = iok; 761 } 762 ISP_UNLOCK(isp); 763 } 764 765 766 #define IspVirt2Off(a, x) \ 767 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 768 _BLK_REG_SHFT] + ((x) & 0xff)) 769 770 #define BXR2(pcs, off) \ 771 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 772 #define BXW2(pcs, off, v) \ 773 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 774 775 776 static INLINE int 777 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 778 { 779 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 780 u_int16_t val0, val1; 781 int i = 0; 782 783 do { 784 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 785 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 786 } while (val0 != val1 && ++i < 1000); 787 if (val0 != val1) { 788 return (1); 789 } 790 *rp = val0; 791 return (0); 792 } 793 794 static int 795 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 796 u_int16_t *semap, u_int16_t *mbp) 797 { 798 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 799 u_int16_t isr, sema; 800 801 if (IS_2100(isp)) { 802 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 803 return (0); 804 } 805 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 806 return (0); 807 } 808 } else { 809 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 810 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 811 } 812 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 813 isr &= INT_PENDING_MASK(isp); 814 sema &= BIU_SEMA_LOCK; 815 if (isr == 0 && sema == 0) { 816 return (0); 817 } 818 *isrp = isr; 819 if ((*semap = sema) != 0) { 820 if (IS_2100(isp)) { 821 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 822 return (0); 823 } 824 } else { 825 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 826 } 827 } 828 return (1); 829 } 830 831 static int 832 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 833 u_int16_t *semap, u_int16_t *mbox0p) 834 { 835 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 836 u_int32_t r2hisr; 837 838 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 839 *isrp = 0; 840 return (0); 841 } 842 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 843 IspVirt2Off(pcs, BIU_R2HSTSLO)); 844 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 845 if ((r2hisr & BIU_R2HST_INTR) == 0) { 846 *isrp = 0; 847 return (0); 848 } 849 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 850 case ISPR2HST_ROM_MBX_OK: 851 case ISPR2HST_ROM_MBX_FAIL: 852 case ISPR2HST_MBX_OK: 853 case ISPR2HST_MBX_FAIL: 854 case ISPR2HST_ASYNC_EVENT: 855 case ISPR2HST_FPOST: 856 case ISPR2HST_FPOST_CTIO: 857 *isrp = r2hisr & 0xffff; 858 *mbox0p = (r2hisr >> 16); 859 *semap = 1; 860 return (1); 861 case ISPR2HST_RSPQ_UPDATE: 862 *isrp = r2hisr & 0xffff; 863 *mbox0p = 0; 864 *semap = 0; 865 return (1); 866 default: 867 return (0); 868 } 869 } 870 871 static u_int16_t 872 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 873 { 874 u_int16_t rv; 875 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 876 int oldconf = 0; 877 878 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 879 /* 880 * We will assume that someone has paused the RISC processor. 881 */ 882 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 883 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 884 oldconf | BIU_PCI_CONF1_SXP); 885 } 886 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 887 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 888 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 889 } 890 return (rv); 891 } 892 893 static void 894 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 895 { 896 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 897 int oldconf = 0; 898 899 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 900 /* 901 * We will assume that someone has paused the RISC processor. 902 */ 903 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 904 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 905 oldconf | BIU_PCI_CONF1_SXP); 906 } 907 BXW2(pcs, IspVirt2Off(isp, regoff), val); 908 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 909 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 910 } 911 } 912 913 static u_int16_t 914 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 915 { 916 u_int16_t rv, oc = 0; 917 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 918 919 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 920 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 921 u_int16_t tc; 922 /* 923 * We will assume that someone has paused the RISC processor. 924 */ 925 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 926 tc = oc & ~BIU_PCI1080_CONF1_DMA; 927 if (regoff & SXP_BANK1_SELECT) 928 tc |= BIU_PCI1080_CONF1_SXP1; 929 else 930 tc |= BIU_PCI1080_CONF1_SXP0; 931 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 932 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 933 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 934 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 935 oc | BIU_PCI1080_CONF1_DMA); 936 } 937 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 938 if (oc) { 939 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 940 } 941 return (rv); 942 } 943 944 static void 945 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 946 { 947 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 948 int oc = 0; 949 950 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 951 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 952 u_int16_t tc; 953 /* 954 * We will assume that someone has paused the RISC processor. 955 */ 956 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 957 tc = oc & ~BIU_PCI1080_CONF1_DMA; 958 if (regoff & SXP_BANK1_SELECT) 959 tc |= BIU_PCI1080_CONF1_SXP1; 960 else 961 tc |= BIU_PCI1080_CONF1_SXP0; 962 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 963 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 964 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 965 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 966 oc | BIU_PCI1080_CONF1_DMA); 967 } 968 BXW2(pcs, IspVirt2Off(isp, regoff), val); 969 if (oc) { 970 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 971 } 972 } 973 974 static void isp_map_rquest(void *, bus_dma_segment_t *, int, int); 975 static void isp_map_result(void *, bus_dma_segment_t *, int, int); 976 static void isp_map_fcscrt(void *, bus_dma_segment_t *, int, int); 977 978 struct imush { 979 struct ispsoftc *isp; 980 int error; 981 }; 982 983 static void 984 isp_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) 985 { 986 struct imush *imushp = (struct imush *) arg; 987 if (error) { 988 imushp->error = error; 989 } else { 990 imushp->isp->isp_rquest_dma = segs->ds_addr; 991 } 992 } 993 994 static void 995 isp_map_result(void *arg, bus_dma_segment_t *segs, int nseg, int error) 996 { 997 struct imush *imushp = (struct imush *) arg; 998 if (error) { 999 imushp->error = error; 1000 } else { 1001 imushp->isp->isp_result_dma = segs->ds_addr; 1002 } 1003 } 1004 1005 static void 1006 isp_map_fcscrt(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1007 { 1008 struct imush *imushp = (struct imush *) arg; 1009 if (error) { 1010 imushp->error = error; 1011 } else { 1012 fcparam *fcp = imushp->isp->isp_param; 1013 fcp->isp_scdma = segs->ds_addr; 1014 } 1015 } 1016 1017 static int 1018 isp_pci_mbxdma(struct ispsoftc *isp) 1019 { 1020 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1021 caddr_t base; 1022 u_int32_t len; 1023 int i, error; 1024 bus_size_t lim; 1025 struct imush im; 1026 1027 1028 /* 1029 * Already been here? If so, leave... 1030 */ 1031 if (isp->isp_rquest) { 1032 return (0); 1033 } 1034 1035 len = sizeof (XS_T **) * isp->isp_maxcmds; 1036 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1037 if (isp->isp_xflist == NULL) { 1038 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1039 return (1); 1040 } 1041 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 1042 pci->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1043 if (pci->dmaps == NULL) { 1044 isp_prt(isp, ISP_LOGERR, "can't alloc dma maps"); 1045 free(isp->isp_xflist, M_DEVBUF); 1046 return (1); 1047 } 1048 1049 if (IS_FC(isp) || IS_ULTRA2(isp)) 1050 lim = BUS_SPACE_MAXADDR + 1; 1051 else 1052 lim = BUS_SPACE_MAXADDR_24BIT + 1; 1053 1054 /* 1055 * Allocate and map the request, result queues, plus FC scratch area. 1056 */ 1057 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1058 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1059 if (IS_FC(isp)) { 1060 len += ISP2100_SCRLEN; 1061 } 1062 if (bus_dma_tag_create(pci->parent_dmat, PAGE_SIZE, lim, 1063 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, 1064 BUS_SPACE_MAXSIZE_32BIT, 0, &pci->cntrol_dmat) != 0) { 1065 isp_prt(isp, ISP_LOGERR, 1066 "cannot create a dma tag for control spaces"); 1067 free(isp->isp_xflist, M_DEVBUF); 1068 free(pci->dmaps, M_DEVBUF); 1069 return (1); 1070 } 1071 if (bus_dmamem_alloc(pci->cntrol_dmat, (void **)&base, 1072 BUS_DMA_NOWAIT, &pci->cntrol_dmap) != 0) { 1073 isp_prt(isp, ISP_LOGERR, 1074 "cannot allocate %d bytes of CCB memory", len); 1075 free(isp->isp_xflist, M_DEVBUF); 1076 free(pci->dmaps, M_DEVBUF); 1077 return (1); 1078 } 1079 1080 isp->isp_rquest = base; 1081 im.isp = isp; 1082 im.error = 0; 1083 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_rquest, 1084 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)), isp_map_rquest, &im, 0); 1085 if (im.error) { 1086 isp_prt(isp, ISP_LOGERR, 1087 "error %d loading dma map for DMA request queue", im.error); 1088 free(isp->isp_xflist, M_DEVBUF); 1089 free(pci->dmaps, M_DEVBUF); 1090 isp->isp_rquest = NULL; 1091 return (1); 1092 } 1093 isp->isp_result = base + ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1094 im.error = 0; 1095 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_result, 1096 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)), isp_map_result, &im, 0); 1097 if (im.error) { 1098 isp_prt(isp, ISP_LOGERR, 1099 "error %d loading dma map for DMA result queue", im.error); 1100 free(isp->isp_xflist, M_DEVBUF); 1101 free(pci->dmaps, M_DEVBUF); 1102 isp->isp_rquest = NULL; 1103 return (1); 1104 } 1105 1106 for (i = 0; i < isp->isp_maxcmds; i++) { 1107 error = bus_dmamap_create(pci->parent_dmat, 0, &pci->dmaps[i]); 1108 if (error) { 1109 isp_prt(isp, ISP_LOGERR, 1110 "error %d creating per-cmd DMA maps", error); 1111 free(isp->isp_xflist, M_DEVBUF); 1112 free(pci->dmaps, M_DEVBUF); 1113 isp->isp_rquest = NULL; 1114 return (1); 1115 } 1116 } 1117 1118 if (IS_FC(isp)) { 1119 fcparam *fcp = (fcparam *) isp->isp_param; 1120 fcp->isp_scratch = base + 1121 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)) + 1122 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1123 im.error = 0; 1124 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, 1125 fcp->isp_scratch, ISP2100_SCRLEN, isp_map_fcscrt, &im, 0); 1126 if (im.error) { 1127 isp_prt(isp, ISP_LOGERR, 1128 "error %d loading FC scratch area", im.error); 1129 free(isp->isp_xflist, M_DEVBUF); 1130 free(pci->dmaps, M_DEVBUF); 1131 isp->isp_rquest = NULL; 1132 return (1); 1133 } 1134 } 1135 return (0); 1136 } 1137 1138 typedef struct { 1139 struct ispsoftc *isp; 1140 void *cmd_token; 1141 void *rq; 1142 u_int16_t *nxtip; 1143 u_int16_t optr; 1144 u_int error; 1145 } mush_t; 1146 1147 #define MUSHERR_NOQENTRIES -2 1148 1149 #ifdef ISP_TARGET_MODE 1150 /* 1151 * We need to handle DMA for target mode differently from initiator mode. 1152 * 1153 * DMA mapping and construction and submission of CTIO Request Entries 1154 * and rendevous for completion are very tightly coupled because we start 1155 * out by knowing (per platform) how much data we have to move, but we 1156 * don't know, up front, how many DMA mapping segments will have to be used 1157 * cover that data, so we don't know how many CTIO Request Entries we 1158 * will end up using. Further, for performance reasons we may want to 1159 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1160 * 1161 * The standard vector still goes through isp_pci_dmasetup, but the callback 1162 * for the DMA mapping routines comes here instead with the whole transfer 1163 * mapped and a pointer to a partially filled in already allocated request 1164 * queue entry. We finish the job. 1165 */ 1166 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1167 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1168 1169 #define STATUS_WITH_DATA 1 1170 1171 static void 1172 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1173 { 1174 mush_t *mp; 1175 struct ccb_scsiio *csio; 1176 struct ispsoftc *isp; 1177 struct isp_pcisoftc *pci; 1178 bus_dmamap_t *dp; 1179 ct_entry_t *cto, *qe; 1180 u_int8_t scsi_status; 1181 u_int16_t curi, nxti, handle; 1182 u_int32_t sflags; 1183 int32_t resid; 1184 int nth_ctio, nctios, send_status; 1185 1186 mp = (mush_t *) arg; 1187 if (error) { 1188 mp->error = error; 1189 return; 1190 } 1191 1192 isp = mp->isp; 1193 csio = mp->cmd_token; 1194 cto = mp->rq; 1195 curi = isp->isp_reqidx; 1196 qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1197 1198 cto->ct_xfrlen = 0; 1199 cto->ct_seg_count = 0; 1200 cto->ct_header.rqs_entry_count = 1; 1201 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1202 1203 if (nseg == 0) { 1204 cto->ct_header.rqs_seqno = 1; 1205 isp_prt(isp, ISP_LOGTDEBUG1, 1206 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1207 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1208 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1209 cto->ct_scsi_status, cto->ct_resid); 1210 ISP_TDQE(isp, "tdma_mk[no data]", curi, cto); 1211 isp_put_ctio(isp, cto, qe); 1212 return; 1213 } 1214 1215 nctios = nseg / ISP_RQDSEG; 1216 if (nseg % ISP_RQDSEG) { 1217 nctios++; 1218 } 1219 1220 /* 1221 * Save syshandle, and potentially any SCSI status, which we'll 1222 * reinsert on the last CTIO we're going to send. 1223 */ 1224 1225 handle = cto->ct_syshandle; 1226 cto->ct_syshandle = 0; 1227 cto->ct_header.rqs_seqno = 0; 1228 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1229 1230 if (send_status) { 1231 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1232 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1233 /* 1234 * Preserve residual. 1235 */ 1236 resid = cto->ct_resid; 1237 1238 /* 1239 * Save actual SCSI status. 1240 */ 1241 scsi_status = cto->ct_scsi_status; 1242 1243 #ifndef STATUS_WITH_DATA 1244 sflags |= CT_NO_DATA; 1245 /* 1246 * We can't do a status at the same time as a data CTIO, so 1247 * we need to synthesize an extra CTIO at this level. 1248 */ 1249 nctios++; 1250 #endif 1251 } else { 1252 sflags = scsi_status = resid = 0; 1253 } 1254 1255 cto->ct_resid = 0; 1256 cto->ct_scsi_status = 0; 1257 1258 pci = (struct isp_pcisoftc *)isp; 1259 dp = &pci->dmaps[isp_handle_index(handle)]; 1260 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1261 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1262 } else { 1263 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1264 } 1265 1266 nxti = *mp->nxtip; 1267 1268 for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { 1269 int seglim; 1270 1271 seglim = nseg; 1272 if (seglim) { 1273 int seg; 1274 1275 if (seglim > ISP_RQDSEG) 1276 seglim = ISP_RQDSEG; 1277 1278 for (seg = 0; seg < seglim; seg++, nseg--) { 1279 /* 1280 * Unlike normal initiator commands, we don't 1281 * do any swizzling here. 1282 */ 1283 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1284 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1285 cto->ct_xfrlen += dm_segs->ds_len; 1286 dm_segs++; 1287 } 1288 cto->ct_seg_count = seg; 1289 } else { 1290 /* 1291 * This case should only happen when we're sending an 1292 * extra CTIO with final status. 1293 */ 1294 if (send_status == 0) { 1295 isp_prt(isp, ISP_LOGWARN, 1296 "tdma_mk ran out of segments"); 1297 mp->error = EINVAL; 1298 return; 1299 } 1300 } 1301 1302 /* 1303 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1304 * ct_tagtype, and ct_timeout have been carried over 1305 * unchanged from what our caller had set. 1306 * 1307 * The dataseg fields and the seg_count fields we just got 1308 * through setting. The data direction we've preserved all 1309 * along and only clear it if we're now sending status. 1310 */ 1311 1312 if (nth_ctio == nctios - 1) { 1313 /* 1314 * We're the last in a sequence of CTIOs, so mark 1315 * this CTIO and save the handle to the CCB such that 1316 * when this CTIO completes we can free dma resources 1317 * and do whatever else we need to do to finish the 1318 * rest of the command. We *don't* give this to the 1319 * firmware to work on- the caller will do that. 1320 */ 1321 1322 cto->ct_syshandle = handle; 1323 cto->ct_header.rqs_seqno = 1; 1324 1325 if (send_status) { 1326 cto->ct_scsi_status = scsi_status; 1327 cto->ct_flags |= sflags; 1328 cto->ct_resid = resid; 1329 } 1330 if (send_status) { 1331 isp_prt(isp, ISP_LOGTDEBUG1, 1332 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 1333 "scsi status %x resid %d", 1334 cto->ct_fwhandle, csio->ccb_h.target_lun, 1335 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 1336 cto->ct_scsi_status, cto->ct_resid); 1337 } else { 1338 isp_prt(isp, ISP_LOGTDEBUG1, 1339 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 1340 cto->ct_fwhandle, csio->ccb_h.target_lun, 1341 cto->ct_iid, cto->ct_tag_val, 1342 cto->ct_flags); 1343 } 1344 isp_put_ctio(isp, cto, qe); 1345 ISP_TDQE(isp, "last tdma_mk", curi, cto); 1346 if (nctios > 1) { 1347 MEMORYBARRIER(isp, SYNC_REQUEST, 1348 curi, QENTRY_LEN); 1349 } 1350 } else { 1351 ct_entry_t *oqe = qe; 1352 1353 /* 1354 * Make sure syshandle fields are clean 1355 */ 1356 cto->ct_syshandle = 0; 1357 cto->ct_header.rqs_seqno = 0; 1358 1359 isp_prt(isp, ISP_LOGTDEBUG1, 1360 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 1361 cto->ct_fwhandle, csio->ccb_h.target_lun, 1362 cto->ct_iid, cto->ct_flags); 1363 1364 /* 1365 * Get a new CTIO 1366 */ 1367 qe = (ct_entry_t *) 1368 ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1369 nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); 1370 if (nxti == mp->optr) { 1371 isp_prt(isp, ISP_LOGTDEBUG0, 1372 "Queue Overflow in tdma_mk"); 1373 mp->error = MUSHERR_NOQENTRIES; 1374 return; 1375 } 1376 1377 /* 1378 * Now that we're done with the old CTIO, 1379 * flush it out to the request queue. 1380 */ 1381 ISP_TDQE(isp, "dma_tgt_fc", curi, cto); 1382 isp_put_ctio(isp, cto, oqe); 1383 if (nth_ctio != 0) { 1384 MEMORYBARRIER(isp, SYNC_REQUEST, curi, 1385 QENTRY_LEN); 1386 } 1387 curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); 1388 1389 /* 1390 * Reset some fields in the CTIO so we can reuse 1391 * for the next one we'll flush to the request 1392 * queue. 1393 */ 1394 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1395 cto->ct_header.rqs_entry_count = 1; 1396 cto->ct_header.rqs_flags = 0; 1397 cto->ct_status = 0; 1398 cto->ct_scsi_status = 0; 1399 cto->ct_xfrlen = 0; 1400 cto->ct_resid = 0; 1401 cto->ct_seg_count = 0; 1402 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1403 } 1404 } 1405 *mp->nxtip = nxti; 1406 } 1407 1408 static void 1409 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1410 { 1411 mush_t *mp; 1412 u_int8_t sense[QLTM_SENSELEN]; 1413 struct ccb_scsiio *csio; 1414 struct ispsoftc *isp; 1415 struct isp_pcisoftc *pci; 1416 bus_dmamap_t *dp; 1417 ct2_entry_t *cto, *qe; 1418 u_int16_t scsi_status, send_status, send_sense, handle; 1419 u_int16_t curi, nxti; 1420 int32_t resid; 1421 int nth_ctio, nctios; 1422 1423 mp = (mush_t *) arg; 1424 if (error) { 1425 mp->error = error; 1426 return; 1427 } 1428 1429 isp = mp->isp; 1430 csio = mp->cmd_token; 1431 cto = mp->rq; 1432 curi = isp->isp_reqidx; 1433 qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1434 1435 if (nseg == 0) { 1436 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1437 isp_prt(isp, ISP_LOGWARN, 1438 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1439 "set (0x%x)", cto->ct_flags); 1440 mp->error = EINVAL; 1441 return; 1442 } 1443 cto->ct_header.rqs_entry_count = 1; 1444 cto->ct_header.rqs_seqno = 1; 1445 /* ct_syshandle contains the handle set by caller */ 1446 /* 1447 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1448 * flags to NO DATA and clear relative offset flags. 1449 * We preserve the ct_resid and the response area. 1450 */ 1451 cto->ct_flags |= CT2_NO_DATA; 1452 if (cto->ct_resid > 0) 1453 cto->rsp.m1.ct_scsi_status |= CT2_DATA_UNDER; 1454 else if (cto->ct_resid < 0) 1455 cto->rsp.m1.ct_scsi_status |= CT2_DATA_OVER; 1456 cto->ct_seg_count = 0; 1457 cto->ct_reloff = 0; 1458 isp_prt(isp, ISP_LOGTDEBUG1, 1459 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1460 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1461 cto->ct_iid, cto->ct_flags, cto->ct_status, 1462 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1463 isp_put_ctio2(isp, cto, qe); 1464 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe); 1465 return; 1466 } 1467 1468 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1469 isp_prt(isp, ISP_LOGWARN, 1470 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1471 "(0x%x)", cto->ct_flags); 1472 mp->error = EINVAL; 1473 return; 1474 } 1475 1476 1477 nctios = nseg / ISP_RQDSEG_T2; 1478 if (nseg % ISP_RQDSEG_T2) { 1479 nctios++; 1480 } 1481 1482 /* 1483 * Save the handle, status, reloff, and residual. We'll reinsert the 1484 * handle into the last CTIO2 we're going to send, and reinsert status 1485 * and residual (and possibly sense data) if that's to be sent as well. 1486 * 1487 * We preserve ct_reloff and adjust it for each data CTIO2 we send past 1488 * the first one. This is needed so that the FCP DATA IUs being sent 1489 * out have the correct offset (they can arrive at the other end out 1490 * of order). 1491 */ 1492 1493 handle = cto->ct_syshandle; 1494 cto->ct_syshandle = 0; 1495 send_status = (cto->ct_flags & CT2_SENDSTATUS) != 0; 1496 1497 if (send_status) { 1498 cto->ct_flags &= ~(CT2_SENDSTATUS|CT2_CCINCR); 1499 1500 /* 1501 * Preserve residual. 1502 */ 1503 resid = cto->ct_resid; 1504 1505 /* 1506 * Save actual SCSI status. We'll reinsert the 1507 * CT2_SNSLEN_VALID later if appropriate. 1508 */ 1509 scsi_status = cto->rsp.m0.ct_scsi_status & 0xff; 1510 send_sense = cto->rsp.m0.ct_scsi_status & CT2_SNSLEN_VALID; 1511 1512 /* 1513 * If we're sending status and have a CHECK CONDTION and 1514 * have sense data, we send one more CTIO2 with just the 1515 * status and sense data. The upper layers have stashed 1516 * the sense data in the dataseg structure for us. 1517 */ 1518 1519 if ((scsi_status & 0xf) == SCSI_STATUS_CHECK_COND && 1520 send_sense) { 1521 bcopy(cto->rsp.m0.ct_dataseg, sense, QLTM_SENSELEN); 1522 nctios++; 1523 } 1524 } else { 1525 scsi_status = send_sense = resid = 0; 1526 } 1527 1528 cto->ct_resid = 0; 1529 cto->rsp.m0.ct_scsi_status = 0; 1530 MEMZERO(&cto->rsp, sizeof (cto->rsp)); 1531 1532 pci = (struct isp_pcisoftc *)isp; 1533 dp = &pci->dmaps[isp_handle_index(handle)]; 1534 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1535 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1536 } else { 1537 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1538 } 1539 1540 nxti = *mp->nxtip; 1541 1542 for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { 1543 u_int32_t oxfrlen; 1544 int seglim; 1545 1546 seglim = nseg; 1547 if (seglim) { 1548 int seg; 1549 if (seglim > ISP_RQDSEG_T2) 1550 seglim = ISP_RQDSEG_T2; 1551 for (seg = 0; seg < seglim; seg++) { 1552 cto->rsp.m0.ct_dataseg[seg].ds_base = 1553 dm_segs->ds_addr; 1554 cto->rsp.m0.ct_dataseg[seg].ds_count = 1555 dm_segs->ds_len; 1556 cto->rsp.m0.ct_xfrlen += dm_segs->ds_len; 1557 dm_segs++; 1558 } 1559 cto->ct_seg_count = seg; 1560 oxfrlen = cto->rsp.m0.ct_xfrlen; 1561 } else { 1562 /* 1563 * This case should only happen when we're sending a 1564 * synthesized MODE1 final status with sense data. 1565 */ 1566 if (send_sense == 0) { 1567 isp_prt(isp, ISP_LOGWARN, 1568 "dma2_tgt_fc ran out of segments, " 1569 "no SENSE DATA"); 1570 mp->error = EINVAL; 1571 return; 1572 } 1573 oxfrlen = 0; 1574 } 1575 1576 1577 /* 1578 * At this point, the fields ct_lun, ct_iid, ct_rxid, 1579 * ct_timeout have been carried over unchanged from what 1580 * our caller had set. 1581 * 1582 * The field ct_reloff is either what the caller set, or 1583 * what we've added to below. 1584 * 1585 * The dataseg fields and the seg_count fields we just got 1586 * through setting. The data direction we've preserved all 1587 * along and only clear it if we're sending a MODE1 status 1588 * as the last CTIO. 1589 * 1590 */ 1591 1592 if (nth_ctio == nctios - 1) { 1593 /* 1594 * We're the last in a sequence of CTIO2s, so mark this 1595 * CTIO2 and save the handle to the CCB such that when 1596 * this CTIO2 completes we can free dma resources and 1597 * do whatever else we need to do to finish the rest 1598 * of the command. 1599 */ 1600 1601 cto->ct_syshandle = handle; 1602 cto->ct_header.rqs_seqno = 1; 1603 1604 if (send_status) { 1605 /* 1606 * Get 'real' residual and set flags based 1607 * on it. 1608 */ 1609 cto->ct_resid = resid; 1610 if (send_sense) { 1611 MEMCPY(cto->rsp.m1.ct_resp, sense, 1612 QLTM_SENSELEN); 1613 cto->rsp.m1.ct_senselen = 1614 QLTM_SENSELEN; 1615 scsi_status |= CT2_SNSLEN_VALID; 1616 cto->rsp.m1.ct_scsi_status = 1617 scsi_status; 1618 cto->ct_flags &= CT2_FLAG_MMASK; 1619 cto->ct_flags |= CT2_FLAG_MODE1 | 1620 CT2_NO_DATA | CT2_SENDSTATUS | 1621 CT2_CCINCR; 1622 if (cto->ct_resid > 0) 1623 cto->rsp.m1.ct_scsi_status |= 1624 CT2_DATA_UNDER; 1625 else if (cto->ct_resid < 0) 1626 cto->rsp.m1.ct_scsi_status |= 1627 CT2_DATA_OVER; 1628 } else { 1629 cto->rsp.m0.ct_scsi_status = 1630 scsi_status; 1631 cto->ct_flags |= 1632 CT2_SENDSTATUS | CT2_CCINCR; 1633 if (cto->ct_resid > 0) 1634 cto->rsp.m0.ct_scsi_status |= 1635 CT2_DATA_UNDER; 1636 else if (cto->ct_resid < 0) 1637 cto->rsp.m0.ct_scsi_status |= 1638 CT2_DATA_OVER; 1639 } 1640 } 1641 isp_prt(isp, ISP_LOGTDEBUG1, 1642 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x" 1643 " ssts 0x%x res %d", cto->ct_rxid, 1644 csio->ccb_h.target_lun, (int) cto->ct_iid, 1645 cto->ct_flags, cto->ct_status, 1646 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1647 isp_put_ctio2(isp, cto, qe); 1648 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe); 1649 if (nctios > 1) { 1650 MEMORYBARRIER(isp, SYNC_REQUEST, 1651 curi, QENTRY_LEN); 1652 } 1653 } else { 1654 ct2_entry_t *oqe = qe; 1655 1656 /* 1657 * Make sure handle fields are clean 1658 */ 1659 cto->ct_syshandle = 0; 1660 cto->ct_header.rqs_seqno = 0; 1661 isp_prt(isp, ISP_LOGTDEBUG1, 1662 "CTIO2[%x] lun %d->iid%d flgs 0x%x", 1663 cto->ct_rxid, csio->ccb_h.target_lun, 1664 (int) cto->ct_iid, cto->ct_flags); 1665 /* 1666 * Get a new CTIO2 entry from the request queue. 1667 */ 1668 qe = (ct2_entry_t *) 1669 ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1670 nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); 1671 if (nxti == mp->optr) { 1672 isp_prt(isp, ISP_LOGWARN, 1673 "Queue Overflow in dma2_tgt_fc"); 1674 mp->error = MUSHERR_NOQENTRIES; 1675 return; 1676 } 1677 1678 /* 1679 * Now that we're done with the old CTIO2, 1680 * flush it out to the request queue. 1681 */ 1682 ISP_TDQE(isp, "tdma_mkfc", curi, cto); 1683 isp_put_ctio2(isp, cto, oqe); 1684 if (nth_ctio != 0) { 1685 MEMORYBARRIER(isp, SYNC_REQUEST, curi, 1686 QENTRY_LEN); 1687 } 1688 curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); 1689 1690 /* 1691 * Reset some fields in the CTIO2 so we can reuse 1692 * for the next one we'll flush to the request 1693 * queue. 1694 */ 1695 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO2; 1696 cto->ct_header.rqs_entry_count = 1; 1697 cto->ct_header.rqs_flags = 0; 1698 cto->ct_status = 0; 1699 cto->ct_resid = 0; 1700 cto->ct_seg_count = 0; 1701 /* 1702 * Adjust the new relative offset by the amount which 1703 * is recorded in the data segment of the old CTIO2 we 1704 * just finished filling out. 1705 */ 1706 cto->ct_reloff += oxfrlen; 1707 MEMZERO(&cto->rsp, sizeof (cto->rsp)); 1708 } 1709 } 1710 *mp->nxtip = nxti; 1711 } 1712 #endif 1713 1714 static void dma2(void *, bus_dma_segment_t *, int, int); 1715 1716 static void 1717 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1718 { 1719 mush_t *mp; 1720 struct ispsoftc *isp; 1721 struct ccb_scsiio *csio; 1722 struct isp_pcisoftc *pci; 1723 bus_dmamap_t *dp; 1724 bus_dma_segment_t *eseg; 1725 ispreq_t *rq; 1726 int seglim, datalen; 1727 u_int16_t nxti; 1728 1729 mp = (mush_t *) arg; 1730 if (error) { 1731 mp->error = error; 1732 return; 1733 } 1734 1735 if (nseg < 1) { 1736 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1737 mp->error = EFAULT; 1738 return; 1739 } 1740 csio = mp->cmd_token; 1741 isp = mp->isp; 1742 rq = mp->rq; 1743 pci = (struct isp_pcisoftc *)mp->isp; 1744 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1745 nxti = *mp->nxtip; 1746 1747 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1748 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1749 } else { 1750 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1751 } 1752 1753 datalen = XS_XFRLEN(csio); 1754 1755 /* 1756 * We're passed an initial partially filled in entry that 1757 * has most fields filled in except for data transfer 1758 * related values. 1759 * 1760 * Our job is to fill in the initial request queue entry and 1761 * then to start allocating and filling in continuation entries 1762 * until we've covered the entire transfer. 1763 */ 1764 1765 if (IS_FC(isp)) { 1766 seglim = ISP_RQDSEG_T2; 1767 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1768 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1769 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1770 } else { 1771 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1772 } 1773 } else { 1774 if (csio->cdb_len > 12) { 1775 seglim = 0; 1776 } else { 1777 seglim = ISP_RQDSEG; 1778 } 1779 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1780 rq->req_flags |= REQFLAG_DATA_IN; 1781 } else { 1782 rq->req_flags |= REQFLAG_DATA_OUT; 1783 } 1784 } 1785 1786 eseg = dm_segs + nseg; 1787 1788 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1789 if (IS_FC(isp)) { 1790 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1791 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1792 dm_segs->ds_addr; 1793 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1794 dm_segs->ds_len; 1795 } else { 1796 rq->req_dataseg[rq->req_seg_count].ds_base = 1797 dm_segs->ds_addr; 1798 rq->req_dataseg[rq->req_seg_count].ds_count = 1799 dm_segs->ds_len; 1800 } 1801 datalen -= dm_segs->ds_len; 1802 rq->req_seg_count++; 1803 dm_segs++; 1804 } 1805 1806 while (datalen > 0 && dm_segs != eseg) { 1807 u_int16_t onxti; 1808 ispcontreq_t local, *crq = &local, *cqe; 1809 1810 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1811 onxti = nxti; 1812 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1813 if (nxti == mp->optr) { 1814 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1815 mp->error = MUSHERR_NOQENTRIES; 1816 return; 1817 } 1818 rq->req_header.rqs_entry_count++; 1819 MEMZERO((void *)crq, sizeof (*crq)); 1820 crq->req_header.rqs_entry_count = 1; 1821 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1822 1823 seglim = 0; 1824 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1825 crq->req_dataseg[seglim].ds_base = 1826 dm_segs->ds_addr; 1827 crq->req_dataseg[seglim].ds_count = 1828 dm_segs->ds_len; 1829 rq->req_seg_count++; 1830 dm_segs++; 1831 seglim++; 1832 datalen -= dm_segs->ds_len; 1833 } 1834 isp_put_cont_req(isp, crq, cqe); 1835 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1836 } 1837 *mp->nxtip = nxti; 1838 } 1839 1840 static int 1841 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1842 u_int16_t *nxtip, u_int16_t optr) 1843 { 1844 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1845 ispreq_t *qep; 1846 bus_dmamap_t *dp = NULL; 1847 mush_t mush, *mp; 1848 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1849 1850 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); 1851 #ifdef ISP_TARGET_MODE 1852 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1853 if (IS_FC(isp)) { 1854 eptr = tdma_mkfc; 1855 } else { 1856 eptr = tdma_mk; 1857 } 1858 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1859 (csio->dxfer_len == 0)) { 1860 mp = &mush; 1861 mp->isp = isp; 1862 mp->cmd_token = csio; 1863 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 1864 mp->nxtip = nxtip; 1865 mp->optr = optr; 1866 mp->error = 0; 1867 (*eptr)(mp, NULL, 0, 0); 1868 goto mbxsync; 1869 } 1870 } else 1871 #endif 1872 eptr = dma2; 1873 1874 1875 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1876 (csio->dxfer_len == 0)) { 1877 rq->req_seg_count = 1; 1878 goto mbxsync; 1879 } 1880 1881 /* 1882 * Do a virtual grapevine step to collect info for 1883 * the callback dma allocation that we have to use... 1884 */ 1885 mp = &mush; 1886 mp->isp = isp; 1887 mp->cmd_token = csio; 1888 mp->rq = rq; 1889 mp->nxtip = nxtip; 1890 mp->optr = optr; 1891 mp->error = 0; 1892 1893 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1894 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1895 int error, s; 1896 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1897 s = splsoftvm(); 1898 error = bus_dmamap_load(pci->parent_dmat, *dp, 1899 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1900 if (error == EINPROGRESS) { 1901 bus_dmamap_unload(pci->parent_dmat, *dp); 1902 mp->error = EINVAL; 1903 isp_prt(isp, ISP_LOGERR, 1904 "deferred dma allocation not supported"); 1905 } else if (error && mp->error == 0) { 1906 #ifdef DIAGNOSTIC 1907 isp_prt(isp, ISP_LOGERR, 1908 "error %d in dma mapping code", error); 1909 #endif 1910 mp->error = error; 1911 } 1912 splx(s); 1913 } else { 1914 /* Pointer to physical buffer */ 1915 struct bus_dma_segment seg; 1916 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1917 seg.ds_len = csio->dxfer_len; 1918 (*eptr)(mp, &seg, 1, 0); 1919 } 1920 } else { 1921 struct bus_dma_segment *segs; 1922 1923 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1924 isp_prt(isp, ISP_LOGERR, 1925 "Physical segment pointers unsupported"); 1926 mp->error = EINVAL; 1927 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1928 isp_prt(isp, ISP_LOGERR, 1929 "Virtual segment addresses unsupported"); 1930 mp->error = EINVAL; 1931 } else { 1932 /* Just use the segments provided */ 1933 segs = (struct bus_dma_segment *) csio->data_ptr; 1934 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1935 } 1936 } 1937 if (mp->error) { 1938 int retval = CMD_COMPLETE; 1939 if (mp->error == MUSHERR_NOQENTRIES) { 1940 retval = CMD_EAGAIN; 1941 } else if (mp->error == EFBIG) { 1942 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1943 } else if (mp->error == EINVAL) { 1944 XS_SETERR(csio, CAM_REQ_INVALID); 1945 } else { 1946 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1947 } 1948 return (retval); 1949 } 1950 mbxsync: 1951 switch (rq->req_header.rqs_entry_type) { 1952 case RQSTYPE_REQUEST: 1953 isp_put_request(isp, rq, qep); 1954 break; 1955 case RQSTYPE_CMDONLY: 1956 isp_put_extended_request(isp, (ispextreq_t *)rq, 1957 (ispextreq_t *)qep); 1958 break; 1959 case RQSTYPE_T2RQS: 1960 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1961 break; 1962 } 1963 return (CMD_QUEUED); 1964 } 1965 1966 static void 1967 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1968 { 1969 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1970 bus_dmamap_t *dp = &pci->dmaps[isp_handle_index(handle)]; 1971 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1972 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTREAD); 1973 } else { 1974 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTWRITE); 1975 } 1976 bus_dmamap_unload(pci->parent_dmat, *dp); 1977 } 1978 1979 1980 static void 1981 isp_pci_reset1(struct ispsoftc *isp) 1982 { 1983 /* Make sure the BIOS is disabled */ 1984 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1985 /* and enable interrupts */ 1986 ENABLE_INTS(isp); 1987 } 1988 1989 static void 1990 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1991 { 1992 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1993 if (msg) 1994 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1995 else 1996 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1997 if (IS_SCSI(isp)) 1998 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1999 else 2000 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 2001 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 2002 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 2003 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 2004 2005 2006 if (IS_SCSI(isp)) { 2007 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 2008 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 2009 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 2010 ISP_READ(isp, CDMA_FIFO_STS)); 2011 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 2012 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 2013 ISP_READ(isp, DDMA_FIFO_STS)); 2014 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 2015 ISP_READ(isp, SXP_INTERRUPT), 2016 ISP_READ(isp, SXP_GROSS_ERR), 2017 ISP_READ(isp, SXP_PINS_CTRL)); 2018 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2019 } 2020 printf(" mbox regs: %x %x %x %x %x\n", 2021 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2022 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2023 ISP_READ(isp, OUTMAILBOX4)); 2024 printf(" PCI Status Command/Status=%x\n", 2025 pci_read_config(pci->pci_dev, PCIR_COMMAND, 1)); 2026 } 2027