1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /* 27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 28 * FreeBSD Version. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 #include <sys/malloc.h> 47 #include <sys/uio.h> 48 49 #ifdef __sparc64__ 50 #include <dev/ofw/openfirm.h> 51 #include <machine/ofw_machdep.h> 52 #endif 53 54 #include <dev/isp/isp_freebsd.h> 55 56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 62 static int isp_pci_rd_isr(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *); 63 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *); 64 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *); 65 static int isp_pci_mbxdma(ispsoftc_t *); 66 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 67 68 69 static void isp_pci_reset0(ispsoftc_t *); 70 static void isp_pci_reset1(ispsoftc_t *); 71 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 72 73 static struct ispmdvec mdvec = { 74 isp_pci_rd_isr, 75 isp_pci_rd_reg, 76 isp_pci_wr_reg, 77 isp_pci_mbxdma, 78 isp_pci_dmasetup, 79 isp_common_dmateardown, 80 isp_pci_reset0, 81 isp_pci_reset1, 82 isp_pci_dumpregs, 83 NULL, 84 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 85 }; 86 87 static struct ispmdvec mdvec_1080 = { 88 isp_pci_rd_isr, 89 isp_pci_rd_reg_1080, 90 isp_pci_wr_reg_1080, 91 isp_pci_mbxdma, 92 isp_pci_dmasetup, 93 isp_common_dmateardown, 94 isp_pci_reset0, 95 isp_pci_reset1, 96 isp_pci_dumpregs, 97 NULL, 98 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 99 }; 100 101 static struct ispmdvec mdvec_12160 = { 102 isp_pci_rd_isr, 103 isp_pci_rd_reg_1080, 104 isp_pci_wr_reg_1080, 105 isp_pci_mbxdma, 106 isp_pci_dmasetup, 107 isp_common_dmateardown, 108 isp_pci_reset0, 109 isp_pci_reset1, 110 isp_pci_dumpregs, 111 NULL, 112 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 113 }; 114 115 static struct ispmdvec mdvec_2100 = { 116 isp_pci_rd_isr, 117 isp_pci_rd_reg, 118 isp_pci_wr_reg, 119 isp_pci_mbxdma, 120 isp_pci_dmasetup, 121 isp_common_dmateardown, 122 isp_pci_reset0, 123 isp_pci_reset1, 124 isp_pci_dumpregs 125 }; 126 127 static struct ispmdvec mdvec_2200 = { 128 isp_pci_rd_isr, 129 isp_pci_rd_reg, 130 isp_pci_wr_reg, 131 isp_pci_mbxdma, 132 isp_pci_dmasetup, 133 isp_common_dmateardown, 134 isp_pci_reset0, 135 isp_pci_reset1, 136 isp_pci_dumpregs 137 }; 138 139 static struct ispmdvec mdvec_2300 = { 140 isp_pci_rd_isr_2300, 141 isp_pci_rd_reg, 142 isp_pci_wr_reg, 143 isp_pci_mbxdma, 144 isp_pci_dmasetup, 145 isp_common_dmateardown, 146 isp_pci_reset0, 147 isp_pci_reset1, 148 isp_pci_dumpregs 149 }; 150 151 static struct ispmdvec mdvec_2400 = { 152 isp_pci_rd_isr_2400, 153 isp_pci_rd_reg_2400, 154 isp_pci_wr_reg_2400, 155 isp_pci_mbxdma, 156 isp_pci_dmasetup, 157 isp_common_dmateardown, 158 isp_pci_reset0, 159 isp_pci_reset1, 160 NULL 161 }; 162 163 static struct ispmdvec mdvec_2500 = { 164 isp_pci_rd_isr_2400, 165 isp_pci_rd_reg_2400, 166 isp_pci_wr_reg_2400, 167 isp_pci_mbxdma, 168 isp_pci_dmasetup, 169 isp_common_dmateardown, 170 isp_pci_reset0, 171 isp_pci_reset1, 172 NULL 173 }; 174 175 #ifndef PCIM_CMD_INVEN 176 #define PCIM_CMD_INVEN 0x10 177 #endif 178 #ifndef PCIM_CMD_BUSMASTEREN 179 #define PCIM_CMD_BUSMASTEREN 0x0004 180 #endif 181 #ifndef PCIM_CMD_PERRESPEN 182 #define PCIM_CMD_PERRESPEN 0x0040 183 #endif 184 #ifndef PCIM_CMD_SEREN 185 #define PCIM_CMD_SEREN 0x0100 186 #endif 187 #ifndef PCIM_CMD_INTX_DISABLE 188 #define PCIM_CMD_INTX_DISABLE 0x0400 189 #endif 190 191 #ifndef PCIR_COMMAND 192 #define PCIR_COMMAND 0x04 193 #endif 194 195 #ifndef PCIR_CACHELNSZ 196 #define PCIR_CACHELNSZ 0x0c 197 #endif 198 199 #ifndef PCIR_LATTIMER 200 #define PCIR_LATTIMER 0x0d 201 #endif 202 203 #ifndef PCIR_ROMADDR 204 #define PCIR_ROMADDR 0x30 205 #endif 206 207 #ifndef PCI_VENDOR_QLOGIC 208 #define PCI_VENDOR_QLOGIC 0x1077 209 #endif 210 211 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 212 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 213 #endif 214 215 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 216 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 217 #endif 218 219 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 220 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 221 #endif 222 223 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 224 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 225 #endif 226 227 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 228 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 229 #endif 230 231 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 232 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 233 #endif 234 235 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 236 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 237 #endif 238 239 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 240 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 241 #endif 242 243 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 244 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 245 #endif 246 247 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 248 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 249 #endif 250 251 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 252 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 253 #endif 254 255 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 256 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 257 #endif 258 259 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 260 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 261 #endif 262 263 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 264 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 265 #endif 266 267 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 268 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 269 #endif 270 271 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 272 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 273 #endif 274 275 #ifndef PCI_PRODUCT_QLOGIC_ISP5432 276 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 277 #endif 278 279 #define PCI_QLOGIC_ISP5432 \ 280 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP1020 \ 283 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP1080 \ 286 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define PCI_QLOGIC_ISP10160 \ 289 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 290 291 #define PCI_QLOGIC_ISP12160 \ 292 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 293 294 #define PCI_QLOGIC_ISP1240 \ 295 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 296 297 #define PCI_QLOGIC_ISP1280 \ 298 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 299 300 #define PCI_QLOGIC_ISP2100 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 302 303 #define PCI_QLOGIC_ISP2200 \ 304 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 305 306 #define PCI_QLOGIC_ISP2300 \ 307 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 308 309 #define PCI_QLOGIC_ISP2312 \ 310 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 311 312 #define PCI_QLOGIC_ISP2322 \ 313 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 314 315 #define PCI_QLOGIC_ISP2422 \ 316 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 317 318 #define PCI_QLOGIC_ISP2432 \ 319 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 320 321 #define PCI_QLOGIC_ISP2532 \ 322 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 323 324 #define PCI_QLOGIC_ISP6312 \ 325 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 326 327 #define PCI_QLOGIC_ISP6322 \ 328 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 329 330 /* 331 * Odd case for some AMI raid cards... We need to *not* attach to this. 332 */ 333 #define AMI_RAID_SUBVENDOR_ID 0x101e 334 335 #define IO_MAP_REG 0x10 336 #define MEM_MAP_REG 0x14 337 338 #define PCI_DFLT_LTNCY 0x40 339 #define PCI_DFLT_LNSZ 0x10 340 341 static int isp_pci_probe (device_t); 342 static int isp_pci_attach (device_t); 343 static int isp_pci_detach (device_t); 344 345 346 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 347 struct isp_pcisoftc { 348 ispsoftc_t pci_isp; 349 device_t pci_dev; 350 struct resource * regs; 351 void * irq; 352 int iqd; 353 int rtp; 354 int rgd; 355 void * ih; 356 int16_t pci_poff[_NREG_BLKS]; 357 bus_dma_tag_t dmat; 358 int msicount; 359 }; 360 361 362 static device_method_t isp_pci_methods[] = { 363 /* Device interface */ 364 DEVMETHOD(device_probe, isp_pci_probe), 365 DEVMETHOD(device_attach, isp_pci_attach), 366 DEVMETHOD(device_detach, isp_pci_detach), 367 { 0, 0 } 368 }; 369 370 static driver_t isp_pci_driver = { 371 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 372 }; 373 static devclass_t isp_devclass; 374 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 375 MODULE_DEPEND(isp, cam, 1, 1, 1); 376 MODULE_DEPEND(isp, firmware, 1, 1, 1); 377 static int isp_nvports = 0; 378 379 static int 380 isp_pci_probe(device_t dev) 381 { 382 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 383 case PCI_QLOGIC_ISP1020: 384 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 385 break; 386 case PCI_QLOGIC_ISP1080: 387 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 388 break; 389 case PCI_QLOGIC_ISP1240: 390 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 391 break; 392 case PCI_QLOGIC_ISP1280: 393 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 394 break; 395 case PCI_QLOGIC_ISP10160: 396 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 397 break; 398 case PCI_QLOGIC_ISP12160: 399 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 400 return (ENXIO); 401 } 402 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 403 break; 404 case PCI_QLOGIC_ISP2100: 405 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 406 break; 407 case PCI_QLOGIC_ISP2200: 408 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 409 break; 410 case PCI_QLOGIC_ISP2300: 411 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 412 break; 413 case PCI_QLOGIC_ISP2312: 414 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 415 break; 416 case PCI_QLOGIC_ISP2322: 417 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 418 break; 419 case PCI_QLOGIC_ISP2422: 420 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 421 break; 422 case PCI_QLOGIC_ISP2432: 423 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 424 break; 425 case PCI_QLOGIC_ISP2532: 426 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 427 break; 428 case PCI_QLOGIC_ISP5432: 429 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 430 break; 431 case PCI_QLOGIC_ISP6312: 432 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 433 break; 434 case PCI_QLOGIC_ISP6322: 435 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 436 break; 437 default: 438 return (ENXIO); 439 } 440 if (isp_announced == 0 && bootverbose) { 441 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 442 "Core Version %d.%d\n", 443 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 444 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 445 isp_announced++; 446 } 447 /* 448 * XXXX: Here is where we might load the f/w module 449 * XXXX: (or increase a reference count to it). 450 */ 451 return (BUS_PROBE_DEFAULT); 452 } 453 454 static void 455 isp_get_generic_options(device_t dev, ispsoftc_t *isp) 456 { 457 int tval; 458 459 tval = 0; 460 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 461 isp->isp_confopts |= ISP_CFG_NORELOAD; 462 } 463 tval = 0; 464 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 465 isp->isp_confopts |= ISP_CFG_NONVRAM; 466 } 467 tval = 0; 468 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 469 if (tval) { 470 isp->isp_dblev = tval; 471 } else { 472 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 473 } 474 if (bootverbose) { 475 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 476 } 477 tval = -1; 478 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 479 if (tval > 0 && tval <= 254) { 480 isp_nvports = tval; 481 } 482 tval = 7; 483 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 484 isp_quickboot_time = tval; 485 } 486 487 static void 488 isp_get_pci_options(device_t dev, int *m1, int *m2) 489 { 490 int tval; 491 /* 492 * Which we should try first - memory mapping or i/o mapping? 493 * 494 * We used to try memory first followed by i/o on alpha, otherwise 495 * the reverse, but we should just try memory first all the time now. 496 */ 497 *m1 = PCIM_CMD_MEMEN; 498 *m2 = PCIM_CMD_PORTEN; 499 500 tval = 0; 501 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 502 *m1 = PCIM_CMD_PORTEN; 503 *m2 = PCIM_CMD_MEMEN; 504 } 505 tval = 0; 506 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 507 *m1 = PCIM_CMD_MEMEN; 508 *m2 = PCIM_CMD_PORTEN; 509 } 510 } 511 512 static void 513 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 514 { 515 const char *sptr; 516 int tval = 0; 517 char prefix[12], name[16]; 518 519 if (chan == 0) 520 prefix[0] = 0; 521 else 522 snprintf(prefix, sizeof(prefix), "chan%d.", chan); 523 snprintf(name, sizeof(name), "%siid", prefix); 524 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 525 name, &tval)) { 526 if (IS_FC(isp)) { 527 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 528 } else { 529 #ifdef __sparc64__ 530 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 531 #else 532 ISP_SPI_PC(isp, chan)->iid = 7; 533 #endif 534 } 535 } else { 536 if (IS_FC(isp)) { 537 ISP_FC_PC(isp, chan)->default_id = tval - chan; 538 } else { 539 ISP_SPI_PC(isp, chan)->iid = tval; 540 } 541 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 542 } 543 544 if (IS_SCSI(isp)) 545 return; 546 547 tval = -1; 548 snprintf(name, sizeof(name), "%srole", prefix); 549 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 550 name, &tval) == 0) { 551 switch (tval) { 552 case ISP_ROLE_NONE: 553 case ISP_ROLE_INITIATOR: 554 case ISP_ROLE_TARGET: 555 case ISP_ROLE_BOTH: 556 device_printf(dev, "Chan %d setting role to 0x%x\n", chan, tval); 557 break; 558 default: 559 tval = -1; 560 break; 561 } 562 } 563 if (tval == -1) { 564 tval = ISP_DEFAULT_ROLES; 565 } 566 ISP_FC_PC(isp, chan)->def_role = tval; 567 568 tval = 0; 569 snprintf(name, sizeof(name), "%sfullduplex", prefix); 570 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 571 name, &tval) == 0 && tval != 0) { 572 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 573 } 574 sptr = 0; 575 snprintf(name, sizeof(name), "%stopology", prefix); 576 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 577 name, (const char **) &sptr) == 0 && sptr != 0) { 578 if (strcmp(sptr, "lport") == 0) { 579 isp->isp_confopts |= ISP_CFG_LPORT; 580 } else if (strcmp(sptr, "nport") == 0) { 581 isp->isp_confopts |= ISP_CFG_NPORT; 582 } else if (strcmp(sptr, "lport-only") == 0) { 583 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 584 } else if (strcmp(sptr, "nport-only") == 0) { 585 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 586 } 587 } 588 589 tval = 0; 590 snprintf(name, sizeof(name), "%snofctape", prefix); 591 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 592 name, &tval); 593 if (tval) { 594 isp->isp_confopts |= ISP_CFG_NOFCTAPE; 595 } 596 597 tval = 0; 598 snprintf(name, sizeof(name), "%sfctape", prefix); 599 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 600 name, &tval); 601 if (tval) { 602 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE; 603 isp->isp_confopts |= ISP_CFG_FCTAPE; 604 } 605 606 607 /* 608 * Because the resource_*_value functions can neither return 609 * 64 bit integer values, nor can they be directly coerced 610 * to interpret the right hand side of the assignment as 611 * you want them to interpret it, we have to force WWN 612 * hint replacement to specify WWN strings with a leading 613 * 'w' (e..g w50000000aaaa0001). Sigh. 614 */ 615 sptr = 0; 616 snprintf(name, sizeof(name), "%sportwwn", prefix); 617 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 618 name, (const char **) &sptr); 619 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 620 char *eptr = 0; 621 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 622 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 623 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 624 ISP_FC_PC(isp, chan)->def_wwpn = 0; 625 } 626 } 627 628 sptr = 0; 629 snprintf(name, sizeof(name), "%snodewwn", prefix); 630 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 631 name, (const char **) &sptr); 632 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 633 char *eptr = 0; 634 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 635 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 636 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 637 ISP_FC_PC(isp, chan)->def_wwnn = 0; 638 } 639 } 640 641 tval = 0; 642 snprintf(name, sizeof(name), "%shysteresis", prefix); 643 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 644 "name", &tval); 645 if (tval >= 0 && tval < 256) { 646 ISP_FC_PC(isp, chan)->hysteresis = tval; 647 } else { 648 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 649 } 650 651 tval = -1; 652 snprintf(name, sizeof(name), "%sloop_down_limit", prefix); 653 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 654 name, &tval); 655 if (tval >= 0 && tval < 0xffff) { 656 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 657 } else { 658 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 659 } 660 661 tval = -1; 662 snprintf(name, sizeof(name), "%sgone_device_time", prefix); 663 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 664 name, &tval); 665 if (tval >= 0 && tval < 0xffff) { 666 ISP_FC_PC(isp, chan)->gone_device_time = tval; 667 } else { 668 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 669 } 670 } 671 672 static int 673 isp_pci_attach(device_t dev) 674 { 675 int i, m1, m2, locksetup = 0; 676 uint32_t data, cmd, linesz, did; 677 struct isp_pcisoftc *pcs; 678 ispsoftc_t *isp; 679 size_t psize, xsize; 680 char fwname[32]; 681 682 pcs = device_get_softc(dev); 683 if (pcs == NULL) { 684 device_printf(dev, "cannot get softc\n"); 685 return (ENOMEM); 686 } 687 memset(pcs, 0, sizeof (*pcs)); 688 689 pcs->pci_dev = dev; 690 isp = &pcs->pci_isp; 691 isp->isp_dev = dev; 692 isp->isp_nchan = 1; 693 if (sizeof (bus_addr_t) > 4) 694 isp->isp_osinfo.sixtyfourbit = 1; 695 696 /* 697 * Get Generic Options 698 */ 699 isp_nvports = 0; 700 isp_get_generic_options(dev, isp); 701 702 /* 703 * Get PCI options- which in this case are just mapping preferences. 704 */ 705 isp_get_pci_options(dev, &m1, &m2); 706 707 linesz = PCI_DFLT_LNSZ; 708 pcs->irq = pcs->regs = NULL; 709 pcs->rgd = pcs->rtp = pcs->iqd = 0; 710 711 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 712 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 713 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 714 if (pcs->regs == NULL) { 715 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 716 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 717 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 718 } 719 if (pcs->regs == NULL) { 720 device_printf(dev, "unable to map any ports\n"); 721 goto bad; 722 } 723 if (bootverbose) { 724 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 725 } 726 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 727 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 728 729 pcs->pci_dev = dev; 730 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 731 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 732 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 733 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 734 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 735 736 switch (pci_get_devid(dev)) { 737 case PCI_QLOGIC_ISP1020: 738 did = 0x1040; 739 isp->isp_mdvec = &mdvec; 740 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 741 break; 742 case PCI_QLOGIC_ISP1080: 743 did = 0x1080; 744 isp->isp_mdvec = &mdvec_1080; 745 isp->isp_type = ISP_HA_SCSI_1080; 746 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 747 break; 748 case PCI_QLOGIC_ISP1240: 749 did = 0x1080; 750 isp->isp_mdvec = &mdvec_1080; 751 isp->isp_type = ISP_HA_SCSI_1240; 752 isp->isp_nchan = 2; 753 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 754 break; 755 case PCI_QLOGIC_ISP1280: 756 did = 0x1080; 757 isp->isp_mdvec = &mdvec_1080; 758 isp->isp_type = ISP_HA_SCSI_1280; 759 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 760 break; 761 case PCI_QLOGIC_ISP10160: 762 did = 0x12160; 763 isp->isp_mdvec = &mdvec_12160; 764 isp->isp_type = ISP_HA_SCSI_10160; 765 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 766 break; 767 case PCI_QLOGIC_ISP12160: 768 did = 0x12160; 769 isp->isp_nchan = 2; 770 isp->isp_mdvec = &mdvec_12160; 771 isp->isp_type = ISP_HA_SCSI_12160; 772 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 773 break; 774 case PCI_QLOGIC_ISP2100: 775 did = 0x2100; 776 isp->isp_mdvec = &mdvec_2100; 777 isp->isp_type = ISP_HA_FC_2100; 778 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 779 if (pci_get_revid(dev) < 3) { 780 /* 781 * XXX: Need to get the actual revision 782 * XXX: number of the 2100 FB. At any rate, 783 * XXX: lower cache line size for early revision 784 * XXX; boards. 785 */ 786 linesz = 1; 787 } 788 break; 789 case PCI_QLOGIC_ISP2200: 790 did = 0x2200; 791 isp->isp_mdvec = &mdvec_2200; 792 isp->isp_type = ISP_HA_FC_2200; 793 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 794 break; 795 case PCI_QLOGIC_ISP2300: 796 did = 0x2300; 797 isp->isp_mdvec = &mdvec_2300; 798 isp->isp_type = ISP_HA_FC_2300; 799 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 800 break; 801 case PCI_QLOGIC_ISP2312: 802 case PCI_QLOGIC_ISP6312: 803 did = 0x2300; 804 isp->isp_mdvec = &mdvec_2300; 805 isp->isp_type = ISP_HA_FC_2312; 806 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 807 break; 808 case PCI_QLOGIC_ISP2322: 809 case PCI_QLOGIC_ISP6322: 810 did = 0x2322; 811 isp->isp_mdvec = &mdvec_2300; 812 isp->isp_type = ISP_HA_FC_2322; 813 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 814 break; 815 case PCI_QLOGIC_ISP2422: 816 case PCI_QLOGIC_ISP2432: 817 did = 0x2400; 818 isp->isp_nchan += isp_nvports; 819 isp->isp_mdvec = &mdvec_2400; 820 isp->isp_type = ISP_HA_FC_2400; 821 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 822 break; 823 case PCI_QLOGIC_ISP2532: 824 did = 0x2500; 825 isp->isp_nchan += isp_nvports; 826 isp->isp_mdvec = &mdvec_2500; 827 isp->isp_type = ISP_HA_FC_2500; 828 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 829 break; 830 case PCI_QLOGIC_ISP5432: 831 did = 0x2500; 832 isp->isp_mdvec = &mdvec_2500; 833 isp->isp_type = ISP_HA_FC_2500; 834 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 835 break; 836 default: 837 device_printf(dev, "unknown device type\n"); 838 goto bad; 839 break; 840 } 841 isp->isp_revision = pci_get_revid(dev); 842 843 if (IS_FC(isp)) { 844 psize = sizeof (fcparam); 845 xsize = sizeof (struct isp_fc); 846 } else { 847 psize = sizeof (sdparam); 848 xsize = sizeof (struct isp_spi); 849 } 850 psize *= isp->isp_nchan; 851 xsize *= isp->isp_nchan; 852 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 853 if (isp->isp_param == NULL) { 854 device_printf(dev, "cannot allocate parameter data\n"); 855 goto bad; 856 } 857 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 858 if (isp->isp_osinfo.pc.ptr == NULL) { 859 device_printf(dev, "cannot allocate parameter data\n"); 860 goto bad; 861 } 862 863 /* 864 * Now that we know who we are (roughly) get/set specific options 865 */ 866 for (i = 0; i < isp->isp_nchan; i++) { 867 isp_get_specific_options(dev, i, isp); 868 } 869 870 isp->isp_osinfo.fw = NULL; 871 if (isp->isp_osinfo.fw == NULL) { 872 snprintf(fwname, sizeof (fwname), "isp_%04x", did); 873 isp->isp_osinfo.fw = firmware_get(fwname); 874 } 875 if (isp->isp_osinfo.fw != NULL) { 876 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname); 877 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 878 } 879 880 /* 881 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set. 882 */ 883 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 884 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 885 if (IS_2300(isp)) { /* per QLogic errata */ 886 cmd &= ~PCIM_CMD_INVEN; 887 } 888 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 889 cmd &= ~PCIM_CMD_INTX_DISABLE; 890 } 891 if (IS_24XX(isp)) { 892 cmd &= ~PCIM_CMD_INTX_DISABLE; 893 } 894 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 895 896 /* 897 * Make sure the Cache Line Size register is set sensibly. 898 */ 899 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 900 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 901 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data); 902 data = linesz; 903 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 904 } 905 906 /* 907 * Make sure the Latency Timer is sane. 908 */ 909 data = pci_read_config(dev, PCIR_LATTIMER, 1); 910 if (data < PCI_DFLT_LTNCY) { 911 data = PCI_DFLT_LTNCY; 912 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data); 913 pci_write_config(dev, PCIR_LATTIMER, data, 1); 914 } 915 916 /* 917 * Make sure we've disabled the ROM. 918 */ 919 data = pci_read_config(dev, PCIR_ROMADDR, 4); 920 data &= ~1; 921 pci_write_config(dev, PCIR_ROMADDR, data, 4); 922 923 /* 924 * Do MSI 925 * 926 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 927 */ 928 if (IS_24XX(isp) || IS_2322(isp)) { 929 pcs->msicount = pci_msi_count(dev); 930 if (pcs->msicount > 1) { 931 pcs->msicount = 1; 932 } 933 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 934 pcs->iqd = 1; 935 } else { 936 pcs->iqd = 0; 937 } 938 } 939 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE); 940 if (pcs->irq == NULL) { 941 device_printf(dev, "could not allocate interrupt\n"); 942 goto bad; 943 } 944 945 /* Make sure the lock is set up. */ 946 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 947 locksetup++; 948 949 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) { 950 device_printf(dev, "could not setup interrupt\n"); 951 goto bad; 952 } 953 954 /* 955 * Last minute checks... 956 */ 957 if (IS_23XX(isp) || IS_24XX(isp)) { 958 isp->isp_port = pci_get_function(dev); 959 } 960 961 /* 962 * Make sure we're in reset state. 963 */ 964 ISP_LOCK(isp); 965 if (isp_reinit(isp, 1) != 0) { 966 ISP_UNLOCK(isp); 967 goto bad; 968 } 969 ISP_UNLOCK(isp); 970 if (isp_attach(isp)) { 971 ISP_LOCK(isp); 972 isp_uninit(isp); 973 ISP_UNLOCK(isp); 974 goto bad; 975 } 976 return (0); 977 978 bad: 979 if (pcs->ih) { 980 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 981 } 982 if (locksetup) { 983 mtx_destroy(&isp->isp_osinfo.lock); 984 } 985 if (pcs->irq) { 986 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 987 } 988 if (pcs->msicount) { 989 pci_release_msi(dev); 990 } 991 if (pcs->regs) { 992 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 993 } 994 if (pcs->pci_isp.isp_param) { 995 free(pcs->pci_isp.isp_param, M_DEVBUF); 996 pcs->pci_isp.isp_param = NULL; 997 } 998 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 999 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1000 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1001 } 1002 return (ENXIO); 1003 } 1004 1005 static int 1006 isp_pci_detach(device_t dev) 1007 { 1008 struct isp_pcisoftc *pcs; 1009 ispsoftc_t *isp; 1010 int status; 1011 1012 pcs = device_get_softc(dev); 1013 if (pcs == NULL) { 1014 return (ENXIO); 1015 } 1016 isp = (ispsoftc_t *) pcs; 1017 status = isp_detach(isp); 1018 if (status) 1019 return (status); 1020 ISP_LOCK(isp); 1021 isp_uninit(isp); 1022 if (pcs->ih) { 1023 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1024 } 1025 ISP_UNLOCK(isp); 1026 mtx_destroy(&isp->isp_osinfo.lock); 1027 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1028 if (pcs->msicount) { 1029 pci_release_msi(dev); 1030 } 1031 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1032 /* 1033 * XXX: THERE IS A LOT OF LEAKAGE HERE 1034 */ 1035 if (pcs->pci_isp.isp_param) { 1036 free(pcs->pci_isp.isp_param, M_DEVBUF); 1037 pcs->pci_isp.isp_param = NULL; 1038 } 1039 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1040 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1041 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1042 } 1043 return (0); 1044 } 1045 1046 #define IspVirt2Off(a, x) \ 1047 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1048 _BLK_REG_SHFT] + ((x) & 0xfff)) 1049 1050 #define BXR2(isp, off) \ 1051 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1052 #define BXW2(isp, off, v) \ 1053 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1054 #define BXR4(isp, off) \ 1055 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1056 #define BXW4(isp, off, v) \ 1057 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1058 1059 1060 static ISP_INLINE int 1061 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1062 { 1063 uint32_t val0, val1; 1064 int i = 0; 1065 1066 do { 1067 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1068 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1069 } while (val0 != val1 && ++i < 1000); 1070 if (val0 != val1) { 1071 return (1); 1072 } 1073 *rp = val0; 1074 return (0); 1075 } 1076 1077 static int 1078 isp_pci_rd_isr(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info) 1079 { 1080 uint16_t isr, sema; 1081 1082 if (IS_2100(isp)) { 1083 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1084 return (0); 1085 } 1086 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1087 return (0); 1088 } 1089 } else { 1090 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1091 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1092 } 1093 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1094 isr &= INT_PENDING_MASK(isp); 1095 sema &= BIU_SEMA_LOCK; 1096 if (isr == 0 && sema == 0) { 1097 return (0); 1098 } 1099 *isrp = isr; 1100 if ((*semap = sema) != 0) { 1101 if (IS_2100(isp)) { 1102 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, info)) { 1103 return (0); 1104 } 1105 } else { 1106 *info = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1107 } 1108 } 1109 return (1); 1110 } 1111 1112 static int 1113 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info) 1114 { 1115 uint32_t hccr, r2hisr; 1116 1117 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1118 *isrp = 0; 1119 return (0); 1120 } 1121 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1122 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1123 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1124 *isrp = 0; 1125 return (0); 1126 } 1127 switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) { 1128 case ISPR2HST_ROM_MBX_OK: 1129 case ISPR2HST_ROM_MBX_FAIL: 1130 case ISPR2HST_MBX_OK: 1131 case ISPR2HST_MBX_FAIL: 1132 case ISPR2HST_ASYNC_EVENT: 1133 *semap = 1; 1134 break; 1135 case ISPR2HST_RIO_16: 1136 *info = ASYNC_RIO16_1; 1137 *semap = 1; 1138 return (1); 1139 case ISPR2HST_FPOST: 1140 *info = ASYNC_CMD_CMPLT; 1141 *semap = 1; 1142 return (1); 1143 case ISPR2HST_FPOST_CTIO: 1144 *info = ASYNC_CTIO_DONE; 1145 *semap = 1; 1146 return (1); 1147 case ISPR2HST_RSPQ_UPDATE: 1148 *semap = 0; 1149 break; 1150 default: 1151 hccr = ISP_READ(isp, HCCR); 1152 if (hccr & HCCR_PAUSE) { 1153 ISP_WRITE(isp, HCCR, HCCR_RESET); 1154 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1155 ISP_WRITE(isp, BIU_ICR, 0); 1156 } else { 1157 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1158 } 1159 return (0); 1160 } 1161 *info = (r2hisr >> 16); 1162 return (1); 1163 } 1164 1165 static int 1166 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info) 1167 { 1168 uint32_t r2hisr; 1169 1170 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1171 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1172 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1173 *isrp = 0; 1174 return (0); 1175 } 1176 switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) { 1177 case ISPR2HST_ROM_MBX_OK: 1178 case ISPR2HST_ROM_MBX_FAIL: 1179 case ISPR2HST_MBX_OK: 1180 case ISPR2HST_MBX_FAIL: 1181 case ISPR2HST_ASYNC_EVENT: 1182 *semap = 1; 1183 break; 1184 case ISPR2HST_RSPQ_UPDATE: 1185 case ISPR2HST_RSPQ_UPDATE2: 1186 case ISPR2HST_ATIO_UPDATE: 1187 case ISPR2HST_ATIO_RSPQ_UPDATE: 1188 case ISPR2HST_ATIO_UPDATE2: 1189 *semap = 0; 1190 break; 1191 default: 1192 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1193 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1194 return (0); 1195 } 1196 *info = (r2hisr >> 16); 1197 return (1); 1198 } 1199 1200 static uint32_t 1201 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1202 { 1203 uint16_t rv; 1204 int oldconf = 0; 1205 1206 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1207 /* 1208 * We will assume that someone has paused the RISC processor. 1209 */ 1210 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1211 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1212 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1213 } 1214 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1215 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1216 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1217 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1218 } 1219 return (rv); 1220 } 1221 1222 static void 1223 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1224 { 1225 int oldconf = 0; 1226 1227 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1228 /* 1229 * We will assume that someone has paused the RISC processor. 1230 */ 1231 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1232 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1233 oldconf | BIU_PCI_CONF1_SXP); 1234 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1235 } 1236 BXW2(isp, IspVirt2Off(isp, regoff), val); 1237 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1238 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1239 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1240 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1241 } 1242 1243 } 1244 1245 static uint32_t 1246 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1247 { 1248 uint32_t rv, oc = 0; 1249 1250 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1251 uint32_t tc; 1252 /* 1253 * We will assume that someone has paused the RISC processor. 1254 */ 1255 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1256 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1257 if (regoff & SXP_BANK1_SELECT) 1258 tc |= BIU_PCI1080_CONF1_SXP1; 1259 else 1260 tc |= BIU_PCI1080_CONF1_SXP0; 1261 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1262 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1263 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1264 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1265 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1266 oc | BIU_PCI1080_CONF1_DMA); 1267 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1268 } 1269 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1270 if (oc) { 1271 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1272 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1273 } 1274 return (rv); 1275 } 1276 1277 static void 1278 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1279 { 1280 int oc = 0; 1281 1282 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1283 uint32_t tc; 1284 /* 1285 * We will assume that someone has paused the RISC processor. 1286 */ 1287 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1288 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1289 if (regoff & SXP_BANK1_SELECT) 1290 tc |= BIU_PCI1080_CONF1_SXP1; 1291 else 1292 tc |= BIU_PCI1080_CONF1_SXP0; 1293 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1294 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1295 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1296 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1297 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1298 oc | BIU_PCI1080_CONF1_DMA); 1299 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1300 } 1301 BXW2(isp, IspVirt2Off(isp, regoff), val); 1302 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1303 if (oc) { 1304 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1305 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1306 } 1307 } 1308 1309 static uint32_t 1310 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1311 { 1312 uint32_t rv; 1313 int block = regoff & _BLK_REG_MASK; 1314 1315 switch (block) { 1316 case BIU_BLOCK: 1317 break; 1318 case MBOX_BLOCK: 1319 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1320 case SXP_BLOCK: 1321 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1322 return (0xffffffff); 1323 case RISC_BLOCK: 1324 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1325 return (0xffffffff); 1326 case DMA_BLOCK: 1327 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1328 return (0xffffffff); 1329 default: 1330 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1331 return (0xffffffff); 1332 } 1333 1334 1335 switch (regoff) { 1336 case BIU2400_FLASH_ADDR: 1337 case BIU2400_FLASH_DATA: 1338 case BIU2400_ICR: 1339 case BIU2400_ISR: 1340 case BIU2400_CSR: 1341 case BIU2400_REQINP: 1342 case BIU2400_REQOUTP: 1343 case BIU2400_RSPINP: 1344 case BIU2400_RSPOUTP: 1345 case BIU2400_PRI_REQINP: 1346 case BIU2400_PRI_REQOUTP: 1347 case BIU2400_ATIO_RSPINP: 1348 case BIU2400_ATIO_RSPOUTP: 1349 case BIU2400_HCCR: 1350 case BIU2400_GPIOD: 1351 case BIU2400_GPIOE: 1352 case BIU2400_HSEMA: 1353 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1354 break; 1355 case BIU2400_R2HSTSLO: 1356 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1357 break; 1358 case BIU2400_R2HSTSHI: 1359 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1360 break; 1361 default: 1362 isp_prt(isp, ISP_LOGERR, 1363 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1364 rv = 0xffffffff; 1365 break; 1366 } 1367 return (rv); 1368 } 1369 1370 static void 1371 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1372 { 1373 int block = regoff & _BLK_REG_MASK; 1374 1375 switch (block) { 1376 case BIU_BLOCK: 1377 break; 1378 case MBOX_BLOCK: 1379 BXW2(isp, IspVirt2Off(isp, regoff), val); 1380 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1381 return; 1382 case SXP_BLOCK: 1383 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1384 return; 1385 case RISC_BLOCK: 1386 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1387 return; 1388 case DMA_BLOCK: 1389 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1390 return; 1391 default: 1392 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1393 regoff); 1394 break; 1395 } 1396 1397 switch (regoff) { 1398 case BIU2400_FLASH_ADDR: 1399 case BIU2400_FLASH_DATA: 1400 case BIU2400_ICR: 1401 case BIU2400_ISR: 1402 case BIU2400_CSR: 1403 case BIU2400_REQINP: 1404 case BIU2400_REQOUTP: 1405 case BIU2400_RSPINP: 1406 case BIU2400_RSPOUTP: 1407 case BIU2400_PRI_REQINP: 1408 case BIU2400_PRI_REQOUTP: 1409 case BIU2400_ATIO_RSPINP: 1410 case BIU2400_ATIO_RSPOUTP: 1411 case BIU2400_HCCR: 1412 case BIU2400_GPIOD: 1413 case BIU2400_GPIOE: 1414 case BIU2400_HSEMA: 1415 BXW4(isp, IspVirt2Off(isp, regoff), val); 1416 #ifdef MEMORYBARRIERW 1417 if (regoff == BIU2400_REQINP || 1418 regoff == BIU2400_RSPOUTP || 1419 regoff == BIU2400_PRI_REQINP || 1420 regoff == BIU2400_ATIO_RSPOUTP) 1421 MEMORYBARRIERW(isp, SYNC_REG, 1422 IspVirt2Off(isp, regoff), 4, -1) 1423 else 1424 #endif 1425 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1426 break; 1427 default: 1428 isp_prt(isp, ISP_LOGERR, 1429 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1430 break; 1431 } 1432 } 1433 1434 1435 struct imush { 1436 ispsoftc_t *isp; 1437 caddr_t vbase; 1438 int chan; 1439 int error; 1440 }; 1441 1442 static void imc(void *, bus_dma_segment_t *, int, int); 1443 static void imc1(void *, bus_dma_segment_t *, int, int); 1444 1445 static void 1446 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1447 { 1448 struct imush *imushp = (struct imush *) arg; 1449 isp_ecmd_t *ecmd; 1450 1451 if (error) { 1452 imushp->error = error; 1453 return; 1454 } 1455 if (nseg != 1) { 1456 imushp->error = EINVAL; 1457 return; 1458 } 1459 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1460 1461 imushp->isp->isp_rquest = imushp->vbase; 1462 imushp->isp->isp_rquest_dma = segs->ds_addr; 1463 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1464 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1465 1466 imushp->isp->isp_result_dma = segs->ds_addr; 1467 imushp->isp->isp_result = imushp->vbase; 1468 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1469 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1470 1471 if (imushp->isp->isp_type >= ISP_HA_FC_2200) { 1472 imushp->isp->isp_osinfo.ecmd_dma = segs->ds_addr; 1473 imushp->isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)imushp->vbase; 1474 imushp->isp->isp_osinfo.ecmd_base = imushp->isp->isp_osinfo.ecmd_free; 1475 for (ecmd = imushp->isp->isp_osinfo.ecmd_free; ecmd < &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) { 1476 if (ecmd == &imushp->isp->isp_osinfo.ecmd_free[N_XCMDS - 1]) { 1477 ecmd->next = NULL; 1478 } else { 1479 ecmd->next = ecmd + 1; 1480 } 1481 } 1482 } 1483 #ifdef ISP_TARGET_MODE 1484 segs->ds_addr += (N_XCMDS * XCMD_SIZE); 1485 imushp->vbase += (N_XCMDS * XCMD_SIZE); 1486 if (IS_24XX(imushp->isp)) { 1487 imushp->isp->isp_atioq_dma = segs->ds_addr; 1488 imushp->isp->isp_atioq = imushp->vbase; 1489 } 1490 #endif 1491 } 1492 1493 static void 1494 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1495 { 1496 struct imush *imushp = (struct imush *) arg; 1497 if (error) { 1498 imushp->error = error; 1499 return; 1500 } 1501 if (nseg != 1) { 1502 imushp->error = EINVAL; 1503 return; 1504 } 1505 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1506 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1507 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1508 } 1509 1510 static int 1511 isp_pci_mbxdma(ispsoftc_t *isp) 1512 { 1513 caddr_t base; 1514 uint32_t len, nsegs; 1515 int i, error, cmap = 0; 1516 bus_size_t slim; /* segment size */ 1517 bus_addr_t llim; /* low limit of unavailable dma */ 1518 bus_addr_t hlim; /* high limit of unavailable dma */ 1519 struct imush im; 1520 1521 /* 1522 * Already been here? If so, leave... 1523 */ 1524 if (isp->isp_rquest) { 1525 return (0); 1526 } 1527 ISP_UNLOCK(isp); 1528 1529 if (isp->isp_maxcmds == 0) { 1530 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1531 ISP_LOCK(isp); 1532 return (1); 1533 } 1534 1535 hlim = BUS_SPACE_MAXADDR; 1536 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1537 if (sizeof (bus_size_t) > 4) { 1538 slim = (bus_size_t) (1ULL << 32); 1539 } else { 1540 slim = (bus_size_t) (1UL << 31); 1541 } 1542 llim = BUS_SPACE_MAXADDR; 1543 } else { 1544 llim = BUS_SPACE_MAXADDR_32BIT; 1545 slim = (1UL << 24); 1546 } 1547 1548 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1549 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1550 if (isp->isp_osinfo.pcmd_pool == NULL) { 1551 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1552 ISP_LOCK(isp); 1553 return (1); 1554 } 1555 1556 if (isp->isp_osinfo.sixtyfourbit) { 1557 nsegs = ISP_NSEG64_MAX; 1558 } else { 1559 nsegs = ISP_NSEG_MAX; 1560 } 1561 1562 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, &isp->isp_osinfo.dmat)) { 1563 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1564 ISP_LOCK(isp); 1565 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1566 return (1); 1567 } 1568 1569 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1570 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1571 if (isp->isp_xflist == NULL) { 1572 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1573 ISP_LOCK(isp); 1574 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1575 return (1); 1576 } 1577 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1578 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1579 } 1580 isp->isp_xffree = isp->isp_xflist; 1581 #ifdef ISP_TARGET_MODE 1582 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1583 isp->isp_tgtlist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1584 if (isp->isp_tgtlist == NULL) { 1585 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1586 free(isp->isp_xflist, M_DEVBUF); 1587 ISP_LOCK(isp); 1588 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1589 return (1); 1590 } 1591 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1592 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1593 } 1594 isp->isp_tgtfree = isp->isp_tgtlist; 1595 #endif 1596 1597 /* 1598 * Allocate and map the request and result queues (and ATIO queue 1599 * if we're a 2400 supporting target mode), and a region for 1600 * external dma addressable command/status structures (23XX and 1601 * later). 1602 */ 1603 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1604 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1605 #ifdef ISP_TARGET_MODE 1606 if (IS_24XX(isp)) { 1607 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1608 } 1609 #endif 1610 if (isp->isp_type >= ISP_HA_FC_2200) { 1611 len += (N_XCMDS * XCMD_SIZE); 1612 } 1613 1614 /* 1615 * Create a tag for the control spaces. We don't always need this 1616 * to be 32 bits, but we do this for simplicity and speed's sake. 1617 */ 1618 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, slim, 0, &isp->isp_osinfo.cdmat)) { 1619 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1620 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1621 free(isp->isp_xflist, M_DEVBUF); 1622 #ifdef ISP_TARGET_MODE 1623 free(isp->isp_tgtlist, M_DEVBUF); 1624 #endif 1625 ISP_LOCK(isp); 1626 return (1); 1627 } 1628 1629 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1630 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1631 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1632 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1633 free(isp->isp_xflist, M_DEVBUF); 1634 #ifdef ISP_TARGET_MODE 1635 free(isp->isp_tgtlist, M_DEVBUF); 1636 #endif 1637 ISP_LOCK(isp); 1638 return (1); 1639 } 1640 1641 im.isp = isp; 1642 im.chan = 0; 1643 im.vbase = base; 1644 im.error = 0; 1645 1646 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1647 if (im.error) { 1648 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1649 goto bad; 1650 } 1651 1652 if (IS_FC(isp)) { 1653 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1654 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1655 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1656 goto bad; 1657 } 1658 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1659 bus_dma_tag_destroy(fc->tdmat); 1660 goto bad; 1661 } 1662 im.isp = isp; 1663 im.chan = cmap; 1664 im.vbase = base; 1665 im.error = 0; 1666 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1667 if (im.error) { 1668 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1669 bus_dma_tag_destroy(fc->tdmat); 1670 goto bad; 1671 } 1672 if (!IS_2100(isp)) { 1673 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) { 1674 struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO); 1675 if (n == NULL) { 1676 while (fc->nexus_free_list) { 1677 n = fc->nexus_free_list; 1678 fc->nexus_free_list = n->next; 1679 free(n, M_DEVBUF); 1680 } 1681 goto bad; 1682 } 1683 n->next = fc->nexus_free_list; 1684 fc->nexus_free_list = n; 1685 } 1686 } 1687 } 1688 } 1689 1690 for (i = 0; i < isp->isp_maxcmds; i++) { 1691 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1692 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1693 if (error) { 1694 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1695 while (--i >= 0) { 1696 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1697 } 1698 goto bad; 1699 } 1700 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0); 1701 if (i == isp->isp_maxcmds-1) { 1702 pcmd->next = NULL; 1703 } else { 1704 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1705 } 1706 } 1707 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1708 ISP_LOCK(isp); 1709 return (0); 1710 1711 bad: 1712 while (--cmap >= 0) { 1713 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1714 bus_dmamap_unload(fc->tdmat, fc->tdmap); 1715 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1716 bus_dma_tag_destroy(fc->tdmat); 1717 while (fc->nexus_free_list) { 1718 struct isp_nexus *n = fc->nexus_free_list; 1719 fc->nexus_free_list = n->next; 1720 free(n, M_DEVBUF); 1721 } 1722 } 1723 if (isp->isp_rquest_dma != 0) 1724 bus_dmamap_unload(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap); 1725 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1726 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1727 free(isp->isp_xflist, M_DEVBUF); 1728 #ifdef ISP_TARGET_MODE 1729 free(isp->isp_tgtlist, M_DEVBUF); 1730 #endif 1731 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1732 isp->isp_rquest = NULL; 1733 ISP_LOCK(isp); 1734 return (1); 1735 } 1736 1737 typedef struct { 1738 ispsoftc_t *isp; 1739 void *cmd_token; 1740 void *rq; /* original request */ 1741 int error; 1742 bus_size_t mapsize; 1743 } mush_t; 1744 1745 #define MUSHERR_NOQENTRIES -2 1746 1747 #ifdef ISP_TARGET_MODE 1748 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1749 static void tdma2(void *, bus_dma_segment_t *, int, int); 1750 1751 static void 1752 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1753 { 1754 mush_t *mp; 1755 mp = (mush_t *)arg; 1756 mp->mapsize = mapsize; 1757 tdma2(arg, dm_segs, nseg, error); 1758 } 1759 1760 static void 1761 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1762 { 1763 mush_t *mp; 1764 ispsoftc_t *isp; 1765 struct ccb_scsiio *csio; 1766 isp_ddir_t ddir; 1767 ispreq_t *rq; 1768 1769 mp = (mush_t *) arg; 1770 if (error) { 1771 mp->error = error; 1772 return; 1773 } 1774 csio = mp->cmd_token; 1775 isp = mp->isp; 1776 rq = mp->rq; 1777 if (nseg) { 1778 if (isp->isp_osinfo.sixtyfourbit) { 1779 if (nseg >= ISP_NSEG64_MAX) { 1780 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1781 mp->error = EFAULT; 1782 return; 1783 } 1784 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1785 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1786 } 1787 } else { 1788 if (nseg >= ISP_NSEG_MAX) { 1789 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1790 mp->error = EFAULT; 1791 return; 1792 } 1793 } 1794 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1795 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1796 ddir = ISP_TO_DEVICE; 1797 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1798 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1799 ddir = ISP_FROM_DEVICE; 1800 } else { 1801 dm_segs = NULL; 1802 nseg = 0; 1803 ddir = ISP_NOXFR; 1804 } 1805 } else { 1806 dm_segs = NULL; 1807 nseg = 0; 1808 ddir = ISP_NOXFR; 1809 } 1810 1811 error = isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len); 1812 switch (error) { 1813 case CMD_EAGAIN: 1814 mp->error = MUSHERR_NOQENTRIES; 1815 case CMD_QUEUED: 1816 break; 1817 default: 1818 mp->error = EIO; 1819 } 1820 } 1821 #endif 1822 1823 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1824 static void dma2(void *, bus_dma_segment_t *, int, int); 1825 1826 static void 1827 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1828 { 1829 mush_t *mp; 1830 mp = (mush_t *)arg; 1831 mp->mapsize = mapsize; 1832 dma2(arg, dm_segs, nseg, error); 1833 } 1834 1835 static void 1836 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1837 { 1838 mush_t *mp; 1839 ispsoftc_t *isp; 1840 struct ccb_scsiio *csio; 1841 isp_ddir_t ddir; 1842 ispreq_t *rq; 1843 1844 mp = (mush_t *) arg; 1845 if (error) { 1846 mp->error = error; 1847 return; 1848 } 1849 csio = mp->cmd_token; 1850 isp = mp->isp; 1851 rq = mp->rq; 1852 if (nseg) { 1853 if (isp->isp_osinfo.sixtyfourbit) { 1854 if (nseg >= ISP_NSEG64_MAX) { 1855 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1856 mp->error = EFAULT; 1857 return; 1858 } 1859 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1860 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1861 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1862 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1863 } 1864 } else { 1865 if (nseg >= ISP_NSEG_MAX) { 1866 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1867 mp->error = EFAULT; 1868 return; 1869 } 1870 } 1871 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1872 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1873 ddir = ISP_FROM_DEVICE; 1874 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1875 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1876 ddir = ISP_TO_DEVICE; 1877 } else { 1878 ddir = ISP_NOXFR; 1879 } 1880 } else { 1881 dm_segs = NULL; 1882 nseg = 0; 1883 ddir = ISP_NOXFR; 1884 } 1885 1886 error = isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, (ispds64_t *)csio->req_map); 1887 switch (error) { 1888 case CMD_EAGAIN: 1889 mp->error = MUSHERR_NOQENTRIES; 1890 break; 1891 case CMD_QUEUED: 1892 break; 1893 default: 1894 mp->error = EIO; 1895 break; 1896 } 1897 } 1898 1899 static int 1900 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1901 { 1902 mush_t mush, *mp; 1903 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1904 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1905 int error; 1906 1907 mp = &mush; 1908 mp->isp = isp; 1909 mp->cmd_token = csio; 1910 mp->rq = ff; 1911 mp->error = 0; 1912 mp->mapsize = 0; 1913 1914 #ifdef ISP_TARGET_MODE 1915 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1916 eptr = tdma2; 1917 eptr2 = tdma2_2; 1918 } else 1919 #endif 1920 { 1921 eptr = dma2; 1922 eptr2 = dma2_2; 1923 } 1924 1925 1926 error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, 1927 (union ccb *)csio, eptr, mp, 0); 1928 if (error == EINPROGRESS) { 1929 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1930 mp->error = EINVAL; 1931 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1932 } else if (error && mp->error == 0) { 1933 #ifdef DIAGNOSTIC 1934 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1935 #endif 1936 mp->error = error; 1937 } 1938 if (mp->error) { 1939 int retval = CMD_COMPLETE; 1940 if (mp->error == MUSHERR_NOQENTRIES) { 1941 retval = CMD_EAGAIN; 1942 } else if (mp->error == EFBIG) { 1943 csio->ccb_h.status = CAM_REQ_TOO_BIG; 1944 } else if (mp->error == EINVAL) { 1945 csio->ccb_h.status = CAM_REQ_INVALID; 1946 } else { 1947 csio->ccb_h.status = CAM_UNREC_HBA_ERROR; 1948 } 1949 return (retval); 1950 } 1951 return (CMD_QUEUED); 1952 } 1953 1954 static void 1955 isp_pci_reset0(ispsoftc_t *isp) 1956 { 1957 ISP_DISABLE_INTS(isp); 1958 } 1959 1960 static void 1961 isp_pci_reset1(ispsoftc_t *isp) 1962 { 1963 if (!IS_24XX(isp)) { 1964 /* Make sure the BIOS is disabled */ 1965 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1966 } 1967 /* and enable interrupts */ 1968 ISP_ENABLE_INTS(isp); 1969 } 1970 1971 static void 1972 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1973 { 1974 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1975 if (msg) 1976 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1977 else 1978 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1979 if (IS_SCSI(isp)) 1980 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1981 else 1982 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1983 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1984 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1985 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1986 1987 1988 if (IS_SCSI(isp)) { 1989 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1990 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1991 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1992 ISP_READ(isp, CDMA_FIFO_STS)); 1993 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1994 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1995 ISP_READ(isp, DDMA_FIFO_STS)); 1996 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1997 ISP_READ(isp, SXP_INTERRUPT), 1998 ISP_READ(isp, SXP_GROSS_ERR), 1999 ISP_READ(isp, SXP_PINS_CTRL)); 2000 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2001 } 2002 printf(" mbox regs: %x %x %x %x %x\n", 2003 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2004 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2005 ISP_READ(isp, OUTMAILBOX4)); 2006 printf(" PCI Status Command/Status=%x\n", 2007 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2008 } 2009