1 /* $FreeBSD$ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * FreeBSD Version. 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000, 2001 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 36 #include <pci/pcireg.h> 37 #include <pci/pcivar.h> 38 39 #include <machine/bus_memio.h> 40 #include <machine/bus_pio.h> 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 46 #include <dev/isp/isp_freebsd.h> 47 48 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 49 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 50 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 51 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 52 static int 53 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 54 static int 55 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 56 static int isp_pci_mbxdma(struct ispsoftc *); 57 static int 58 isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, u_int16_t *, u_int16_t); 59 static void 60 isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 61 62 static void isp_pci_reset1(struct ispsoftc *); 63 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 64 65 #ifndef ISP_CODE_ORG 66 #define ISP_CODE_ORG 0x1000 67 #endif 68 69 static struct ispmdvec mdvec = { 70 isp_pci_rd_isr, 71 isp_pci_rd_reg, 72 isp_pci_wr_reg, 73 isp_pci_mbxdma, 74 isp_pci_dmasetup, 75 isp_pci_dmateardown, 76 NULL, 77 isp_pci_reset1, 78 isp_pci_dumpregs, 79 NULL, 80 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 81 }; 82 83 static struct ispmdvec mdvec_1080 = { 84 isp_pci_rd_isr, 85 isp_pci_rd_reg_1080, 86 isp_pci_wr_reg_1080, 87 isp_pci_mbxdma, 88 isp_pci_dmasetup, 89 isp_pci_dmateardown, 90 NULL, 91 isp_pci_reset1, 92 isp_pci_dumpregs, 93 NULL, 94 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 95 }; 96 97 static struct ispmdvec mdvec_12160 = { 98 isp_pci_rd_isr, 99 isp_pci_rd_reg_1080, 100 isp_pci_wr_reg_1080, 101 isp_pci_mbxdma, 102 isp_pci_dmasetup, 103 isp_pci_dmateardown, 104 NULL, 105 isp_pci_reset1, 106 isp_pci_dumpregs, 107 NULL, 108 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 109 }; 110 111 static struct ispmdvec mdvec_2100 = { 112 isp_pci_rd_isr, 113 isp_pci_rd_reg, 114 isp_pci_wr_reg, 115 isp_pci_mbxdma, 116 isp_pci_dmasetup, 117 isp_pci_dmateardown, 118 NULL, 119 isp_pci_reset1, 120 isp_pci_dumpregs 121 }; 122 123 static struct ispmdvec mdvec_2200 = { 124 isp_pci_rd_isr, 125 isp_pci_rd_reg, 126 isp_pci_wr_reg, 127 isp_pci_mbxdma, 128 isp_pci_dmasetup, 129 isp_pci_dmateardown, 130 NULL, 131 isp_pci_reset1, 132 isp_pci_dumpregs 133 }; 134 135 static struct ispmdvec mdvec_2300 = { 136 isp_pci_rd_isr_2300, 137 isp_pci_rd_reg, 138 isp_pci_wr_reg, 139 isp_pci_mbxdma, 140 isp_pci_dmasetup, 141 isp_pci_dmateardown, 142 NULL, 143 isp_pci_reset1, 144 isp_pci_dumpregs 145 }; 146 147 #ifndef PCIM_CMD_INVEN 148 #define PCIM_CMD_INVEN 0x10 149 #endif 150 #ifndef PCIM_CMD_BUSMASTEREN 151 #define PCIM_CMD_BUSMASTEREN 0x0004 152 #endif 153 #ifndef PCIM_CMD_PERRESPEN 154 #define PCIM_CMD_PERRESPEN 0x0040 155 #endif 156 #ifndef PCIM_CMD_SEREN 157 #define PCIM_CMD_SEREN 0x0100 158 #endif 159 160 #ifndef PCIR_COMMAND 161 #define PCIR_COMMAND 0x04 162 #endif 163 164 #ifndef PCIR_CACHELNSZ 165 #define PCIR_CACHELNSZ 0x0c 166 #endif 167 168 #ifndef PCIR_LATTIMER 169 #define PCIR_LATTIMER 0x0d 170 #endif 171 172 #ifndef PCIR_ROMADDR 173 #define PCIR_ROMADDR 0x30 174 #endif 175 176 #ifndef PCI_VENDOR_QLOGIC 177 #define PCI_VENDOR_QLOGIC 0x1077 178 #endif 179 180 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 181 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 182 #endif 183 184 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 185 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 186 #endif 187 188 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 189 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 190 #endif 191 192 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 193 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 194 #endif 195 196 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 197 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 198 #endif 199 200 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 201 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 202 #endif 203 204 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 205 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 206 #endif 207 208 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 209 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 210 #endif 211 212 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 213 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 214 #endif 215 216 #define PCI_QLOGIC_ISP1020 \ 217 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 218 219 #define PCI_QLOGIC_ISP1080 \ 220 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 221 222 #define PCI_QLOGIC_ISP12160 \ 223 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 224 225 #define PCI_QLOGIC_ISP1240 \ 226 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 227 228 #define PCI_QLOGIC_ISP1280 \ 229 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 230 231 #define PCI_QLOGIC_ISP2100 \ 232 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 233 234 #define PCI_QLOGIC_ISP2200 \ 235 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 236 237 #define PCI_QLOGIC_ISP2300 \ 238 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 239 240 #define PCI_QLOGIC_ISP2312 \ 241 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 242 243 /* 244 * Odd case for some AMI raid cards... We need to *not* attach to this. 245 */ 246 #define AMI_RAID_SUBVENDOR_ID 0x101e 247 248 #define IO_MAP_REG 0x10 249 #define MEM_MAP_REG 0x14 250 251 #define PCI_DFLT_LTNCY 0x40 252 #define PCI_DFLT_LNSZ 0x10 253 254 static int isp_pci_probe (device_t); 255 static int isp_pci_attach (device_t); 256 257 struct isp_pcisoftc { 258 struct ispsoftc pci_isp; 259 device_t pci_dev; 260 struct resource * pci_reg; 261 bus_space_tag_t pci_st; 262 bus_space_handle_t pci_sh; 263 void * ih; 264 int16_t pci_poff[_NREG_BLKS]; 265 bus_dma_tag_t parent_dmat; 266 bus_dma_tag_t cntrol_dmat; 267 bus_dmamap_t cntrol_dmap; 268 bus_dmamap_t *dmaps; 269 }; 270 ispfwfunc *isp_get_firmware_p = NULL; 271 272 static device_method_t isp_pci_methods[] = { 273 /* Device interface */ 274 DEVMETHOD(device_probe, isp_pci_probe), 275 DEVMETHOD(device_attach, isp_pci_attach), 276 { 0, 0 } 277 }; 278 static void isp_pci_intr(void *); 279 280 static driver_t isp_pci_driver = { 281 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 282 }; 283 static devclass_t isp_devclass; 284 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 285 MODULE_VERSION(isp, 1); 286 287 static int 288 isp_pci_probe(device_t dev) 289 { 290 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 291 case PCI_QLOGIC_ISP1020: 292 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 293 break; 294 case PCI_QLOGIC_ISP1080: 295 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 296 break; 297 case PCI_QLOGIC_ISP1240: 298 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 299 break; 300 case PCI_QLOGIC_ISP1280: 301 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 302 break; 303 case PCI_QLOGIC_ISP12160: 304 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 305 return (ENXIO); 306 } 307 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 308 break; 309 case PCI_QLOGIC_ISP2100: 310 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 311 break; 312 case PCI_QLOGIC_ISP2200: 313 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 314 break; 315 case PCI_QLOGIC_ISP2300: 316 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 317 break; 318 case PCI_QLOGIC_ISP2312: 319 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 320 break; 321 default: 322 return (ENXIO); 323 } 324 if (device_get_unit(dev) == 0 && bootverbose) { 325 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 326 "Core Version %d.%d\n", 327 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 328 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 329 } 330 /* 331 * XXXX: Here is where we might load the f/w module 332 * XXXX: (or increase a reference count to it). 333 */ 334 return (0); 335 } 336 337 static int 338 isp_pci_attach(device_t dev) 339 { 340 struct resource *regs, *irq; 341 int tval, rtp, rgd, iqd, m1, m2, isp_debug, role; 342 u_int32_t data, cmd, linesz, psize, basetype; 343 struct isp_pcisoftc *pcs; 344 struct ispsoftc *isp = NULL; 345 struct ispmdvec *mdvp; 346 bus_size_t lim; 347 const char *sptr; 348 int locksetup = 0; 349 350 /* 351 * Figure out if we're supposed to skip this one. 352 * If we are, we actually go to ISP_ROLE_NONE. 353 */ 354 355 tval = 0; 356 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 357 "disable", &tval) == 0 && tval) { 358 device_printf(dev, "device is disabled\n"); 359 /* but return 0 so the !$)$)*!$*) unit isn't reused */ 360 return (0); 361 } 362 363 role = 0; 364 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 365 "role", &role) == 0 && 366 ((role & ~(ISP_ROLE_INITIATOR|ISP_ROLE_TARGET)) == 0)) { 367 device_printf(dev, "setting role to 0x%x\n", role); 368 } else { 369 #ifdef ISP_TARGET_MODE 370 role = ISP_ROLE_INITIATOR|ISP_ROLE_TARGET; 371 #else 372 role = ISP_DEFAULT_ROLES; 373 #endif 374 } 375 376 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT | M_ZERO); 377 if (pcs == NULL) { 378 device_printf(dev, "cannot allocate softc\n"); 379 return (ENOMEM); 380 } 381 382 /* 383 * Figure out which we should try first - memory mapping or i/o mapping? 384 */ 385 #ifdef __alpha__ 386 m1 = PCIM_CMD_MEMEN; 387 m2 = PCIM_CMD_PORTEN; 388 #else 389 m1 = PCIM_CMD_PORTEN; 390 m2 = PCIM_CMD_MEMEN; 391 #endif 392 393 tval = 0; 394 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 395 "prefer_iomap", &tval) == 0 && tval != 0) { 396 m1 = PCIM_CMD_PORTEN; 397 m2 = PCIM_CMD_MEMEN; 398 } 399 tval = 0; 400 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 401 "prefer_memmap", &tval) == 0 && tval != 0) { 402 m1 = PCIM_CMD_MEMEN; 403 m2 = PCIM_CMD_PORTEN; 404 } 405 406 linesz = PCI_DFLT_LNSZ; 407 irq = regs = NULL; 408 rgd = rtp = iqd = 0; 409 410 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 411 if (cmd & m1) { 412 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 413 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 414 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 415 } 416 if (regs == NULL && (cmd & m2)) { 417 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 418 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 419 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 420 } 421 if (regs == NULL) { 422 device_printf(dev, "unable to map any ports\n"); 423 goto bad; 424 } 425 if (bootverbose) 426 device_printf(dev, "using %s space register mapping\n", 427 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 428 pcs->pci_dev = dev; 429 pcs->pci_reg = regs; 430 pcs->pci_st = rman_get_bustag(regs); 431 pcs->pci_sh = rman_get_bushandle(regs); 432 433 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 434 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 435 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 436 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 437 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 438 mdvp = &mdvec; 439 basetype = ISP_HA_SCSI_UNKNOWN; 440 psize = sizeof (sdparam); 441 lim = BUS_SPACE_MAXSIZE_32BIT; 442 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 443 mdvp = &mdvec; 444 basetype = ISP_HA_SCSI_UNKNOWN; 445 psize = sizeof (sdparam); 446 lim = BUS_SPACE_MAXSIZE_24BIT; 447 } 448 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 449 mdvp = &mdvec_1080; 450 basetype = ISP_HA_SCSI_1080; 451 psize = sizeof (sdparam); 452 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 453 ISP1080_DMA_REGS_OFF; 454 } 455 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 456 mdvp = &mdvec_1080; 457 basetype = ISP_HA_SCSI_1240; 458 psize = 2 * sizeof (sdparam); 459 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 460 ISP1080_DMA_REGS_OFF; 461 } 462 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 463 mdvp = &mdvec_1080; 464 basetype = ISP_HA_SCSI_1280; 465 psize = 2 * sizeof (sdparam); 466 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 467 ISP1080_DMA_REGS_OFF; 468 } 469 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 470 mdvp = &mdvec_12160; 471 basetype = ISP_HA_SCSI_12160; 472 psize = 2 * sizeof (sdparam); 473 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 474 ISP1080_DMA_REGS_OFF; 475 } 476 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 477 mdvp = &mdvec_2100; 478 basetype = ISP_HA_FC_2100; 479 psize = sizeof (fcparam); 480 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 481 PCI_MBOX_REGS2100_OFF; 482 if (pci_get_revid(dev) < 3) { 483 /* 484 * XXX: Need to get the actual revision 485 * XXX: number of the 2100 FB. At any rate, 486 * XXX: lower cache line size for early revision 487 * XXX; boards. 488 */ 489 linesz = 1; 490 } 491 } 492 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 493 mdvp = &mdvec_2200; 494 basetype = ISP_HA_FC_2200; 495 psize = sizeof (fcparam); 496 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 497 PCI_MBOX_REGS2100_OFF; 498 } 499 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2300 || 500 pci_get_devid(dev) == PCI_QLOGIC_ISP2312) { 501 mdvp = &mdvec_2300; 502 basetype = ISP_HA_FC_2300; 503 psize = sizeof (fcparam); 504 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 505 PCI_MBOX_REGS2300_OFF; 506 } 507 isp = &pcs->pci_isp; 508 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 509 if (isp->isp_param == NULL) { 510 device_printf(dev, "cannot allocate parameter data\n"); 511 goto bad; 512 } 513 isp->isp_mdvec = mdvp; 514 isp->isp_type = basetype; 515 isp->isp_revision = pci_get_revid(dev); 516 isp->isp_role = role; 517 isp->isp_dev = dev; 518 519 /* 520 * Try and find firmware for this device. 521 */ 522 523 if (isp_get_firmware_p) { 524 int device = (int) pci_get_device(dev); 525 #ifdef ISP_TARGET_MODE 526 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 527 #else 528 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 529 #endif 530 } 531 532 /* 533 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 534 * are set. 535 */ 536 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 537 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 538 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 539 540 /* 541 * Make sure the Cache Line Size register is set sensibly. 542 */ 543 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 544 if (data != linesz) { 545 data = PCI_DFLT_LNSZ; 546 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 547 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 548 } 549 550 /* 551 * Make sure the Latency Timer is sane. 552 */ 553 data = pci_read_config(dev, PCIR_LATTIMER, 1); 554 if (data < PCI_DFLT_LTNCY) { 555 data = PCI_DFLT_LTNCY; 556 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 557 pci_write_config(dev, PCIR_LATTIMER, data, 1); 558 } 559 560 /* 561 * Make sure we've disabled the ROM. 562 */ 563 data = pci_read_config(dev, PCIR_ROMADDR, 4); 564 data &= ~1; 565 pci_write_config(dev, PCIR_ROMADDR, data, 4); 566 567 568 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 569 BUS_SPACE_MAXADDR, NULL, NULL, lim + 1, 570 255, lim, 0, &pcs->parent_dmat) != 0) { 571 device_printf(dev, "could not create master dma tag\n"); 572 free(isp->isp_param, M_DEVBUF); 573 free(pcs, M_DEVBUF); 574 return (ENXIO); 575 } 576 577 iqd = 0; 578 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 579 1, RF_ACTIVE | RF_SHAREABLE); 580 if (irq == NULL) { 581 device_printf(dev, "could not allocate interrupt\n"); 582 goto bad; 583 } 584 585 tval = 0; 586 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 587 "fwload_disable", &tval) == 0 && tval != 0) { 588 isp->isp_confopts |= ISP_CFG_NORELOAD; 589 } 590 tval = 0; 591 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 592 "ignore_nvram", &tval) == 0 && tval != 0) { 593 isp->isp_confopts |= ISP_CFG_NONVRAM; 594 } 595 tval = 0; 596 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 597 "fullduplex", &tval) == 0 && tval != 0) { 598 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 599 } 600 601 sptr = 0; 602 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 603 "topology", (const char **) &sptr) == 0 && sptr != 0) { 604 if (strcmp(sptr, "lport") == 0) { 605 isp->isp_confopts |= ISP_CFG_LPORT; 606 } else if (strcmp(sptr, "nport") == 0) { 607 isp->isp_confopts |= ISP_CFG_NPORT; 608 } else if (strcmp(sptr, "lport-only") == 0) { 609 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 610 } else if (strcmp(sptr, "nport-only") == 0) { 611 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 612 } 613 } 614 615 /* 616 * Because the resource_*_value functions can neither return 617 * 64 bit integer values, nor can they be directly coerced 618 * to interpret the right hand side of the assignment as 619 * you want them to interpret it, we have to force WWN 620 * hint replacement to specify WWN strings with a leading 621 * 'w' (e..g w50000000aaaa0001). Sigh. 622 */ 623 sptr = 0; 624 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 625 "portwwn", (const char **) &sptr); 626 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 627 char *eptr = 0; 628 isp->isp_osinfo.default_port_wwn = strtouq(sptr, &eptr, 16); 629 if (eptr < sptr + 16 || isp->isp_osinfo.default_port_wwn == 0) { 630 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 631 isp->isp_osinfo.default_port_wwn = 0; 632 } else { 633 isp->isp_confopts |= ISP_CFG_OWNWWN; 634 } 635 } 636 if (isp->isp_osinfo.default_port_wwn == 0) { 637 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 638 } 639 640 sptr = 0; 641 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 642 "nodewwn", (const char **) &sptr); 643 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 644 char *eptr = 0; 645 isp->isp_osinfo.default_node_wwn = strtouq(sptr, &eptr, 16); 646 if (eptr < sptr + 16 || isp->isp_osinfo.default_node_wwn == 0) { 647 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 648 isp->isp_osinfo.default_node_wwn = 0; 649 } else { 650 isp->isp_confopts |= ISP_CFG_OWNWWN; 651 } 652 } 653 if (isp->isp_osinfo.default_node_wwn == 0) { 654 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 655 } 656 657 isp_debug = 0; 658 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 659 "debug", &isp_debug); 660 661 /* Make sure the lock is set up. */ 662 mtx_init(&isp->isp_osinfo.lock, "isp", MTX_DEF); 663 locksetup++; 664 665 #ifdef ISP_SMPLOCK 666 #define INTR_FLAGS INTR_TYPE_CAM | INTR_MPSAFE | INTR_ENTROPY 667 #else 668 #define INTR_FLAGS INTR_TYPE_CAM | INTR_ENTROPY 669 #endif 670 if (bus_setup_intr(dev, irq, INTR_FLAGS, isp_pci_intr, isp, &pcs->ih)) { 671 device_printf(dev, "could not setup interrupt\n"); 672 goto bad; 673 } 674 675 /* 676 * Set up logging levels. 677 */ 678 if (isp_debug) { 679 isp->isp_dblev = isp_debug; 680 } else { 681 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 682 } 683 if (bootverbose) 684 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 685 686 /* 687 * Make sure we're in reset state. 688 */ 689 ISP_LOCK(isp); 690 isp_reset(isp); 691 if (isp->isp_state != ISP_RESETSTATE) { 692 ISP_UNLOCK(isp); 693 goto bad; 694 } 695 isp_init(isp); 696 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_INITSTATE) { 697 isp_uninit(isp); 698 ISP_UNLOCK(isp); 699 goto bad; 700 } 701 isp_attach(isp); 702 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_RUNSTATE) { 703 isp_uninit(isp); 704 ISP_UNLOCK(isp); 705 goto bad; 706 } 707 /* 708 * XXXX: Here is where we might unload the f/w module 709 * XXXX: (or decrease the reference count to it). 710 */ 711 ISP_UNLOCK(isp); 712 return (0); 713 714 bad: 715 716 if (pcs && pcs->ih) { 717 (void) bus_teardown_intr(dev, irq, pcs->ih); 718 } 719 720 if (locksetup && isp) { 721 mtx_destroy(&isp->isp_osinfo.lock); 722 } 723 724 if (irq) { 725 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 726 } 727 728 729 if (regs) { 730 (void) bus_release_resource(dev, rtp, rgd, regs); 731 } 732 733 if (pcs) { 734 if (pcs->pci_isp.isp_param) 735 free(pcs->pci_isp.isp_param, M_DEVBUF); 736 free(pcs, M_DEVBUF); 737 } 738 739 /* 740 * XXXX: Here is where we might unload the f/w module 741 * XXXX: (or decrease the reference count to it). 742 */ 743 return (ENXIO); 744 } 745 746 static void 747 isp_pci_intr(void *arg) 748 { 749 struct ispsoftc *isp = arg; 750 u_int16_t isr, sema, mbox; 751 752 ISP_LOCK(isp); 753 isp->isp_intcnt++; 754 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 755 isp->isp_intbogus++; 756 } else { 757 int iok = isp->isp_osinfo.intsok; 758 isp->isp_osinfo.intsok = 0; 759 isp_intr(isp, isr, sema, mbox); 760 isp->isp_osinfo.intsok = iok; 761 } 762 ISP_UNLOCK(isp); 763 } 764 765 766 #define IspVirt2Off(a, x) \ 767 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 768 _BLK_REG_SHFT] + ((x) & 0xff)) 769 770 #define BXR2(pcs, off) \ 771 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 772 #define BXW2(pcs, off, v) \ 773 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 774 775 776 static INLINE int 777 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 778 { 779 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 780 u_int16_t val0, val1; 781 int i = 0; 782 783 do { 784 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 785 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 786 } while (val0 != val1 && ++i < 1000); 787 if (val0 != val1) { 788 return (1); 789 } 790 *rp = val0; 791 return (0); 792 } 793 794 static int 795 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 796 u_int16_t *semap, u_int16_t *mbp) 797 { 798 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 799 u_int16_t isr, sema; 800 801 if (IS_2100(isp)) { 802 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 803 return (0); 804 } 805 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 806 return (0); 807 } 808 } else { 809 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 810 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 811 } 812 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 813 isr &= INT_PENDING_MASK(isp); 814 sema &= BIU_SEMA_LOCK; 815 if (isr == 0 && sema == 0) { 816 return (0); 817 } 818 *isrp = isr; 819 if ((*semap = sema) != 0) { 820 if (IS_2100(isp)) { 821 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 822 return (0); 823 } 824 } else { 825 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 826 } 827 } 828 return (1); 829 } 830 831 static int 832 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 833 u_int16_t *semap, u_int16_t *mbox0p) 834 { 835 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 836 u_int32_t r2hisr; 837 838 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 839 IspVirt2Off(pcs, BIU_R2HSTSLO)); 840 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 841 if ((r2hisr & BIU_R2HST_INTR) == 0) { 842 *isrp = 0; 843 return (0); 844 } 845 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 846 case ISPR2HST_ROM_MBX_OK: 847 case ISPR2HST_ROM_MBX_FAIL: 848 case ISPR2HST_MBX_OK: 849 case ISPR2HST_MBX_FAIL: 850 case ISPR2HST_ASYNC_EVENT: 851 case ISPR2HST_FPOST: 852 case ISPR2HST_FPOST_CTIO: 853 *isrp = r2hisr & 0xffff; 854 *mbox0p = (r2hisr >> 16); 855 *semap = 1; 856 return (1); 857 case ISPR2HST_RSPQ_UPDATE: 858 *isrp = r2hisr & 0xffff; 859 *mbox0p = 0; 860 *semap = 0; 861 return (1); 862 default: 863 return (0); 864 } 865 } 866 867 static u_int16_t 868 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 869 { 870 u_int16_t rv; 871 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 872 int oldconf = 0; 873 874 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 875 /* 876 * We will assume that someone has paused the RISC processor. 877 */ 878 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 879 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 880 oldconf | BIU_PCI_CONF1_SXP); 881 } 882 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 883 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 884 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 885 } 886 return (rv); 887 } 888 889 static void 890 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 891 { 892 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 893 int oldconf = 0; 894 895 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 896 /* 897 * We will assume that someone has paused the RISC processor. 898 */ 899 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 900 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 901 oldconf | BIU_PCI_CONF1_SXP); 902 } 903 BXW2(pcs, IspVirt2Off(isp, regoff), val); 904 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 905 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 906 } 907 } 908 909 static u_int16_t 910 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 911 { 912 u_int16_t rv, oc = 0; 913 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 914 915 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 916 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 917 u_int16_t tc; 918 /* 919 * We will assume that someone has paused the RISC processor. 920 */ 921 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 922 tc = oc & ~BIU_PCI1080_CONF1_DMA; 923 if (regoff & SXP_BANK1_SELECT) 924 tc |= BIU_PCI1080_CONF1_SXP1; 925 else 926 tc |= BIU_PCI1080_CONF1_SXP0; 927 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 928 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 929 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 930 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 931 oc | BIU_PCI1080_CONF1_DMA); 932 } 933 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 934 if (oc) { 935 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 936 } 937 return (rv); 938 } 939 940 static void 941 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 942 { 943 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 944 int oc = 0; 945 946 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 947 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 948 u_int16_t tc; 949 /* 950 * We will assume that someone has paused the RISC processor. 951 */ 952 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 953 tc = oc & ~BIU_PCI1080_CONF1_DMA; 954 if (regoff & SXP_BANK1_SELECT) 955 tc |= BIU_PCI1080_CONF1_SXP1; 956 else 957 tc |= BIU_PCI1080_CONF1_SXP0; 958 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 959 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 960 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 961 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 962 oc | BIU_PCI1080_CONF1_DMA); 963 } 964 BXW2(pcs, IspVirt2Off(isp, regoff), val); 965 if (oc) { 966 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 967 } 968 } 969 970 static void isp_map_rquest(void *, bus_dma_segment_t *, int, int); 971 static void isp_map_result(void *, bus_dma_segment_t *, int, int); 972 static void isp_map_fcscrt(void *, bus_dma_segment_t *, int, int); 973 974 struct imush { 975 struct ispsoftc *isp; 976 int error; 977 }; 978 979 static void 980 isp_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) 981 { 982 struct imush *imushp = (struct imush *) arg; 983 if (error) { 984 imushp->error = error; 985 } else { 986 imushp->isp->isp_rquest_dma = segs->ds_addr; 987 } 988 } 989 990 static void 991 isp_map_result(void *arg, bus_dma_segment_t *segs, int nseg, int error) 992 { 993 struct imush *imushp = (struct imush *) arg; 994 if (error) { 995 imushp->error = error; 996 } else { 997 imushp->isp->isp_result_dma = segs->ds_addr; 998 } 999 } 1000 1001 static void 1002 isp_map_fcscrt(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1003 { 1004 struct imush *imushp = (struct imush *) arg; 1005 if (error) { 1006 imushp->error = error; 1007 } else { 1008 fcparam *fcp = imushp->isp->isp_param; 1009 fcp->isp_scdma = segs->ds_addr; 1010 } 1011 } 1012 1013 static int 1014 isp_pci_mbxdma(struct ispsoftc *isp) 1015 { 1016 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1017 caddr_t base; 1018 u_int32_t len; 1019 int i, error; 1020 bus_size_t lim; 1021 struct imush im; 1022 1023 1024 /* 1025 * Already been here? If so, leave... 1026 */ 1027 if (isp->isp_rquest) { 1028 return (0); 1029 } 1030 1031 len = sizeof (XS_T **) * isp->isp_maxcmds; 1032 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1033 if (isp->isp_xflist == NULL) { 1034 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1035 return (1); 1036 } 1037 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 1038 pci->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1039 if (pci->dmaps == NULL) { 1040 isp_prt(isp, ISP_LOGERR, "can't alloc dma maps"); 1041 free(isp->isp_xflist, M_DEVBUF); 1042 return (1); 1043 } 1044 1045 if (IS_FC(isp) || IS_ULTRA2(isp)) 1046 lim = BUS_SPACE_MAXADDR + 1; 1047 else 1048 lim = BUS_SPACE_MAXADDR_24BIT + 1; 1049 1050 /* 1051 * Allocate and map the request, result queues, plus FC scratch area. 1052 */ 1053 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1054 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1055 if (IS_FC(isp)) { 1056 len += ISP2100_SCRLEN; 1057 } 1058 if (bus_dma_tag_create(pci->parent_dmat, PAGE_SIZE, lim, 1059 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, 1060 BUS_SPACE_MAXSIZE_32BIT, 0, &pci->cntrol_dmat) != 0) { 1061 isp_prt(isp, ISP_LOGERR, 1062 "cannot create a dma tag for control spaces"); 1063 free(isp->isp_xflist, M_DEVBUF); 1064 free(pci->dmaps, M_DEVBUF); 1065 return (1); 1066 } 1067 if (bus_dmamem_alloc(pci->cntrol_dmat, (void **)&base, 1068 BUS_DMA_NOWAIT, &pci->cntrol_dmap) != 0) { 1069 isp_prt(isp, ISP_LOGERR, 1070 "cannot allocate %d bytes of CCB memory", len); 1071 free(isp->isp_xflist, M_DEVBUF); 1072 free(pci->dmaps, M_DEVBUF); 1073 return (1); 1074 } 1075 1076 isp->isp_rquest = base; 1077 im.isp = isp; 1078 im.error = 0; 1079 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_rquest, 1080 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)), isp_map_rquest, &im, 0); 1081 if (im.error) { 1082 isp_prt(isp, ISP_LOGERR, 1083 "error %d loading dma map for DMA request queue", im.error); 1084 free(isp->isp_xflist, M_DEVBUF); 1085 free(pci->dmaps, M_DEVBUF); 1086 isp->isp_rquest = NULL; 1087 return (1); 1088 } 1089 isp->isp_result = base + ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1090 im.error = 0; 1091 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, isp->isp_result, 1092 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)), isp_map_result, &im, 0); 1093 if (im.error) { 1094 isp_prt(isp, ISP_LOGERR, 1095 "error %d loading dma map for DMA result queue", im.error); 1096 free(isp->isp_xflist, M_DEVBUF); 1097 free(pci->dmaps, M_DEVBUF); 1098 isp->isp_rquest = NULL; 1099 return (1); 1100 } 1101 1102 for (i = 0; i < isp->isp_maxcmds; i++) { 1103 error = bus_dmamap_create(pci->parent_dmat, 0, &pci->dmaps[i]); 1104 if (error) { 1105 isp_prt(isp, ISP_LOGERR, 1106 "error %d creating per-cmd DMA maps", error); 1107 free(isp->isp_xflist, M_DEVBUF); 1108 free(pci->dmaps, M_DEVBUF); 1109 isp->isp_rquest = NULL; 1110 return (1); 1111 } 1112 } 1113 1114 if (IS_FC(isp)) { 1115 fcparam *fcp = (fcparam *) isp->isp_param; 1116 fcp->isp_scratch = base + 1117 ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)) + 1118 ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1119 im.error = 0; 1120 bus_dmamap_load(pci->cntrol_dmat, pci->cntrol_dmap, 1121 fcp->isp_scratch, ISP2100_SCRLEN, isp_map_fcscrt, &im, 0); 1122 if (im.error) { 1123 isp_prt(isp, ISP_LOGERR, 1124 "error %d loading FC scratch area", im.error); 1125 free(isp->isp_xflist, M_DEVBUF); 1126 free(pci->dmaps, M_DEVBUF); 1127 isp->isp_rquest = NULL; 1128 return (1); 1129 } 1130 } 1131 return (0); 1132 } 1133 1134 typedef struct { 1135 struct ispsoftc *isp; 1136 void *cmd_token; 1137 void *rq; 1138 u_int16_t *iptrp; 1139 u_int16_t optr; 1140 u_int error; 1141 } mush_t; 1142 1143 #define MUSHERR_NOQENTRIES -2 1144 1145 #ifdef ISP_TARGET_MODE 1146 /* 1147 * We need to handle DMA for target mode differently from initiator mode. 1148 * 1149 * DMA mapping and construction and submission of CTIO Request Entries 1150 * and rendevous for completion are very tightly coupled because we start 1151 * out by knowing (per platform) how much data we have to move, but we 1152 * don't know, up front, how many DMA mapping segments will have to be used 1153 * cover that data, so we don't know how many CTIO Request Entries we 1154 * will end up using. Further, for performance reasons we may want to 1155 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1156 * 1157 * The standard vector still goes through isp_pci_dmasetup, but the callback 1158 * for the DMA mapping routines comes here instead with the whole transfer 1159 * mapped and a pointer to a partially filled in already allocated request 1160 * queue entry. We finish the job. 1161 */ 1162 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1163 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1164 1165 #define STATUS_WITH_DATA 1 1166 1167 static void 1168 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1169 { 1170 mush_t *mp; 1171 struct ccb_scsiio *csio; 1172 struct isp_pcisoftc *pci; 1173 bus_dmamap_t *dp; 1174 u_int8_t scsi_status; 1175 ct_entry_t *cto; 1176 u_int16_t handle; 1177 u_int32_t sflags; 1178 int nctios, send_status; 1179 int32_t resid; 1180 int i, j; 1181 1182 mp = (mush_t *) arg; 1183 if (error) { 1184 mp->error = error; 1185 return; 1186 } 1187 csio = mp->cmd_token; 1188 cto = mp->rq; 1189 1190 cto->ct_xfrlen = 0; 1191 cto->ct_seg_count = 0; 1192 cto->ct_header.rqs_entry_count = 1; 1193 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1194 1195 if (nseg == 0) { 1196 cto->ct_header.rqs_seqno = 1; 1197 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1198 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1199 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1200 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1201 cto->ct_scsi_status, cto->ct_resid); 1202 ISP_TDQE(mp->isp, "tdma_mk[no data]", *mp->iptrp, cto); 1203 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1204 return; 1205 } 1206 1207 nctios = nseg / ISP_RQDSEG; 1208 if (nseg % ISP_RQDSEG) { 1209 nctios++; 1210 } 1211 1212 /* 1213 * Check to see that we don't overflow. 1214 */ 1215 for (i = 0, j = *mp->iptrp; i < nctios; i++) { 1216 j = ISP_NXT_QENTRY(j, RQUEST_QUEUE_LEN(isp)); 1217 if (j == mp->optr) { 1218 isp_prt(mp->isp, ISP_LOGWARN, 1219 "Request Queue Overflow [tdma_mk]"); 1220 mp->error = MUSHERR_NOQENTRIES; 1221 return; 1222 } 1223 } 1224 1225 /* 1226 * Save syshandle, and potentially any SCSI status, which we'll 1227 * reinsert on the last CTIO we're going to send. 1228 */ 1229 handle = cto->ct_syshandle; 1230 cto->ct_syshandle = 0; 1231 cto->ct_header.rqs_seqno = 0; 1232 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1233 1234 if (send_status) { 1235 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1236 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1237 /* 1238 * Preserve residual. 1239 */ 1240 resid = cto->ct_resid; 1241 1242 /* 1243 * Save actual SCSI status. 1244 */ 1245 scsi_status = cto->ct_scsi_status; 1246 1247 #ifndef STATUS_WITH_DATA 1248 sflags |= CT_NO_DATA; 1249 /* 1250 * We can't do a status at the same time as a data CTIO, so 1251 * we need to synthesize an extra CTIO at this level. 1252 */ 1253 nctios++; 1254 #endif 1255 } else { 1256 sflags = scsi_status = resid = 0; 1257 } 1258 1259 cto->ct_resid = 0; 1260 cto->ct_scsi_status = 0; 1261 1262 pci = (struct isp_pcisoftc *)mp->isp; 1263 dp = &pci->dmaps[isp_handle_index(handle)]; 1264 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1265 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1266 } else { 1267 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1268 } 1269 1270 1271 while (nctios--) { 1272 int seglim; 1273 1274 seglim = nseg; 1275 if (seglim) { 1276 int seg; 1277 1278 if (seglim > ISP_RQDSEG) 1279 seglim = ISP_RQDSEG; 1280 1281 for (seg = 0; seg < seglim; seg++, nseg--) { 1282 /* 1283 * Unlike normal initiator commands, we don't 1284 * do any swizzling here. 1285 */ 1286 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1287 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1288 cto->ct_xfrlen += dm_segs->ds_len; 1289 dm_segs++; 1290 } 1291 cto->ct_seg_count = seg; 1292 } else { 1293 /* 1294 * This case should only happen when we're sending an 1295 * extra CTIO with final status. 1296 */ 1297 if (send_status == 0) { 1298 isp_prt(mp->isp, ISP_LOGWARN, 1299 "tdma_mk ran out of segments"); 1300 mp->error = EINVAL; 1301 return; 1302 } 1303 } 1304 1305 /* 1306 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1307 * ct_tagtype, and ct_timeout have been carried over 1308 * unchanged from what our caller had set. 1309 * 1310 * The dataseg fields and the seg_count fields we just got 1311 * through setting. The data direction we've preserved all 1312 * along and only clear it if we're now sending status. 1313 */ 1314 1315 if (nctios == 0) { 1316 /* 1317 * We're the last in a sequence of CTIOs, so mark 1318 * this CTIO and save the handle to the CCB such that 1319 * when this CTIO completes we can free dma resources 1320 * and do whatever else we need to do to finish the 1321 * rest of the command. We *don't* give this to the 1322 * firmware to work on- the caller will do that. 1323 */ 1324 cto->ct_syshandle = handle; 1325 cto->ct_header.rqs_seqno = 1; 1326 1327 if (send_status) { 1328 cto->ct_scsi_status = scsi_status; 1329 cto->ct_flags |= sflags; 1330 cto->ct_resid = resid; 1331 } 1332 if (send_status) { 1333 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1334 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 1335 "scsi status %x resid %d", 1336 cto->ct_fwhandle, csio->ccb_h.target_lun, 1337 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 1338 cto->ct_scsi_status, cto->ct_resid); 1339 } else { 1340 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1341 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 1342 cto->ct_fwhandle, csio->ccb_h.target_lun, 1343 cto->ct_iid, cto->ct_tag_val, 1344 cto->ct_flags); 1345 } 1346 ISP_TDQE(mp->isp, "last tdma_mk", *mp->iptrp, cto); 1347 ISP_SWIZ_CTIO(mp->isp, cto, cto); 1348 } else { 1349 ct_entry_t *octo = cto; 1350 1351 /* 1352 * Make sure syshandle fields are clean 1353 */ 1354 cto->ct_syshandle = 0; 1355 cto->ct_header.rqs_seqno = 0; 1356 1357 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1358 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 1359 cto->ct_fwhandle, csio->ccb_h.target_lun, 1360 cto->ct_iid, cto->ct_flags); 1361 ISP_TDQE(mp->isp, "tdma_mk", *mp->iptrp, cto); 1362 1363 /* 1364 * Get a new CTIO 1365 */ 1366 cto = (ct_entry_t *) 1367 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1368 j = *mp->iptrp; 1369 *mp->iptrp = 1370 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1371 if (*mp->iptrp == mp->optr) { 1372 isp_prt(mp->isp, ISP_LOGTDEBUG0, 1373 "Queue Overflow in tdma_mk"); 1374 mp->error = MUSHERR_NOQENTRIES; 1375 return; 1376 } 1377 /* 1378 * Fill in the new CTIO with info from the old one. 1379 */ 1380 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1381 cto->ct_header.rqs_entry_count = 1; 1382 cto->ct_fwhandle = octo->ct_fwhandle; 1383 cto->ct_header.rqs_flags = 0; 1384 cto->ct_lun = octo->ct_lun; 1385 cto->ct_iid = octo->ct_iid; 1386 cto->ct_reserved2 = octo->ct_reserved2; 1387 cto->ct_tgt = octo->ct_tgt; 1388 cto->ct_flags = octo->ct_flags; 1389 cto->ct_status = 0; 1390 cto->ct_scsi_status = 0; 1391 cto->ct_tag_val = octo->ct_tag_val; 1392 cto->ct_tag_type = octo->ct_tag_type; 1393 cto->ct_xfrlen = 0; 1394 cto->ct_resid = 0; 1395 cto->ct_timeout = octo->ct_timeout; 1396 cto->ct_seg_count = 0; 1397 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1398 /* 1399 * Now swizzle the old one for the consumption 1400 * of the chip and give it to the firmware to 1401 * work on while we do the next. 1402 */ 1403 ISP_SWIZ_CTIO(mp->isp, octo, octo); 1404 ISP_ADD_REQUEST(mp->isp, j); 1405 } 1406 } 1407 } 1408 1409 static void 1410 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1411 { 1412 mush_t *mp; 1413 struct ccb_scsiio *csio; 1414 struct isp_pcisoftc *pci; 1415 bus_dmamap_t *dp; 1416 ct2_entry_t *cto; 1417 u_int16_t scsi_status, send_status, send_sense, handle; 1418 int32_t resid; 1419 u_int8_t sense[QLTM_SENSELEN]; 1420 int nctios, j; 1421 1422 mp = (mush_t *) arg; 1423 if (error) { 1424 mp->error = error; 1425 return; 1426 } 1427 1428 csio = mp->cmd_token; 1429 cto = mp->rq; 1430 1431 if (nseg == 0) { 1432 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1433 isp_prt(mp->isp, ISP_LOGWARN, 1434 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1435 "set (0x%x)", cto->ct_flags); 1436 mp->error = EINVAL; 1437 return; 1438 } 1439 cto->ct_header.rqs_entry_count = 1; 1440 cto->ct_header.rqs_seqno = 1; 1441 /* ct_syshandle contains the handle set by caller */ 1442 /* 1443 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1444 * flags to NO DATA and clear relative offset flags. 1445 * We preserve the ct_resid and the response area. 1446 */ 1447 cto->ct_flags |= CT2_NO_DATA; 1448 if (cto->ct_resid > 0) 1449 cto->rsp.m1.ct_scsi_status |= CT2_DATA_UNDER; 1450 else if (cto->ct_resid < 0) 1451 cto->rsp.m1.ct_scsi_status |= CT2_DATA_OVER; 1452 cto->ct_seg_count = 0; 1453 cto->ct_reloff = 0; 1454 ISP_TDQE(mp->isp, "dma2_tgt_fc[no data]", *mp->iptrp, cto); 1455 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1456 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1457 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1458 cto->ct_iid, cto->ct_flags, cto->ct_status, 1459 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1460 ISP_SWIZ_CTIO2(isp, cto, cto); 1461 return; 1462 } 1463 1464 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1465 isp_prt(mp->isp, ISP_LOGWARN, 1466 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1467 "(0x%x)", cto->ct_flags); 1468 mp->error = EINVAL; 1469 return; 1470 } 1471 1472 1473 nctios = nseg / ISP_RQDSEG_T2; 1474 if (nseg % ISP_RQDSEG_T2) { 1475 nctios++; 1476 } 1477 1478 /* 1479 * Save the handle, status, reloff, and residual. We'll reinsert the 1480 * handle into the last CTIO2 we're going to send, and reinsert status 1481 * and residual (and possibly sense data) if that's to be sent as well. 1482 * 1483 * We preserve ct_reloff and adjust it for each data CTIO2 we send past 1484 * the first one. This is needed so that the FCP DATA IUs being sent 1485 * out have the correct offset (they can arrive at the other end out 1486 * of order). 1487 */ 1488 1489 handle = cto->ct_syshandle; 1490 cto->ct_syshandle = 0; 1491 send_status = (cto->ct_flags & CT2_SENDSTATUS) != 0; 1492 1493 if (send_status) { 1494 cto->ct_flags &= ~(CT2_SENDSTATUS|CT2_CCINCR); 1495 1496 /* 1497 * Preserve residual. 1498 */ 1499 resid = cto->ct_resid; 1500 1501 /* 1502 * Save actual SCSI status. We'll reinsert the 1503 * CT2_SNSLEN_VALID later if appropriate. 1504 */ 1505 scsi_status = cto->rsp.m0.ct_scsi_status & 0xff; 1506 send_sense = cto->rsp.m0.ct_scsi_status & CT2_SNSLEN_VALID; 1507 1508 /* 1509 * If we're sending status and have a CHECK CONDTION and 1510 * have sense data, we send one more CTIO2 with just the 1511 * status and sense data. The upper layers have stashed 1512 * the sense data in the dataseg structure for us. 1513 */ 1514 1515 if ((scsi_status & 0xf) == SCSI_STATUS_CHECK_COND && 1516 send_sense) { 1517 bcopy(cto->rsp.m0.ct_dataseg, sense, QLTM_SENSELEN); 1518 nctios++; 1519 } 1520 } else { 1521 scsi_status = send_sense = resid = 0; 1522 } 1523 1524 cto->ct_resid = 0; 1525 cto->rsp.m0.ct_scsi_status = 0; 1526 MEMZERO(&cto->rsp, sizeof (cto->rsp)); 1527 1528 pci = (struct isp_pcisoftc *)mp->isp; 1529 dp = &pci->dmaps[isp_handle_index(handle)]; 1530 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1531 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1532 } else { 1533 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1534 } 1535 1536 while (nctios--) { 1537 int seg, seglim; 1538 1539 seglim = nseg; 1540 if (seglim) { 1541 if (seglim > ISP_RQDSEG_T2) 1542 seglim = ISP_RQDSEG_T2; 1543 1544 for (seg = 0; seg < seglim; seg++) { 1545 cto->rsp.m0.ct_dataseg[seg].ds_base = 1546 dm_segs->ds_addr; 1547 cto->rsp.m0.ct_dataseg[seg].ds_count = 1548 dm_segs->ds_len; 1549 cto->rsp.m0.ct_xfrlen += dm_segs->ds_len; 1550 dm_segs++; 1551 } 1552 cto->ct_seg_count = seg; 1553 } else { 1554 /* 1555 * This case should only happen when we're sending a 1556 * synthesized MODE1 final status with sense data. 1557 */ 1558 if (send_sense == 0) { 1559 isp_prt(mp->isp, ISP_LOGWARN, 1560 "dma2_tgt_fc ran out of segments, " 1561 "no SENSE DATA"); 1562 mp->error = EINVAL; 1563 return; 1564 } 1565 } 1566 1567 /* 1568 * At this point, the fields ct_lun, ct_iid, ct_rxid, 1569 * ct_timeout have been carried over unchanged from what 1570 * our caller had set. 1571 * 1572 * The field ct_reloff is either what the caller set, or 1573 * what we've added to below. 1574 * 1575 * The dataseg fields and the seg_count fields we just got 1576 * through setting. The data direction we've preserved all 1577 * along and only clear it if we're sending a MODE1 status 1578 * as the last CTIO. 1579 * 1580 */ 1581 1582 if (nctios == 0) { 1583 1584 /* 1585 * We're the last in a sequence of CTIO2s, so mark this 1586 * CTIO2 and save the handle to the CCB such that when 1587 * this CTIO2 completes we can free dma resources and 1588 * do whatever else we need to do to finish the rest 1589 * of the command. 1590 */ 1591 1592 cto->ct_syshandle = handle; 1593 cto->ct_header.rqs_seqno = 1; 1594 1595 if (send_status) { 1596 /* 1597 * Get 'real' residual and set flags based 1598 * on it. 1599 */ 1600 cto->ct_resid = resid; 1601 if (send_sense) { 1602 MEMCPY(cto->rsp.m1.ct_resp, sense, 1603 QLTM_SENSELEN); 1604 cto->rsp.m1.ct_senselen = 1605 QLTM_SENSELEN; 1606 scsi_status |= CT2_SNSLEN_VALID; 1607 cto->rsp.m1.ct_scsi_status = 1608 scsi_status; 1609 cto->ct_flags &= CT2_FLAG_MMASK; 1610 cto->ct_flags |= CT2_FLAG_MODE1 | 1611 CT2_NO_DATA | CT2_SENDSTATUS | 1612 CT2_CCINCR; 1613 if (cto->ct_resid > 0) 1614 cto->rsp.m1.ct_scsi_status |= 1615 CT2_DATA_UNDER; 1616 else if (cto->ct_resid < 0) 1617 cto->rsp.m1.ct_scsi_status |= 1618 CT2_DATA_OVER; 1619 } else { 1620 cto->rsp.m0.ct_scsi_status = 1621 scsi_status; 1622 cto->ct_flags |= 1623 CT2_SENDSTATUS | CT2_CCINCR; 1624 if (cto->ct_resid > 0) 1625 cto->rsp.m0.ct_scsi_status |= 1626 CT2_DATA_UNDER; 1627 else if (cto->ct_resid < 0) 1628 cto->rsp.m0.ct_scsi_status |= 1629 CT2_DATA_OVER; 1630 } 1631 } 1632 ISP_TDQE(mp->isp, "last dma2_tgt_fc", *mp->iptrp, cto); 1633 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1634 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x" 1635 " ssts 0x%x res %d", cto->ct_rxid, 1636 csio->ccb_h.target_lun, (int) cto->ct_iid, 1637 cto->ct_flags, cto->ct_status, 1638 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1639 ISP_SWIZ_CTIO2(isp, cto, cto); 1640 } else { 1641 ct2_entry_t *octo = cto; 1642 1643 /* 1644 * Make sure handle fields are clean 1645 */ 1646 cto->ct_syshandle = 0; 1647 cto->ct_header.rqs_seqno = 0; 1648 1649 ISP_TDQE(mp->isp, "dma2_tgt_fc", *mp->iptrp, cto); 1650 isp_prt(mp->isp, ISP_LOGTDEBUG1, 1651 "CTIO2[%x] lun %d->iid%d flgs 0x%x", 1652 cto->ct_rxid, csio->ccb_h.target_lun, 1653 (int) cto->ct_iid, cto->ct_flags); 1654 /* 1655 * Get a new CTIO2 1656 */ 1657 cto = (ct2_entry_t *) 1658 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1659 j = *mp->iptrp; 1660 *mp->iptrp = 1661 ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1662 if (*mp->iptrp == mp->optr) { 1663 isp_prt(mp->isp, ISP_LOGWARN, 1664 "Queue Overflow in dma2_tgt_fc"); 1665 mp->error = MUSHERR_NOQENTRIES; 1666 return; 1667 } 1668 1669 /* 1670 * Fill in the new CTIO2 with info from the old one. 1671 */ 1672 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO2; 1673 cto->ct_header.rqs_entry_count = 1; 1674 cto->ct_header.rqs_flags = 0; 1675 /* ct_header.rqs_seqno && ct_syshandle done later */ 1676 cto->ct_fwhandle = octo->ct_fwhandle; 1677 cto->ct_lun = octo->ct_lun; 1678 cto->ct_iid = octo->ct_iid; 1679 cto->ct_rxid = octo->ct_rxid; 1680 cto->ct_flags = octo->ct_flags; 1681 cto->ct_status = 0; 1682 cto->ct_resid = 0; 1683 cto->ct_timeout = octo->ct_timeout; 1684 cto->ct_seg_count = 0; 1685 /* 1686 * Adjust the new relative offset by the amount which 1687 * is recorded in the data segment of the old CTIO2 we 1688 * just finished filling out. 1689 */ 1690 cto->ct_reloff += octo->rsp.m0.ct_xfrlen; 1691 MEMZERO(&cto->rsp, sizeof (cto->rsp)); 1692 ISP_SWIZ_CTIO2(isp, octo, octo); 1693 ISP_ADD_REQUEST(mp->isp, j); 1694 } 1695 } 1696 } 1697 #endif 1698 1699 static void dma2(void *, bus_dma_segment_t *, int, int); 1700 1701 static void 1702 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1703 { 1704 mush_t *mp; 1705 struct ccb_scsiio *csio; 1706 struct isp_pcisoftc *pci; 1707 bus_dmamap_t *dp; 1708 bus_dma_segment_t *eseg; 1709 ispreq_t *rq; 1710 ispcontreq_t *crq; 1711 int seglim, datalen; 1712 1713 mp = (mush_t *) arg; 1714 if (error) { 1715 mp->error = error; 1716 return; 1717 } 1718 1719 if (nseg < 1) { 1720 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1721 mp->error = EFAULT; 1722 return; 1723 } 1724 csio = mp->cmd_token; 1725 rq = mp->rq; 1726 pci = (struct isp_pcisoftc *)mp->isp; 1727 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1728 1729 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1730 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREREAD); 1731 } else { 1732 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_PREWRITE); 1733 } 1734 1735 datalen = XS_XFRLEN(csio); 1736 1737 /* 1738 * We're passed an initial partially filled in entry that 1739 * has most fields filled in except for data transfer 1740 * related values. 1741 * 1742 * Our job is to fill in the initial request queue entry and 1743 * then to start allocating and filling in continuation entries 1744 * until we've covered the entire transfer. 1745 */ 1746 1747 if (IS_FC(mp->isp)) { 1748 seglim = ISP_RQDSEG_T2; 1749 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1750 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1751 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1752 } else { 1753 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1754 } 1755 } else { 1756 if (csio->cdb_len > 12) { 1757 seglim = 0; 1758 } else { 1759 seglim = ISP_RQDSEG; 1760 } 1761 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1762 rq->req_flags |= REQFLAG_DATA_IN; 1763 } else { 1764 rq->req_flags |= REQFLAG_DATA_OUT; 1765 } 1766 } 1767 1768 eseg = dm_segs + nseg; 1769 1770 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1771 if (IS_FC(mp->isp)) { 1772 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1773 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1774 dm_segs->ds_addr; 1775 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1776 dm_segs->ds_len; 1777 } else { 1778 rq->req_dataseg[rq->req_seg_count].ds_base = 1779 dm_segs->ds_addr; 1780 rq->req_dataseg[rq->req_seg_count].ds_count = 1781 dm_segs->ds_len; 1782 } 1783 datalen -= dm_segs->ds_len; 1784 #if 0 1785 if (IS_FC(mp->isp)) { 1786 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1787 device_printf(mp->isp->isp_dev, 1788 "seg0[%d] cnt 0x%x paddr 0x%08x\n", 1789 rq->req_seg_count, 1790 rq2->req_dataseg[rq2->req_seg_count].ds_count, 1791 rq2->req_dataseg[rq2->req_seg_count].ds_base); 1792 } else { 1793 device_printf(mp->isp->isp_dev, 1794 "seg0[%d] cnt 0x%x paddr 0x%08x\n", 1795 rq->req_seg_count, 1796 rq->req_dataseg[rq->req_seg_count].ds_count, 1797 rq->req_dataseg[rq->req_seg_count].ds_base); 1798 } 1799 #endif 1800 rq->req_seg_count++; 1801 dm_segs++; 1802 } 1803 1804 while (datalen > 0 && dm_segs != eseg) { 1805 crq = (ispcontreq_t *) 1806 ISP_QUEUE_ENTRY(mp->isp->isp_rquest, *mp->iptrp); 1807 *mp->iptrp = ISP_NXT_QENTRY(*mp->iptrp, RQUEST_QUEUE_LEN(isp)); 1808 if (*mp->iptrp == mp->optr) { 1809 isp_prt(mp->isp, 1810 ISP_LOGDEBUG0, "Request Queue Overflow++"); 1811 mp->error = MUSHERR_NOQENTRIES; 1812 return; 1813 } 1814 rq->req_header.rqs_entry_count++; 1815 bzero((void *)crq, sizeof (*crq)); 1816 crq->req_header.rqs_entry_count = 1; 1817 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1818 1819 seglim = 0; 1820 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1821 crq->req_dataseg[seglim].ds_base = 1822 dm_segs->ds_addr; 1823 crq->req_dataseg[seglim].ds_count = 1824 dm_segs->ds_len; 1825 #if 0 1826 device_printf(mp->isp->isp_dev, 1827 "seg%d[%d] cnt 0x%x paddr 0x%08x\n", 1828 rq->req_header.rqs_entry_count-1, 1829 seglim, crq->req_dataseg[seglim].ds_count, 1830 crq->req_dataseg[seglim].ds_base); 1831 #endif 1832 rq->req_seg_count++; 1833 dm_segs++; 1834 seglim++; 1835 datalen -= dm_segs->ds_len; 1836 } 1837 } 1838 } 1839 1840 static int 1841 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1842 u_int16_t *iptrp, u_int16_t optr) 1843 { 1844 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1845 bus_dmamap_t *dp = NULL; 1846 mush_t mush, *mp; 1847 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1848 1849 #ifdef ISP_TARGET_MODE 1850 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1851 if (IS_FC(isp)) { 1852 eptr = tdma_mkfc; 1853 } else { 1854 eptr = tdma_mk; 1855 } 1856 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1857 (csio->dxfer_len == 0)) { 1858 mp = &mush; 1859 mp->isp = isp; 1860 mp->cmd_token = csio; 1861 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 1862 mp->iptrp = iptrp; 1863 mp->optr = optr; 1864 mp->error = 0; 1865 (*eptr)(mp, NULL, 0, 0); 1866 goto exit; 1867 } 1868 } else 1869 #endif 1870 eptr = dma2; 1871 1872 /* 1873 * NB: if we need to do request queue entry swizzling, 1874 * NB: this is where it would need to be done for cmds 1875 * NB: that move no data. For commands that move data, 1876 * NB: swizzling would take place in those functions. 1877 */ 1878 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1879 (csio->dxfer_len == 0)) { 1880 rq->req_seg_count = 1; 1881 return (CMD_QUEUED); 1882 } 1883 1884 /* 1885 * Do a virtual grapevine step to collect info for 1886 * the callback dma allocation that we have to use... 1887 */ 1888 mp = &mush; 1889 mp->isp = isp; 1890 mp->cmd_token = csio; 1891 mp->rq = rq; 1892 mp->iptrp = iptrp; 1893 mp->optr = optr; 1894 mp->error = 0; 1895 1896 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1897 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1898 int error, s; 1899 dp = &pci->dmaps[isp_handle_index(rq->req_handle)]; 1900 s = splsoftvm(); 1901 error = bus_dmamap_load(pci->parent_dmat, *dp, 1902 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1903 if (error == EINPROGRESS) { 1904 bus_dmamap_unload(pci->parent_dmat, *dp); 1905 mp->error = EINVAL; 1906 isp_prt(isp, ISP_LOGERR, 1907 "deferred dma allocation not supported"); 1908 } else if (error && mp->error == 0) { 1909 #ifdef DIAGNOSTIC 1910 isp_prt(isp, ISP_LOGERR, 1911 "error %d in dma mapping code", error); 1912 #endif 1913 mp->error = error; 1914 } 1915 splx(s); 1916 } else { 1917 /* Pointer to physical buffer */ 1918 struct bus_dma_segment seg; 1919 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1920 seg.ds_len = csio->dxfer_len; 1921 (*eptr)(mp, &seg, 1, 0); 1922 } 1923 } else { 1924 struct bus_dma_segment *segs; 1925 1926 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1927 isp_prt(isp, ISP_LOGERR, 1928 "Physical segment pointers unsupported"); 1929 mp->error = EINVAL; 1930 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1931 isp_prt(isp, ISP_LOGERR, 1932 "Virtual segment addresses unsupported"); 1933 mp->error = EINVAL; 1934 } else { 1935 /* Just use the segments provided */ 1936 segs = (struct bus_dma_segment *) csio->data_ptr; 1937 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1938 } 1939 } 1940 #ifdef ISP_TARGET_MODE 1941 exit: 1942 #endif 1943 if (mp->error) { 1944 int retval = CMD_COMPLETE; 1945 if (mp->error == MUSHERR_NOQENTRIES) { 1946 retval = CMD_EAGAIN; 1947 } else if (mp->error == EFBIG) { 1948 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1949 } else if (mp->error == EINVAL) { 1950 XS_SETERR(csio, CAM_REQ_INVALID); 1951 } else { 1952 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1953 } 1954 return (retval); 1955 } else { 1956 /* 1957 * Check to see if we weren't cancelled while sleeping on 1958 * getting DMA resources... 1959 */ 1960 if ((csio->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 1961 if (dp) { 1962 bus_dmamap_unload(pci->parent_dmat, *dp); 1963 } 1964 return (CMD_COMPLETE); 1965 } 1966 return (CMD_QUEUED); 1967 } 1968 } 1969 1970 static void 1971 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1972 { 1973 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1974 bus_dmamap_t *dp = &pci->dmaps[isp_handle_index(handle)]; 1975 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1976 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTREAD); 1977 } else { 1978 bus_dmamap_sync(pci->parent_dmat, *dp, BUS_DMASYNC_POSTWRITE); 1979 } 1980 bus_dmamap_unload(pci->parent_dmat, *dp); 1981 } 1982 1983 1984 static void 1985 isp_pci_reset1(struct ispsoftc *isp) 1986 { 1987 /* Make sure the BIOS is disabled */ 1988 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1989 /* and enable interrupts */ 1990 ENABLE_INTS(isp); 1991 } 1992 1993 static void 1994 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1995 { 1996 struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp; 1997 if (msg) 1998 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1999 else 2000 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 2001 if (IS_SCSI(isp)) 2002 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 2003 else 2004 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 2005 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 2006 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 2007 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 2008 2009 2010 if (IS_SCSI(isp)) { 2011 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 2012 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 2013 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 2014 ISP_READ(isp, CDMA_FIFO_STS)); 2015 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 2016 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 2017 ISP_READ(isp, DDMA_FIFO_STS)); 2018 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 2019 ISP_READ(isp, SXP_INTERRUPT), 2020 ISP_READ(isp, SXP_GROSS_ERR), 2021 ISP_READ(isp, SXP_PINS_CTRL)); 2022 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2023 } 2024 printf(" mbox regs: %x %x %x %x %x\n", 2025 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2026 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2027 ISP_READ(isp, OUTMAILBOX4)); 2028 printf(" PCI Status Command/Status=%x\n", 2029 pci_read_config(pci->pci_dev, PCIR_COMMAND, 1)); 2030 } 2031