1 /* $FreeBSD$ */ 2 /* 3 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 4 * FreeBSD Version. 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000, 2001 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 36 #include <pci/pcireg.h> 37 #include <pci/pcivar.h> 38 39 #include <machine/bus_memio.h> 40 #include <machine/bus_pio.h> 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 46 #include <dev/isp/isp_freebsd.h> 47 48 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 49 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 50 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 51 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 52 static int 53 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 54 static int 55 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 56 static int isp_pci_mbxdma(struct ispsoftc *); 57 static int 58 isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, u_int16_t *, u_int16_t); 59 static void 60 isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 61 62 static void isp_pci_reset1(struct ispsoftc *); 63 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 64 65 static struct ispmdvec mdvec = { 66 isp_pci_rd_isr, 67 isp_pci_rd_reg, 68 isp_pci_wr_reg, 69 isp_pci_mbxdma, 70 isp_pci_dmasetup, 71 isp_pci_dmateardown, 72 NULL, 73 isp_pci_reset1, 74 isp_pci_dumpregs, 75 NULL, 76 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 77 }; 78 79 static struct ispmdvec mdvec_1080 = { 80 isp_pci_rd_isr, 81 isp_pci_rd_reg_1080, 82 isp_pci_wr_reg_1080, 83 isp_pci_mbxdma, 84 isp_pci_dmasetup, 85 isp_pci_dmateardown, 86 NULL, 87 isp_pci_reset1, 88 isp_pci_dumpregs, 89 NULL, 90 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 91 }; 92 93 static struct ispmdvec mdvec_12160 = { 94 isp_pci_rd_isr, 95 isp_pci_rd_reg_1080, 96 isp_pci_wr_reg_1080, 97 isp_pci_mbxdma, 98 isp_pci_dmasetup, 99 isp_pci_dmateardown, 100 NULL, 101 isp_pci_reset1, 102 isp_pci_dumpregs, 103 NULL, 104 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 105 }; 106 107 static struct ispmdvec mdvec_2100 = { 108 isp_pci_rd_isr, 109 isp_pci_rd_reg, 110 isp_pci_wr_reg, 111 isp_pci_mbxdma, 112 isp_pci_dmasetup, 113 isp_pci_dmateardown, 114 NULL, 115 isp_pci_reset1, 116 isp_pci_dumpregs 117 }; 118 119 static struct ispmdvec mdvec_2200 = { 120 isp_pci_rd_isr, 121 isp_pci_rd_reg, 122 isp_pci_wr_reg, 123 isp_pci_mbxdma, 124 isp_pci_dmasetup, 125 isp_pci_dmateardown, 126 NULL, 127 isp_pci_reset1, 128 isp_pci_dumpregs 129 }; 130 131 static struct ispmdvec mdvec_2300 = { 132 isp_pci_rd_isr_2300, 133 isp_pci_rd_reg, 134 isp_pci_wr_reg, 135 isp_pci_mbxdma, 136 isp_pci_dmasetup, 137 isp_pci_dmateardown, 138 NULL, 139 isp_pci_reset1, 140 isp_pci_dumpregs 141 }; 142 143 #ifndef PCIM_CMD_INVEN 144 #define PCIM_CMD_INVEN 0x10 145 #endif 146 #ifndef PCIM_CMD_BUSMASTEREN 147 #define PCIM_CMD_BUSMASTEREN 0x0004 148 #endif 149 #ifndef PCIM_CMD_PERRESPEN 150 #define PCIM_CMD_PERRESPEN 0x0040 151 #endif 152 #ifndef PCIM_CMD_SEREN 153 #define PCIM_CMD_SEREN 0x0100 154 #endif 155 156 #ifndef PCIR_COMMAND 157 #define PCIR_COMMAND 0x04 158 #endif 159 160 #ifndef PCIR_CACHELNSZ 161 #define PCIR_CACHELNSZ 0x0c 162 #endif 163 164 #ifndef PCIR_LATTIMER 165 #define PCIR_LATTIMER 0x0d 166 #endif 167 168 #ifndef PCIR_ROMADDR 169 #define PCIR_ROMADDR 0x30 170 #endif 171 172 #ifndef PCI_VENDOR_QLOGIC 173 #define PCI_VENDOR_QLOGIC 0x1077 174 #endif 175 176 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 177 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 178 #endif 179 180 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 181 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 182 #endif 183 184 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 185 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 186 #endif 187 188 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 189 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 190 #endif 191 192 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 193 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 194 #endif 195 196 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 197 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 198 #endif 199 200 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 201 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 202 #endif 203 204 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 205 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 206 #endif 207 208 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 209 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 210 #endif 211 212 #define PCI_QLOGIC_ISP1020 \ 213 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 214 215 #define PCI_QLOGIC_ISP1080 \ 216 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 217 218 #define PCI_QLOGIC_ISP12160 \ 219 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 220 221 #define PCI_QLOGIC_ISP1240 \ 222 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 223 224 #define PCI_QLOGIC_ISP1280 \ 225 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 226 227 #define PCI_QLOGIC_ISP2100 \ 228 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 229 230 #define PCI_QLOGIC_ISP2200 \ 231 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 232 233 #define PCI_QLOGIC_ISP2300 \ 234 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 235 236 #define PCI_QLOGIC_ISP2312 \ 237 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 238 239 /* 240 * Odd case for some AMI raid cards... We need to *not* attach to this. 241 */ 242 #define AMI_RAID_SUBVENDOR_ID 0x101e 243 244 #define IO_MAP_REG 0x10 245 #define MEM_MAP_REG 0x14 246 247 #define PCI_DFLT_LTNCY 0x40 248 #define PCI_DFLT_LNSZ 0x10 249 250 static int isp_pci_probe (device_t); 251 static int isp_pci_attach (device_t); 252 253 254 struct isp_pcisoftc { 255 struct ispsoftc pci_isp; 256 device_t pci_dev; 257 struct resource * pci_reg; 258 bus_space_tag_t pci_st; 259 bus_space_handle_t pci_sh; 260 void * ih; 261 int16_t pci_poff[_NREG_BLKS]; 262 bus_dma_tag_t dmat; 263 bus_dmamap_t *dmaps; 264 }; 265 extern ispfwfunc *isp_get_firmware_p; 266 267 static device_method_t isp_pci_methods[] = { 268 /* Device interface */ 269 DEVMETHOD(device_probe, isp_pci_probe), 270 DEVMETHOD(device_attach, isp_pci_attach), 271 { 0, 0 } 272 }; 273 static void isp_pci_intr(void *); 274 275 static driver_t isp_pci_driver = { 276 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 277 }; 278 static devclass_t isp_devclass; 279 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 280 281 static int 282 isp_pci_probe(device_t dev) 283 { 284 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 285 case PCI_QLOGIC_ISP1020: 286 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 287 break; 288 case PCI_QLOGIC_ISP1080: 289 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 290 break; 291 case PCI_QLOGIC_ISP1240: 292 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 293 break; 294 case PCI_QLOGIC_ISP1280: 295 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 296 break; 297 case PCI_QLOGIC_ISP12160: 298 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 299 return (ENXIO); 300 } 301 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 302 break; 303 case PCI_QLOGIC_ISP2100: 304 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 305 break; 306 case PCI_QLOGIC_ISP2200: 307 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 308 break; 309 case PCI_QLOGIC_ISP2300: 310 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 311 break; 312 case PCI_QLOGIC_ISP2312: 313 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 314 break; 315 default: 316 return (ENXIO); 317 } 318 if (isp_announced == 0 && bootverbose) { 319 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 320 "Core Version %d.%d\n", 321 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 322 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 323 isp_announced++; 324 } 325 /* 326 * XXXX: Here is where we might load the f/w module 327 * XXXX: (or increase a reference count to it). 328 */ 329 return (0); 330 } 331 332 static int 333 isp_pci_attach(device_t dev) 334 { 335 struct resource *regs, *irq; 336 int tval, rtp, rgd, iqd, m1, m2, isp_debug, role; 337 u_int32_t data, cmd, linesz, psize, basetype; 338 struct isp_pcisoftc *pcs; 339 struct ispsoftc *isp = NULL; 340 struct ispmdvec *mdvp; 341 const char *sptr; 342 int locksetup = 0; 343 344 /* 345 * Figure out if we're supposed to skip this one. 346 * If we are, we actually go to ISP_ROLE_NONE. 347 */ 348 349 tval = 0; 350 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 351 "disable", &tval) == 0 && tval) { 352 device_printf(dev, "device is disabled\n"); 353 /* but return 0 so the !$)$)*!$*) unit isn't reused */ 354 return (0); 355 } 356 357 role = 0; 358 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 359 "role", &role) == 0 && 360 ((role & ~(ISP_ROLE_INITIATOR|ISP_ROLE_TARGET)) == 0)) { 361 device_printf(dev, "setting role to 0x%x\n", role); 362 } else { 363 #ifdef ISP_TARGET_MODE 364 role = ISP_ROLE_INITIATOR|ISP_ROLE_TARGET; 365 #else 366 role = ISP_DEFAULT_ROLES; 367 #endif 368 } 369 370 pcs = malloc(sizeof (struct isp_pcisoftc), M_DEVBUF, M_NOWAIT | M_ZERO); 371 if (pcs == NULL) { 372 device_printf(dev, "cannot allocate softc\n"); 373 return (ENOMEM); 374 } 375 376 /* 377 * Figure out which we should try first - memory mapping or i/o mapping? 378 */ 379 #ifdef __alpha__ 380 m1 = PCIM_CMD_MEMEN; 381 m2 = PCIM_CMD_PORTEN; 382 #else 383 m1 = PCIM_CMD_PORTEN; 384 m2 = PCIM_CMD_MEMEN; 385 #endif 386 387 tval = 0; 388 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 389 "prefer_iomap", &tval) == 0 && tval != 0) { 390 m1 = PCIM_CMD_PORTEN; 391 m2 = PCIM_CMD_MEMEN; 392 } 393 tval = 0; 394 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 395 "prefer_memmap", &tval) == 0 && tval != 0) { 396 m1 = PCIM_CMD_MEMEN; 397 m2 = PCIM_CMD_PORTEN; 398 } 399 400 linesz = PCI_DFLT_LNSZ; 401 irq = regs = NULL; 402 rgd = rtp = iqd = 0; 403 404 cmd = pci_read_config(dev, PCIR_COMMAND, 1); 405 if (cmd & m1) { 406 rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 407 rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 408 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 409 } 410 if (regs == NULL && (cmd & m2)) { 411 rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 412 rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 413 regs = bus_alloc_resource(dev, rtp, &rgd, 0, ~0, 1, RF_ACTIVE); 414 } 415 if (regs == NULL) { 416 device_printf(dev, "unable to map any ports\n"); 417 goto bad; 418 } 419 if (bootverbose) 420 device_printf(dev, "using %s space register mapping\n", 421 (rgd == IO_MAP_REG)? "I/O" : "Memory"); 422 pcs->pci_dev = dev; 423 pcs->pci_reg = regs; 424 pcs->pci_st = rman_get_bustag(regs); 425 pcs->pci_sh = rman_get_bushandle(regs); 426 427 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 428 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 429 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 430 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 431 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 432 mdvp = &mdvec; 433 basetype = ISP_HA_SCSI_UNKNOWN; 434 psize = sizeof (sdparam); 435 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1020) { 436 mdvp = &mdvec; 437 basetype = ISP_HA_SCSI_UNKNOWN; 438 psize = sizeof (sdparam); 439 } 440 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1080) { 441 mdvp = &mdvec_1080; 442 basetype = ISP_HA_SCSI_1080; 443 psize = sizeof (sdparam); 444 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 445 ISP1080_DMA_REGS_OFF; 446 } 447 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1240) { 448 mdvp = &mdvec_1080; 449 basetype = ISP_HA_SCSI_1240; 450 psize = 2 * sizeof (sdparam); 451 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 452 ISP1080_DMA_REGS_OFF; 453 } 454 if (pci_get_devid(dev) == PCI_QLOGIC_ISP1280) { 455 mdvp = &mdvec_1080; 456 basetype = ISP_HA_SCSI_1280; 457 psize = 2 * sizeof (sdparam); 458 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 459 ISP1080_DMA_REGS_OFF; 460 } 461 if (pci_get_devid(dev) == PCI_QLOGIC_ISP12160) { 462 mdvp = &mdvec_12160; 463 basetype = ISP_HA_SCSI_12160; 464 psize = 2 * sizeof (sdparam); 465 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 466 ISP1080_DMA_REGS_OFF; 467 } 468 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2100) { 469 mdvp = &mdvec_2100; 470 basetype = ISP_HA_FC_2100; 471 psize = sizeof (fcparam); 472 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 473 PCI_MBOX_REGS2100_OFF; 474 if (pci_get_revid(dev) < 3) { 475 /* 476 * XXX: Need to get the actual revision 477 * XXX: number of the 2100 FB. At any rate, 478 * XXX: lower cache line size for early revision 479 * XXX; boards. 480 */ 481 linesz = 1; 482 } 483 } 484 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2200) { 485 mdvp = &mdvec_2200; 486 basetype = ISP_HA_FC_2200; 487 psize = sizeof (fcparam); 488 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 489 PCI_MBOX_REGS2100_OFF; 490 } 491 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2300) { 492 mdvp = &mdvec_2300; 493 basetype = ISP_HA_FC_2300; 494 psize = sizeof (fcparam); 495 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 496 PCI_MBOX_REGS2300_OFF; 497 } 498 if (pci_get_devid(dev) == PCI_QLOGIC_ISP2312) { 499 mdvp = &mdvec_2300; 500 basetype = ISP_HA_FC_2312; 501 psize = sizeof (fcparam); 502 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 503 PCI_MBOX_REGS2300_OFF; 504 } 505 isp = &pcs->pci_isp; 506 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 507 if (isp->isp_param == NULL) { 508 device_printf(dev, "cannot allocate parameter data\n"); 509 goto bad; 510 } 511 isp->isp_mdvec = mdvp; 512 isp->isp_type = basetype; 513 isp->isp_revision = pci_get_revid(dev); 514 isp->isp_role = role; 515 isp->isp_dev = dev; 516 517 /* 518 * Try and find firmware for this device. 519 */ 520 521 if (isp_get_firmware_p) { 522 int device = (int) pci_get_device(dev); 523 #ifdef ISP_TARGET_MODE 524 (*isp_get_firmware_p)(0, 1, device, &mdvp->dv_ispfw); 525 #else 526 (*isp_get_firmware_p)(0, 0, device, &mdvp->dv_ispfw); 527 #endif 528 } 529 530 /* 531 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 532 * are set. 533 */ 534 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 535 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 536 if (IS_2300(isp)) { /* per QLogic errata */ 537 cmd &= ~PCIM_CMD_INVEN; 538 } 539 if (IS_23XX(isp)) { 540 /* 541 * Can't tell if ROM will hang on 'ABOUT FIRMWARE' command. 542 */ 543 isp->isp_touched = 1; 544 545 } 546 pci_write_config(dev, PCIR_COMMAND, cmd, 1); 547 548 /* 549 * Make sure the Cache Line Size register is set sensibly. 550 */ 551 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 552 if (data != linesz) { 553 data = PCI_DFLT_LNSZ; 554 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d", data); 555 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 556 } 557 558 /* 559 * Make sure the Latency Timer is sane. 560 */ 561 data = pci_read_config(dev, PCIR_LATTIMER, 1); 562 if (data < PCI_DFLT_LTNCY) { 563 data = PCI_DFLT_LTNCY; 564 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 565 pci_write_config(dev, PCIR_LATTIMER, data, 1); 566 } 567 568 /* 569 * Make sure we've disabled the ROM. 570 */ 571 data = pci_read_config(dev, PCIR_ROMADDR, 4); 572 data &= ~1; 573 pci_write_config(dev, PCIR_ROMADDR, data, 4); 574 575 iqd = 0; 576 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &iqd, 0, ~0, 577 1, RF_ACTIVE | RF_SHAREABLE); 578 if (irq == NULL) { 579 device_printf(dev, "could not allocate interrupt\n"); 580 goto bad; 581 } 582 583 tval = 0; 584 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 585 "fwload_disable", &tval) == 0 && tval != 0) { 586 isp->isp_confopts |= ISP_CFG_NORELOAD; 587 } 588 tval = 0; 589 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 590 "ignore_nvram", &tval) == 0 && tval != 0) { 591 isp->isp_confopts |= ISP_CFG_NONVRAM; 592 } 593 tval = 0; 594 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 595 "fullduplex", &tval) == 0 && tval != 0) { 596 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 597 } 598 #ifdef ISP_FW_CRASH_DUMP 599 tval = 0; 600 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 601 "fw_dump_enable", &tval) == 0 && tval != 0) { 602 size_t amt = 0; 603 if (IS_2200(isp)) { 604 amt = QLA2200_RISC_IMAGE_DUMP_SIZE; 605 } else if (IS_23XX(isp)) { 606 amt = QLA2300_RISC_IMAGE_DUMP_SIZE; 607 } 608 if (amt) { 609 FCPARAM(isp)->isp_dump_data = 610 malloc(amt, M_DEVBUF, M_WAITOK | M_ZERO); 611 } else { 612 device_printf(dev, 613 "f/w crash dumps not supported for this model\n"); 614 } 615 } 616 #endif 617 618 sptr = 0; 619 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 620 "topology", (const char **) &sptr) == 0 && sptr != 0) { 621 if (strcmp(sptr, "lport") == 0) { 622 isp->isp_confopts |= ISP_CFG_LPORT; 623 } else if (strcmp(sptr, "nport") == 0) { 624 isp->isp_confopts |= ISP_CFG_NPORT; 625 } else if (strcmp(sptr, "lport-only") == 0) { 626 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 627 } else if (strcmp(sptr, "nport-only") == 0) { 628 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 629 } 630 } 631 632 /* 633 * Because the resource_*_value functions can neither return 634 * 64 bit integer values, nor can they be directly coerced 635 * to interpret the right hand side of the assignment as 636 * you want them to interpret it, we have to force WWN 637 * hint replacement to specify WWN strings with a leading 638 * 'w' (e..g w50000000aaaa0001). Sigh. 639 */ 640 sptr = 0; 641 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 642 "portwwn", (const char **) &sptr); 643 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 644 char *eptr = 0; 645 isp->isp_osinfo.default_port_wwn = strtouq(sptr, &eptr, 16); 646 if (eptr < sptr + 16 || isp->isp_osinfo.default_port_wwn == 0) { 647 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 648 isp->isp_osinfo.default_port_wwn = 0; 649 } else { 650 isp->isp_confopts |= ISP_CFG_OWNWWPN; 651 } 652 } 653 if (isp->isp_osinfo.default_port_wwn == 0) { 654 isp->isp_osinfo.default_port_wwn = 0x400000007F000009ull; 655 } 656 657 sptr = 0; 658 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), 659 "nodewwn", (const char **) &sptr); 660 if (tval == 0 && sptr != 0 && *sptr++ == 'w') { 661 char *eptr = 0; 662 isp->isp_osinfo.default_node_wwn = strtouq(sptr, &eptr, 16); 663 if (eptr < sptr + 16 || isp->isp_osinfo.default_node_wwn == 0) { 664 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 665 isp->isp_osinfo.default_node_wwn = 0; 666 } else { 667 isp->isp_confopts |= ISP_CFG_OWNWWNN; 668 } 669 } 670 if (isp->isp_osinfo.default_node_wwn == 0) { 671 isp->isp_osinfo.default_node_wwn = 0x400000007F000009ull; 672 } 673 674 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 675 "iid", &tval) == 0) { 676 isp->isp_osinfo.default_id = tval; 677 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 678 } 679 if (isp->isp_osinfo.default_id == 0) { 680 if (IS_FC(isp)) { 681 isp->isp_osinfo.default_id = 109; 682 } else { 683 isp->isp_osinfo.default_id = 7; 684 } 685 } 686 687 isp_debug = 0; 688 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 689 "debug", &isp_debug); 690 691 /* Make sure the lock is set up. */ 692 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF); 693 locksetup++; 694 695 #ifdef ISP_SMPLOCK 696 #define INTR_FLAGS INTR_TYPE_CAM | INTR_MPSAFE | INTR_ENTROPY 697 #else 698 #define INTR_FLAGS INTR_TYPE_CAM | INTR_ENTROPY 699 #endif 700 if (bus_setup_intr(dev, irq, INTR_FLAGS, isp_pci_intr, isp, &pcs->ih)) { 701 device_printf(dev, "could not setup interrupt\n"); 702 goto bad; 703 } 704 705 /* 706 * Set up logging levels. 707 */ 708 if (isp_debug) { 709 isp->isp_dblev = isp_debug; 710 } else { 711 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 712 } 713 if (bootverbose) 714 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 715 716 /* 717 * Last minute checks... 718 */ 719 if (IS_2312(isp)) { 720 isp->isp_port = pci_get_function(dev); 721 } 722 723 /* 724 * Make sure we're in reset state. 725 */ 726 ISP_LOCK(isp); 727 isp_reset(isp); 728 if (isp->isp_state != ISP_RESETSTATE) { 729 ISP_UNLOCK(isp); 730 goto bad; 731 } 732 isp_init(isp); 733 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_INITSTATE) { 734 isp_uninit(isp); 735 ISP_UNLOCK(isp); 736 goto bad; 737 } 738 isp_attach(isp); 739 if (isp->isp_role != ISP_ROLE_NONE && isp->isp_state != ISP_RUNSTATE) { 740 isp_uninit(isp); 741 ISP_UNLOCK(isp); 742 goto bad; 743 } 744 /* 745 * XXXX: Here is where we might unload the f/w module 746 * XXXX: (or decrease the reference count to it). 747 */ 748 ISP_UNLOCK(isp); 749 return (0); 750 751 bad: 752 753 if (pcs && pcs->ih) { 754 (void) bus_teardown_intr(dev, irq, pcs->ih); 755 } 756 757 if (locksetup && isp) { 758 mtx_destroy(&isp->isp_osinfo.lock); 759 } 760 761 if (irq) { 762 (void) bus_release_resource(dev, SYS_RES_IRQ, iqd, irq); 763 } 764 765 766 if (regs) { 767 (void) bus_release_resource(dev, rtp, rgd, regs); 768 } 769 770 if (pcs) { 771 if (pcs->pci_isp.isp_param) 772 free(pcs->pci_isp.isp_param, M_DEVBUF); 773 free(pcs, M_DEVBUF); 774 } 775 776 /* 777 * XXXX: Here is where we might unload the f/w module 778 * XXXX: (or decrease the reference count to it). 779 */ 780 return (ENXIO); 781 } 782 783 static void 784 isp_pci_intr(void *arg) 785 { 786 struct ispsoftc *isp = arg; 787 u_int16_t isr, sema, mbox; 788 789 ISP_LOCK(isp); 790 isp->isp_intcnt++; 791 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 792 isp->isp_intbogus++; 793 } else { 794 int iok = isp->isp_osinfo.intsok; 795 isp->isp_osinfo.intsok = 0; 796 isp_intr(isp, isr, sema, mbox); 797 isp->isp_osinfo.intsok = iok; 798 } 799 ISP_UNLOCK(isp); 800 } 801 802 803 #define IspVirt2Off(a, x) \ 804 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 805 _BLK_REG_SHFT] + ((x) & 0xff)) 806 807 #define BXR2(pcs, off) \ 808 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 809 #define BXW2(pcs, off, v) \ 810 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 811 812 813 static INLINE int 814 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 815 { 816 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 817 u_int16_t val0, val1; 818 int i = 0; 819 820 do { 821 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 822 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 823 } while (val0 != val1 && ++i < 1000); 824 if (val0 != val1) { 825 return (1); 826 } 827 *rp = val0; 828 return (0); 829 } 830 831 static int 832 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 833 u_int16_t *semap, u_int16_t *mbp) 834 { 835 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 836 u_int16_t isr, sema; 837 838 if (IS_2100(isp)) { 839 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 840 return (0); 841 } 842 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 843 return (0); 844 } 845 } else { 846 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 847 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 848 } 849 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 850 isr &= INT_PENDING_MASK(isp); 851 sema &= BIU_SEMA_LOCK; 852 if (isr == 0 && sema == 0) { 853 return (0); 854 } 855 *isrp = isr; 856 if ((*semap = sema) != 0) { 857 if (IS_2100(isp)) { 858 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 859 return (0); 860 } 861 } else { 862 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 863 } 864 } 865 return (1); 866 } 867 868 static int 869 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 870 u_int16_t *semap, u_int16_t *mbox0p) 871 { 872 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 873 u_int32_t r2hisr; 874 875 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 876 *isrp = 0; 877 return (0); 878 } 879 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 880 IspVirt2Off(pcs, BIU_R2HSTSLO)); 881 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 882 if ((r2hisr & BIU_R2HST_INTR) == 0) { 883 *isrp = 0; 884 return (0); 885 } 886 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 887 case ISPR2HST_ROM_MBX_OK: 888 case ISPR2HST_ROM_MBX_FAIL: 889 case ISPR2HST_MBX_OK: 890 case ISPR2HST_MBX_FAIL: 891 case ISPR2HST_ASYNC_EVENT: 892 case ISPR2HST_RIO_16: 893 case ISPR2HST_FPOST: 894 case ISPR2HST_FPOST_CTIO: 895 *isrp = r2hisr & 0xffff; 896 *mbox0p = (r2hisr >> 16); 897 *semap = 1; 898 return (1); 899 case ISPR2HST_RSPQ_UPDATE: 900 *isrp = r2hisr & 0xffff; 901 *mbox0p = 0; 902 *semap = 0; 903 return (1); 904 default: 905 return (0); 906 } 907 } 908 909 static u_int16_t 910 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 911 { 912 u_int16_t rv; 913 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 914 int oldconf = 0; 915 916 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 917 /* 918 * We will assume that someone has paused the RISC processor. 919 */ 920 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 921 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 922 oldconf | BIU_PCI_CONF1_SXP); 923 } 924 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 925 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 926 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 927 } 928 return (rv); 929 } 930 931 static void 932 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 933 { 934 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 935 int oldconf = 0; 936 937 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 938 /* 939 * We will assume that someone has paused the RISC processor. 940 */ 941 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 942 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 943 oldconf | BIU_PCI_CONF1_SXP); 944 } 945 BXW2(pcs, IspVirt2Off(isp, regoff), val); 946 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 947 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 948 } 949 } 950 951 static u_int16_t 952 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 953 { 954 u_int16_t rv, oc = 0; 955 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 956 957 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 958 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 959 u_int16_t tc; 960 /* 961 * We will assume that someone has paused the RISC processor. 962 */ 963 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 964 tc = oc & ~BIU_PCI1080_CONF1_DMA; 965 if (regoff & SXP_BANK1_SELECT) 966 tc |= BIU_PCI1080_CONF1_SXP1; 967 else 968 tc |= BIU_PCI1080_CONF1_SXP0; 969 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 970 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 971 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 972 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 973 oc | BIU_PCI1080_CONF1_DMA); 974 } 975 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 976 if (oc) { 977 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 978 } 979 return (rv); 980 } 981 982 static void 983 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 984 { 985 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 986 int oc = 0; 987 988 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 989 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 990 u_int16_t tc; 991 /* 992 * We will assume that someone has paused the RISC processor. 993 */ 994 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 995 tc = oc & ~BIU_PCI1080_CONF1_DMA; 996 if (regoff & SXP_BANK1_SELECT) 997 tc |= BIU_PCI1080_CONF1_SXP1; 998 else 999 tc |= BIU_PCI1080_CONF1_SXP0; 1000 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1001 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1002 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1003 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1004 oc | BIU_PCI1080_CONF1_DMA); 1005 } 1006 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1007 if (oc) { 1008 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1009 } 1010 } 1011 1012 1013 struct imush { 1014 struct ispsoftc *isp; 1015 int error; 1016 }; 1017 1018 static void imc(void *, bus_dma_segment_t *, int, int); 1019 1020 static void 1021 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1022 { 1023 struct imush *imushp = (struct imush *) arg; 1024 if (error) { 1025 imushp->error = error; 1026 } else { 1027 struct ispsoftc *isp =imushp->isp; 1028 bus_addr_t addr = segs->ds_addr; 1029 1030 isp->isp_rquest_dma = addr; 1031 addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1032 isp->isp_result_dma = addr; 1033 if (IS_FC(isp)) { 1034 addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1035 FCPARAM(isp)->isp_scdma = addr; 1036 } 1037 } 1038 } 1039 1040 /* 1041 * Should be BUS_SPACE_MAXSIZE, but MAXPHYS is larger than BUS_SPACE_MAXSIZE 1042 */ 1043 #define ISP_NSEGS ((MAXPHYS / PAGE_SIZE) + 1) 1044 1045 static int 1046 isp_pci_mbxdma(struct ispsoftc *isp) 1047 { 1048 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1049 caddr_t base; 1050 u_int32_t len; 1051 int i, error, ns; 1052 bus_size_t bl; 1053 struct imush im; 1054 1055 /* 1056 * Already been here? If so, leave... 1057 */ 1058 if (isp->isp_rquest) { 1059 return (0); 1060 } 1061 1062 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1063 bl = BUS_SPACE_UNRESTRICTED; 1064 } else { 1065 bl = BUS_SPACE_MAXADDR_24BIT; 1066 } 1067 1068 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR, 1069 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 1070 ISP_NSEGS, bl, 0, &pcs->dmat)) { 1071 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1072 return(1); 1073 } 1074 1075 1076 len = sizeof (XS_T **) * isp->isp_maxcmds; 1077 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1078 if (isp->isp_xflist == NULL) { 1079 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1080 return (1); 1081 } 1082 len = sizeof (bus_dmamap_t) * isp->isp_maxcmds; 1083 pcs->dmaps = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1084 if (pcs->dmaps == NULL) { 1085 isp_prt(isp, ISP_LOGERR, "can't alloc dma map storage"); 1086 free(isp->isp_xflist, M_DEVBUF); 1087 return (1); 1088 } 1089 1090 /* 1091 * Allocate and map the request, result queues, plus FC scratch area. 1092 */ 1093 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1094 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1095 if (IS_FC(isp)) { 1096 len += ISP2100_SCRLEN; 1097 } 1098 1099 ns = (len / PAGE_SIZE) + 1; 1100 if (bus_dma_tag_create(pcs->dmat, QENTRY_LEN, 0, BUS_SPACE_MAXADDR, 1101 BUS_SPACE_MAXADDR, NULL, NULL, len, ns, bl, 0, &isp->isp_cdmat)) { 1102 isp_prt(isp, ISP_LOGERR, 1103 "cannot create a dma tag for control spaces"); 1104 free(pcs->dmaps, M_DEVBUF); 1105 free(isp->isp_xflist, M_DEVBUF); 1106 return (1); 1107 } 1108 1109 if (bus_dmamem_alloc(isp->isp_cdmat, (void **)&base, BUS_DMA_NOWAIT, 1110 &isp->isp_cdmap) != 0) { 1111 isp_prt(isp, ISP_LOGERR, 1112 "cannot allocate %d bytes of CCB memory", len); 1113 bus_dma_tag_destroy(isp->isp_cdmat); 1114 free(isp->isp_xflist, M_DEVBUF); 1115 free(pcs->dmaps, M_DEVBUF); 1116 return (1); 1117 } 1118 1119 for (i = 0; i < isp->isp_maxcmds; i++) { 1120 error = bus_dmamap_create(pcs->dmat, 0, &pcs->dmaps[i]); 1121 if (error) { 1122 isp_prt(isp, ISP_LOGERR, 1123 "error %d creating per-cmd DMA maps", error); 1124 while (--i >= 0) { 1125 bus_dmamap_destroy(pcs->dmat, pcs->dmaps[i]); 1126 } 1127 goto bad; 1128 } 1129 } 1130 1131 im.isp = isp; 1132 im.error = 0; 1133 bus_dmamap_load(isp->isp_cdmat, isp->isp_cdmap, base, len, imc, &im, 0); 1134 if (im.error) { 1135 isp_prt(isp, ISP_LOGERR, 1136 "error %d loading dma map for control areas", im.error); 1137 goto bad; 1138 } 1139 1140 isp->isp_rquest = base; 1141 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1142 isp->isp_result = base; 1143 if (IS_FC(isp)) { 1144 base += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1145 FCPARAM(isp)->isp_scratch = base; 1146 } 1147 return (0); 1148 1149 bad: 1150 bus_dmamem_free(isp->isp_cdmat, base, isp->isp_cdmap); 1151 bus_dma_tag_destroy(isp->isp_cdmat); 1152 free(isp->isp_xflist, M_DEVBUF); 1153 free(pcs->dmaps, M_DEVBUF); 1154 isp->isp_rquest = NULL; 1155 return (1); 1156 } 1157 1158 typedef struct { 1159 struct ispsoftc *isp; 1160 void *cmd_token; 1161 void *rq; 1162 u_int16_t *nxtip; 1163 u_int16_t optr; 1164 u_int error; 1165 } mush_t; 1166 1167 #define MUSHERR_NOQENTRIES -2 1168 1169 #ifdef ISP_TARGET_MODE 1170 /* 1171 * We need to handle DMA for target mode differently from initiator mode. 1172 * 1173 * DMA mapping and construction and submission of CTIO Request Entries 1174 * and rendevous for completion are very tightly coupled because we start 1175 * out by knowing (per platform) how much data we have to move, but we 1176 * don't know, up front, how many DMA mapping segments will have to be used 1177 * cover that data, so we don't know how many CTIO Request Entries we 1178 * will end up using. Further, for performance reasons we may want to 1179 * (on the last CTIO for Fibre Channel), send status too (if all went well). 1180 * 1181 * The standard vector still goes through isp_pci_dmasetup, but the callback 1182 * for the DMA mapping routines comes here instead with the whole transfer 1183 * mapped and a pointer to a partially filled in already allocated request 1184 * queue entry. We finish the job. 1185 */ 1186 static void tdma_mk(void *, bus_dma_segment_t *, int, int); 1187 static void tdma_mkfc(void *, bus_dma_segment_t *, int, int); 1188 1189 #define STATUS_WITH_DATA 1 1190 1191 static void 1192 tdma_mk(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1193 { 1194 mush_t *mp; 1195 struct ccb_scsiio *csio; 1196 struct ispsoftc *isp; 1197 struct isp_pcisoftc *pcs; 1198 bus_dmamap_t *dp; 1199 ct_entry_t *cto, *qe; 1200 u_int8_t scsi_status; 1201 u_int16_t curi, nxti, handle; 1202 u_int32_t sflags; 1203 int32_t resid; 1204 int nth_ctio, nctios, send_status; 1205 1206 mp = (mush_t *) arg; 1207 if (error) { 1208 mp->error = error; 1209 return; 1210 } 1211 1212 isp = mp->isp; 1213 csio = mp->cmd_token; 1214 cto = mp->rq; 1215 curi = isp->isp_reqidx; 1216 qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1217 1218 cto->ct_xfrlen = 0; 1219 cto->ct_seg_count = 0; 1220 cto->ct_header.rqs_entry_count = 1; 1221 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1222 1223 if (nseg == 0) { 1224 cto->ct_header.rqs_seqno = 1; 1225 isp_prt(isp, ISP_LOGTDEBUG1, 1226 "CTIO[%x] lun%d iid%d tag %x flgs %x sts %x ssts %x res %d", 1227 cto->ct_fwhandle, csio->ccb_h.target_lun, cto->ct_iid, 1228 cto->ct_tag_val, cto->ct_flags, cto->ct_status, 1229 cto->ct_scsi_status, cto->ct_resid); 1230 ISP_TDQE(isp, "tdma_mk[no data]", curi, cto); 1231 isp_put_ctio(isp, cto, qe); 1232 return; 1233 } 1234 1235 nctios = nseg / ISP_RQDSEG; 1236 if (nseg % ISP_RQDSEG) { 1237 nctios++; 1238 } 1239 1240 /* 1241 * Save syshandle, and potentially any SCSI status, which we'll 1242 * reinsert on the last CTIO we're going to send. 1243 */ 1244 1245 handle = cto->ct_syshandle; 1246 cto->ct_syshandle = 0; 1247 cto->ct_header.rqs_seqno = 0; 1248 send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; 1249 1250 if (send_status) { 1251 sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); 1252 cto->ct_flags &= ~(CT_SENDSTATUS | CT_CCINCR); 1253 /* 1254 * Preserve residual. 1255 */ 1256 resid = cto->ct_resid; 1257 1258 /* 1259 * Save actual SCSI status. 1260 */ 1261 scsi_status = cto->ct_scsi_status; 1262 1263 #ifndef STATUS_WITH_DATA 1264 sflags |= CT_NO_DATA; 1265 /* 1266 * We can't do a status at the same time as a data CTIO, so 1267 * we need to synthesize an extra CTIO at this level. 1268 */ 1269 nctios++; 1270 #endif 1271 } else { 1272 sflags = scsi_status = resid = 0; 1273 } 1274 1275 cto->ct_resid = 0; 1276 cto->ct_scsi_status = 0; 1277 1278 pcs = (struct isp_pcisoftc *)isp; 1279 dp = &pcs->dmaps[isp_handle_index(handle)]; 1280 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1281 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1282 } else { 1283 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1284 } 1285 1286 nxti = *mp->nxtip; 1287 1288 for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { 1289 int seglim; 1290 1291 seglim = nseg; 1292 if (seglim) { 1293 int seg; 1294 1295 if (seglim > ISP_RQDSEG) 1296 seglim = ISP_RQDSEG; 1297 1298 for (seg = 0; seg < seglim; seg++, nseg--) { 1299 /* 1300 * Unlike normal initiator commands, we don't 1301 * do any swizzling here. 1302 */ 1303 cto->ct_dataseg[seg].ds_count = dm_segs->ds_len; 1304 cto->ct_dataseg[seg].ds_base = dm_segs->ds_addr; 1305 cto->ct_xfrlen += dm_segs->ds_len; 1306 dm_segs++; 1307 } 1308 cto->ct_seg_count = seg; 1309 } else { 1310 /* 1311 * This case should only happen when we're sending an 1312 * extra CTIO with final status. 1313 */ 1314 if (send_status == 0) { 1315 isp_prt(isp, ISP_LOGWARN, 1316 "tdma_mk ran out of segments"); 1317 mp->error = EINVAL; 1318 return; 1319 } 1320 } 1321 1322 /* 1323 * At this point, the fields ct_lun, ct_iid, ct_tagval, 1324 * ct_tagtype, and ct_timeout have been carried over 1325 * unchanged from what our caller had set. 1326 * 1327 * The dataseg fields and the seg_count fields we just got 1328 * through setting. The data direction we've preserved all 1329 * along and only clear it if we're now sending status. 1330 */ 1331 1332 if (nth_ctio == nctios - 1) { 1333 /* 1334 * We're the last in a sequence of CTIOs, so mark 1335 * this CTIO and save the handle to the CCB such that 1336 * when this CTIO completes we can free dma resources 1337 * and do whatever else we need to do to finish the 1338 * rest of the command. We *don't* give this to the 1339 * firmware to work on- the caller will do that. 1340 */ 1341 1342 cto->ct_syshandle = handle; 1343 cto->ct_header.rqs_seqno = 1; 1344 1345 if (send_status) { 1346 cto->ct_scsi_status = scsi_status; 1347 cto->ct_flags |= sflags; 1348 cto->ct_resid = resid; 1349 } 1350 if (send_status) { 1351 isp_prt(isp, ISP_LOGTDEBUG1, 1352 "CTIO[%x] lun%d iid %d tag %x ct_flags %x " 1353 "scsi status %x resid %d", 1354 cto->ct_fwhandle, csio->ccb_h.target_lun, 1355 cto->ct_iid, cto->ct_tag_val, cto->ct_flags, 1356 cto->ct_scsi_status, cto->ct_resid); 1357 } else { 1358 isp_prt(isp, ISP_LOGTDEBUG1, 1359 "CTIO[%x] lun%d iid%d tag %x ct_flags 0x%x", 1360 cto->ct_fwhandle, csio->ccb_h.target_lun, 1361 cto->ct_iid, cto->ct_tag_val, 1362 cto->ct_flags); 1363 } 1364 isp_put_ctio(isp, cto, qe); 1365 ISP_TDQE(isp, "last tdma_mk", curi, cto); 1366 if (nctios > 1) { 1367 MEMORYBARRIER(isp, SYNC_REQUEST, 1368 curi, QENTRY_LEN); 1369 } 1370 } else { 1371 ct_entry_t *oqe = qe; 1372 1373 /* 1374 * Make sure syshandle fields are clean 1375 */ 1376 cto->ct_syshandle = 0; 1377 cto->ct_header.rqs_seqno = 0; 1378 1379 isp_prt(isp, ISP_LOGTDEBUG1, 1380 "CTIO[%x] lun%d for ID%d ct_flags 0x%x", 1381 cto->ct_fwhandle, csio->ccb_h.target_lun, 1382 cto->ct_iid, cto->ct_flags); 1383 1384 /* 1385 * Get a new CTIO 1386 */ 1387 qe = (ct_entry_t *) 1388 ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1389 nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); 1390 if (nxti == mp->optr) { 1391 isp_prt(isp, ISP_LOGTDEBUG0, 1392 "Queue Overflow in tdma_mk"); 1393 mp->error = MUSHERR_NOQENTRIES; 1394 return; 1395 } 1396 1397 /* 1398 * Now that we're done with the old CTIO, 1399 * flush it out to the request queue. 1400 */ 1401 ISP_TDQE(isp, "dma_tgt_fc", curi, cto); 1402 isp_put_ctio(isp, cto, oqe); 1403 if (nth_ctio != 0) { 1404 MEMORYBARRIER(isp, SYNC_REQUEST, curi, 1405 QENTRY_LEN); 1406 } 1407 curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); 1408 1409 /* 1410 * Reset some fields in the CTIO so we can reuse 1411 * for the next one we'll flush to the request 1412 * queue. 1413 */ 1414 cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; 1415 cto->ct_header.rqs_entry_count = 1; 1416 cto->ct_header.rqs_flags = 0; 1417 cto->ct_status = 0; 1418 cto->ct_scsi_status = 0; 1419 cto->ct_xfrlen = 0; 1420 cto->ct_resid = 0; 1421 cto->ct_seg_count = 0; 1422 MEMZERO(cto->ct_dataseg, sizeof(cto->ct_dataseg)); 1423 } 1424 } 1425 *mp->nxtip = nxti; 1426 } 1427 1428 /* 1429 * We don't have to do multiple CTIOs here. Instead, we can just do 1430 * continuation segments as needed. This greatly simplifies the code 1431 * improves performance. 1432 */ 1433 1434 static void 1435 tdma_mkfc(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1436 { 1437 mush_t *mp; 1438 struct ccb_scsiio *csio; 1439 struct ispsoftc *isp; 1440 ct2_entry_t *cto, *qe; 1441 u_int16_t curi, nxti; 1442 int segcnt; 1443 1444 mp = (mush_t *) arg; 1445 if (error) { 1446 mp->error = error; 1447 return; 1448 } 1449 1450 isp = mp->isp; 1451 csio = mp->cmd_token; 1452 cto = mp->rq; 1453 1454 curi = isp->isp_reqidx; 1455 qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); 1456 1457 if (nseg == 0) { 1458 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { 1459 isp_prt(isp, ISP_LOGWARN, 1460 "dma2_tgt_fc, a status CTIO2 without MODE1 " 1461 "set (0x%x)", cto->ct_flags); 1462 mp->error = EINVAL; 1463 return; 1464 } 1465 /* 1466 * We preserve ct_lun, ct_iid, ct_rxid. We set the data 1467 * flags to NO DATA and clear relative offset flags. 1468 * We preserve the ct_resid and the response area. 1469 */ 1470 cto->ct_header.rqs_seqno = 1; 1471 cto->ct_seg_count = 0; 1472 cto->ct_reloff = 0; 1473 isp_prt(isp, ISP_LOGTDEBUG1, 1474 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts " 1475 "0x%x res %d", cto->ct_rxid, csio->ccb_h.target_lun, 1476 cto->ct_iid, cto->ct_flags, cto->ct_status, 1477 cto->rsp.m1.ct_scsi_status, cto->ct_resid); 1478 isp_put_ctio2(isp, cto, qe); 1479 ISP_TDQE(isp, "dma2_tgt_fc[no data]", curi, qe); 1480 return; 1481 } 1482 1483 if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { 1484 isp_prt(isp, ISP_LOGERR, 1485 "dma2_tgt_fc, a data CTIO2 without MODE0 set " 1486 "(0x%x)", cto->ct_flags); 1487 mp->error = EINVAL; 1488 return; 1489 } 1490 1491 1492 nxti = *mp->nxtip; 1493 1494 /* 1495 * Set up the CTIO2 data segments. 1496 */ 1497 for (segcnt = 0; cto->ct_seg_count < ISP_RQDSEG_T2 && segcnt < nseg; 1498 cto->ct_seg_count++, segcnt++) { 1499 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_base = 1500 dm_segs[segcnt].ds_addr; 1501 cto->rsp.m0.ct_dataseg[cto->ct_seg_count].ds_count = 1502 dm_segs[segcnt].ds_len; 1503 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1504 isp_prt(isp, ISP_LOGTDEBUG1, "isp_send_ctio2: ent0[%d]0x%x:%d", 1505 cto->ct_seg_count, dm_segs[segcnt].ds_addr, 1506 dm_segs[segcnt].ds_len); 1507 } 1508 1509 while (segcnt < nseg) { 1510 u_int16_t curip; 1511 int seg; 1512 ispcontreq_t local, *crq = &local, *qep; 1513 1514 qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1515 curip = nxti; 1516 nxti = ISP_NXT_QENTRY(curip, RQUEST_QUEUE_LEN(isp)); 1517 if (nxti == mp->optr) { 1518 ISP_UNLOCK(isp); 1519 isp_prt(isp, ISP_LOGTDEBUG0, 1520 "tdma_mkfc: request queue overflow"); 1521 mp->error = MUSHERR_NOQENTRIES; 1522 return; 1523 } 1524 cto->ct_header.rqs_entry_count++; 1525 MEMZERO((void *)crq, sizeof (*crq)); 1526 crq->req_header.rqs_entry_count = 1; 1527 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1528 for (seg = 0; segcnt < nseg && seg < ISP_CDSEG; 1529 segcnt++, seg++) { 1530 crq->req_dataseg[seg].ds_base = dm_segs[segcnt].ds_addr; 1531 crq->req_dataseg[seg].ds_count = dm_segs[segcnt].ds_len; 1532 isp_prt(isp, ISP_LOGTDEBUG1, 1533 "isp_send_ctio2: ent%d[%d]%x:%u", 1534 cto->ct_header.rqs_entry_count-1, seg, 1535 dm_segs[segcnt].ds_addr, dm_segs[segcnt].ds_len); 1536 cto->rsp.m0.ct_xfrlen += dm_segs[segcnt].ds_len; 1537 cto->ct_seg_count++; 1538 } 1539 MEMORYBARRIER(isp, SYNC_REQUEST, curip, QENTRY_LEN); 1540 isp_put_cont_req(isp, crq, qep); 1541 ISP_TDQE(isp, "cont entry", curi, qep); 1542 } 1543 1544 /* 1545 * No do final twiddling for the CTIO itself. 1546 */ 1547 cto->ct_header.rqs_seqno = 1; 1548 isp_prt(isp, ISP_LOGTDEBUG1, 1549 "CTIO2[%x] lun %d->iid%d flgs 0x%x sts 0x%x ssts 0x%x resid %d", 1550 cto->ct_rxid, csio->ccb_h.target_lun, (int) cto->ct_iid, 1551 cto->ct_flags, cto->ct_status, cto->rsp.m1.ct_scsi_status, 1552 cto->ct_resid); 1553 isp_put_ctio2(isp, cto, qe); 1554 ISP_TDQE(isp, "last dma2_tgt_fc", curi, qe); 1555 *mp->nxtip = nxti; 1556 } 1557 #endif 1558 1559 static void dma2(void *, bus_dma_segment_t *, int, int); 1560 1561 static void 1562 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1563 { 1564 mush_t *mp; 1565 struct ispsoftc *isp; 1566 struct ccb_scsiio *csio; 1567 struct isp_pcisoftc *pcs; 1568 bus_dmamap_t *dp; 1569 bus_dma_segment_t *eseg; 1570 ispreq_t *rq; 1571 int seglim, datalen; 1572 u_int16_t nxti; 1573 1574 mp = (mush_t *) arg; 1575 if (error) { 1576 mp->error = error; 1577 return; 1578 } 1579 1580 if (nseg < 1) { 1581 isp_prt(mp->isp, ISP_LOGERR, "bad segment count (%d)", nseg); 1582 mp->error = EFAULT; 1583 return; 1584 } 1585 csio = mp->cmd_token; 1586 isp = mp->isp; 1587 rq = mp->rq; 1588 pcs = (struct isp_pcisoftc *)mp->isp; 1589 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1590 nxti = *mp->nxtip; 1591 1592 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1593 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREREAD); 1594 } else { 1595 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_PREWRITE); 1596 } 1597 1598 datalen = XS_XFRLEN(csio); 1599 1600 /* 1601 * We're passed an initial partially filled in entry that 1602 * has most fields filled in except for data transfer 1603 * related values. 1604 * 1605 * Our job is to fill in the initial request queue entry and 1606 * then to start allocating and filling in continuation entries 1607 * until we've covered the entire transfer. 1608 */ 1609 1610 if (IS_FC(isp)) { 1611 seglim = ISP_RQDSEG_T2; 1612 ((ispreqt2_t *)rq)->req_totalcnt = datalen; 1613 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1614 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; 1615 } else { 1616 ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; 1617 } 1618 } else { 1619 if (csio->cdb_len > 12) { 1620 seglim = 0; 1621 } else { 1622 seglim = ISP_RQDSEG; 1623 } 1624 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1625 rq->req_flags |= REQFLAG_DATA_IN; 1626 } else { 1627 rq->req_flags |= REQFLAG_DATA_OUT; 1628 } 1629 } 1630 1631 eseg = dm_segs + nseg; 1632 1633 while (datalen != 0 && rq->req_seg_count < seglim && dm_segs != eseg) { 1634 if (IS_FC(isp)) { 1635 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1636 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1637 dm_segs->ds_addr; 1638 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1639 dm_segs->ds_len; 1640 } else { 1641 rq->req_dataseg[rq->req_seg_count].ds_base = 1642 dm_segs->ds_addr; 1643 rq->req_dataseg[rq->req_seg_count].ds_count = 1644 dm_segs->ds_len; 1645 } 1646 datalen -= dm_segs->ds_len; 1647 rq->req_seg_count++; 1648 dm_segs++; 1649 } 1650 1651 while (datalen > 0 && dm_segs != eseg) { 1652 u_int16_t onxti; 1653 ispcontreq_t local, *crq = &local, *cqe; 1654 1655 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1656 onxti = nxti; 1657 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1658 if (nxti == mp->optr) { 1659 isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow++"); 1660 mp->error = MUSHERR_NOQENTRIES; 1661 return; 1662 } 1663 rq->req_header.rqs_entry_count++; 1664 MEMZERO((void *)crq, sizeof (*crq)); 1665 crq->req_header.rqs_entry_count = 1; 1666 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1667 1668 seglim = 0; 1669 while (datalen > 0 && seglim < ISP_CDSEG && dm_segs != eseg) { 1670 crq->req_dataseg[seglim].ds_base = 1671 dm_segs->ds_addr; 1672 crq->req_dataseg[seglim].ds_count = 1673 dm_segs->ds_len; 1674 rq->req_seg_count++; 1675 dm_segs++; 1676 seglim++; 1677 datalen -= dm_segs->ds_len; 1678 } 1679 isp_put_cont_req(isp, crq, cqe); 1680 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1681 } 1682 *mp->nxtip = nxti; 1683 } 1684 1685 static int 1686 isp_pci_dmasetup(struct ispsoftc *isp, struct ccb_scsiio *csio, ispreq_t *rq, 1687 u_int16_t *nxtip, u_int16_t optr) 1688 { 1689 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1690 ispreq_t *qep; 1691 bus_dmamap_t *dp = NULL; 1692 mush_t mush, *mp; 1693 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1694 1695 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); 1696 #ifdef ISP_TARGET_MODE 1697 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1698 if (IS_FC(isp)) { 1699 eptr = tdma_mkfc; 1700 } else { 1701 eptr = tdma_mk; 1702 } 1703 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1704 (csio->dxfer_len == 0)) { 1705 mp = &mush; 1706 mp->isp = isp; 1707 mp->cmd_token = csio; 1708 mp->rq = rq; /* really a ct_entry_t or ct2_entry_t */ 1709 mp->nxtip = nxtip; 1710 mp->optr = optr; 1711 mp->error = 0; 1712 (*eptr)(mp, NULL, 0, 0); 1713 goto mbxsync; 1714 } 1715 } else 1716 #endif 1717 eptr = dma2; 1718 1719 1720 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || 1721 (csio->dxfer_len == 0)) { 1722 rq->req_seg_count = 1; 1723 goto mbxsync; 1724 } 1725 1726 /* 1727 * Do a virtual grapevine step to collect info for 1728 * the callback dma allocation that we have to use... 1729 */ 1730 mp = &mush; 1731 mp->isp = isp; 1732 mp->cmd_token = csio; 1733 mp->rq = rq; 1734 mp->nxtip = nxtip; 1735 mp->optr = optr; 1736 mp->error = 0; 1737 1738 if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1739 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1740 int error, s; 1741 dp = &pcs->dmaps[isp_handle_index(rq->req_handle)]; 1742 s = splsoftvm(); 1743 error = bus_dmamap_load(pcs->dmat, *dp, 1744 csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1745 if (error == EINPROGRESS) { 1746 bus_dmamap_unload(pcs->dmat, *dp); 1747 mp->error = EINVAL; 1748 isp_prt(isp, ISP_LOGERR, 1749 "deferred dma allocation not supported"); 1750 } else if (error && mp->error == 0) { 1751 #ifdef DIAGNOSTIC 1752 isp_prt(isp, ISP_LOGERR, 1753 "error %d in dma mapping code", error); 1754 #endif 1755 mp->error = error; 1756 } 1757 splx(s); 1758 } else { 1759 /* Pointer to physical buffer */ 1760 struct bus_dma_segment seg; 1761 seg.ds_addr = (bus_addr_t)csio->data_ptr; 1762 seg.ds_len = csio->dxfer_len; 1763 (*eptr)(mp, &seg, 1, 0); 1764 } 1765 } else { 1766 struct bus_dma_segment *segs; 1767 1768 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1769 isp_prt(isp, ISP_LOGERR, 1770 "Physical segment pointers unsupported"); 1771 mp->error = EINVAL; 1772 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1773 isp_prt(isp, ISP_LOGERR, 1774 "Virtual segment addresses unsupported"); 1775 mp->error = EINVAL; 1776 } else { 1777 /* Just use the segments provided */ 1778 segs = (struct bus_dma_segment *) csio->data_ptr; 1779 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1780 } 1781 } 1782 if (mp->error) { 1783 int retval = CMD_COMPLETE; 1784 if (mp->error == MUSHERR_NOQENTRIES) { 1785 retval = CMD_EAGAIN; 1786 } else if (mp->error == EFBIG) { 1787 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1788 } else if (mp->error == EINVAL) { 1789 XS_SETERR(csio, CAM_REQ_INVALID); 1790 } else { 1791 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1792 } 1793 return (retval); 1794 } 1795 mbxsync: 1796 switch (rq->req_header.rqs_entry_type) { 1797 case RQSTYPE_REQUEST: 1798 isp_put_request(isp, rq, qep); 1799 break; 1800 case RQSTYPE_CMDONLY: 1801 isp_put_extended_request(isp, (ispextreq_t *)rq, 1802 (ispextreq_t *)qep); 1803 break; 1804 case RQSTYPE_T2RQS: 1805 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1806 break; 1807 } 1808 return (CMD_QUEUED); 1809 } 1810 1811 static void 1812 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1813 { 1814 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1815 bus_dmamap_t *dp = &pcs->dmaps[isp_handle_index(handle)]; 1816 if ((xs->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1817 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTREAD); 1818 } else { 1819 bus_dmamap_sync(pcs->dmat, *dp, BUS_DMASYNC_POSTWRITE); 1820 } 1821 bus_dmamap_unload(pcs->dmat, *dp); 1822 } 1823 1824 1825 static void 1826 isp_pci_reset1(struct ispsoftc *isp) 1827 { 1828 /* Make sure the BIOS is disabled */ 1829 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1830 /* and enable interrupts */ 1831 ENABLE_INTS(isp); 1832 } 1833 1834 static void 1835 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1836 { 1837 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1838 if (msg) 1839 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1840 else 1841 printf("%s:\n", device_get_nameunit(isp->isp_dev)); 1842 if (IS_SCSI(isp)) 1843 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1844 else 1845 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1846 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1847 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1848 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1849 1850 1851 if (IS_SCSI(isp)) { 1852 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1853 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1854 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1855 ISP_READ(isp, CDMA_FIFO_STS)); 1856 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1857 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1858 ISP_READ(isp, DDMA_FIFO_STS)); 1859 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1860 ISP_READ(isp, SXP_INTERRUPT), 1861 ISP_READ(isp, SXP_GROSS_ERR), 1862 ISP_READ(isp, SXP_PINS_CTRL)); 1863 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1864 } 1865 printf(" mbox regs: %x %x %x %x %x\n", 1866 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1867 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1868 ISP_READ(isp, OUTMAILBOX4)); 1869 printf(" PCI Status Command/Status=%x\n", 1870 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 1871 } 1872