1 /*- 2 * Copyright (c) 2015 Michael Gmelin <freebsd@grem.de> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _ISL_H_ 28 #define _ISL_H_ 29 30 /* Command register 1 (bits 7-5) */ 31 #define REG_CMD1 0x00 32 #define CMD1_MASK_POWER_DOWN 0x00 /* 00000000 */ 33 #define CMD1_MASK_ALS_ONCE 0x01 << 5 /* 00100000 */ 34 #define CMD1_MASK_IR_ONCE 0x02 << 5 /* 01000000 */ 35 #define CMD1_MASK_PROX_ONCE 0x03 << 5 /* 01100000 */ 36 /* RESERVED */ /* 10000000 */ 37 #define CMD1_MASK_ALS_CONT 0x05 << 5 /* 10100000 */ 38 #define CMD1_MASK_IR_CONT 0x06 << 5 /* 11000000 */ 39 #define CMD1_MASK_PROX_CONT 0x07 << 5 /* 11100000 */ 40 41 /* Command register 2 (bits) */ 42 #define REG_CMD2 0x01 43 44 /* data registers */ 45 #define REG_DATA1 0x02 46 #define REG_DATA2 0x03 47 #define CMD2_SHIFT_RANGE 0x00 48 #define CMD2_MASK_RANGE (0x03 << CMD2_SHIFT_RANGE) 49 #define CMD2_SHIFT_RESOLUTION 0x02 50 #define CMD2_MASK_RESOLUTION (0x03 << CMD2_SHIFT_RESOLUTION) 51 52 /* Interrupt registers */ 53 #define REG_INT_LO_LSB 0x04 54 #define REG_INT_LO_MSB 0x05 55 #define REG_INT_HI_LSB 0x06 56 #define REG_INT_HI_MSB 0x07 57 58 /* Test register (should hold 0x00 at all times */ 59 #define REG_TEST 0x08 60 61 #endif 62