1 /*- 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 33 * * Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * * Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in 37 * the documentation and/or other materials provided with the 38 * distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 * $FreeBSD$ 53 */ 54 #ifndef _SCIF_SAS_CONTROLLER_H_ 55 #define _SCIF_SAS_CONTROLLER_H_ 56 57 /** 58 * @file 59 * 60 * @brief This file contains the protected interface structures, constants, 61 * and methods for the SCIF_SAS_CONTROLLER object. 62 */ 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif // __cplusplus 67 68 #include <dev/isci/scil/sci_types.h> 69 #include <dev/isci/scil/sci_abstract_list.h> 70 #include <dev/isci/scil/sci_controller_constants.h> 71 #include <dev/isci/scil/sci_memory_descriptor_list.h> 72 #include <dev/isci/scil/sci_base_controller.h> 73 #include <dev/isci/scil/scif_controller.h> 74 #include <dev/isci/scil/scif_config_parameters.h> 75 #include <dev/isci/scil/scif_sas_domain.h> 76 #include <dev/isci/scil/scif_sas_io_request.h> 77 #include <dev/isci/scil/scif_sas_task_request.h> 78 #include <dev/isci/scil/scif_sas_constants.h> 79 #include <dev/isci/scil/sci_pool.h> 80 #include <dev/isci/scil/scif_sas_internal_io_request.h> 81 #include <dev/isci/scil/scif_sas_high_priority_request_queue.h> 82 #include <dev/isci/scil/scif_sas_smp_phy.h> 83 84 85 // Currently there is only a need for 1 memory descriptor. This descriptor 86 // describes the internal IO request memory. 87 #define SCIF_SAS_MAX_MEMORY_DESCRIPTORS 1 88 89 enum _SCIF_SAS_MAX_MEMORY_DESCRIPTORS 90 { 91 SCIF_SAS_MDE_INTERNAL_IO = 0 92 93 }; 94 95 /** 96 * @struct SCIF_SAS_CONTROLLER 97 * 98 * @brief The SCI SAS Framework controller object abstracts storage controller 99 * level behavior for the framework component. 100 */ 101 typedef struct SCIF_SAS_CONTROLLER 102 { 103 /** 104 * The SCI_BASE_CONTROLLER is the parent object for the SCIF_SAS_CONTROLLER 105 * object. 106 */ 107 SCI_BASE_CONTROLLER_T parent; 108 109 /** 110 * This field contains the handle for the SCI Core controller object that 111 * is managed by this framework controller. 112 */ 113 SCI_CONTROLLER_HANDLE_T core_object; 114 115 /** 116 * This field references the list of state specific handler methods to 117 * be utilized for this controller instance. 118 */ 119 SCI_BASE_CONTROLLER_STATE_HANDLER_T * state_handlers; 120 121 /** 122 * This field contains the memory desciptors defining the physical 123 * memory requirements for this controller. 124 */ 125 SCI_PHYSICAL_MEMORY_DESCRIPTOR_T mdes[SCIF_SAS_MAX_MEMORY_DESCRIPTORS]; 126 127 /** 128 * This field contains the SAS domain objects managed by this controller. 129 */ 130 SCIF_SAS_DOMAIN_T domains[SCI_MAX_DOMAINS]; 131 132 /** 133 * This field represents the pool of available remote device objects 134 * supported by the controller. 135 */ 136 SCI_ABSTRACT_ELEMENT_POOL_T free_remote_device_pool; 137 138 /** 139 * This field contains the maximum number of abstract elements that 140 * can be placed in the pool. 141 */ 142 SCI_ABSTRACT_ELEMENT_T remote_device_pool_elements[SCI_MAX_REMOTE_DEVICES]; 143 144 /** 145 * This field provides the controller object a scratch area to indicate 146 * status of an ongoing operation. 147 */ 148 SCI_STATUS operation_status; 149 150 /** 151 * This field will contain an user specified parameter information 152 * to be utilized by the framework. 153 */ 154 SCIF_USER_PARAMETERS_T user_parameters; 155 156 /** 157 * This field records the index for the current domain to clear affiliation 158 * EA SATA remote devices, during the controller stop process. 159 */ 160 U8 current_domain_to_clear_affiliation; 161 162 U32 internal_request_entries; 163 164 /** 165 * This field provides a pool to manage the memory resource for all internal 166 * requests. 167 * requests. 168 */ 169 SCI_POOL_CREATE( 170 internal_request_memory_pool, 171 POINTER_UINT, 172 SCIF_SAS_MAX_INTERNAL_REQUEST_COUNT 173 ); 174 175 /** 176 * This field provides a queue for built internal requests waiting to be 177 * started. 178 */ 179 SCIF_SAS_HIGH_PRIORITY_REQUEST_QUEUE_T hprq; 180 181 /** 182 * This represents the number of available SMP phy objects that can 183 * be managed by the framework. 184 */ 185 SCIF_SAS_SMP_PHY_T smp_phy_array[SCIF_SAS_SMP_PHY_COUNT]; 186 187 /** 188 * This field provides a list to manage the memory resource for all 189 * smp_phy objects. 190 */ 191 SCI_FAST_LIST_T smp_phy_memory_list; 192 193 #if !defined(DISABLE_INTERRUPTS) 194 /** 195 * This field saves the interrupt coalescing count before changing interrupt 196 * coalescence. 197 */ 198 U16 saved_interrupt_coalesce_number; 199 200 /** 201 * This field saves the interrupt coalescing timeout values in micorseconds 202 * before changing interrupt coalescence. 203 */ 204 U32 saved_interrupt_coalesce_timeout; 205 #endif // !defined(DISABLE_INTERRUPTS) 206 207 } SCIF_SAS_CONTROLLER_T; 208 209 extern SCI_BASE_STATE_T scif_sas_controller_state_table[]; 210 extern SCI_BASE_CONTROLLER_STATE_HANDLER_T 211 scif_sas_controller_state_handler_table[]; 212 213 SCI_STATUS scif_sas_controller_continue_io( 214 SCI_CONTROLLER_HANDLE_T controller, 215 SCI_REMOTE_DEVICE_HANDLE_T remote_device, 216 SCI_IO_REQUEST_HANDLE_T io_request 217 ); 218 219 void scif_sas_controller_destruct( 220 SCIF_SAS_CONTROLLER_T * fw_controller 221 ); 222 223 void * scif_sas_controller_allocate_internal_request( 224 SCIF_SAS_CONTROLLER_T * fw_controller 225 ); 226 227 void scif_sas_controller_free_internal_request( 228 SCIF_SAS_CONTROLLER_T * fw_controller, 229 void * fw_internal_request_buffer 230 ); 231 232 void scif_sas_controller_start_high_priority_io( 233 SCIF_SAS_CONTROLLER_T * fw_controller 234 ); 235 236 BOOL scif_sas_controller_sufficient_resource( 237 SCIF_SAS_CONTROLLER_T *fw_controller 238 ); 239 240 SCI_STATUS scif_sas_controller_complete_high_priority_io( 241 SCIF_SAS_CONTROLLER_T * fw_controller, 242 SCIF_SAS_REMOTE_DEVICE_T * remote_device, 243 SCIF_SAS_REQUEST_T * io_request 244 ); 245 246 SCIF_SAS_SMP_PHY_T * scif_sas_controller_allocate_smp_phy( 247 SCIF_SAS_CONTROLLER_T * fw_controller 248 ); 249 250 void scif_sas_controller_free_smp_phy( 251 SCIF_SAS_CONTROLLER_T * fw_controller, 252 SCIF_SAS_SMP_PHY_T * smp_phy 253 ); 254 255 SCI_STATUS scif_sas_controller_clear_affiliation( 256 SCIF_SAS_CONTROLLER_T * fw_controller 257 ); 258 259 SCI_STATUS scif_sas_controller_continue_to_stop( 260 SCIF_SAS_CONTROLLER_T * fw_controller 261 ); 262 263 void scif_sas_controller_set_default_config_parameters( 264 SCIF_SAS_CONTROLLER_T * this_controller 265 ); 266 267 SCI_STATUS scif_sas_controller_release_resource( 268 SCIF_SAS_CONTROLLER_T * fw_controller 269 ); 270 271 void scif_sas_controller_build_mdl( 272 SCIF_SAS_CONTROLLER_T * fw_controller 273 ); 274 275 #if !defined(DISABLE_INTERRUPTS) 276 277 void scif_sas_controller_save_interrupt_coalescence( 278 SCIF_SAS_CONTROLLER_T * fw_controller 279 ); 280 281 void scif_sas_controller_restore_interrupt_coalescence( 282 SCIF_SAS_CONTROLLER_T * fw_controller 283 ); 284 285 #else // !defined(DISABLE_INTERRUPTS) 286 #define scif_sas_controller_save_interrupt_coalescence(controller) 287 #define scif_sas_controller_restore_interrupt_coalescence(controller) 288 #endif // !defined(DISABLE_INTERRUPTS) 289 290 #ifdef SCI_LOGGING 291 void scif_sas_controller_initialize_state_logging( 292 SCIF_SAS_CONTROLLER_T *this_controller 293 ); 294 295 void scif_sas_controller_deinitialize_state_logging( 296 SCIF_SAS_CONTROLLER_T *this_controller 297 ); 298 #else // SCI_LOGGING 299 #define scif_sas_controller_initialize_state_logging(x) 300 #define scif_sas_controller_deinitialize_state_logging(x) 301 #endif // SCI_LOGGING 302 303 #ifdef __cplusplus 304 } 305 #endif // __cplusplus 306 307 #endif // _SCIF_SAS_CONTROLLER_H_ 308 309