1 /*- 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 33 * * Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * * Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in 37 * the documentation and/or other materials provided with the 38 * distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 * $FreeBSD$ 53 */ 54 #ifndef _SCIC_SDS_PCI_H_ 55 #define _SCIC_SDS_PCI_H_ 56 57 /** 58 * @file 59 * 60 * @brief This file contains the prototypes/macros utilized in writing 61 * out PCI data for the SCI core. 62 */ 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif // __cplusplus 67 68 #include <dev/isci/scil/sci_types.h> 69 70 #define PATSBURG_SMU_BAR 0 71 #define PATSBURG_SCU_BAR 1 72 #define PATSBURG_IO_SPACE_BAR0 2 73 #define PATSBURG_IO_SPACE_BAR1 3 74 75 #define SCIC_SDS_PCI_REVISION_A0 0 76 #define SCIC_SDS_PCI_REVISION_A2 2 77 #define SCIC_SDS_PCI_REVISION_B0 4 78 #define SCIC_SDS_PCI_REVISION_C0 5 79 #define SCIC_SDS_PCI_REVISION_C1 6 80 81 enum SCU_CONTROLLER_PCI_REVISION_CODE 82 { 83 SCU_PBG_HBA_REV_A0 = SCIC_SDS_PCI_REVISION_A0, 84 SCU_PBG_HBA_REV_A2 = SCIC_SDS_PCI_REVISION_A2, 85 SCU_PBG_HBA_REV_B0 = SCIC_SDS_PCI_REVISION_B0, 86 SCU_PBG_HBA_REV_C0 = SCIC_SDS_PCI_REVISION_C0, 87 SCU_PBG_HBA_REV_C1 = SCIC_SDS_PCI_REVISION_C1 88 }; 89 90 struct SCIC_SDS_CONTROLLER; 91 92 void scic_sds_pci_bar_initialization( 93 struct SCIC_SDS_CONTROLLER * this_controller 94 ); 95 96 #if !defined(ENABLE_PCI_IO_SPACE_ACCESS) || defined(ARLINGTON_BUILD) 97 98 #define scic_sds_pci_read_smu_dword scic_cb_pci_read_dword 99 #define scic_sds_pci_write_smu_dword scic_cb_pci_write_dword 100 #define scic_sds_pci_read_scu_dword scic_cb_pci_read_dword 101 #define scic_sds_pci_write_scu_dword scic_cb_pci_write_dword 102 103 #else // !defined(ENABLE_PCI_IO_SPACE_ACCESS) 104 105 // These two registers form the Data/Index pair equivalent in the 106 // SCU. They are only used for access registers in BAR 1, not BAR 0. 107 #define SCU_MMR_ADDRESS_WINDOW_OFFSET 0xA0 108 #define SCU_MMR_DATA_WINDOW_OFFSET 0xA4 109 110 U32 scic_sds_pci_read_smu_dword( 111 SCI_CONTROLLER_HANDLE_T controller, 112 void * address 113 ); 114 115 void scic_sds_pci_write_smu_dword( 116 SCI_CONTROLLER_HANDLE_T controller, 117 void * address, 118 U32 write_value 119 ); 120 121 U32 scic_sds_pci_read_scu_dword( 122 SCI_CONTROLLER_HANDLE_T controller, 123 void * address 124 ); 125 126 void scic_sds_pci_write_scu_dword( 127 SCI_CONTROLLER_HANDLE_T controller, 128 void * address, 129 U32 write_value 130 ); 131 132 #endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS) 133 134 #ifdef __cplusplus 135 } 136 #endif // __cplusplus 137 138 #endif // _SCIC_SDS_PCI_H_ 139