1 /*- 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 33 * * Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * * Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in 37 * the documentation and/or other materials provided with the 38 * distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 * $FreeBSD$ 53 */ 54 #ifndef _SCI_BASE_CONTROLLER_H_ 55 #define _SCI_BASE_CONTROLLER_H_ 56 57 /** 58 * @file 59 * 60 * @brief This file contains all of the structures, constants, and methods 61 * common to all controller object definitions. 62 */ 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif // __cplusplus 67 68 #include <dev/isci/scil/intel_sas.h> 69 #include <dev/isci/scil/sci_controller_constants.h> 70 71 #include <dev/isci/scil/sci_base_object.h> 72 #include <dev/isci/scil/sci_base_state.h> 73 #include <dev/isci/scil/sci_base_logger.h> 74 #include <dev/isci/scil/sci_base_memory_descriptor_list.h> 75 #include <dev/isci/scil/sci_base_state_machine.h> 76 #include <dev/isci/scil/sci_base_state_machine_logger.h> 77 78 /** 79 * @enum SCI_BASE_CONTROLLER_STATES 80 * 81 * @brief This enumeration depicts all the states for the common controller 82 * state machine. 83 */ 84 typedef enum _SCI_BASE_CONTROLLER_STATES 85 { 86 /** 87 * Simply the initial state for the base controller state machine. 88 */ 89 SCI_BASE_CONTROLLER_STATE_INITIAL = 0, 90 91 /** 92 * This state indicates that the controller is reset. The memory for 93 * the controller is in it's initial state, but the controller requires 94 * initialization. 95 * This state is entered from the INITIAL state. 96 * This state is entered from the RESETTING state. 97 */ 98 SCI_BASE_CONTROLLER_STATE_RESET, 99 100 /** 101 * This state is typically an action state that indicates the controller 102 * is in the process of initialization. In this state no new IO operations 103 * are permitted. 104 * This state is entered from the RESET state. 105 */ 106 SCI_BASE_CONTROLLER_STATE_INITIALIZING, 107 108 /** 109 * This state indicates that the controller has been successfully 110 * initialized. In this state no new IO operations are permitted. 111 * This state is entered from the INITIALIZING state. 112 */ 113 SCI_BASE_CONTROLLER_STATE_INITIALIZED, 114 115 /** 116 * This state indicates the controller is in the process of becoming 117 * ready (i.e. starting). In this state no new IO operations are permitted. 118 * This state is entered from the INITIALIZED state. 119 */ 120 SCI_BASE_CONTROLLER_STATE_STARTING, 121 122 /** 123 * This state indicates the controller is now ready. Thus, the user 124 * is able to perform IO operations on the controller. 125 * This state is entered from the STARTING state. 126 */ 127 SCI_BASE_CONTROLLER_STATE_READY, 128 129 /** 130 * This state is typically an action state that indicates the controller 131 * is in the process of resetting. Thus, the user is unable to perform 132 * IO operations on the controller. A reset is considered destructive in 133 * most cases. 134 * This state is entered from the READY state. 135 * This state is entered from the FAILED state. 136 * This state is entered from the STOPPED state. 137 */ 138 SCI_BASE_CONTROLLER_STATE_RESETTING, 139 140 /** 141 * This state indicates that the controller is in the process of stopping. 142 * In this state no new IO operations are permitted, but existing IO 143 * operations are allowed to complete. 144 * This state is entered from the READY state. 145 */ 146 SCI_BASE_CONTROLLER_STATE_STOPPING, 147 148 /** 149 * This state indicates that the controller has successfully been stopped. 150 * In this state no new IO operations are permitted. 151 * This state is entered from the STOPPING state. 152 */ 153 SCI_BASE_CONTROLLER_STATE_STOPPED, 154 155 /** 156 * This state indicates that the controller could not successfully be 157 * initialized. In this state no new IO operations are permitted. 158 * This state is entered from the INITIALIZING state. 159 * This state is entered from the STARTING state. 160 * This state is entered from the STOPPING state. 161 * This state is entered from the RESETTING state. 162 */ 163 SCI_BASE_CONTROLLER_STATE_FAILED, 164 165 SCI_BASE_CONTROLLER_MAX_STATES 166 167 } SCI_BASE_CONTROLLER_STATES; 168 169 /** 170 * @struct SCI_BASE_CONTROLLER 171 * 172 * @brief The base controller object abstracts the fields common to all 173 * SCI controller objects. 174 */ 175 typedef struct SCI_BASE_CONTROLLER 176 { 177 /** 178 * The field specifies that the parent object for the base controller 179 * is the base object itself. 180 */ 181 SCI_BASE_OBJECT_T parent; 182 183 /** 184 * This field points to the memory descriptor list associated with this 185 * controller. The MDL indicates the memory requirements necessary for 186 * this controller object. 187 */ 188 SCI_BASE_MEMORY_DESCRIPTOR_LIST_T mdl; 189 190 /** 191 * This field records the fact that the controller has encountered a fatal memory 192 * error and controller must stay in failed state. 193 */ 194 U8 error; 195 196 /** 197 * This field contains the information for the base controller state 198 * machine. 199 */ 200 SCI_BASE_STATE_MACHINE_T state_machine; 201 202 #ifdef SCI_LOGGING 203 SCI_BASE_STATE_MACHINE_LOGGER_T state_machine_logger; 204 #endif // SCI_LOGGING 205 206 } SCI_BASE_CONTROLLER_T; 207 208 // Forward declarations 209 struct SCI_BASE_REMOTE_DEVICE; 210 struct SCI_BASE_REQUEST; 211 212 typedef SCI_STATUS (*SCI_BASE_CONTROLLER_HANDLER_T)( 213 SCI_BASE_CONTROLLER_T * 214 ); 215 216 typedef SCI_STATUS (*SCI_BASE_CONTROLLER_TIMED_HANDLER_T)( 217 SCI_BASE_CONTROLLER_T *, 218 U32 219 ); 220 221 typedef SCI_STATUS (*SCI_BASE_CONTROLLER_REQUEST_HANDLER_T)( 222 SCI_BASE_CONTROLLER_T *, 223 struct SCI_BASE_REMOTE_DEVICE *, 224 struct SCI_BASE_REQUEST * 225 ); 226 227 typedef SCI_STATUS (*SCI_BASE_CONTROLLER_START_REQUEST_HANDLER_T)( 228 SCI_BASE_CONTROLLER_T *, 229 struct SCI_BASE_REMOTE_DEVICE *, 230 struct SCI_BASE_REQUEST *, 231 U16 232 ); 233 234 235 /** 236 * @struct SCI_BASE_CONTROLLER_STATE_HANDLER 237 * 238 * @brief This structure contains all of the state handler methods common to 239 * base controller state machines. Handler methods provide the ability 240 * to change the behavior for user requests or transitions depending 241 * on the state the machine is in. 242 */ 243 typedef struct SCI_BASE_CONTROLLER_STATE_HANDLER 244 { 245 /** 246 * The start_handler specifies the method invoked when a user attempts to 247 * start a controller. 248 */ 249 SCI_BASE_CONTROLLER_TIMED_HANDLER_T start_handler; 250 251 /** 252 * The stop_handler specifies the method invoked when a user attempts to 253 * stop a controller. 254 */ 255 SCI_BASE_CONTROLLER_TIMED_HANDLER_T stop_handler; 256 257 /** 258 * The reset_handler specifies the method invoked when a user attempts to 259 * reset a controller. 260 */ 261 SCI_BASE_CONTROLLER_HANDLER_T reset_handler; 262 263 /** 264 * The initialize_handler specifies the method invoked when a user 265 * attempts to initialize a controller. 266 */ 267 SCI_BASE_CONTROLLER_HANDLER_T initialize_handler; 268 269 /** 270 * The start_io_handler specifies the method invoked when a user 271 * attempts to start an IO request for a controller. 272 */ 273 SCI_BASE_CONTROLLER_START_REQUEST_HANDLER_T start_io_handler; 274 275 /** 276 * The start_internal_request_handler specifies the method invoked when a user 277 * attempts to start an internal request for a controller. 278 */ 279 SCI_BASE_CONTROLLER_START_REQUEST_HANDLER_T start_high_priority_io_handler; 280 281 /** 282 * The complete_io_handler specifies the method invoked when a user 283 * attempts to complete an IO request for a controller. 284 */ 285 SCI_BASE_CONTROLLER_REQUEST_HANDLER_T complete_io_handler; 286 287 /** 288 * The complete_high_priority_io_handler specifies the method invoked when a user 289 * attempts to complete a high priority IO request for a controller. 290 */ 291 SCI_BASE_CONTROLLER_REQUEST_HANDLER_T complete_high_priority_io_handler; 292 293 /** 294 * The continue_io_handler specifies the method invoked when a user 295 * attempts to continue an IO request for a controller. 296 */ 297 SCI_BASE_CONTROLLER_REQUEST_HANDLER_T continue_io_handler; 298 299 /** 300 * The start_task_handler specifies the method invoked when a user 301 * attempts to start a task management request for a controller. 302 */ 303 SCI_BASE_CONTROLLER_START_REQUEST_HANDLER_T start_task_handler; 304 305 /** 306 * The complete_task_handler specifies the method invoked when a user 307 * attempts to complete a task management request for a controller. 308 */ 309 SCI_BASE_CONTROLLER_REQUEST_HANDLER_T complete_task_handler; 310 311 } SCI_BASE_CONTROLLER_STATE_HANDLER_T; 312 313 /** 314 * @brief Construct the base controller 315 * 316 * @param[in] this_controller This parameter specifies the base controller 317 * to be constructed. 318 * @param[in] logger This parameter specifies the logger associated with 319 * this base controller object. 320 * @param[in] state_table This parameter specifies the table of state 321 * definitions to be utilized for the controller state machine. 322 * @param[in] mde_array This parameter specifies the array of memory 323 * descriptor entries to be managed by this list. 324 * @param[in] mde_array_length This parameter specifies the size of the 325 * array of entries. 326 * @param[in] next_mdl This parameter specifies a subsequent MDL object 327 * to be managed by this MDL object. 328 * @param[in] oem_parameters This parameter specifies the original 329 * equipment manufacturer parameters to be utilized by this 330 * controller object. 331 * 332 * @return none 333 */ 334 void sci_base_controller_construct( 335 SCI_BASE_CONTROLLER_T * this_controller, 336 SCI_BASE_LOGGER_T * logger, 337 SCI_BASE_STATE_T * state_table, 338 SCI_PHYSICAL_MEMORY_DESCRIPTOR_T * mdes, 339 U32 mde_count, 340 SCI_MEMORY_DESCRIPTOR_LIST_HANDLE_T next_mdl 341 ); 342 343 #ifdef __cplusplus 344 } 345 #endif // __cplusplus 346 347 #endif // _SCI_BASE_CONTROLLER_H_ 348