1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2026 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include "irdma_main.h" 36 37 /** 38 * irdma_query_device - get device attributes 39 * @ibdev: device pointer from stack 40 * @props: returning device attributes 41 * @udata: user data 42 */ 43 static int 44 irdma_query_device(struct ib_device *ibdev, 45 struct ib_device_attr *props, 46 struct ib_udata *udata) 47 { 48 struct irdma_device *iwdev = to_iwdev(ibdev); 49 struct irdma_pci_f *rf = iwdev->rf; 50 struct pci_dev *pcidev = iwdev->rf->pcidev; 51 struct irdma_hw_attrs *hw_attrs = &rf->sc_dev.hw_attrs; 52 53 if (udata->inlen || udata->outlen) 54 return -EINVAL; 55 56 memset(props, 0, sizeof(*props)); 57 addrconf_addr_eui48((u8 *)&props->sys_image_guid, 58 if_getlladdr(iwdev->netdev)); 59 props->fw_ver = (u64)irdma_fw_major_ver(&rf->sc_dev) << 32 | 60 irdma_fw_minor_ver(&rf->sc_dev); 61 props->device_cap_flags = IB_DEVICE_MEM_WINDOW | 62 IB_DEVICE_MEM_MGT_EXTENSIONS; 63 props->vendor_id = pcidev->vendor; 64 props->vendor_part_id = pcidev->device; 65 props->hw_ver = pcidev->revision; 66 props->page_size_cap = hw_attrs->page_size_cap; 67 props->max_mr_size = hw_attrs->max_mr_size; 68 props->max_qp = rf->max_qp - rf->used_qps; 69 props->max_qp_wr = hw_attrs->max_qp_wr; 70 set_max_sge(props, rf); 71 props->max_cq = rf->max_cq - rf->used_cqs; 72 props->max_cqe = rf->max_cqe - 1; 73 props->max_mr = rf->max_mr - rf->used_mrs; 74 props->max_pd = rf->max_pd - rf->used_pds; 75 props->max_sge_rd = hw_attrs->uk_attrs.max_hw_read_sges; 76 props->max_qp_rd_atom = hw_attrs->max_hw_ird; 77 props->max_qp_init_rd_atom = hw_attrs->max_hw_ord; 78 if (rdma_protocol_roce(ibdev, 1)) { 79 props->device_cap_flags |= IB_DEVICE_RC_RNR_NAK_GEN; 80 props->max_pkeys = IRDMA_PKEY_TBL_SZ; 81 props->max_ah = rf->max_ah; 82 if (hw_attrs->uk_attrs.hw_rev == IRDMA_GEN_2) { 83 props->max_mcast_grp = rf->max_mcg; 84 props->max_mcast_qp_attach = IRDMA_MAX_MGS_PER_CTX; 85 props->max_total_mcast_qp_attach = rf->max_qp * IRDMA_MAX_MGS_PER_CTX; 86 } 87 } 88 props->max_fast_reg_page_list_len = IRDMA_MAX_PAGES_PER_FMR; 89 if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_2) 90 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 91 92 return 0; 93 } 94 95 static int 96 irdma_mmap_legacy(struct irdma_ucontext *ucontext, 97 struct vm_area_struct *vma) 98 { 99 u64 pfn; 100 101 if (vma->vm_pgoff || vma->vm_end - vma->vm_start != PAGE_SIZE) 102 return -EINVAL; 103 104 vma->vm_private_data = ucontext; 105 pfn = ((uintptr_t)ucontext->iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET] + 106 pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT; 107 108 return rdma_user_mmap_io(&ucontext->ibucontext, vma, pfn, PAGE_SIZE, 109 pgprot_noncached(vma->vm_page_prot), NULL); 110 } 111 112 static void 113 irdma_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 114 { 115 struct irdma_user_mmap_entry *entry = to_irdma_mmap_entry(rdma_entry); 116 117 kfree(entry); 118 } 119 120 struct rdma_user_mmap_entry * 121 irdma_user_mmap_entry_insert(struct irdma_ucontext *ucontext, u64 bar_offset, 122 enum irdma_mmap_flag mmap_flag, u64 *mmap_offset) 123 { 124 struct irdma_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL); 125 int ret; 126 127 if (!entry) 128 return NULL; 129 130 entry->bar_offset = bar_offset; 131 entry->mmap_flag = mmap_flag; 132 133 ret = rdma_user_mmap_entry_insert(&ucontext->ibucontext, 134 &entry->rdma_entry, PAGE_SIZE); 135 if (ret) { 136 kfree(entry); 137 return NULL; 138 } 139 *mmap_offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 140 141 return &entry->rdma_entry; 142 } 143 144 /** 145 * irdma_mmap - user memory map 146 * @context: context created during alloc 147 * @vma: kernel info for user memory map 148 */ 149 static int 150 irdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 151 { 152 struct rdma_user_mmap_entry *rdma_entry; 153 struct irdma_user_mmap_entry *entry; 154 struct irdma_ucontext *ucontext; 155 u64 pfn; 156 int ret; 157 158 ucontext = to_ucontext(context); 159 160 /* Legacy support for libi40iw with hard-coded mmap key */ 161 if (ucontext->legacy_mode) 162 return irdma_mmap_legacy(ucontext, vma); 163 164 rdma_entry = rdma_user_mmap_entry_get(&ucontext->ibucontext, vma); 165 if (!rdma_entry) { 166 irdma_debug(&ucontext->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 167 "pgoff[0x%lx] does not have valid entry\n", 168 vma->vm_pgoff); 169 return -EINVAL; 170 } 171 172 entry = to_irdma_mmap_entry(rdma_entry); 173 irdma_debug(&ucontext->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 174 "bar_offset [0x%lx] mmap_flag [%d]\n", entry->bar_offset, 175 entry->mmap_flag); 176 177 pfn = (entry->bar_offset + 178 pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT; 179 180 switch (entry->mmap_flag) { 181 case IRDMA_MMAP_IO_NC: 182 ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE, 183 pgprot_noncached(vma->vm_page_prot), 184 rdma_entry); 185 break; 186 case IRDMA_MMAP_IO_WC: 187 ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE, 188 pgprot_writecombine(vma->vm_page_prot), 189 rdma_entry); 190 break; 191 default: 192 ret = -EINVAL; 193 } 194 195 if (ret) 196 irdma_debug(&ucontext->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 197 "bar_offset [0x%lx] mmap_flag[%d] err[%d]\n", 198 entry->bar_offset, entry->mmap_flag, ret); 199 rdma_user_mmap_entry_put(rdma_entry); 200 201 return ret; 202 } 203 204 /** 205 * irdma_alloc_push_page - allocate a push page for qp 206 * @iwqp: qp pointer 207 */ 208 static void 209 irdma_alloc_push_page(struct irdma_qp *iwqp) 210 { 211 struct irdma_cqp_request *cqp_request; 212 struct cqp_cmds_info *cqp_info; 213 struct irdma_device *iwdev = iwqp->iwdev; 214 struct irdma_sc_qp *qp = &iwqp->sc_qp; 215 int status; 216 217 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); 218 if (!cqp_request) 219 return; 220 221 cqp_info = &cqp_request->info; 222 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE; 223 cqp_info->post_sq = 1; 224 cqp_info->in.u.manage_push_page.info.push_idx = 0; 225 cqp_info->in.u.manage_push_page.info.qs_handle = 226 qp->vsi->qos[qp->user_pri].qs_handle; 227 cqp_info->in.u.manage_push_page.info.free_page = 0; 228 cqp_info->in.u.manage_push_page.info.push_page_type = 0; 229 cqp_info->in.u.manage_push_page.cqp = &iwdev->rf->cqp.sc_cqp; 230 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request; 231 cqp_info->create = true; 232 233 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 234 if (!status && cqp_request->compl_info.op_ret_val < 235 iwdev->rf->sc_dev.hw_attrs.max_hw_device_pages) { 236 qp->push_idx = cqp_request->compl_info.op_ret_val; 237 qp->push_offset = 0; 238 } 239 240 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 241 } 242 243 /** 244 * irdma_get_pbl - Retrieve pbl from a list given a virtual 245 * address 246 * @va: user virtual address 247 * @pbl_list: pbl list to search in (QP's or CQ's) 248 */ 249 struct irdma_pbl * 250 irdma_get_pbl(unsigned long va, 251 struct list_head *pbl_list) 252 { 253 struct irdma_pbl *iwpbl; 254 255 list_for_each_entry(iwpbl, pbl_list, list) { 256 if (iwpbl->user_base == va) { 257 list_del(&iwpbl->list); 258 iwpbl->on_list = false; 259 return iwpbl; 260 } 261 } 262 263 return NULL; 264 } 265 266 /** 267 * irdma_clean_cqes - clean cq entries for qp 268 * @iwqp: qp ptr (user or kernel) 269 * @iwcq: cq ptr 270 */ 271 void 272 irdma_clean_cqes(struct irdma_qp *iwqp, struct irdma_cq *iwcq) 273 { 274 struct irdma_cq_uk *ukcq = &iwcq->sc_cq.cq_uk; 275 unsigned long flags; 276 struct irdma_cmpl_gen *cmpl_node; 277 struct list_head *tmp_node, *list_node; 278 279 spin_lock_irqsave(&iwcq->lock, flags); 280 irdma_uk_clean_cq(&iwqp->sc_qp.qp_uk, ukcq); 281 282 list_for_each_safe(list_node, tmp_node, &iwcq->cmpl_generated) { 283 cmpl_node = list_entry(list_node, struct irdma_cmpl_gen, list); 284 if (cmpl_node->cpi.qp_id == iwqp->ibqp.qp_num) { 285 list_del(&cmpl_node->list); 286 kfree(cmpl_node); 287 } 288 } 289 290 spin_unlock_irqrestore(&iwcq->lock, flags); 291 } 292 293 static u64 irdma_compute_push_wqe_offset(struct irdma_device *iwdev, u32 page_idx){ 294 u64 bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET]; 295 296 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) { 297 /* skip over db page */ 298 bar_off += IRDMA_HW_PAGE_SIZE; 299 /* skip over reserved space */ 300 bar_off += IRDMA_PF_BAR_RSVD; 301 } 302 303 /* push wqe page */ 304 bar_off += (u64)page_idx * IRDMA_HW_PAGE_SIZE; 305 306 return bar_off; 307 } 308 309 void 310 irdma_remove_push_mmap_entries(struct irdma_qp *iwqp) 311 { 312 if (iwqp->push_db_mmap_entry) { 313 rdma_user_mmap_entry_remove(iwqp->push_db_mmap_entry); 314 iwqp->push_db_mmap_entry = NULL; 315 } 316 if (iwqp->push_wqe_mmap_entry) { 317 rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry); 318 iwqp->push_wqe_mmap_entry = NULL; 319 } 320 } 321 322 static int 323 irdma_setup_push_mmap_entries(struct irdma_ucontext *ucontext, 324 struct irdma_qp *iwqp, 325 u64 *push_wqe_mmap_key, 326 u64 *push_db_mmap_key) 327 { 328 struct irdma_device *iwdev = ucontext->iwdev; 329 u64 bar_off; 330 331 WARN_ON_ONCE(iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_2); 332 333 bar_off = irdma_compute_push_wqe_offset(iwdev, iwqp->sc_qp.push_idx); 334 335 iwqp->push_wqe_mmap_entry = irdma_user_mmap_entry_insert(ucontext, 336 bar_off, IRDMA_MMAP_IO_WC, 337 push_wqe_mmap_key); 338 if (!iwqp->push_wqe_mmap_entry) 339 return -ENOMEM; 340 341 /* push doorbell page */ 342 bar_off += IRDMA_HW_PAGE_SIZE; 343 iwqp->push_db_mmap_entry = irdma_user_mmap_entry_insert(ucontext, 344 bar_off, IRDMA_MMAP_IO_NC, 345 push_db_mmap_key); 346 if (!iwqp->push_db_mmap_entry) { 347 rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry); 348 return -ENOMEM; 349 } 350 351 return 0; 352 } 353 354 /** 355 * irdma_setup_virt_qp - setup for allocation of virtual qp 356 * @iwdev: irdma device 357 * @iwqp: qp ptr 358 * @init_info: initialize info to return 359 */ 360 void 361 irdma_setup_virt_qp(struct irdma_device *iwdev, 362 struct irdma_qp *iwqp, 363 struct irdma_qp_init_info *init_info) 364 { 365 struct irdma_pbl *iwpbl = iwqp->iwpbl; 366 struct irdma_qp_mr *qpmr = &iwpbl->qp_mr; 367 368 iwqp->page = qpmr->sq_page; 369 init_info->shadow_area_pa = qpmr->shadow; 370 if (iwpbl->pbl_allocated) { 371 init_info->virtual_map = true; 372 init_info->sq_pa = qpmr->sq_pbl.idx; 373 init_info->rq_pa = qpmr->rq_pbl.idx; 374 } else { 375 init_info->sq_pa = qpmr->sq_pbl.addr; 376 init_info->rq_pa = qpmr->rq_pbl.addr; 377 } 378 } 379 380 /** 381 * irdma_setup_umode_qp - setup sq and rq size in user mode qp 382 * @udata: user data 383 * @iwdev: iwarp device 384 * @iwqp: qp ptr (user or kernel) 385 * @info: initialize info to return 386 * @init_attr: Initial QP create attributes 387 */ 388 int 389 irdma_setup_umode_qp(struct ib_udata *udata, 390 struct irdma_device *iwdev, 391 struct irdma_qp *iwqp, 392 struct irdma_qp_init_info *info, 393 struct ib_qp_init_attr *init_attr) 394 { 395 struct irdma_ucontext *ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext); 396 struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info; 397 struct irdma_create_qp_req req = {0}; 398 unsigned long flags; 399 int ret; 400 401 ret = ib_copy_from_udata(&req, udata, 402 min(sizeof(req), udata->inlen)); 403 if (ret) { 404 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, "ib_copy_from_data fail\n"); 405 return ret; 406 } 407 408 iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx; 409 iwqp->user_mode = 1; 410 if (req.user_wqe_bufs) { 411 info->qp_uk_init_info.legacy_mode = ucontext->legacy_mode; 412 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags); 413 iwqp->iwpbl = irdma_get_pbl((unsigned long)req.user_wqe_bufs, 414 &ucontext->qp_reg_mem_list); 415 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); 416 417 if (!iwqp->iwpbl) { 418 ret = -ENODATA; 419 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, "no pbl info\n"); 420 return ret; 421 } 422 } 423 424 if (!ucontext->use_raw_attrs) { 425 /** 426 * Maintain backward compat with older ABI which passes sq and 427 * rq depth in quanta in cap.max_send_wr and cap.max_recv_wr. 428 * There is no way to compute the correct value of 429 * iwqp->max_send_wr/max_recv_wr in the kernel. 430 */ 431 iwqp->max_send_wr = init_attr->cap.max_send_wr; 432 iwqp->max_recv_wr = init_attr->cap.max_recv_wr; 433 ukinfo->sq_size = init_attr->cap.max_send_wr; 434 ukinfo->rq_size = init_attr->cap.max_recv_wr; 435 irdma_uk_calc_shift_wq(ukinfo, &ukinfo->sq_shift, &ukinfo->rq_shift); 436 } else { 437 ret = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth, 438 &ukinfo->sq_shift); 439 if (ret) 440 return ret; 441 442 ret = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth, 443 &ukinfo->rq_shift); 444 if (ret) 445 return ret; 446 447 iwqp->max_send_wr = (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift; 448 iwqp->max_recv_wr = (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift; 449 ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift; 450 ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift; 451 } 452 if (req.comp_mask & IRDMA_CREATE_QP_USE_START_WQE_IDX && 453 iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) 454 ukinfo->start_wqe_idx = 4; 455 irdma_setup_virt_qp(iwdev, iwqp, info); 456 457 return 0; 458 } 459 460 /** 461 * irdma_setup_kmode_qp - setup initialization for kernel mode qp 462 * @iwdev: iwarp device 463 * @iwqp: qp ptr (user or kernel) 464 * @info: initialize info to return 465 * @init_attr: Initial QP create attributes 466 */ 467 int 468 irdma_setup_kmode_qp(struct irdma_device *iwdev, 469 struct irdma_qp *iwqp, 470 struct irdma_qp_init_info *info, 471 struct ib_qp_init_attr *init_attr) 472 { 473 struct irdma_dma_mem *mem = &iwqp->kqp.dma_mem; 474 u32 size; 475 int status; 476 struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info; 477 478 status = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth, 479 &ukinfo->sq_shift); 480 if (status) 481 return status; 482 483 status = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth, 484 &ukinfo->rq_shift); 485 if (status) 486 return status; 487 488 iwqp->kqp.sq_wrid_mem = 489 kcalloc(ukinfo->sq_depth, sizeof(*iwqp->kqp.sq_wrid_mem), GFP_KERNEL); 490 if (!iwqp->kqp.sq_wrid_mem) 491 return -ENOMEM; 492 493 iwqp->kqp.rq_wrid_mem = 494 kcalloc(ukinfo->rq_depth, sizeof(*iwqp->kqp.rq_wrid_mem), GFP_KERNEL); 495 if (!iwqp->kqp.rq_wrid_mem) { 496 kfree(iwqp->kqp.sq_wrid_mem); 497 iwqp->kqp.sq_wrid_mem = NULL; 498 return -ENOMEM; 499 } 500 501 iwqp->kqp.sig_trk_mem = kcalloc(ukinfo->sq_depth, sizeof(u32), GFP_KERNEL); 502 memset(iwqp->kqp.sig_trk_mem, 0, ukinfo->sq_depth * sizeof(u32)); 503 if (!iwqp->kqp.sig_trk_mem) { 504 kfree(iwqp->kqp.sq_wrid_mem); 505 iwqp->kqp.sq_wrid_mem = NULL; 506 kfree(iwqp->kqp.rq_wrid_mem); 507 iwqp->kqp.rq_wrid_mem = NULL; 508 return -ENOMEM; 509 } 510 ukinfo->sq_sigwrtrk_array = (void *)iwqp->kqp.sig_trk_mem; 511 ukinfo->sq_wrtrk_array = iwqp->kqp.sq_wrid_mem; 512 ukinfo->rq_wrid_array = iwqp->kqp.rq_wrid_mem; 513 514 size = (ukinfo->sq_depth + ukinfo->rq_depth) * IRDMA_QP_WQE_MIN_SIZE; 515 size += (IRDMA_SHADOW_AREA_SIZE << 3); 516 517 mem->size = size; 518 mem->va = irdma_allocate_dma_mem(&iwdev->rf->hw, mem, mem->size, 519 256); 520 if (!mem->va) { 521 kfree(iwqp->kqp.sq_wrid_mem); 522 iwqp->kqp.sq_wrid_mem = NULL; 523 kfree(iwqp->kqp.rq_wrid_mem); 524 iwqp->kqp.rq_wrid_mem = NULL; 525 return -ENOMEM; 526 } 527 528 ukinfo->sq = mem->va; 529 info->sq_pa = mem->pa; 530 ukinfo->rq = &ukinfo->sq[ukinfo->sq_depth]; 531 info->rq_pa = info->sq_pa + (ukinfo->sq_depth * IRDMA_QP_WQE_MIN_SIZE); 532 ukinfo->shadow_area = ukinfo->rq[ukinfo->rq_depth].elem; 533 info->shadow_area_pa = info->rq_pa + (ukinfo->rq_depth * IRDMA_QP_WQE_MIN_SIZE); 534 ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift; 535 ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift; 536 537 iwqp->max_send_wr = (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift; 538 iwqp->max_recv_wr = (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift; 539 init_attr->cap.max_send_wr = iwqp->max_send_wr; 540 init_attr->cap.max_recv_wr = iwqp->max_recv_wr; 541 542 return 0; 543 } 544 545 int 546 irdma_cqp_create_qp_cmd(struct irdma_qp *iwqp) 547 { 548 struct irdma_pci_f *rf = iwqp->iwdev->rf; 549 struct irdma_cqp_request *cqp_request; 550 struct cqp_cmds_info *cqp_info; 551 struct irdma_create_qp_info *qp_info; 552 int status; 553 554 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); 555 if (!cqp_request) 556 return -ENOMEM; 557 558 cqp_info = &cqp_request->info; 559 qp_info = &cqp_request->info.in.u.qp_create.info; 560 qp_info->mac_valid = true; 561 qp_info->cq_num_valid = true; 562 qp_info->next_iwarp_state = IRDMA_QP_STATE_IDLE; 563 564 cqp_info->cqp_cmd = IRDMA_OP_QP_CREATE; 565 cqp_info->post_sq = 1; 566 cqp_info->in.u.qp_create.qp = &iwqp->sc_qp; 567 cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request; 568 cqp_info->create = true; 569 status = irdma_handle_cqp_op(rf, cqp_request); 570 irdma_put_cqp_request(&rf->cqp, cqp_request); 571 572 return status; 573 } 574 575 void 576 irdma_roce_fill_and_set_qpctx_info(struct irdma_qp *iwqp, 577 struct irdma_qp_host_ctx_info *ctx_info) 578 { 579 struct irdma_device *iwdev = iwqp->iwdev; 580 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; 581 struct irdma_roce_offload_info *roce_info; 582 struct irdma_udp_offload_info *udp_info; 583 584 udp_info = &iwqp->udp_info; 585 udp_info->snd_mss = ib_mtu_enum_to_int(iboe_get_mtu(iwdev->vsi.mtu)); 586 udp_info->cwnd = iwdev->roce_cwnd; 587 udp_info->rexmit_thresh = 2; 588 udp_info->rnr_nak_thresh = 2; 589 udp_info->src_port = 0xc000; 590 udp_info->dst_port = ROCE_V2_UDP_DPORT; 591 roce_info = &iwqp->roce_info; 592 ether_addr_copy(roce_info->mac_addr, if_getlladdr(iwdev->netdev)); 593 594 roce_info->rd_en = true; 595 roce_info->wr_rdresp_en = true; 596 roce_info->dcqcn_en = false; 597 roce_info->rtomin = iwdev->roce_rtomin; 598 599 roce_info->ack_credits = iwdev->roce_ackcreds; 600 roce_info->ird_size = dev->hw_attrs.max_hw_ird; 601 roce_info->ord_size = dev->hw_attrs.max_hw_ord; 602 603 if (!iwqp->user_mode) { 604 roce_info->priv_mode_en = true; 605 roce_info->fast_reg_en = true; 606 roce_info->udprivcq_en = true; 607 } 608 roce_info->roce_tver = 0; 609 610 ctx_info->roce_info = &iwqp->roce_info; 611 ctx_info->udp_info = &iwqp->udp_info; 612 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info); 613 } 614 615 void 616 irdma_iw_fill_and_set_qpctx_info(struct irdma_qp *iwqp, 617 struct irdma_qp_host_ctx_info *ctx_info) 618 { 619 struct irdma_device *iwdev = iwqp->iwdev; 620 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; 621 struct irdma_iwarp_offload_info *iwarp_info; 622 623 iwarp_info = &iwqp->iwarp_info; 624 ether_addr_copy(iwarp_info->mac_addr, if_getlladdr(iwdev->netdev)); 625 iwarp_info->rd_en = true; 626 iwarp_info->wr_rdresp_en = true; 627 iwarp_info->ecn_en = true; 628 iwarp_info->rtomin = 5; 629 630 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 631 iwarp_info->ib_rd_en = true; 632 if (!iwqp->user_mode) { 633 iwarp_info->priv_mode_en = true; 634 iwarp_info->fast_reg_en = true; 635 } 636 iwarp_info->ddp_ver = 1; 637 iwarp_info->rdmap_ver = 1; 638 639 ctx_info->iwarp_info = &iwqp->iwarp_info; 640 ctx_info->iwarp_info_valid = true; 641 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info); 642 ctx_info->iwarp_info_valid = false; 643 } 644 645 int 646 irdma_validate_qp_attrs(struct ib_qp_init_attr *init_attr, 647 struct irdma_device *iwdev) 648 { 649 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; 650 struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs; 651 652 if (init_attr->create_flags) 653 return -EOPNOTSUPP; 654 655 if (init_attr->cap.max_inline_data > uk_attrs->max_hw_inline || 656 init_attr->cap.max_send_sge > uk_attrs->max_hw_wq_frags || 657 init_attr->cap.max_send_wr > uk_attrs->max_hw_wq_quanta || 658 init_attr->cap.max_recv_wr > uk_attrs->max_hw_rq_quanta || 659 init_attr->cap.max_recv_sge > uk_attrs->max_hw_wq_frags) 660 return -EINVAL; 661 662 if (rdma_protocol_roce(&iwdev->ibdev, 1)) { 663 if (init_attr->qp_type != IB_QPT_RC && 664 init_attr->qp_type != IB_QPT_UD && 665 init_attr->qp_type != IB_QPT_GSI) 666 return -EOPNOTSUPP; 667 } else { 668 if (init_attr->qp_type != IB_QPT_RC) 669 return -EOPNOTSUPP; 670 } 671 672 return 0; 673 } 674 675 void 676 irdma_sched_qp_flush_work(struct irdma_qp *iwqp) 677 { 678 unsigned long flags; 679 680 if (iwqp->sc_qp.qp_uk.destroy_pending) 681 return; 682 irdma_qp_add_ref(&iwqp->ibqp); 683 spin_lock_irqsave(&iwqp->dwork_flush_lock, flags); 684 if (mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush, 685 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS))) 686 irdma_qp_rem_ref(&iwqp->ibqp); 687 spin_unlock_irqrestore(&iwqp->dwork_flush_lock, flags); 688 } 689 690 void 691 irdma_user_flush_worker(struct work_struct *work) 692 { 693 struct delayed_work *dwork = to_delayed_work(work); 694 struct irdma_qp *iwqp = container_of(dwork, struct irdma_qp, 695 dwork_flush); 696 697 /* 698 * Set the WAIT flag to prevent a massive buildup of flush commands in the extreme case of many QPs lingering 699 * in the ERROR state. 700 */ 701 irdma_flush_wqes(iwqp, IRDMA_FLUSH_SQ | IRDMA_FLUSH_RQ | IRDMA_REFLUSH | 702 IRDMA_FLUSH_WAIT); 703 704 /* Re-arm continuously. Work is canceled when QP is deleted. */ 705 mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush, 706 msecs_to_jiffies(IRDMA_PERIODIC_FLUSH_MS)); 707 } 708 709 void 710 irdma_kern_flush_worker(struct work_struct *work) 711 { 712 struct delayed_work *dwork = to_delayed_work(work); 713 struct irdma_qp *iwqp = container_of(dwork, struct irdma_qp, dwork_flush); 714 715 irdma_generate_flush_completions(iwqp); 716 /* For the add in irdma_sched_qp_flush_work */ 717 irdma_qp_rem_ref(&iwqp->ibqp); 718 } 719 720 static int 721 irdma_get_ib_acc_flags(struct irdma_qp *iwqp) 722 { 723 int acc_flags = 0; 724 725 if (rdma_protocol_roce(iwqp->ibqp.device, 1)) { 726 if (iwqp->roce_info.wr_rdresp_en) { 727 acc_flags |= IB_ACCESS_LOCAL_WRITE; 728 acc_flags |= IB_ACCESS_REMOTE_WRITE; 729 } 730 if (iwqp->roce_info.rd_en) 731 acc_flags |= IB_ACCESS_REMOTE_READ; 732 } else { 733 if (iwqp->iwarp_info.wr_rdresp_en) { 734 acc_flags |= IB_ACCESS_LOCAL_WRITE; 735 acc_flags |= IB_ACCESS_REMOTE_WRITE; 736 } 737 if (iwqp->iwarp_info.rd_en) 738 acc_flags |= IB_ACCESS_REMOTE_READ; 739 } 740 return acc_flags; 741 } 742 743 /** 744 * irdma_query_qp - query qp attributes 745 * @ibqp: qp pointer 746 * @attr: attributes pointer 747 * @attr_mask: Not used 748 * @init_attr: qp attributes to return 749 */ 750 static int 751 irdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 752 int attr_mask, struct ib_qp_init_attr *init_attr) 753 { 754 struct irdma_qp *iwqp = to_iwqp(ibqp); 755 struct irdma_sc_qp *qp = &iwqp->sc_qp; 756 757 memset(attr, 0, sizeof(*attr)); 758 memset(init_attr, 0, sizeof(*init_attr)); 759 760 attr->qp_state = iwqp->ibqp_state; 761 attr->cur_qp_state = iwqp->ibqp_state; 762 attr->cap.max_send_wr = iwqp->max_send_wr; 763 attr->cap.max_recv_wr = iwqp->max_recv_wr; 764 attr->cap.max_inline_data = qp->qp_uk.max_inline_data; 765 attr->cap.max_send_sge = qp->qp_uk.max_sq_frag_cnt; 766 attr->cap.max_recv_sge = qp->qp_uk.max_rq_frag_cnt; 767 attr->qp_access_flags = irdma_get_ib_acc_flags(iwqp); 768 attr->port_num = 1; 769 if (rdma_protocol_roce(ibqp->device, 1)) { 770 attr->path_mtu = ib_mtu_int_to_enum(iwqp->udp_info.snd_mss); 771 attr->qkey = iwqp->roce_info.qkey; 772 attr->rq_psn = iwqp->udp_info.epsn; 773 attr->sq_psn = iwqp->udp_info.psn_nxt; 774 attr->dest_qp_num = iwqp->roce_info.dest_qp; 775 attr->pkey_index = iwqp->roce_info.p_key; 776 attr->retry_cnt = iwqp->udp_info.rexmit_thresh; 777 attr->rnr_retry = iwqp->udp_info.rnr_nak_thresh; 778 attr->max_rd_atomic = iwqp->roce_info.ord_size; 779 attr->max_dest_rd_atomic = iwqp->roce_info.ird_size; 780 } 781 782 init_attr->event_handler = iwqp->ibqp.event_handler; 783 init_attr->qp_context = iwqp->ibqp.qp_context; 784 init_attr->send_cq = iwqp->ibqp.send_cq; 785 init_attr->recv_cq = iwqp->ibqp.recv_cq; 786 init_attr->cap = attr->cap; 787 788 return 0; 789 } 790 791 static int 792 irdma_wait_for_suspend(struct irdma_qp *iwqp) 793 { 794 if (!wait_event_timeout(iwqp->iwdev->suspend_wq, 795 !iwqp->suspend_pending, 796 msecs_to_jiffies(IRDMA_EVENT_TIMEOUT_MS))) { 797 iwqp->suspend_pending = false; 798 irdma_dev_warn(&iwqp->iwdev->ibdev, 799 "modify_qp timed out waiting for suspend. qp_id = %d, last_ae = 0x%x\n", 800 iwqp->ibqp.qp_num, iwqp->last_aeq); 801 return -EBUSY; 802 } 803 804 return 0; 805 } 806 807 /** 808 * irdma_modify_qp_roce - modify qp request 809 * @ibqp: qp's pointer for modify 810 * @attr: access attributes 811 * @attr_mask: state mask 812 * @udata: user data 813 */ 814 int 815 irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr, 816 int attr_mask, struct ib_udata *udata) 817 { 818 #define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush) 819 #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid) 820 struct irdma_pd *iwpd = to_iwpd(ibqp->pd); 821 struct irdma_qp *iwqp = to_iwqp(ibqp); 822 struct irdma_device *iwdev = iwqp->iwdev; 823 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; 824 struct irdma_qp_host_ctx_info *ctx_info; 825 struct irdma_roce_offload_info *roce_info; 826 struct irdma_udp_offload_info *udp_info; 827 struct irdma_modify_qp_info info = {0}; 828 struct irdma_modify_qp_resp uresp = {}; 829 struct irdma_modify_qp_req ureq; 830 unsigned long flags; 831 u8 issue_modify_qp = 0; 832 int ret = 0; 833 834 ctx_info = &iwqp->ctx_info; 835 roce_info = &iwqp->roce_info; 836 udp_info = &iwqp->udp_info; 837 838 if (udata) { 839 if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) || 840 (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN)) 841 return -EINVAL; 842 } 843 844 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 845 return -EOPNOTSUPP; 846 847 if (attr_mask & IB_QP_DEST_QPN) 848 roce_info->dest_qp = attr->dest_qp_num; 849 850 if (attr_mask & IB_QP_PKEY_INDEX) { 851 ret = irdma_query_pkey(ibqp->device, 0, attr->pkey_index, 852 &roce_info->p_key); 853 if (ret) 854 return ret; 855 } 856 857 if (attr_mask & IB_QP_QKEY) 858 roce_info->qkey = attr->qkey; 859 860 if (attr_mask & IB_QP_PATH_MTU) 861 udp_info->snd_mss = ib_mtu_enum_to_int(attr->path_mtu); 862 863 if (attr_mask & IB_QP_SQ_PSN) { 864 udp_info->psn_nxt = attr->sq_psn; 865 udp_info->lsn = 0xffff; 866 udp_info->psn_una = attr->sq_psn; 867 udp_info->psn_max = attr->sq_psn; 868 } 869 870 if (attr_mask & IB_QP_RQ_PSN) 871 udp_info->epsn = attr->rq_psn; 872 873 if (attr_mask & IB_QP_RNR_RETRY) 874 udp_info->rnr_nak_thresh = attr->rnr_retry; 875 876 if (attr_mask & IB_QP_RETRY_CNT) 877 udp_info->rexmit_thresh = attr->retry_cnt; 878 879 ctx_info->roce_info->pd_id = iwpd->sc_pd.pd_id; 880 881 if (attr_mask & IB_QP_AV) { 882 struct irdma_av *av = &iwqp->roce_ah.av; 883 u16 vlan_id = VLAN_N_VID; 884 u32 local_ip[4] = {}; 885 886 memset(&iwqp->roce_ah, 0, sizeof(iwqp->roce_ah)); 887 if (attr->ah_attr.ah_flags & IB_AH_GRH) { 888 udp_info->ttl = attr->ah_attr.grh.hop_limit; 889 udp_info->flow_label = attr->ah_attr.grh.flow_label; 890 udp_info->tos = attr->ah_attr.grh.traffic_class; 891 892 udp_info->src_port = kc_rdma_get_udp_sport(udp_info->flow_label, 893 ibqp->qp_num, 894 roce_info->dest_qp); 895 896 irdma_qp_rem_qos(&iwqp->sc_qp); 897 dev->ws_remove(iwqp->sc_qp.vsi, ctx_info->user_pri); 898 if (iwqp->sc_qp.vsi->dscp_mode) 899 ctx_info->user_pri = 900 iwqp->sc_qp.vsi->dscp_map[irdma_tos2dscp(udp_info->tos)]; 901 else 902 ctx_info->user_pri = rt_tos2priority(udp_info->tos); 903 } 904 ret = kc_irdma_set_roce_cm_info(iwqp, attr, &vlan_id); 905 if (ret) 906 return ret; 907 if (dev->ws_add(iwqp->sc_qp.vsi, ctx_info->user_pri)) 908 return -ENOMEM; 909 iwqp->sc_qp.user_pri = ctx_info->user_pri; 910 irdma_qp_add_qos(&iwqp->sc_qp); 911 912 if (vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode) 913 vlan_id = 0; 914 if (vlan_id < VLAN_N_VID) { 915 udp_info->insert_vlan_tag = true; 916 udp_info->vlan_tag = vlan_id | 917 ctx_info->user_pri << VLAN_PRIO_SHIFT; 918 } else { 919 udp_info->insert_vlan_tag = false; 920 } 921 922 av->attrs = attr->ah_attr; 923 rdma_gid2ip((struct sockaddr *)&av->dgid_addr, &attr->ah_attr.grh.dgid); 924 if (av->net_type == RDMA_NETWORK_IPV6) { 925 __be32 *daddr = 926 av->dgid_addr.saddr_in6.sin6_addr.__u6_addr.__u6_addr32; 927 __be32 *saddr = 928 av->sgid_addr.saddr_in6.sin6_addr.__u6_addr.__u6_addr32; 929 930 irdma_copy_ip_ntohl(&udp_info->dest_ip_addr[0], daddr); 931 irdma_copy_ip_ntohl(&udp_info->local_ipaddr[0], saddr); 932 933 udp_info->ipv4 = false; 934 irdma_copy_ip_ntohl(local_ip, daddr); 935 } else if (av->net_type == RDMA_NETWORK_IPV4) { 936 __be32 saddr = av->sgid_addr.saddr_in.sin_addr.s_addr; 937 __be32 daddr = av->dgid_addr.saddr_in.sin_addr.s_addr; 938 939 local_ip[0] = ntohl(daddr); 940 941 udp_info->ipv4 = true; 942 udp_info->dest_ip_addr[0] = 0; 943 udp_info->dest_ip_addr[1] = 0; 944 udp_info->dest_ip_addr[2] = 0; 945 udp_info->dest_ip_addr[3] = local_ip[0]; 946 947 udp_info->local_ipaddr[0] = 0; 948 udp_info->local_ipaddr[1] = 0; 949 udp_info->local_ipaddr[2] = 0; 950 udp_info->local_ipaddr[3] = ntohl(saddr); 951 } else { 952 return -EINVAL; 953 } 954 udp_info->arp_idx = 955 irdma_add_arp(iwdev->rf, local_ip, 956 ah_attr_to_dmac(attr->ah_attr)); 957 } 958 959 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 960 if (attr->max_rd_atomic > dev->hw_attrs.max_hw_ord) { 961 irdma_dev_err(&iwdev->ibdev, 962 "rd_atomic = %d, above max_hw_ord=%d\n", 963 attr->max_rd_atomic, 964 dev->hw_attrs.max_hw_ord); 965 return -EINVAL; 966 } 967 if (attr->max_rd_atomic) 968 roce_info->ord_size = attr->max_rd_atomic; 969 info.ord_valid = true; 970 } 971 972 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 973 if (attr->max_dest_rd_atomic > dev->hw_attrs.max_hw_ird) { 974 irdma_dev_err(&iwdev->ibdev, 975 "rd_atomic = %d, above max_hw_ird=%d\n", 976 attr->max_rd_atomic, 977 dev->hw_attrs.max_hw_ird); 978 return -EINVAL; 979 } 980 if (attr->max_dest_rd_atomic) 981 roce_info->ird_size = attr->max_dest_rd_atomic; 982 } 983 984 if (attr_mask & IB_QP_ACCESS_FLAGS) { 985 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE) 986 roce_info->wr_rdresp_en = true; 987 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 988 roce_info->wr_rdresp_en = true; 989 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 990 roce_info->rd_en = true; 991 } 992 993 wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend)); 994 995 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 996 "caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d attr_mask=0x%x\n", 997 __builtin_return_address(0), ibqp->qp_num, attr->qp_state, 998 iwqp->ibqp_state, iwqp->iwarp_state, attr_mask); 999 1000 spin_lock_irqsave(&iwqp->lock, flags); 1001 if (attr_mask & IB_QP_STATE) { 1002 if (!ib_modify_qp_is_ok(iwqp->ibqp_state, attr->qp_state, 1003 iwqp->ibqp.qp_type, attr_mask)) { 1004 irdma_dev_warn(&iwdev->ibdev, "modify_qp invalid for qp_id=%d, old_state=0x%x, new_state=0x%x\n", 1005 iwqp->ibqp.qp_num, iwqp->ibqp_state, 1006 attr->qp_state); 1007 ret = -EINVAL; 1008 goto exit; 1009 } 1010 info.curr_iwarp_state = iwqp->iwarp_state; 1011 1012 switch (attr->qp_state) { 1013 case IB_QPS_INIT: 1014 if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) { 1015 ret = -EINVAL; 1016 goto exit; 1017 } 1018 1019 if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) { 1020 info.next_iwarp_state = IRDMA_QP_STATE_IDLE; 1021 issue_modify_qp = 1; 1022 } 1023 break; 1024 case IB_QPS_RTR: 1025 if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) { 1026 ret = -EINVAL; 1027 goto exit; 1028 } 1029 info.arp_cache_idx_valid = true; 1030 info.cq_num_valid = true; 1031 info.next_iwarp_state = IRDMA_QP_STATE_RTR; 1032 issue_modify_qp = 1; 1033 break; 1034 case IB_QPS_RTS: 1035 if (iwqp->ibqp_state < IB_QPS_RTR || 1036 iwqp->ibqp_state == IB_QPS_ERR) { 1037 ret = -EINVAL; 1038 goto exit; 1039 } 1040 1041 info.arp_cache_idx_valid = true; 1042 info.cq_num_valid = true; 1043 info.ord_valid = true; 1044 info.next_iwarp_state = IRDMA_QP_STATE_RTS; 1045 issue_modify_qp = 1; 1046 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) 1047 iwdev->rf->check_fc(&iwdev->vsi, &iwqp->sc_qp); 1048 udp_info->cwnd = iwdev->roce_cwnd; 1049 roce_info->ack_credits = iwdev->roce_ackcreds; 1050 if (iwdev->push_mode && udata && 1051 iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 1052 spin_unlock_irqrestore(&iwqp->lock, flags); 1053 irdma_alloc_push_page(iwqp); 1054 spin_lock_irqsave(&iwqp->lock, flags); 1055 } 1056 break; 1057 case IB_QPS_SQD: 1058 if (iwqp->iwarp_state == IRDMA_QP_STATE_SQD) 1059 goto exit; 1060 1061 if (iwqp->iwarp_state != IRDMA_QP_STATE_RTS) { 1062 ret = -EINVAL; 1063 goto exit; 1064 } 1065 1066 info.next_iwarp_state = IRDMA_QP_STATE_SQD; 1067 issue_modify_qp = 1; 1068 iwqp->suspend_pending = true; 1069 break; 1070 case IB_QPS_SQE: 1071 case IB_QPS_ERR: 1072 case IB_QPS_RESET: 1073 if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) { 1074 spin_unlock_irqrestore(&iwqp->lock, flags); 1075 if (udata && udata->inlen) { 1076 if (ib_copy_from_udata(&ureq, udata, 1077 min(sizeof(ureq), udata->inlen))) 1078 return -EINVAL; 1079 1080 irdma_flush_wqes(iwqp, 1081 (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) | 1082 (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) | 1083 IRDMA_REFLUSH); 1084 } 1085 return 0; 1086 } 1087 1088 info.next_iwarp_state = IRDMA_QP_STATE_ERROR; 1089 issue_modify_qp = 1; 1090 break; 1091 default: 1092 ret = -EINVAL; 1093 goto exit; 1094 } 1095 1096 iwqp->ibqp_state = attr->qp_state; 1097 } 1098 1099 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id; 1100 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id; 1101 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info); 1102 spin_unlock_irqrestore(&iwqp->lock, flags); 1103 1104 if (attr_mask & IB_QP_STATE) { 1105 if (issue_modify_qp) { 1106 ctx_info->rem_endpoint_idx = udp_info->arp_idx; 1107 if (irdma_hw_modify_qp(iwdev, iwqp, &info, true)) 1108 return -EINVAL; 1109 if (info.next_iwarp_state == IRDMA_QP_STATE_SQD) { 1110 ret = irdma_wait_for_suspend(iwqp); 1111 if (ret) 1112 return ret; 1113 } 1114 spin_lock_irqsave(&iwqp->lock, flags); 1115 if (iwqp->iwarp_state == info.curr_iwarp_state) { 1116 iwqp->iwarp_state = info.next_iwarp_state; 1117 iwqp->ibqp_state = attr->qp_state; 1118 iwqp->sc_qp.qp_state = iwqp->iwarp_state; 1119 } 1120 if (iwqp->ibqp_state > IB_QPS_RTS && 1121 !atomic_read(&iwqp->flush_issued)) { 1122 spin_unlock_irqrestore(&iwqp->lock, flags); 1123 irdma_flush_wqes(iwqp, IRDMA_FLUSH_SQ | 1124 IRDMA_FLUSH_RQ | 1125 IRDMA_FLUSH_WAIT); 1126 1127 } else { 1128 spin_unlock_irqrestore(&iwqp->lock, flags); 1129 } 1130 } else { 1131 iwqp->ibqp_state = attr->qp_state; 1132 } 1133 if (udata && udata->outlen && dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1134 struct irdma_ucontext *ucontext; 1135 1136 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext); 1137 if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX && 1138 !iwqp->push_wqe_mmap_entry && 1139 !irdma_setup_push_mmap_entries(ucontext, iwqp, 1140 &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) { 1141 uresp.push_valid = 1; 1142 uresp.push_offset = iwqp->sc_qp.push_offset; 1143 } 1144 uresp.rd_fence_rate = iwdev->rd_fence_rate; 1145 ret = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), 1146 udata->outlen)); 1147 if (ret) { 1148 irdma_remove_push_mmap_entries(iwqp); 1149 irdma_debug(&iwdev->rf->sc_dev, 1150 IRDMA_DEBUG_VERBS, 1151 "copy_to_udata failed\n"); 1152 return ret; 1153 } 1154 } 1155 } 1156 1157 return 0; 1158 exit: 1159 spin_unlock_irqrestore(&iwqp->lock, flags); 1160 1161 return ret; 1162 } 1163 1164 /** 1165 * irdma_modify_qp - modify qp request 1166 * @ibqp: qp's pointer for modify 1167 * @attr: access attributes 1168 * @attr_mask: state mask 1169 * @udata: user data 1170 */ 1171 int 1172 irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, 1173 struct ib_udata *udata) 1174 { 1175 #define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush) 1176 #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid) 1177 struct irdma_qp *iwqp = to_iwqp(ibqp); 1178 struct irdma_device *iwdev = iwqp->iwdev; 1179 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; 1180 struct irdma_qp_host_ctx_info *ctx_info; 1181 struct irdma_tcp_offload_info *tcp_info; 1182 struct irdma_iwarp_offload_info *offload_info; 1183 struct irdma_modify_qp_info info = {0}; 1184 struct irdma_modify_qp_resp uresp = {}; 1185 struct irdma_modify_qp_req ureq = {}; 1186 u8 issue_modify_qp = 0; 1187 u8 dont_wait = 0; 1188 int err; 1189 unsigned long flags; 1190 1191 if (udata) { 1192 if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) || 1193 (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN)) 1194 return -EINVAL; 1195 } 1196 1197 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 1198 return -EOPNOTSUPP; 1199 1200 ctx_info = &iwqp->ctx_info; 1201 offload_info = &iwqp->iwarp_info; 1202 tcp_info = &iwqp->tcp_info; 1203 wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend)); 1204 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 1205 "caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d last_aeq=%d hw_tcp_state=%d hw_iwarp_state=%d attr_mask=0x%x\n", 1206 __builtin_return_address(0), ibqp->qp_num, attr->qp_state, 1207 iwqp->ibqp_state, iwqp->iwarp_state, iwqp->last_aeq, 1208 iwqp->hw_tcp_state, iwqp->hw_iwarp_state, attr_mask); 1209 1210 spin_lock_irqsave(&iwqp->lock, flags); 1211 if (attr_mask & IB_QP_STATE) { 1212 info.curr_iwarp_state = iwqp->iwarp_state; 1213 switch (attr->qp_state) { 1214 case IB_QPS_INIT: 1215 case IB_QPS_RTR: 1216 if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) { 1217 err = -EINVAL; 1218 goto exit; 1219 } 1220 1221 if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) { 1222 info.next_iwarp_state = IRDMA_QP_STATE_IDLE; 1223 issue_modify_qp = 1; 1224 } 1225 if (iwdev->push_mode && udata && 1226 iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 1227 spin_unlock_irqrestore(&iwqp->lock, flags); 1228 irdma_alloc_push_page(iwqp); 1229 spin_lock_irqsave(&iwqp->lock, flags); 1230 } 1231 break; 1232 case IB_QPS_RTS: 1233 if (iwqp->iwarp_state > IRDMA_QP_STATE_RTS || 1234 !iwqp->cm_id) { 1235 err = -EINVAL; 1236 goto exit; 1237 } 1238 1239 issue_modify_qp = 1; 1240 iwqp->hw_tcp_state = IRDMA_TCP_STATE_ESTABLISHED; 1241 iwqp->hte_added = 1; 1242 info.next_iwarp_state = IRDMA_QP_STATE_RTS; 1243 info.tcp_ctx_valid = true; 1244 info.ord_valid = true; 1245 info.arp_cache_idx_valid = true; 1246 info.cq_num_valid = true; 1247 break; 1248 case IB_QPS_SQD: 1249 if (iwqp->hw_iwarp_state > IRDMA_QP_STATE_RTS) { 1250 err = 0; 1251 goto exit; 1252 } 1253 1254 if (iwqp->iwarp_state == IRDMA_QP_STATE_CLOSING || 1255 iwqp->iwarp_state < IRDMA_QP_STATE_RTS) { 1256 err = 0; 1257 goto exit; 1258 } 1259 1260 if (iwqp->iwarp_state > IRDMA_QP_STATE_CLOSING) { 1261 err = -EINVAL; 1262 goto exit; 1263 } 1264 1265 info.next_iwarp_state = IRDMA_QP_STATE_CLOSING; 1266 issue_modify_qp = 1; 1267 break; 1268 case IB_QPS_SQE: 1269 if (iwqp->iwarp_state >= IRDMA_QP_STATE_TERMINATE) { 1270 err = -EINVAL; 1271 goto exit; 1272 } 1273 1274 info.next_iwarp_state = IRDMA_QP_STATE_TERMINATE; 1275 issue_modify_qp = 1; 1276 break; 1277 case IB_QPS_ERR: 1278 case IB_QPS_RESET: 1279 if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) { 1280 spin_unlock_irqrestore(&iwqp->lock, flags); 1281 if (udata && udata->inlen) { 1282 if (ib_copy_from_udata(&ureq, udata, 1283 min(sizeof(ureq), udata->inlen))) 1284 return -EINVAL; 1285 1286 irdma_flush_wqes(iwqp, 1287 (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) | 1288 (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) | 1289 IRDMA_REFLUSH); 1290 } 1291 return 0; 1292 } 1293 1294 if (iwqp->sc_qp.term_flags) { 1295 spin_unlock_irqrestore(&iwqp->lock, flags); 1296 irdma_terminate_del_timer(&iwqp->sc_qp); 1297 spin_lock_irqsave(&iwqp->lock, flags); 1298 } 1299 info.next_iwarp_state = IRDMA_QP_STATE_ERROR; 1300 if (iwqp->hw_tcp_state > IRDMA_TCP_STATE_CLOSED && 1301 iwdev->iw_status && 1302 iwqp->hw_tcp_state != IRDMA_TCP_STATE_TIME_WAIT) 1303 info.reset_tcp_conn = true; 1304 else 1305 dont_wait = 1; 1306 1307 issue_modify_qp = 1; 1308 info.next_iwarp_state = IRDMA_QP_STATE_ERROR; 1309 break; 1310 default: 1311 err = -EINVAL; 1312 goto exit; 1313 } 1314 1315 iwqp->ibqp_state = attr->qp_state; 1316 } 1317 if (attr_mask & IB_QP_ACCESS_FLAGS) { 1318 ctx_info->iwarp_info_valid = true; 1319 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE) 1320 offload_info->wr_rdresp_en = true; 1321 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 1322 offload_info->wr_rdresp_en = true; 1323 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 1324 offload_info->rd_en = true; 1325 } 1326 1327 if (ctx_info->iwarp_info_valid) { 1328 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id; 1329 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id; 1330 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info); 1331 } 1332 spin_unlock_irqrestore(&iwqp->lock, flags); 1333 1334 if (attr_mask & IB_QP_STATE) { 1335 if (issue_modify_qp) { 1336 ctx_info->rem_endpoint_idx = tcp_info->arp_idx; 1337 if (irdma_hw_modify_qp(iwdev, iwqp, &info, true)) 1338 return -EINVAL; 1339 } 1340 1341 spin_lock_irqsave(&iwqp->lock, flags); 1342 if (iwqp->iwarp_state == info.curr_iwarp_state) { 1343 iwqp->iwarp_state = info.next_iwarp_state; 1344 iwqp->ibqp_state = attr->qp_state; 1345 iwqp->sc_qp.qp_state = iwqp->iwarp_state; 1346 } 1347 spin_unlock_irqrestore(&iwqp->lock, flags); 1348 } 1349 1350 if (issue_modify_qp && iwqp->ibqp_state > IB_QPS_RTS) { 1351 if (dont_wait) { 1352 if (iwqp->hw_tcp_state) { 1353 spin_lock_irqsave(&iwqp->lock, flags); 1354 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSED; 1355 iwqp->last_aeq = IRDMA_AE_RESET_SENT; 1356 spin_unlock_irqrestore(&iwqp->lock, flags); 1357 } 1358 irdma_cm_disconn(iwqp); 1359 } else { 1360 int close_timer_started; 1361 1362 spin_lock_irqsave(&iwdev->cm_core.ht_lock, flags); 1363 1364 if (iwqp->cm_node) { 1365 irdma_add_ref_cmnode(iwqp->cm_node); 1366 spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags); 1367 close_timer_started = atomic_inc_return(&iwqp->close_timer_started); 1368 if (iwqp->cm_id && close_timer_started == 1) 1369 irdma_schedule_cm_timer(iwqp->cm_node, 1370 (struct irdma_puda_buf *)iwqp, 1371 IRDMA_TIMER_TYPE_CLOSE, 1, 0); 1372 1373 irdma_rem_ref_cmnode(iwqp->cm_node); 1374 } else { 1375 spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags); 1376 } 1377 } 1378 } 1379 if (attr_mask & IB_QP_STATE && udata && udata->outlen && 1380 dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1381 struct irdma_ucontext *ucontext; 1382 1383 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext); 1384 if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX && 1385 !iwqp->push_wqe_mmap_entry && 1386 !irdma_setup_push_mmap_entries(ucontext, iwqp, 1387 &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) { 1388 uresp.push_valid = 1; 1389 uresp.push_offset = iwqp->sc_qp.push_offset; 1390 } 1391 uresp.rd_fence_rate = iwdev->rd_fence_rate; 1392 1393 err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), 1394 udata->outlen)); 1395 if (err) { 1396 irdma_remove_push_mmap_entries(iwqp); 1397 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 1398 "copy_to_udata failed\n"); 1399 return err; 1400 } 1401 } 1402 1403 return 0; 1404 exit: 1405 spin_unlock_irqrestore(&iwqp->lock, flags); 1406 1407 return err; 1408 } 1409 1410 /** 1411 * irdma_cq_free_rsrc - free up resources for cq 1412 * @rf: RDMA PCI function 1413 * @iwcq: cq ptr 1414 */ 1415 void 1416 irdma_cq_free_rsrc(struct irdma_pci_f *rf, struct irdma_cq *iwcq) 1417 { 1418 struct irdma_sc_cq *cq = &iwcq->sc_cq; 1419 1420 if (!iwcq->user_mode) { 1421 irdma_free_dma_mem(rf->sc_dev.hw, &iwcq->kmem); 1422 irdma_free_dma_mem(rf->sc_dev.hw, &iwcq->kmem_shadow); 1423 } 1424 1425 irdma_free_rsrc(rf, rf->allocated_cqs, cq->cq_uk.cq_id); 1426 } 1427 1428 /** 1429 * irdma_free_cqbuf - worker to free a cq buffer 1430 * @work: provides access to the cq buffer to free 1431 */ 1432 static void 1433 irdma_free_cqbuf(struct work_struct *work) 1434 { 1435 struct irdma_cq_buf *cq_buf = container_of(work, struct irdma_cq_buf, work); 1436 1437 irdma_free_dma_mem(cq_buf->hw, &cq_buf->kmem_buf); 1438 kfree(cq_buf); 1439 } 1440 1441 /** 1442 * irdma_process_resize_list - remove resized cq buffers from the resize_list 1443 * @iwcq: cq which owns the resize_list 1444 * @iwdev: irdma device 1445 * @lcqe_buf: the buffer where the last cqe is received 1446 */ 1447 int 1448 irdma_process_resize_list(struct irdma_cq *iwcq, 1449 struct irdma_device *iwdev, 1450 struct irdma_cq_buf *lcqe_buf) 1451 { 1452 struct list_head *tmp_node, *list_node; 1453 struct irdma_cq_buf *cq_buf; 1454 int cnt = 0; 1455 1456 list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) { 1457 cq_buf = list_entry(list_node, struct irdma_cq_buf, list); 1458 if (cq_buf == lcqe_buf) 1459 return cnt; 1460 1461 list_del(&cq_buf->list); 1462 queue_work(iwdev->cleanup_wq, &cq_buf->work); 1463 cnt++; 1464 } 1465 1466 return cnt; 1467 } 1468 1469 /** 1470 * irdma_resize_cq - resize cq 1471 * @ibcq: cq to be resized 1472 * @entries: desired cq size 1473 * @udata: user data 1474 */ 1475 static int 1476 irdma_resize_cq(struct ib_cq *ibcq, int entries, 1477 struct ib_udata *udata) 1478 { 1479 #define IRDMA_RESIZE_CQ_MIN_REQ_LEN offsetofend(struct irdma_resize_cq_req, user_cq_buffer) 1480 struct irdma_cq *iwcq = to_iwcq(ibcq); 1481 struct irdma_sc_dev *dev = iwcq->sc_cq.dev; 1482 struct irdma_cqp_request *cqp_request; 1483 struct cqp_cmds_info *cqp_info; 1484 struct irdma_modify_cq_info *m_info; 1485 struct irdma_modify_cq_info info = {0}; 1486 struct irdma_dma_mem kmem_buf; 1487 struct irdma_cq_mr *cqmr_buf; 1488 struct irdma_pbl *iwpbl_buf; 1489 struct irdma_device *iwdev; 1490 struct irdma_pci_f *rf; 1491 struct irdma_cq_buf *cq_buf = NULL; 1492 unsigned long flags; 1493 int ret; 1494 1495 iwdev = to_iwdev(ibcq->device); 1496 rf = iwdev->rf; 1497 1498 if (!(rf->sc_dev.hw_attrs.uk_attrs.feature_flags & 1499 IRDMA_FEATURE_CQ_RESIZE)) 1500 return -EOPNOTSUPP; 1501 1502 if (udata && udata->inlen < IRDMA_RESIZE_CQ_MIN_REQ_LEN) 1503 return -EINVAL; 1504 1505 if (entries > rf->max_cqe) 1506 return -EINVAL; 1507 1508 if (!iwcq->user_mode) { 1509 entries++; 1510 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) 1511 entries *= 2; 1512 } 1513 1514 info.cq_size = max_t(int, entries, 4); 1515 1516 if (info.cq_size == iwcq->sc_cq.cq_uk.cq_size - 1) 1517 return 0; 1518 1519 if (udata) { 1520 struct irdma_resize_cq_req req = {}; 1521 struct irdma_ucontext *ucontext = 1522 rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext); 1523 1524 /* CQ resize not supported with legacy GEN_1 libi40iw */ 1525 if (ucontext->legacy_mode) 1526 return -EOPNOTSUPP; 1527 1528 if (ib_copy_from_udata(&req, udata, 1529 min(sizeof(req), udata->inlen))) 1530 return -EINVAL; 1531 1532 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); 1533 iwpbl_buf = irdma_get_pbl((unsigned long)req.user_cq_buffer, 1534 &ucontext->cq_reg_mem_list); 1535 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); 1536 1537 if (!iwpbl_buf) 1538 return -ENOMEM; 1539 1540 cqmr_buf = &iwpbl_buf->cq_mr; 1541 if (iwpbl_buf->pbl_allocated) { 1542 info.virtual_map = true; 1543 info.pbl_chunk_size = 1; 1544 info.first_pm_pbl_idx = cqmr_buf->cq_pbl.idx; 1545 } else { 1546 info.cq_pa = cqmr_buf->cq_pbl.addr; 1547 } 1548 } else { 1549 /* Kmode CQ resize */ 1550 int rsize; 1551 1552 rsize = info.cq_size * sizeof(struct irdma_cqe); 1553 kmem_buf.size = round_up(rsize, 256); 1554 kmem_buf.va = irdma_allocate_dma_mem(dev->hw, &kmem_buf, 1555 kmem_buf.size, 256); 1556 if (!kmem_buf.va) 1557 return -ENOMEM; 1558 1559 info.cq_base = kmem_buf.va; 1560 info.cq_pa = kmem_buf.pa; 1561 cq_buf = kzalloc(sizeof(*cq_buf), GFP_KERNEL); 1562 if (!cq_buf) { 1563 ret = -ENOMEM; 1564 goto error; 1565 } 1566 } 1567 1568 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); 1569 if (!cqp_request) { 1570 ret = -ENOMEM; 1571 goto error; 1572 } 1573 1574 info.shadow_read_threshold = iwcq->sc_cq.shadow_read_threshold; 1575 info.cq_resize = true; 1576 1577 cqp_info = &cqp_request->info; 1578 m_info = &cqp_info->in.u.cq_modify.info; 1579 memcpy(m_info, &info, sizeof(*m_info)); 1580 1581 cqp_info->cqp_cmd = IRDMA_OP_CQ_MODIFY; 1582 cqp_info->in.u.cq_modify.cq = &iwcq->sc_cq; 1583 cqp_info->in.u.cq_modify.scratch = (uintptr_t)cqp_request; 1584 cqp_info->post_sq = 1; 1585 cqp_info->create = true; 1586 ret = irdma_handle_cqp_op(rf, cqp_request); 1587 irdma_put_cqp_request(&rf->cqp, cqp_request); 1588 if (ret) 1589 goto error; 1590 1591 spin_lock_irqsave(&iwcq->lock, flags); 1592 if (cq_buf) { 1593 cq_buf->kmem_buf = iwcq->kmem; 1594 cq_buf->hw = dev->hw; 1595 memcpy(&cq_buf->cq_uk, &iwcq->sc_cq.cq_uk, sizeof(cq_buf->cq_uk)); 1596 INIT_WORK(&cq_buf->work, irdma_free_cqbuf); 1597 list_add_tail(&cq_buf->list, &iwcq->resize_list); 1598 iwcq->kmem = kmem_buf; 1599 } 1600 1601 irdma_sc_cq_resize(&iwcq->sc_cq, &info); 1602 ibcq->cqe = info.cq_size - 1; 1603 spin_unlock_irqrestore(&iwcq->lock, flags); 1604 1605 return 0; 1606 error: 1607 if (!udata) 1608 irdma_free_dma_mem(dev->hw, &kmem_buf); 1609 kfree(cq_buf); 1610 1611 return ret; 1612 } 1613 1614 /** 1615 * irdma_get_mr_access - get hw MR access permissions from IB access flags 1616 * @access: IB access flags 1617 * @hw_rev: Hardware version 1618 */ 1619 static inline u16 irdma_get_mr_access(int access, u8 hw_rev) 1620 { 1621 u16 hw_access = 0; 1622 1623 hw_access |= (access & IB_ACCESS_LOCAL_WRITE) ? 1624 IRDMA_ACCESS_FLAGS_LOCALWRITE : 0; 1625 hw_access |= (access & IB_ACCESS_REMOTE_WRITE) ? 1626 IRDMA_ACCESS_FLAGS_REMOTEWRITE : 0; 1627 hw_access |= (access & IB_ACCESS_REMOTE_READ) ? 1628 IRDMA_ACCESS_FLAGS_REMOTEREAD : 0; 1629 hw_access |= (access & IB_ZERO_BASED) ? 1630 IRDMA_ACCESS_FLAGS_ZERO_BASED : 0; 1631 hw_access |= IRDMA_ACCESS_FLAGS_LOCALREAD; 1632 1633 return hw_access; 1634 } 1635 1636 /** 1637 * irdma_free_stag - free stag resource 1638 * @iwdev: irdma device 1639 * @stag: stag to free 1640 */ 1641 void 1642 irdma_free_stag(struct irdma_device *iwdev, u32 stag) 1643 { 1644 u32 stag_idx; 1645 1646 stag_idx = (stag & iwdev->rf->mr_stagmask) >> IRDMA_CQPSQ_STAG_IDX_S; 1647 irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_mrs, stag_idx); 1648 } 1649 1650 /** 1651 * irdma_create_stag - create random stag 1652 * @iwdev: irdma device 1653 */ 1654 u32 1655 irdma_create_stag(struct irdma_device *iwdev) 1656 { 1657 u32 stag; 1658 u32 stag_index = 0; 1659 u32 next_stag_index; 1660 u32 driver_key; 1661 u32 random; 1662 u8 consumer_key; 1663 int ret; 1664 1665 get_random_bytes(&random, sizeof(random)); 1666 consumer_key = (u8)random; 1667 1668 driver_key = random & ~iwdev->rf->mr_stagmask; 1669 next_stag_index = (random & iwdev->rf->mr_stagmask) >> 8; 1670 next_stag_index %= iwdev->rf->max_mr; 1671 1672 ret = irdma_alloc_rsrc(iwdev->rf, iwdev->rf->allocated_mrs, 1673 iwdev->rf->max_mr, &stag_index, 1674 &next_stag_index); 1675 if (ret) 1676 return 0; 1677 stag = stag_index << IRDMA_CQPSQ_STAG_IDX_S; 1678 stag |= driver_key; 1679 stag += (u32)consumer_key; 1680 1681 return stag; 1682 } 1683 1684 /** 1685 * irdma_check_mem_contiguous - check if pbls stored in arr are contiguous 1686 * @arr: lvl1 pbl array 1687 * @npages: page count 1688 * @pg_size: page size 1689 * 1690 */ 1691 static bool 1692 irdma_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size) 1693 { 1694 u32 pg_idx; 1695 1696 for (pg_idx = 0; pg_idx < npages; pg_idx++) { 1697 if ((*arr + ((u64)pg_size * pg_idx)) != arr[pg_idx]) 1698 return false; 1699 } 1700 1701 return true; 1702 } 1703 1704 /** 1705 * irdma_check_mr_contiguous - check if MR is physically contiguous 1706 * @palloc: pbl allocation struct 1707 * @pg_size: page size 1708 */ 1709 static bool 1710 irdma_check_mr_contiguous(struct irdma_pble_alloc *palloc, 1711 u32 pg_size) 1712 { 1713 struct irdma_pble_level2 *lvl2 = &palloc->level2; 1714 struct irdma_pble_info *leaf = lvl2->leaf; 1715 u64 *arr = NULL; 1716 u64 *start_addr = NULL; 1717 int i; 1718 bool ret; 1719 1720 if (palloc->level == PBLE_LEVEL_1) { 1721 arr = palloc->level1.addr; 1722 ret = irdma_check_mem_contiguous(arr, palloc->total_cnt, 1723 pg_size); 1724 return ret; 1725 } 1726 1727 start_addr = leaf->addr; 1728 1729 for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) { 1730 arr = leaf->addr; 1731 if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr) 1732 return false; 1733 ret = irdma_check_mem_contiguous(arr, leaf->cnt, pg_size); 1734 if (!ret) 1735 return false; 1736 } 1737 1738 return true; 1739 } 1740 1741 /** 1742 * irdma_setup_pbles - copy user pg address to pble's 1743 * @rf: RDMA PCI function 1744 * @iwmr: mr pointer for this memory registration 1745 * @lvl: requested pble levels 1746 */ 1747 static int 1748 irdma_setup_pbles(struct irdma_pci_f *rf, struct irdma_mr *iwmr, 1749 u8 lvl) 1750 { 1751 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 1752 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; 1753 struct irdma_pble_info *pinfo; 1754 u64 *pbl; 1755 int status; 1756 enum irdma_pble_level level = PBLE_LEVEL_1; 1757 1758 if (lvl) { 1759 status = irdma_get_pble(rf->pble_rsrc, palloc, iwmr->page_cnt, 1760 lvl); 1761 if (status) 1762 return status; 1763 1764 iwpbl->pbl_allocated = true; 1765 level = palloc->level; 1766 pinfo = (level == PBLE_LEVEL_1) ? &palloc->level1 : 1767 palloc->level2.leaf; 1768 pbl = pinfo->addr; 1769 } else { 1770 pbl = iwmr->pgaddrmem; 1771 } 1772 1773 irdma_copy_user_pgaddrs(iwmr, pbl, level); 1774 1775 if (lvl) 1776 iwmr->pgaddrmem[0] = *pbl; 1777 1778 return 0; 1779 } 1780 1781 /** 1782 * irdma_handle_q_mem - handle memory for qp and cq 1783 * @iwdev: irdma device 1784 * @req: information for q memory management 1785 * @iwpbl: pble struct 1786 * @lvl: pble level mask 1787 */ 1788 static int 1789 irdma_handle_q_mem(struct irdma_device *iwdev, 1790 struct irdma_mem_reg_req *req, 1791 struct irdma_pbl *iwpbl, u8 lvl) 1792 { 1793 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; 1794 struct irdma_mr *iwmr = iwpbl->iwmr; 1795 struct irdma_qp_mr *qpmr = &iwpbl->qp_mr; 1796 struct irdma_cq_mr *cqmr = &iwpbl->cq_mr; 1797 struct irdma_hmc_pble *hmc_p; 1798 u64 *arr = iwmr->pgaddrmem; 1799 u32 pg_size, total; 1800 int err = 0; 1801 bool ret = true; 1802 1803 pg_size = iwmr->page_size; 1804 err = irdma_setup_pbles(iwdev->rf, iwmr, lvl); 1805 if (err) 1806 return err; 1807 1808 if (lvl) 1809 arr = palloc->level1.addr; 1810 1811 switch (iwmr->type) { 1812 case IRDMA_MEMREG_TYPE_QP: 1813 total = req->sq_pages + req->rq_pages; 1814 hmc_p = &qpmr->sq_pbl; 1815 qpmr->shadow = (dma_addr_t) arr[total]; 1816 if (lvl) { 1817 ret = irdma_check_mem_contiguous(arr, req->sq_pages, 1818 pg_size); 1819 if (ret) 1820 ret = irdma_check_mem_contiguous(&arr[req->sq_pages], 1821 req->rq_pages, 1822 pg_size); 1823 } 1824 1825 if (!ret) { 1826 hmc_p->idx = palloc->level1.idx; 1827 hmc_p = &qpmr->rq_pbl; 1828 hmc_p->idx = palloc->level1.idx + req->sq_pages; 1829 } else { 1830 hmc_p->addr = arr[0]; 1831 hmc_p = &qpmr->rq_pbl; 1832 hmc_p->addr = arr[req->sq_pages]; 1833 } 1834 break; 1835 case IRDMA_MEMREG_TYPE_CQ: 1836 hmc_p = &cqmr->cq_pbl; 1837 1838 if (!cqmr->split) 1839 cqmr->shadow = (dma_addr_t) arr[req->cq_pages]; 1840 1841 if (lvl) 1842 ret = irdma_check_mem_contiguous(arr, req->cq_pages, 1843 pg_size); 1844 1845 if (!ret) 1846 hmc_p->idx = palloc->level1.idx; 1847 else 1848 hmc_p->addr = arr[0]; 1849 break; 1850 default: 1851 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, "MR type error\n"); 1852 err = -EINVAL; 1853 } 1854 1855 if (lvl && ret) { 1856 irdma_free_pble(iwdev->rf->pble_rsrc, palloc); 1857 iwpbl->pbl_allocated = false; 1858 } 1859 1860 return err; 1861 } 1862 1863 /** 1864 * irdma_hw_alloc_mw - create the hw memory window 1865 * @iwdev: irdma device 1866 * @iwmr: pointer to memory window info 1867 */ 1868 int 1869 irdma_hw_alloc_mw(struct irdma_device *iwdev, struct irdma_mr *iwmr) 1870 { 1871 struct irdma_mw_alloc_info *info; 1872 struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd); 1873 struct irdma_cqp_request *cqp_request; 1874 struct cqp_cmds_info *cqp_info; 1875 int status; 1876 1877 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); 1878 if (!cqp_request) 1879 return -ENOMEM; 1880 1881 cqp_info = &cqp_request->info; 1882 info = &cqp_info->in.u.mw_alloc.info; 1883 if (iwmr->ibmw.type == IB_MW_TYPE_1) 1884 info->mw_wide = true; 1885 1886 info->page_size = PAGE_SIZE; 1887 info->mw_stag_index = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S; 1888 info->pd_id = iwpd->sc_pd.pd_id; 1889 info->remote_access = true; 1890 cqp_info->cqp_cmd = IRDMA_OP_MW_ALLOC; 1891 cqp_info->post_sq = 1; 1892 cqp_info->in.u.mw_alloc.dev = &iwdev->rf->sc_dev; 1893 cqp_info->in.u.mw_alloc.scratch = (uintptr_t)cqp_request; 1894 cqp_info->create = true; 1895 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 1896 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 1897 1898 return status; 1899 } 1900 1901 /** 1902 * irdma_hw_alloc_stag - cqp command to allocate stag 1903 * @iwdev: irdma device 1904 * @iwmr: irdma mr pointer 1905 */ 1906 int 1907 irdma_hw_alloc_stag(struct irdma_device *iwdev, 1908 struct irdma_mr *iwmr) 1909 { 1910 struct irdma_allocate_stag_info *info; 1911 struct ib_pd *pd = iwmr->ibmr.pd; 1912 struct irdma_pd *iwpd = to_iwpd(pd); 1913 struct irdma_cqp_request *cqp_request; 1914 struct cqp_cmds_info *cqp_info; 1915 int status; 1916 1917 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); 1918 if (!cqp_request) 1919 return -ENOMEM; 1920 1921 cqp_info = &cqp_request->info; 1922 info = &cqp_info->in.u.alloc_stag.info; 1923 info->page_size = PAGE_SIZE; 1924 info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S; 1925 info->pd_id = iwpd->sc_pd.pd_id; 1926 info->total_len = iwmr->len; 1927 info->all_memory = (pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY) ? true : false; 1928 info->remote_access = true; 1929 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_STAG; 1930 cqp_info->post_sq = 1; 1931 cqp_info->in.u.alloc_stag.dev = &iwdev->rf->sc_dev; 1932 cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request; 1933 cqp_info->create = true; 1934 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 1935 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 1936 if (!status) 1937 iwmr->is_hwreg = 1; 1938 1939 return status; 1940 } 1941 1942 /** 1943 * irdma_set_page - populate pbl list for fmr 1944 * @ibmr: ib mem to access iwarp mr pointer 1945 * @addr: page dma address fro pbl list 1946 */ 1947 static int 1948 irdma_set_page(struct ib_mr *ibmr, u64 addr) 1949 { 1950 struct irdma_mr *iwmr = to_iwmr(ibmr); 1951 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 1952 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; 1953 u64 *pbl; 1954 1955 if (unlikely(iwmr->npages == iwmr->page_cnt)) 1956 return -ENOMEM; 1957 1958 if (palloc->level == PBLE_LEVEL_2) { 1959 struct irdma_pble_info *palloc_info = 1960 palloc->level2.leaf + (iwmr->npages >> PBLE_512_SHIFT); 1961 1962 palloc_info->addr[iwmr->npages & (PBLE_PER_PAGE - 1)] = addr; 1963 } else { 1964 pbl = palloc->level1.addr; 1965 pbl[iwmr->npages] = addr; 1966 } 1967 1968 iwmr->npages++; 1969 return 0; 1970 } 1971 1972 /** 1973 * irdma_map_mr_sg - map of sg list for fmr 1974 * @ibmr: ib mem to access iwarp mr pointer 1975 * @sg: scatter gather list 1976 * @sg_nents: number of sg pages 1977 * @sg_offset: scatter gather list for fmr 1978 */ 1979 static int 1980 irdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, 1981 int sg_nents, unsigned int *sg_offset) 1982 { 1983 struct irdma_mr *iwmr = to_iwmr(ibmr); 1984 1985 iwmr->npages = 0; 1986 1987 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, irdma_set_page); 1988 } 1989 1990 /** 1991 * irdma_hwreg_mr - send cqp command for memory registration 1992 * @iwdev: irdma device 1993 * @iwmr: irdma mr pointer 1994 * @access: access for MR 1995 */ 1996 int 1997 irdma_hwreg_mr(struct irdma_device *iwdev, struct irdma_mr *iwmr, 1998 u16 access) 1999 { 2000 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 2001 struct irdma_reg_ns_stag_info *stag_info; 2002 struct ib_pd *pd = iwmr->ibmr.pd; 2003 struct irdma_pd *iwpd = to_iwpd(pd); 2004 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; 2005 struct irdma_cqp_request *cqp_request; 2006 struct cqp_cmds_info *cqp_info; 2007 int ret; 2008 2009 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); 2010 if (!cqp_request) 2011 return -ENOMEM; 2012 2013 cqp_info = &cqp_request->info; 2014 stag_info = &cqp_info->in.u.mr_reg_non_shared.info; 2015 stag_info->va = iwpbl->user_base; 2016 stag_info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S; 2017 stag_info->stag_key = (u8)iwmr->stag; 2018 stag_info->total_len = iwmr->len; 2019 if ((pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY) || iwmr->dma_mr) 2020 stag_info->all_memory = true; 2021 else 2022 stag_info->all_memory = false; 2023 stag_info->access_rights = irdma_get_mr_access(access, 2024 iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev); 2025 stag_info->pd_id = iwpd->sc_pd.pd_id; 2026 if (stag_info->access_rights & IRDMA_ACCESS_FLAGS_ZERO_BASED) 2027 stag_info->addr_type = IRDMA_ADDR_TYPE_ZERO_BASED; 2028 else 2029 stag_info->addr_type = IRDMA_ADDR_TYPE_VA_BASED; 2030 stag_info->page_size = iwmr->page_size; 2031 2032 if (iwpbl->pbl_allocated) { 2033 if (palloc->level == PBLE_LEVEL_1) { 2034 stag_info->first_pm_pbl_index = palloc->level1.idx; 2035 stag_info->chunk_size = 1; 2036 } else { 2037 stag_info->first_pm_pbl_index = palloc->level2.root.idx; 2038 stag_info->chunk_size = 3; 2039 } 2040 } else { 2041 stag_info->reg_addr_pa = iwmr->pgaddrmem[0]; 2042 } 2043 2044 cqp_info->cqp_cmd = IRDMA_OP_MR_REG_NON_SHARED; 2045 cqp_info->post_sq = 1; 2046 cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->rf->sc_dev; 2047 cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request; 2048 cqp_info->create = true; 2049 ret = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2050 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2051 2052 if (!ret) 2053 iwmr->is_hwreg = 1; 2054 2055 return ret; 2056 } 2057 2058 /* 2059 * irdma_alloc_iwmr - Allocate iwmr @region - memory region @pd - protection domain @virt - virtual address @reg_type - 2060 * registration type 2061 */ 2062 struct irdma_mr * 2063 irdma_alloc_iwmr(struct ib_umem *region, 2064 struct ib_pd *pd, u64 virt, 2065 enum irdma_memreg_type reg_type) 2066 { 2067 struct irdma_pbl *iwpbl; 2068 struct irdma_mr *iwmr; 2069 2070 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL); 2071 if (!iwmr) 2072 return ERR_PTR(-ENOMEM); 2073 2074 iwpbl = &iwmr->iwpbl; 2075 iwpbl->iwmr = iwmr; 2076 iwmr->region = region; 2077 iwmr->ibmr.pd = pd; 2078 iwmr->ibmr.device = pd->device; 2079 iwmr->ibmr.iova = virt; 2080 iwmr->type = reg_type; 2081 2082 /* Some OOT versions of irdma_copy_user_pg_addr require the pg mask */ 2083 iwmr->page_msk = ~(IRDMA_HW_PAGE_SIZE - 1); 2084 iwmr->page_size = IRDMA_HW_PAGE_SIZE; 2085 iwmr->len = region->length; 2086 iwpbl->user_base = virt; 2087 iwmr->page_cnt = irdma_ib_umem_num_dma_blocks(region, iwmr->page_size, virt); 2088 2089 return iwmr; 2090 } 2091 2092 void 2093 irdma_free_iwmr(struct irdma_mr *iwmr) 2094 { 2095 kfree(iwmr); 2096 } 2097 2098 /* 2099 * irdma_reg_user_mr_type_mem - Handle memory registration @iwmr - irdma mr @access - access rights @create_stag - flag 2100 * to create stag or not 2101 */ 2102 int 2103 irdma_reg_user_mr_type_mem(struct irdma_mr *iwmr, int access, 2104 bool create_stag) 2105 { 2106 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); 2107 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 2108 u32 stag = 0; 2109 int err; 2110 u8 lvl; 2111 2112 lvl = iwmr->page_cnt != 1 ? PBLE_LEVEL_1 | PBLE_LEVEL_2 : PBLE_LEVEL_0; 2113 2114 err = irdma_setup_pbles(iwdev->rf, iwmr, lvl); 2115 if (err) 2116 return err; 2117 2118 if (lvl) { 2119 err = irdma_check_mr_contiguous(&iwpbl->pble_alloc, 2120 iwmr->page_size); 2121 if (err) { 2122 irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc); 2123 iwpbl->pbl_allocated = false; 2124 } 2125 } 2126 2127 if (create_stag) { 2128 stag = irdma_create_stag(iwdev); 2129 if (!stag) { 2130 err = -ENOMEM; 2131 goto free_pble; 2132 } 2133 2134 iwmr->stag = stag; 2135 iwmr->ibmr.rkey = stag; 2136 iwmr->ibmr.lkey = stag; 2137 } 2138 iwmr->access = access; 2139 err = irdma_hwreg_mr(iwdev, iwmr, access); 2140 if (err) 2141 goto err_hwreg; 2142 2143 return 0; 2144 2145 err_hwreg: 2146 if (stag) 2147 irdma_free_stag(iwdev, stag); 2148 2149 free_pble: 2150 if (iwpbl->pble_alloc.level != PBLE_LEVEL_0 && iwpbl->pbl_allocated) 2151 irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc); 2152 2153 return err; 2154 } 2155 2156 /* 2157 * irdma_reg_user_mr_type_qp - Handle QP memory registration @req - memory reg req @udata - user info @iwmr - irdma mr 2158 */ 2159 int 2160 irdma_reg_user_mr_type_qp(struct irdma_mem_reg_req req, 2161 struct ib_udata *udata, 2162 struct irdma_mr *iwmr) 2163 { 2164 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); 2165 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 2166 struct irdma_ucontext *ucontext; 2167 unsigned long flags; 2168 u32 total; 2169 int err; 2170 u8 lvl; 2171 2172 /* iWarp: Catch page not starting on OS page boundary */ 2173 if (!rdma_protocol_roce(&iwdev->ibdev, 1) && 2174 ib_umem_offset(iwmr->region)) 2175 return -EINVAL; 2176 2177 total = req.sq_pages + req.rq_pages + IRDMA_SHADOW_PGCNT; 2178 if (total > iwmr->page_cnt) 2179 return -EINVAL; 2180 2181 total = req.sq_pages + req.rq_pages; 2182 lvl = total > 2 ? PBLE_LEVEL_1 : PBLE_LEVEL_0; 2183 err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl); 2184 if (err) 2185 return err; 2186 2187 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext); 2188 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags); 2189 list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list); 2190 iwpbl->on_list = true; 2191 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); 2192 2193 return 0; 2194 } 2195 2196 /* 2197 * irdma_reg_user_mr_type_cq - Handle CQ memory registration @req - memory reg req @udata - user info @iwmr - irdma mr 2198 */ 2199 int 2200 irdma_reg_user_mr_type_cq(struct irdma_mem_reg_req req, 2201 struct ib_udata *udata, 2202 struct irdma_mr *iwmr) 2203 { 2204 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); 2205 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 2206 struct irdma_ucontext *ucontext; 2207 unsigned long flags; 2208 u32 total; 2209 int err; 2210 u8 lvl; 2211 2212 total = req.cq_pages + 2213 ((iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_CQ_RESIZE) ? 0 : IRDMA_SHADOW_PGCNT); 2214 if (total > iwmr->page_cnt) 2215 return -EINVAL; 2216 2217 lvl = req.cq_pages > 1 ? PBLE_LEVEL_1 : PBLE_LEVEL_0; 2218 err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl); 2219 if (err) 2220 return err; 2221 2222 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext); 2223 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); 2224 list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list); 2225 iwpbl->on_list = true; 2226 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); 2227 2228 return 0; 2229 } 2230 2231 int 2232 irdma_hwdereg_mr(struct ib_mr *ib_mr) 2233 { 2234 struct irdma_device *iwdev = to_iwdev(ib_mr->device); 2235 struct irdma_mr *iwmr = to_iwmr(ib_mr); 2236 struct irdma_pd *iwpd = to_iwpd(ib_mr->pd); 2237 struct irdma_dealloc_stag_info *info; 2238 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 2239 struct irdma_cqp_request *cqp_request; 2240 struct cqp_cmds_info *cqp_info; 2241 int status; 2242 2243 /* 2244 * Skip HW MR de-register when it is already de-registered during an MR re-reregister and the re-registration 2245 * fails 2246 */ 2247 if (!iwmr->is_hwreg) 2248 return 0; 2249 2250 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); 2251 if (!cqp_request) 2252 return -ENOMEM; 2253 2254 cqp_info = &cqp_request->info; 2255 info = &cqp_info->in.u.dealloc_stag.info; 2256 info->pd_id = iwpd->sc_pd.pd_id; 2257 info->stag_idx = RS_64_1(ib_mr->rkey, IRDMA_CQPSQ_STAG_IDX_S); 2258 info->mr = true; 2259 if (iwmr->type != IRDMA_MEMREG_TYPE_MEM) 2260 info->skip_flush_markers = true; 2261 if (iwpbl->pbl_allocated) 2262 info->dealloc_pbl = true; 2263 2264 cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG; 2265 cqp_info->post_sq = 1; 2266 cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev; 2267 cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request; 2268 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2269 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2270 2271 if (!status) 2272 iwmr->is_hwreg = 0; 2273 2274 return status; 2275 } 2276 2277 /* 2278 * irdma_rereg_mr_trans - Re-register a user MR for a change translation. @iwmr: ptr of iwmr @start: virtual start 2279 * address @len: length of mr @virt: virtual address 2280 * 2281 * Re-register a user memory region when a change translation is requested. Re-register a new region while reusing the 2282 * stag from the original registration. 2283 */ 2284 struct ib_mr * 2285 irdma_rereg_mr_trans(struct irdma_mr *iwmr, u64 start, u64 len, 2286 u64 virt, struct ib_udata *udata) 2287 { 2288 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); 2289 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 2290 struct ib_pd *pd = iwmr->ibmr.pd; 2291 struct ib_umem *region; 2292 int err; 2293 2294 region = ib_umem_get(pd->uobject->context, start, len, iwmr->access, 0); 2295 2296 if (IS_ERR(region)) { 2297 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 2298 "Failed to create ib_umem region err=%ld\n", 2299 PTR_ERR(region)); 2300 return (struct ib_mr *)region; 2301 } 2302 2303 iwmr->region = region; 2304 iwmr->ibmr.iova = virt; 2305 iwmr->ibmr.pd = pd; 2306 iwmr->page_size = PAGE_SIZE; 2307 2308 iwmr->len = region->length; 2309 iwpbl->user_base = virt; 2310 iwmr->page_cnt = irdma_ib_umem_num_dma_blocks(region, iwmr->page_size, 2311 virt); 2312 2313 err = irdma_reg_user_mr_type_mem(iwmr, iwmr->access, false); 2314 if (err) 2315 goto err; 2316 2317 return &iwmr->ibmr; 2318 2319 err: 2320 ib_umem_release(region); 2321 return ERR_PTR(err); 2322 } 2323 2324 /** 2325 * irdma_reg_phys_mr - register kernel physical memory 2326 * @pd: ibpd pointer 2327 * @addr: physical address of memory to register 2328 * @size: size of memory to register 2329 * @access: Access rights 2330 * @iova_start: start of virtual address for physical buffers 2331 * @dma_mr: Flag indicating DMA Mem region 2332 */ 2333 struct ib_mr * 2334 irdma_reg_phys_mr(struct ib_pd *pd, u64 addr, u64 size, int access, 2335 u64 *iova_start, bool dma_mr) 2336 { 2337 struct irdma_device *iwdev = to_iwdev(pd->device); 2338 struct irdma_pbl *iwpbl; 2339 struct irdma_mr *iwmr; 2340 u32 stag; 2341 int ret; 2342 2343 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL); 2344 if (!iwmr) 2345 return ERR_PTR(-ENOMEM); 2346 2347 iwmr->ibmr.pd = pd; 2348 iwmr->ibmr.device = pd->device; 2349 iwpbl = &iwmr->iwpbl; 2350 iwpbl->iwmr = iwmr; 2351 iwmr->type = IRDMA_MEMREG_TYPE_MEM; 2352 iwmr->dma_mr = dma_mr; 2353 iwpbl->user_base = *iova_start; 2354 stag = irdma_create_stag(iwdev); 2355 if (!stag) { 2356 ret = -ENOMEM; 2357 goto err; 2358 } 2359 2360 iwmr->stag = stag; 2361 iwmr->ibmr.iova = *iova_start; 2362 iwmr->ibmr.rkey = stag; 2363 iwmr->ibmr.lkey = stag; 2364 iwmr->page_cnt = 1; 2365 iwmr->pgaddrmem[0] = addr; 2366 iwmr->len = size; 2367 iwmr->page_size = SZ_4K; 2368 ret = irdma_hwreg_mr(iwdev, iwmr, access); 2369 if (ret) { 2370 irdma_free_stag(iwdev, stag); 2371 goto err; 2372 } 2373 2374 return &iwmr->ibmr; 2375 2376 err: 2377 kfree(iwmr); 2378 2379 return ERR_PTR(ret); 2380 } 2381 2382 /** 2383 * irdma_get_dma_mr - register physical mem 2384 * @pd: ptr of pd 2385 * @acc: access for memory 2386 */ 2387 static struct ib_mr * 2388 irdma_get_dma_mr(struct ib_pd *pd, int acc) 2389 { 2390 u64 kva = 0; 2391 2392 return irdma_reg_phys_mr(pd, 0, 0, acc, &kva, true); 2393 } 2394 2395 /** 2396 * irdma_del_memlist - Deleting pbl list entries for CQ/QP 2397 * @iwmr: iwmr for IB's user page addresses 2398 * @ucontext: ptr to user context 2399 */ 2400 void 2401 irdma_del_memlist(struct irdma_mr *iwmr, 2402 struct irdma_ucontext *ucontext) 2403 { 2404 struct irdma_pbl *iwpbl = &iwmr->iwpbl; 2405 unsigned long flags; 2406 2407 switch (iwmr->type) { 2408 case IRDMA_MEMREG_TYPE_CQ: 2409 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); 2410 if (iwpbl->on_list) { 2411 iwpbl->on_list = false; 2412 list_del(&iwpbl->list); 2413 } 2414 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); 2415 break; 2416 case IRDMA_MEMREG_TYPE_QP: 2417 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags); 2418 if (iwpbl->on_list) { 2419 iwpbl->on_list = false; 2420 list_del(&iwpbl->list); 2421 } 2422 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); 2423 break; 2424 default: 2425 break; 2426 } 2427 } 2428 2429 /** 2430 * irdma_post_send - kernel application wr 2431 * @ibqp: qp ptr for wr 2432 * @ib_wr: work request ptr 2433 * @bad_wr: return of bad wr if err 2434 */ 2435 static int 2436 irdma_post_send(struct ib_qp *ibqp, 2437 const struct ib_send_wr *ib_wr, 2438 const struct ib_send_wr **bad_wr) 2439 { 2440 struct irdma_qp *iwqp; 2441 struct irdma_qp_uk *ukqp; 2442 struct irdma_sc_dev *dev; 2443 struct irdma_post_sq_info info; 2444 int err = 0; 2445 unsigned long flags; 2446 bool inv_stag; 2447 struct irdma_ah *ah; 2448 2449 iwqp = to_iwqp(ibqp); 2450 ukqp = &iwqp->sc_qp.qp_uk; 2451 dev = &iwqp->iwdev->rf->sc_dev; 2452 2453 spin_lock_irqsave(&iwqp->lock, flags); 2454 while (ib_wr) { 2455 memset(&info, 0, sizeof(info)); 2456 inv_stag = false; 2457 info.wr_id = (ib_wr->wr_id); 2458 if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all) 2459 info.signaled = true; 2460 if (ib_wr->send_flags & IB_SEND_FENCE) 2461 info.read_fence = true; 2462 switch (ib_wr->opcode) { 2463 case IB_WR_SEND_WITH_IMM: 2464 if (ukqp->qp_caps & IRDMA_SEND_WITH_IMM) { 2465 info.imm_data_valid = true; 2466 info.imm_data = ntohl(ib_wr->ex.imm_data); 2467 } else { 2468 err = -EINVAL; 2469 break; 2470 } 2471 /* fallthrough */ 2472 case IB_WR_SEND: 2473 case IB_WR_SEND_WITH_INV: 2474 if (ib_wr->opcode == IB_WR_SEND || 2475 ib_wr->opcode == IB_WR_SEND_WITH_IMM) { 2476 if (ib_wr->send_flags & IB_SEND_SOLICITED) 2477 info.op_type = IRDMA_OP_TYPE_SEND_SOL; 2478 else 2479 info.op_type = IRDMA_OP_TYPE_SEND; 2480 } else { 2481 if (ib_wr->send_flags & IB_SEND_SOLICITED) 2482 info.op_type = IRDMA_OP_TYPE_SEND_SOL_INV; 2483 else 2484 info.op_type = IRDMA_OP_TYPE_SEND_INV; 2485 info.stag_to_inv = ib_wr->ex.invalidate_rkey; 2486 } 2487 2488 info.op.send.num_sges = ib_wr->num_sge; 2489 info.op.send.sg_list = ib_wr->sg_list; 2490 if (iwqp->ibqp.qp_type == IB_QPT_UD || 2491 iwqp->ibqp.qp_type == IB_QPT_GSI) { 2492 ah = to_iwah(ud_wr(ib_wr)->ah); 2493 info.op.send.ah_id = ah->sc_ah.ah_info.ah_idx; 2494 info.op.send.qkey = ud_wr(ib_wr)->remote_qkey; 2495 info.op.send.dest_qp = ud_wr(ib_wr)->remote_qpn; 2496 } 2497 2498 if (ib_wr->send_flags & IB_SEND_INLINE) 2499 err = irdma_uk_inline_send(ukqp, &info, false); 2500 else 2501 err = irdma_uk_send(ukqp, &info, false); 2502 break; 2503 case IB_WR_RDMA_WRITE_WITH_IMM: 2504 if (ukqp->qp_caps & IRDMA_WRITE_WITH_IMM) { 2505 info.imm_data_valid = true; 2506 info.imm_data = ntohl(ib_wr->ex.imm_data); 2507 } else { 2508 err = -EINVAL; 2509 break; 2510 } 2511 /* fallthrough */ 2512 case IB_WR_RDMA_WRITE: 2513 if (ib_wr->send_flags & IB_SEND_SOLICITED) 2514 info.op_type = IRDMA_OP_TYPE_RDMA_WRITE_SOL; 2515 else 2516 info.op_type = IRDMA_OP_TYPE_RDMA_WRITE; 2517 2518 info.op.rdma_write.num_lo_sges = ib_wr->num_sge; 2519 info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list; 2520 info.op.rdma_write.rem_addr.addr = rdma_wr(ib_wr)->remote_addr; 2521 info.op.rdma_write.rem_addr.lkey = rdma_wr(ib_wr)->rkey; 2522 if (ib_wr->send_flags & IB_SEND_INLINE) 2523 err = irdma_uk_inline_rdma_write(ukqp, &info, false); 2524 else 2525 err = irdma_uk_rdma_write(ukqp, &info, false); 2526 break; 2527 case IB_WR_RDMA_READ_WITH_INV: 2528 inv_stag = true; 2529 /* fallthrough */ 2530 case IB_WR_RDMA_READ: 2531 if (ib_wr->num_sge > 2532 dev->hw_attrs.uk_attrs.max_hw_read_sges) { 2533 err = -EINVAL; 2534 break; 2535 } 2536 info.op_type = IRDMA_OP_TYPE_RDMA_READ; 2537 info.op.rdma_read.rem_addr.addr = rdma_wr(ib_wr)->remote_addr; 2538 info.op.rdma_read.rem_addr.lkey = rdma_wr(ib_wr)->rkey; 2539 info.op.rdma_read.lo_sg_list = (void *)ib_wr->sg_list; 2540 info.op.rdma_read.num_lo_sges = ib_wr->num_sge; 2541 err = irdma_uk_rdma_read(ukqp, &info, inv_stag, false); 2542 break; 2543 case IB_WR_LOCAL_INV: 2544 info.op_type = IRDMA_OP_TYPE_INV_STAG; 2545 info.local_fence = true; 2546 info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey; 2547 err = irdma_uk_stag_local_invalidate(ukqp, &info, true); 2548 break; 2549 case IB_WR_REG_MR:{ 2550 struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr); 2551 struct irdma_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc; 2552 struct irdma_fast_reg_stag_info stag_info = {0}; 2553 2554 stag_info.signaled = info.signaled; 2555 stag_info.read_fence = info.read_fence; 2556 stag_info.access_rights = 2557 irdma_get_mr_access(reg_wr(ib_wr)->access, 2558 dev->hw_attrs.uk_attrs.hw_rev); 2559 stag_info.stag_key = reg_wr(ib_wr)->key & 0xff; 2560 stag_info.stag_idx = reg_wr(ib_wr)->key >> 8; 2561 stag_info.page_size = reg_wr(ib_wr)->mr->page_size; 2562 stag_info.wr_id = ib_wr->wr_id; 2563 stag_info.addr_type = IRDMA_ADDR_TYPE_VA_BASED; 2564 stag_info.va = (void *)(uintptr_t)iwmr->ibmr.iova; 2565 stag_info.total_len = iwmr->ibmr.length; 2566 if (palloc->level == PBLE_LEVEL_2) { 2567 stag_info.chunk_size = 3; 2568 stag_info.first_pm_pbl_index = palloc->level2.root.idx; 2569 } else { 2570 stag_info.chunk_size = 1; 2571 stag_info.first_pm_pbl_index = palloc->level1.idx; 2572 } 2573 stag_info.local_fence = ib_wr->send_flags & IB_SEND_FENCE; 2574 err = irdma_sc_mr_fast_register(&iwqp->sc_qp, &stag_info, 2575 true); 2576 break; 2577 } 2578 default: 2579 err = -EINVAL; 2580 irdma_debug(&iwqp->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 2581 "upost_send bad opcode = 0x%x\n", 2582 ib_wr->opcode); 2583 break; 2584 } 2585 2586 if (err) 2587 break; 2588 ib_wr = ib_wr->next; 2589 } 2590 2591 if (!atomic_read(&iwqp->flush_issued)) { 2592 if (iwqp->hw_iwarp_state <= IRDMA_QP_STATE_RTS) 2593 irdma_uk_qp_post_wr(ukqp); 2594 spin_unlock_irqrestore(&iwqp->lock, flags); 2595 } else { 2596 spin_unlock_irqrestore(&iwqp->lock, flags); 2597 irdma_sched_qp_flush_work(iwqp); 2598 } 2599 2600 if (err) 2601 *bad_wr = ib_wr; 2602 2603 return err; 2604 } 2605 2606 /** 2607 * irdma_post_recv - post receive wr for kernel application 2608 * @ibqp: ib qp pointer 2609 * @ib_wr: work request for receive 2610 * @bad_wr: bad wr caused an error 2611 */ 2612 static int 2613 irdma_post_recv(struct ib_qp *ibqp, 2614 const struct ib_recv_wr *ib_wr, 2615 const struct ib_recv_wr **bad_wr) 2616 { 2617 struct irdma_qp *iwqp = to_iwqp(ibqp); 2618 struct irdma_qp_uk *ukqp = &iwqp->sc_qp.qp_uk; 2619 struct irdma_post_rq_info post_recv = {0}; 2620 unsigned long flags; 2621 int err = 0; 2622 2623 spin_lock_irqsave(&iwqp->lock, flags); 2624 2625 while (ib_wr) { 2626 if (ib_wr->num_sge > ukqp->max_rq_frag_cnt) { 2627 err = -EINVAL; 2628 goto out; 2629 } 2630 post_recv.num_sges = ib_wr->num_sge; 2631 post_recv.wr_id = ib_wr->wr_id; 2632 post_recv.sg_list = ib_wr->sg_list; 2633 err = irdma_uk_post_receive(ukqp, &post_recv); 2634 if (err) { 2635 irdma_debug(&iwqp->iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 2636 "post_recv err %d\n", err); 2637 goto out; 2638 } 2639 ib_wr = ib_wr->next; 2640 } 2641 2642 out: 2643 spin_unlock_irqrestore(&iwqp->lock, flags); 2644 2645 if (atomic_read(&iwqp->flush_issued)) 2646 irdma_sched_qp_flush_work(iwqp); 2647 2648 if (err) 2649 *bad_wr = ib_wr; 2650 2651 return err; 2652 } 2653 2654 /** 2655 * irdma_flush_err_to_ib_wc_status - return change flush error code to IB status 2656 * @opcode: iwarp flush code 2657 */ 2658 static enum ib_wc_status 2659 irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode opcode) 2660 { 2661 switch (opcode) { 2662 case FLUSH_PROT_ERR: 2663 return IB_WC_LOC_PROT_ERR; 2664 case FLUSH_REM_ACCESS_ERR: 2665 return IB_WC_REM_ACCESS_ERR; 2666 case FLUSH_LOC_QP_OP_ERR: 2667 return IB_WC_LOC_QP_OP_ERR; 2668 case FLUSH_REM_OP_ERR: 2669 return IB_WC_REM_OP_ERR; 2670 case FLUSH_LOC_LEN_ERR: 2671 return IB_WC_LOC_LEN_ERR; 2672 case FLUSH_GENERAL_ERR: 2673 return IB_WC_WR_FLUSH_ERR; 2674 case FLUSH_MW_BIND_ERR: 2675 return IB_WC_MW_BIND_ERR; 2676 case FLUSH_REM_INV_REQ_ERR: 2677 return IB_WC_REM_INV_REQ_ERR; 2678 case FLUSH_RETRY_EXC_ERR: 2679 return IB_WC_RETRY_EXC_ERR; 2680 case FLUSH_FATAL_ERR: 2681 default: 2682 return IB_WC_FATAL_ERR; 2683 } 2684 } 2685 2686 /** 2687 * irdma_process_cqe - process cqe info 2688 * @entry: processed cqe 2689 * @cq_poll_info: cqe info 2690 */ 2691 static void 2692 irdma_process_cqe(struct ib_wc *entry, 2693 struct irdma_cq_poll_info *cq_poll_info) 2694 { 2695 struct irdma_sc_qp *qp; 2696 2697 entry->wc_flags = 0; 2698 entry->pkey_index = 0; 2699 entry->wr_id = cq_poll_info->wr_id; 2700 2701 qp = cq_poll_info->qp_handle; 2702 entry->qp = qp->qp_uk.back_qp; 2703 2704 if (cq_poll_info->error) { 2705 entry->status = (cq_poll_info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) ? 2706 irdma_flush_err_to_ib_wc_status(cq_poll_info->minor_err) : IB_WC_GENERAL_ERR; 2707 2708 entry->vendor_err = cq_poll_info->major_err << 16 | 2709 cq_poll_info->minor_err; 2710 } else { 2711 entry->status = IB_WC_SUCCESS; 2712 if (cq_poll_info->imm_valid) { 2713 entry->ex.imm_data = htonl(cq_poll_info->imm_data); 2714 entry->wc_flags |= IB_WC_WITH_IMM; 2715 } 2716 if (cq_poll_info->ud_smac_valid) { 2717 ether_addr_copy(entry->smac, cq_poll_info->ud_smac); 2718 entry->wc_flags |= IB_WC_WITH_SMAC; 2719 } 2720 2721 if (cq_poll_info->ud_vlan_valid) { 2722 u16 vlan = cq_poll_info->ud_vlan & EVL_VLID_MASK; 2723 2724 entry->sl = cq_poll_info->ud_vlan >> VLAN_PRIO_SHIFT; 2725 if (vlan) { 2726 entry->vlan_id = vlan; 2727 entry->wc_flags |= IB_WC_WITH_VLAN; 2728 } 2729 } else { 2730 entry->sl = 0; 2731 } 2732 } 2733 2734 if (cq_poll_info->q_type == IRDMA_CQE_QTYPE_SQ) { 2735 set_ib_wc_op_sq(cq_poll_info, entry); 2736 } else { 2737 set_ib_wc_op_rq(cq_poll_info, entry, 2738 qp->qp_uk.qp_caps & IRDMA_SEND_WITH_IMM ? 2739 true : false); 2740 if (qp->qp_uk.qp_type != IRDMA_QP_TYPE_ROCE_UD && 2741 cq_poll_info->stag_invalid_set) { 2742 entry->ex.invalidate_rkey = cq_poll_info->inv_stag; 2743 entry->wc_flags |= IB_WC_WITH_INVALIDATE; 2744 } 2745 } 2746 2747 if (qp->qp_uk.qp_type == IRDMA_QP_TYPE_ROCE_UD) { 2748 entry->src_qp = cq_poll_info->ud_src_qpn; 2749 entry->slid = 0; 2750 entry->wc_flags |= 2751 (IB_WC_GRH | IB_WC_WITH_NETWORK_HDR_TYPE); 2752 entry->network_hdr_type = cq_poll_info->ipv4 ? 2753 RDMA_NETWORK_IPV4 : 2754 RDMA_NETWORK_IPV6; 2755 } else { 2756 entry->src_qp = cq_poll_info->qp_id; 2757 } 2758 2759 entry->byte_len = cq_poll_info->bytes_xfered; 2760 } 2761 2762 /** 2763 * irdma_poll_one - poll one entry of the CQ 2764 * @ukcq: ukcq to poll 2765 * @cur_cqe: current CQE info to be filled in 2766 * @entry: ibv_wc object to be filled for non-extended CQ or NULL for extended CQ 2767 * 2768 * Returns the internal irdma device error code or 0 on success 2769 */ 2770 static inline int 2771 irdma_poll_one(struct irdma_cq_uk *ukcq, 2772 struct irdma_cq_poll_info *cur_cqe, 2773 struct ib_wc *entry) 2774 { 2775 int ret = irdma_uk_cq_poll_cmpl(ukcq, cur_cqe); 2776 2777 if (ret) 2778 return ret; 2779 2780 irdma_process_cqe(entry, cur_cqe); 2781 2782 return 0; 2783 } 2784 2785 /** 2786 * __irdma_poll_cq - poll cq for completion (kernel apps) 2787 * @iwcq: cq to poll 2788 * @num_entries: number of entries to poll 2789 * @entry: wr of a completed entry 2790 */ 2791 static int 2792 __irdma_poll_cq(struct irdma_cq *iwcq, int num_entries, struct ib_wc *entry) 2793 { 2794 struct list_head *tmp_node, *list_node; 2795 struct irdma_cq_buf *last_buf = NULL; 2796 struct irdma_cq_poll_info *cur_cqe = &iwcq->cur_cqe; 2797 struct irdma_cq_buf *cq_buf; 2798 int ret; 2799 struct irdma_device *iwdev; 2800 struct irdma_cq_uk *ukcq; 2801 bool cq_new_cqe = false; 2802 int resized_bufs = 0; 2803 int npolled = 0; 2804 2805 iwdev = to_iwdev(iwcq->ibcq.device); 2806 ukcq = &iwcq->sc_cq.cq_uk; 2807 2808 /* go through the list of previously resized CQ buffers */ 2809 list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) { 2810 cq_buf = container_of(list_node, struct irdma_cq_buf, list); 2811 while (npolled < num_entries) { 2812 ret = irdma_poll_one(&cq_buf->cq_uk, cur_cqe, entry + npolled); 2813 if (!ret) { 2814 ++npolled; 2815 cq_new_cqe = true; 2816 continue; 2817 } 2818 if (ret == -ENOENT) 2819 break; 2820 /* QP using the CQ is destroyed. Skip reporting this CQE */ 2821 if (ret == -EFAULT) { 2822 cq_new_cqe = true; 2823 continue; 2824 } 2825 goto error; 2826 } 2827 2828 /* save the resized CQ buffer which received the last cqe */ 2829 if (cq_new_cqe) 2830 last_buf = cq_buf; 2831 cq_new_cqe = false; 2832 } 2833 2834 /* check the current CQ for new cqes */ 2835 while (npolled < num_entries) { 2836 ret = irdma_poll_one(ukcq, cur_cqe, entry + npolled); 2837 if (ret == -ENOENT) { 2838 ret = irdma_generated_cmpls(iwcq, cur_cqe); 2839 if (!ret) 2840 irdma_process_cqe(entry + npolled, cur_cqe); 2841 } 2842 if (!ret) { 2843 ++npolled; 2844 cq_new_cqe = true; 2845 continue; 2846 } 2847 2848 if (ret == -ENOENT) 2849 break; 2850 /* QP using the CQ is destroyed. Skip reporting this CQE */ 2851 if (ret == -EFAULT) { 2852 cq_new_cqe = true; 2853 continue; 2854 } 2855 goto error; 2856 } 2857 2858 if (cq_new_cqe) 2859 /* all previous CQ resizes are complete */ 2860 resized_bufs = irdma_process_resize_list(iwcq, iwdev, NULL); 2861 else if (last_buf) 2862 /* only CQ resizes up to the last_buf are complete */ 2863 resized_bufs = irdma_process_resize_list(iwcq, iwdev, last_buf); 2864 if (resized_bufs) 2865 /* report to the HW the number of complete CQ resizes */ 2866 irdma_uk_cq_set_resized_cnt(ukcq, resized_bufs); 2867 2868 return npolled; 2869 error: 2870 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 2871 "%s: Error polling CQ, irdma_err: %d\n", __func__, ret); 2872 2873 return ret; 2874 } 2875 2876 /** 2877 * irdma_poll_cq - poll cq for completion (kernel apps) 2878 * @ibcq: cq to poll 2879 * @num_entries: number of entries to poll 2880 * @entry: wr of a completed entry 2881 */ 2882 static int 2883 irdma_poll_cq(struct ib_cq *ibcq, int num_entries, 2884 struct ib_wc *entry) 2885 { 2886 struct irdma_cq *iwcq; 2887 unsigned long flags; 2888 int ret; 2889 2890 iwcq = to_iwcq(ibcq); 2891 2892 spin_lock_irqsave(&iwcq->lock, flags); 2893 ret = __irdma_poll_cq(iwcq, num_entries, entry); 2894 spin_unlock_irqrestore(&iwcq->lock, flags); 2895 2896 return ret; 2897 } 2898 2899 /** 2900 * irdma_req_notify_cq - arm cq kernel application 2901 * @ibcq: cq to arm 2902 * @notify_flags: notofication flags 2903 */ 2904 static int 2905 irdma_req_notify_cq(struct ib_cq *ibcq, 2906 enum ib_cq_notify_flags notify_flags) 2907 { 2908 struct irdma_cq *iwcq; 2909 struct irdma_cq_uk *ukcq; 2910 unsigned long flags; 2911 enum irdma_cmpl_notify cq_notify = IRDMA_CQ_COMPL_EVENT; 2912 bool promo_event = false; 2913 int ret = 0; 2914 2915 iwcq = to_iwcq(ibcq); 2916 ukcq = &iwcq->sc_cq.cq_uk; 2917 2918 spin_lock_irqsave(&iwcq->lock, flags); 2919 if (notify_flags == IB_CQ_SOLICITED) { 2920 cq_notify = IRDMA_CQ_COMPL_SOLICITED; 2921 } else { 2922 if (iwcq->last_notify == IRDMA_CQ_COMPL_SOLICITED) 2923 promo_event = true; 2924 } 2925 2926 if (!atomic_cmpxchg(&iwcq->armed, 0, 1) || promo_event) { 2927 iwcq->last_notify = cq_notify; 2928 irdma_uk_cq_request_notification(ukcq, cq_notify); 2929 } 2930 2931 if ((notify_flags & IB_CQ_REPORT_MISSED_EVENTS) && 2932 (!irdma_uk_cq_empty(&iwcq->sc_cq.cq_uk) || !list_empty(&iwcq->cmpl_generated))) 2933 ret = 1; 2934 spin_unlock_irqrestore(&iwcq->lock, flags); 2935 2936 return ret; 2937 } 2938 2939 /** 2940 * mcast_list_add - Add a new mcast item to list 2941 * @rf: RDMA PCI function 2942 * @new_elem: pointer to element to add 2943 */ 2944 static void 2945 mcast_list_add(struct irdma_pci_f *rf, 2946 struct mc_table_list *new_elem) 2947 { 2948 list_add(&new_elem->list, &rf->mc_qht_list.list); 2949 } 2950 2951 /** 2952 * mcast_list_del - Remove an mcast item from list 2953 * @mc_qht_elem: pointer to mcast table list element 2954 */ 2955 static void 2956 mcast_list_del(struct mc_table_list *mc_qht_elem) 2957 { 2958 if (mc_qht_elem) 2959 list_del(&mc_qht_elem->list); 2960 } 2961 2962 /** 2963 * mcast_list_lookup_ip - Search mcast list for address 2964 * @rf: RDMA PCI function 2965 * @ip_mcast: pointer to mcast IP address 2966 */ 2967 static struct mc_table_list * 2968 mcast_list_lookup_ip(struct irdma_pci_f *rf, 2969 u32 *ip_mcast) 2970 { 2971 struct mc_table_list *mc_qht_el; 2972 struct list_head *pos, *q; 2973 2974 list_for_each_safe(pos, q, &rf->mc_qht_list.list) { 2975 mc_qht_el = list_entry(pos, struct mc_table_list, list); 2976 if (!memcmp(mc_qht_el->mc_info.dest_ip, ip_mcast, 2977 sizeof(mc_qht_el->mc_info.dest_ip))) 2978 return mc_qht_el; 2979 } 2980 2981 return NULL; 2982 } 2983 2984 /** 2985 * irdma_mcast_cqp_op - perform a mcast cqp operation 2986 * @iwdev: irdma device 2987 * @mc_grp_ctx: mcast group info 2988 * @op: operation 2989 * 2990 * returns error status 2991 */ 2992 static int 2993 irdma_mcast_cqp_op(struct irdma_device *iwdev, 2994 struct irdma_mcast_grp_info *mc_grp_ctx, u8 op) 2995 { 2996 struct cqp_cmds_info *cqp_info; 2997 struct irdma_cqp_request *cqp_request; 2998 int status; 2999 3000 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); 3001 if (!cqp_request) 3002 return -ENOMEM; 3003 3004 cqp_request->info.in.u.mc_create.info = *mc_grp_ctx; 3005 cqp_info = &cqp_request->info; 3006 cqp_info->cqp_cmd = op; 3007 cqp_info->post_sq = 1; 3008 cqp_info->in.u.mc_create.scratch = (uintptr_t)cqp_request; 3009 cqp_info->in.u.mc_create.cqp = &iwdev->rf->cqp.sc_cqp; 3010 3011 if (op == IRDMA_OP_MC_CREATE) 3012 cqp_info->create = true; 3013 3014 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 3015 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 3016 3017 return status; 3018 } 3019 3020 /** 3021 * irdma_attach_mcast - attach a qp to a multicast group 3022 * @ibqp: ptr to qp 3023 * @ibgid: pointer to global ID 3024 * @lid: local ID 3025 * 3026 * returns error status 3027 */ 3028 static int 3029 irdma_attach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid) 3030 { 3031 struct irdma_qp *iwqp = to_iwqp(ibqp); 3032 struct irdma_device *iwdev = iwqp->iwdev; 3033 struct irdma_pci_f *rf = iwdev->rf; 3034 struct mc_table_list *mc_qht_elem; 3035 struct irdma_mcast_grp_ctx_entry_info mcg_info = {0}; 3036 unsigned long flags; 3037 u32 ip_addr[4] = {0}; 3038 u32 mgn; 3039 u32 no_mgs; 3040 int ret = 0; 3041 bool ipv4; 3042 u16 vlan_id; 3043 union irdma_sockaddr sgid_addr; 3044 unsigned char dmac[ETHER_ADDR_LEN]; 3045 3046 rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid); 3047 3048 if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid)) { 3049 irdma_copy_ip_ntohl(ip_addr, 3050 sgid_addr.saddr_in6.sin6_addr.__u6_addr.__u6_addr32); 3051 irdma_get_vlan_mac_ipv6(iwqp->cm_id, ip_addr, &vlan_id, NULL); 3052 ipv4 = false; 3053 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 3054 "qp_id=%d, IP6address=%x:%x:%x:%x\n", ibqp->qp_num, 3055 IRDMA_PRINT_IP6(ip_addr)); 3056 irdma_mcast_mac_v6(ip_addr, dmac); 3057 } else { 3058 ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr); 3059 ipv4 = true; 3060 vlan_id = irdma_get_vlan_ipv4(iwqp->cm_id, ip_addr); 3061 irdma_mcast_mac_v4(ip_addr, dmac); 3062 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 3063 "qp_id=%d, IP4address=%x, MAC=%x:%x:%x:%x:%x:%x\n", 3064 ibqp->qp_num, ip_addr[0], dmac[0], dmac[1], dmac[2], 3065 dmac[3], dmac[4], dmac[5]); 3066 } 3067 3068 spin_lock_irqsave(&rf->qh_list_lock, flags); 3069 mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr); 3070 if (!mc_qht_elem) { 3071 struct irdma_dma_mem *dma_mem_mc; 3072 3073 spin_unlock_irqrestore(&rf->qh_list_lock, flags); 3074 mc_qht_elem = kzalloc(sizeof(*mc_qht_elem), GFP_KERNEL); 3075 if (!mc_qht_elem) 3076 return -ENOMEM; 3077 3078 mc_qht_elem->mc_info.ipv4_valid = ipv4; 3079 memcpy(mc_qht_elem->mc_info.dest_ip, ip_addr, 3080 sizeof(mc_qht_elem->mc_info.dest_ip)); 3081 ret = irdma_alloc_rsrc(rf, rf->allocated_mcgs, rf->max_mcg, 3082 &mgn, &rf->next_mcg); 3083 if (ret) { 3084 kfree(mc_qht_elem); 3085 return -ENOMEM; 3086 } 3087 3088 mc_qht_elem->mc_info.mgn = mgn; 3089 dma_mem_mc = &mc_qht_elem->mc_grp_ctx.dma_mem_mc; 3090 dma_mem_mc->size = sizeof(u64)* IRDMA_MAX_MGS_PER_CTX; 3091 dma_mem_mc->va = irdma_allocate_dma_mem(&rf->hw, dma_mem_mc, 3092 dma_mem_mc->size, 3093 IRDMA_HW_PAGE_SIZE); 3094 if (!dma_mem_mc->va) { 3095 irdma_free_rsrc(rf, rf->allocated_mcgs, mgn); 3096 kfree(mc_qht_elem); 3097 return -ENOMEM; 3098 } 3099 3100 mc_qht_elem->mc_grp_ctx.mg_id = (u16)mgn; 3101 memcpy(mc_qht_elem->mc_grp_ctx.dest_ip_addr, ip_addr, 3102 sizeof(mc_qht_elem->mc_grp_ctx.dest_ip_addr)); 3103 mc_qht_elem->mc_grp_ctx.ipv4_valid = ipv4; 3104 mc_qht_elem->mc_grp_ctx.vlan_id = vlan_id; 3105 if (vlan_id < VLAN_N_VID) 3106 mc_qht_elem->mc_grp_ctx.vlan_valid = true; 3107 mc_qht_elem->mc_grp_ctx.hmc_fcn_id = iwdev->rf->sc_dev.hmc_fn_id; 3108 mc_qht_elem->mc_grp_ctx.qs_handle = 3109 iwqp->sc_qp.vsi->qos[iwqp->sc_qp.user_pri].qs_handle; 3110 ether_addr_copy(mc_qht_elem->mc_grp_ctx.dest_mac_addr, dmac); 3111 3112 spin_lock_irqsave(&rf->qh_list_lock, flags); 3113 mcast_list_add(rf, mc_qht_elem); 3114 } else { 3115 if (mc_qht_elem->mc_grp_ctx.no_of_mgs == 3116 IRDMA_MAX_MGS_PER_CTX) { 3117 spin_unlock_irqrestore(&rf->qh_list_lock, flags); 3118 return -ENOMEM; 3119 } 3120 } 3121 3122 mcg_info.qp_id = iwqp->ibqp.qp_num; 3123 no_mgs = mc_qht_elem->mc_grp_ctx.no_of_mgs; 3124 irdma_sc_add_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info); 3125 spin_unlock_irqrestore(&rf->qh_list_lock, flags); 3126 3127 /* Only if there is a change do we need to modify or create */ 3128 if (!no_mgs) { 3129 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx, 3130 IRDMA_OP_MC_CREATE); 3131 } else if (no_mgs != mc_qht_elem->mc_grp_ctx.no_of_mgs) { 3132 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx, 3133 IRDMA_OP_MC_MODIFY); 3134 } else { 3135 return 0; 3136 } 3137 3138 if (ret) 3139 goto error; 3140 3141 return 0; 3142 3143 error: 3144 irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info); 3145 if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) { 3146 mcast_list_del(mc_qht_elem); 3147 irdma_free_dma_mem(&rf->hw, 3148 &mc_qht_elem->mc_grp_ctx.dma_mem_mc); 3149 irdma_free_rsrc(rf, rf->allocated_mcgs, 3150 mc_qht_elem->mc_grp_ctx.mg_id); 3151 kfree(mc_qht_elem); 3152 } 3153 3154 return ret; 3155 } 3156 3157 /** 3158 * irdma_detach_mcast - detach a qp from a multicast group 3159 * @ibqp: ptr to qp 3160 * @ibgid: pointer to global ID 3161 * @lid: local ID 3162 * 3163 * returns error status 3164 */ 3165 static int 3166 irdma_detach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid) 3167 { 3168 struct irdma_qp *iwqp = to_iwqp(ibqp); 3169 struct irdma_device *iwdev = iwqp->iwdev; 3170 struct irdma_pci_f *rf = iwdev->rf; 3171 u32 ip_addr[4] = {0}; 3172 struct mc_table_list *mc_qht_elem; 3173 struct irdma_mcast_grp_ctx_entry_info mcg_info = {0}; 3174 int ret; 3175 unsigned long flags; 3176 union irdma_sockaddr sgid_addr; 3177 3178 rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid); 3179 if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid)) 3180 irdma_copy_ip_ntohl(ip_addr, 3181 sgid_addr.saddr_in6.sin6_addr.__u6_addr.__u6_addr32); 3182 else 3183 ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr); 3184 3185 spin_lock_irqsave(&rf->qh_list_lock, flags); 3186 mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr); 3187 if (!mc_qht_elem) { 3188 spin_unlock_irqrestore(&rf->qh_list_lock, flags); 3189 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 3190 "address not found MCG\n"); 3191 return 0; 3192 } 3193 3194 mcg_info.qp_id = iwqp->ibqp.qp_num; 3195 irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info); 3196 if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) { 3197 mcast_list_del(mc_qht_elem); 3198 spin_unlock_irqrestore(&rf->qh_list_lock, flags); 3199 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx, 3200 IRDMA_OP_MC_DESTROY); 3201 if (ret) { 3202 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 3203 "failed MC_DESTROY MCG\n"); 3204 spin_lock_irqsave(&rf->qh_list_lock, flags); 3205 mcast_list_add(rf, mc_qht_elem); 3206 spin_unlock_irqrestore(&rf->qh_list_lock, flags); 3207 return -EAGAIN; 3208 } 3209 3210 irdma_free_dma_mem(&rf->hw, 3211 &mc_qht_elem->mc_grp_ctx.dma_mem_mc); 3212 irdma_free_rsrc(rf, rf->allocated_mcgs, 3213 mc_qht_elem->mc_grp_ctx.mg_id); 3214 kfree(mc_qht_elem); 3215 } else { 3216 spin_unlock_irqrestore(&rf->qh_list_lock, flags); 3217 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx, 3218 IRDMA_OP_MC_MODIFY); 3219 if (ret) { 3220 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, 3221 "failed Modify MCG\n"); 3222 return ret; 3223 } 3224 } 3225 3226 return 0; 3227 } 3228 3229 /** 3230 * irdma_query_ah - Query address handle 3231 * @ibah: pointer to address handle 3232 * @ah_attr: address handle attributes 3233 */ 3234 static int 3235 irdma_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr) 3236 { 3237 struct irdma_ah *ah = to_iwah(ibah); 3238 3239 memset(ah_attr, 0, sizeof(*ah_attr)); 3240 if (ah->av.attrs.ah_flags & IB_AH_GRH) { 3241 ah_attr->ah_flags = IB_AH_GRH; 3242 ah_attr->grh.flow_label = ah->sc_ah.ah_info.flow_label; 3243 ah_attr->grh.traffic_class = ah->sc_ah.ah_info.tc_tos; 3244 ah_attr->grh.hop_limit = ah->sc_ah.ah_info.hop_ttl; 3245 ah_attr->grh.sgid_index = ah->sgid_index; 3246 ah_attr->grh.sgid_index = ah->sgid_index; 3247 memcpy(&ah_attr->grh.dgid, &ah->dgid, 3248 sizeof(ah_attr->grh.dgid)); 3249 } 3250 3251 return 0; 3252 } 3253 3254 static if_t irdma_get_netdev(struct ib_device *ibdev, u8 port_num){ 3255 struct irdma_device *iwdev = to_iwdev(ibdev); 3256 3257 if (iwdev->netdev) { 3258 dev_hold(iwdev->netdev); 3259 return iwdev->netdev; 3260 } 3261 3262 return NULL; 3263 } 3264 3265 static void 3266 irdma_set_device_ops(struct ib_device *ibdev) 3267 { 3268 struct ib_device *dev_ops = ibdev; 3269 3270 dev_ops->ops.driver_id = RDMA_DRIVER_I40IW; 3271 dev_ops->ops.size_ib_ah = IRDMA_SET_RDMA_OBJ_SIZE(ib_ah, irdma_ah, ibah); 3272 dev_ops->ops.size_ib_cq = IRDMA_SET_RDMA_OBJ_SIZE(ib_cq, irdma_cq, ibcq); 3273 dev_ops->ops.size_ib_pd = IRDMA_SET_RDMA_OBJ_SIZE(ib_pd, irdma_pd, ibpd); 3274 dev_ops->ops.size_ib_ucontext = IRDMA_SET_RDMA_OBJ_SIZE(ib_ucontext, 3275 irdma_ucontext, 3276 ibucontext); 3277 3278 dev_ops->alloc_hw_stats = irdma_alloc_hw_stats; 3279 dev_ops->alloc_mr = irdma_alloc_mr; 3280 dev_ops->alloc_pd = irdma_alloc_pd; 3281 dev_ops->alloc_ucontext = irdma_alloc_ucontext; 3282 dev_ops->create_cq = irdma_create_cq; 3283 dev_ops->create_qp = irdma_create_qp; 3284 dev_ops->dealloc_pd = irdma_dealloc_pd; 3285 dev_ops->dealloc_ucontext = irdma_dealloc_ucontext; 3286 dev_ops->dereg_mr = irdma_dereg_mr; 3287 dev_ops->destroy_cq = irdma_destroy_cq; 3288 dev_ops->destroy_qp = irdma_destroy_qp; 3289 dev_ops->disassociate_ucontext = irdma_disassociate_ucontext; 3290 dev_ops->get_dev_fw_str = irdma_get_dev_fw_str; 3291 dev_ops->get_dma_mr = irdma_get_dma_mr; 3292 dev_ops->get_hw_stats = irdma_get_hw_stats; 3293 dev_ops->get_netdev = irdma_get_netdev; 3294 dev_ops->map_mr_sg = irdma_map_mr_sg; 3295 dev_ops->mmap = irdma_mmap; 3296 dev_ops->mmap_free = irdma_mmap_free; 3297 dev_ops->poll_cq = irdma_poll_cq; 3298 dev_ops->post_recv = irdma_post_recv; 3299 dev_ops->post_send = irdma_post_send; 3300 dev_ops->query_device = irdma_query_device; 3301 dev_ops->query_port = irdma_query_port; 3302 dev_ops->modify_port = irdma_modify_port; 3303 dev_ops->query_qp = irdma_query_qp; 3304 dev_ops->reg_user_mr = irdma_reg_user_mr; 3305 dev_ops->rereg_user_mr = irdma_rereg_user_mr; 3306 dev_ops->req_notify_cq = irdma_req_notify_cq; 3307 dev_ops->resize_cq = irdma_resize_cq; 3308 } 3309 3310 static void 3311 irdma_set_device_mcast_ops(struct ib_device *ibdev) 3312 { 3313 struct ib_device *dev_ops = ibdev; 3314 3315 dev_ops->attach_mcast = irdma_attach_mcast; 3316 dev_ops->detach_mcast = irdma_detach_mcast; 3317 } 3318 3319 static void 3320 irdma_set_device_roce_ops(struct ib_device *ibdev) 3321 { 3322 struct ib_device *dev_ops = ibdev; 3323 3324 dev_ops->create_ah = irdma_create_ah; 3325 dev_ops->destroy_ah = irdma_destroy_ah; 3326 dev_ops->get_link_layer = irdma_get_link_layer; 3327 dev_ops->get_port_immutable = irdma_roce_port_immutable; 3328 dev_ops->modify_qp = irdma_modify_qp_roce; 3329 dev_ops->query_ah = irdma_query_ah; 3330 dev_ops->query_gid = irdma_query_gid_roce; 3331 dev_ops->query_pkey = irdma_query_pkey; 3332 ibdev->add_gid = irdma_add_gid; 3333 ibdev->del_gid = irdma_del_gid; 3334 } 3335 3336 static void 3337 irdma_set_device_iw_ops(struct ib_device *ibdev) 3338 { 3339 struct ib_device *dev_ops = ibdev; 3340 3341 ibdev->uverbs_cmd_mask |= 3342 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3343 (1ull << IB_USER_VERBS_CMD_DESTROY_AH); 3344 3345 dev_ops->create_ah = irdma_create_ah_stub; 3346 dev_ops->destroy_ah = irdma_destroy_ah_stub; 3347 dev_ops->get_port_immutable = irdma_iw_port_immutable; 3348 dev_ops->modify_qp = irdma_modify_qp; 3349 dev_ops->query_gid = irdma_query_gid; 3350 dev_ops->query_pkey = irdma_iw_query_pkey; 3351 } 3352 3353 static inline void 3354 irdma_set_device_gen1_ops(struct ib_device *ibdev) 3355 { 3356 } 3357 3358 /** 3359 * irdma_init_roce_device - initialization of roce rdma device 3360 * @iwdev: irdma device 3361 */ 3362 static void 3363 irdma_init_roce_device(struct irdma_device *iwdev) 3364 { 3365 kc_set_roce_uverbs_cmd_mask(iwdev); 3366 iwdev->ibdev.node_type = RDMA_NODE_IB_CA; 3367 addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid, 3368 if_getlladdr(iwdev->netdev)); 3369 irdma_set_device_roce_ops(&iwdev->ibdev); 3370 if (iwdev->rf->rdma_ver == IRDMA_GEN_2) 3371 irdma_set_device_mcast_ops(&iwdev->ibdev); 3372 } 3373 3374 /** 3375 * irdma_init_iw_device - initialization of iwarp rdma device 3376 * @iwdev: irdma device 3377 */ 3378 static int 3379 irdma_init_iw_device(struct irdma_device *iwdev) 3380 { 3381 if_t netdev = iwdev->netdev; 3382 3383 iwdev->ibdev.node_type = RDMA_NODE_RNIC; 3384 addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid, 3385 if_getlladdr(netdev)); 3386 iwdev->ibdev.iwcm = kzalloc(sizeof(*iwdev->ibdev.iwcm), GFP_KERNEL); 3387 if (!iwdev->ibdev.iwcm) 3388 return -ENOMEM; 3389 3390 iwdev->ibdev.iwcm->add_ref = irdma_qp_add_ref; 3391 iwdev->ibdev.iwcm->rem_ref = irdma_qp_rem_ref; 3392 iwdev->ibdev.iwcm->get_qp = irdma_get_qp; 3393 iwdev->ibdev.iwcm->connect = irdma_connect; 3394 iwdev->ibdev.iwcm->accept = irdma_accept; 3395 iwdev->ibdev.iwcm->reject = irdma_reject; 3396 iwdev->ibdev.iwcm->create_listen = irdma_create_listen; 3397 iwdev->ibdev.iwcm->destroy_listen = irdma_destroy_listen; 3398 memcpy(iwdev->ibdev.iwcm->ifname, if_name(netdev), 3399 sizeof(iwdev->ibdev.iwcm->ifname)); 3400 irdma_set_device_iw_ops(&iwdev->ibdev); 3401 3402 return 0; 3403 } 3404 3405 /** 3406 * irdma_init_rdma_device - initialization of rdma device 3407 * @iwdev: irdma device 3408 */ 3409 static int 3410 irdma_init_rdma_device(struct irdma_device *iwdev) 3411 { 3412 int ret; 3413 3414 iwdev->ibdev.owner = THIS_MODULE; 3415 iwdev->ibdev.uverbs_abi_ver = IRDMA_ABI_VER; 3416 kc_set_rdma_uverbs_cmd_mask(iwdev); 3417 3418 if (iwdev->roce_mode) { 3419 irdma_init_roce_device(iwdev); 3420 } else { 3421 ret = irdma_init_iw_device(iwdev); 3422 if (ret) 3423 return ret; 3424 } 3425 3426 iwdev->ibdev.phys_port_cnt = 1; 3427 iwdev->ibdev.num_comp_vectors = iwdev->rf->ceqs_count; 3428 iwdev->ibdev.dev.parent = iwdev->rf->dev_ctx.dev; 3429 set_ibdev_dma_device(iwdev->ibdev, &iwdev->rf->pcidev->dev); 3430 irdma_set_device_ops(&iwdev->ibdev); 3431 if (iwdev->rf->rdma_ver == IRDMA_GEN_1) 3432 irdma_set_device_gen1_ops(&iwdev->ibdev); 3433 3434 return 0; 3435 } 3436 3437 /** 3438 * irdma_port_ibevent - indicate port event 3439 * @iwdev: irdma device 3440 */ 3441 void 3442 irdma_port_ibevent(struct irdma_device *iwdev) 3443 { 3444 struct ib_event event; 3445 3446 event.device = &iwdev->ibdev; 3447 event.element.port_num = 1; 3448 event.event = 3449 iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3450 ib_dispatch_event(&event); 3451 } 3452 3453 /** 3454 * irdma_ib_unregister_device - unregister rdma device from IB 3455 * core 3456 * @iwdev: irdma device 3457 */ 3458 void 3459 irdma_ib_unregister_device(struct irdma_device *iwdev) 3460 { 3461 iwdev->iw_status = 0; 3462 irdma_port_ibevent(iwdev); 3463 ib_unregister_device(&iwdev->ibdev); 3464 dev_put(iwdev->netdev); 3465 kfree(iwdev->ibdev.iwcm); 3466 iwdev->ibdev.iwcm = NULL; 3467 } 3468 3469 /** 3470 * irdma_ib_register_device - register irdma device to IB core 3471 * @iwdev: irdma device 3472 */ 3473 int 3474 irdma_ib_register_device(struct irdma_device *iwdev) 3475 { 3476 int ret; 3477 3478 ret = irdma_init_rdma_device(iwdev); 3479 if (ret) 3480 return ret; 3481 3482 dev_hold(iwdev->netdev); 3483 sprintf(iwdev->ibdev.name, "irdma-%s", if_name(iwdev->netdev)); 3484 ret = ib_register_device(&iwdev->ibdev, NULL); 3485 if (ret) 3486 goto error; 3487 3488 iwdev->iw_status = 1; 3489 irdma_port_ibevent(iwdev); 3490 3491 return 0; 3492 3493 error: 3494 kfree(iwdev->ibdev.iwcm); 3495 iwdev->ibdev.iwcm = NULL; 3496 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_VERBS, "Register RDMA device fail\n"); 3497 3498 return ret; 3499 } 3500