1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2021 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #ifndef IRDMA_USER_H 37 #define IRDMA_USER_H 38 39 #define irdma_handle void * 40 #define irdma_adapter_handle irdma_handle 41 #define irdma_qp_handle irdma_handle 42 #define irdma_cq_handle irdma_handle 43 #define irdma_pd_id irdma_handle 44 #define irdma_stag_handle irdma_handle 45 #define irdma_stag_index u32 46 #define irdma_stag u32 47 #define irdma_stag_key u8 48 #define irdma_tagged_offset u64 49 #define irdma_access_privileges u32 50 #define irdma_physical_fragment u64 51 #define irdma_address_list u64 * 52 #define irdma_sgl struct irdma_sge * 53 54 #define IRDMA_MAX_MR_SIZE 0x200000000000ULL 55 56 #define IRDMA_ACCESS_FLAGS_LOCALREAD 0x01 57 #define IRDMA_ACCESS_FLAGS_LOCALWRITE 0x02 58 #define IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04 59 #define IRDMA_ACCESS_FLAGS_REMOTEREAD 0x05 60 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08 61 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE 0x0a 62 #define IRDMA_ACCESS_FLAGS_BIND_WINDOW 0x10 63 #define IRDMA_ACCESS_FLAGS_ZERO_BASED 0x20 64 #define IRDMA_ACCESS_FLAGS_ALL 0x3f 65 66 #define IRDMA_OP_TYPE_RDMA_WRITE 0x00 67 #define IRDMA_OP_TYPE_RDMA_READ 0x01 68 #define IRDMA_OP_TYPE_SEND 0x03 69 #define IRDMA_OP_TYPE_SEND_INV 0x04 70 #define IRDMA_OP_TYPE_SEND_SOL 0x05 71 #define IRDMA_OP_TYPE_SEND_SOL_INV 0x06 72 #define IRDMA_OP_TYPE_RDMA_WRITE_SOL 0x0d 73 #define IRDMA_OP_TYPE_BIND_MW 0x08 74 #define IRDMA_OP_TYPE_FAST_REG_NSMR 0x09 75 #define IRDMA_OP_TYPE_INV_STAG 0x0a 76 #define IRDMA_OP_TYPE_RDMA_READ_INV_STAG 0x0b 77 #define IRDMA_OP_TYPE_NOP 0x0c 78 #define IRDMA_OP_TYPE_REC 0x3e 79 #define IRDMA_OP_TYPE_REC_IMM 0x3f 80 81 #define IRDMA_FLUSH_MAJOR_ERR 1 82 83 enum irdma_device_caps_const { 84 IRDMA_WQE_SIZE = 4, 85 IRDMA_CQP_WQE_SIZE = 8, 86 IRDMA_CQE_SIZE = 4, 87 IRDMA_EXTENDED_CQE_SIZE = 8, 88 IRDMA_AEQE_SIZE = 2, 89 IRDMA_CEQE_SIZE = 1, 90 IRDMA_CQP_CTX_SIZE = 8, 91 IRDMA_SHADOW_AREA_SIZE = 8, 92 IRDMA_GATHER_STATS_BUF_SIZE = 1024, 93 IRDMA_MIN_IW_QP_ID = 0, 94 IRDMA_QUERY_FPM_BUF_SIZE = 176, 95 IRDMA_COMMIT_FPM_BUF_SIZE = 176, 96 IRDMA_MAX_IW_QP_ID = 262143, 97 IRDMA_MIN_CEQID = 0, 98 IRDMA_MAX_CEQID = 1023, 99 IRDMA_CEQ_MAX_COUNT = IRDMA_MAX_CEQID + 1, 100 IRDMA_MIN_CQID = 0, 101 IRDMA_MAX_CQID = 524287, 102 IRDMA_MIN_AEQ_ENTRIES = 1, 103 IRDMA_MAX_AEQ_ENTRIES = 524287, 104 IRDMA_MIN_CEQ_ENTRIES = 1, 105 IRDMA_MAX_CEQ_ENTRIES = 262143, 106 IRDMA_MIN_CQ_SIZE = 1, 107 IRDMA_MAX_CQ_SIZE = 1048575, 108 IRDMA_DB_ID_ZERO = 0, 109 /* 64K + 1 */ 110 IRDMA_MAX_OUTBOUND_MSG_SIZE = 65537, 111 /* 64K +1 */ 112 IRDMA_MAX_INBOUND_MSG_SIZE = 65537, 113 IRDMA_MAX_PUSH_PAGE_COUNT = 1024, 114 IRDMA_MAX_PE_ENA_VF_COUNT = 32, 115 IRDMA_MAX_VF_FPM_ID = 47, 116 IRDMA_MAX_SQ_PAYLOAD_SIZE = 2145386496, 117 IRDMA_MAX_INLINE_DATA_SIZE = 101, 118 IRDMA_MAX_WQ_ENTRIES = 32768, 119 IRDMA_Q2_BUF_SIZE = 256, 120 IRDMA_QP_CTX_SIZE = 256, 121 IRDMA_MAX_PDS = 262144, 122 }; 123 124 enum irdma_addressing_type { 125 IRDMA_ADDR_TYPE_ZERO_BASED = 0, 126 IRDMA_ADDR_TYPE_VA_BASED = 1, 127 }; 128 129 enum irdma_flush_opcode { 130 FLUSH_INVALID = 0, 131 FLUSH_GENERAL_ERR, 132 FLUSH_PROT_ERR, 133 FLUSH_REM_ACCESS_ERR, 134 FLUSH_LOC_QP_OP_ERR, 135 FLUSH_REM_OP_ERR, 136 FLUSH_LOC_LEN_ERR, 137 FLUSH_FATAL_ERR, 138 FLUSH_MW_BIND_ERR, 139 FLUSH_REM_INV_REQ_ERR, 140 FLUSH_RETRY_EXC_ERR, 141 }; 142 143 enum irdma_cmpl_status { 144 IRDMA_COMPL_STATUS_SUCCESS = 0, 145 IRDMA_COMPL_STATUS_FLUSHED, 146 IRDMA_COMPL_STATUS_INVALID_WQE, 147 IRDMA_COMPL_STATUS_QP_CATASTROPHIC, 148 IRDMA_COMPL_STATUS_REMOTE_TERMINATION, 149 IRDMA_COMPL_STATUS_INVALID_STAG, 150 IRDMA_COMPL_STATUS_BASE_BOUND_VIOLATION, 151 IRDMA_COMPL_STATUS_ACCESS_VIOLATION, 152 IRDMA_COMPL_STATUS_INVALID_PD_ID, 153 IRDMA_COMPL_STATUS_WRAP_ERROR, 154 IRDMA_COMPL_STATUS_STAG_INVALID_PDID, 155 IRDMA_COMPL_STATUS_RDMA_READ_ZERO_ORD, 156 IRDMA_COMPL_STATUS_QP_NOT_PRIVLEDGED, 157 IRDMA_COMPL_STATUS_STAG_NOT_INVALID, 158 IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_SIZE, 159 IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_ENTRY, 160 IRDMA_COMPL_STATUS_INVALID_FBO, 161 IRDMA_COMPL_STATUS_INVALID_LEN, 162 IRDMA_COMPL_STATUS_INVALID_ACCESS, 163 IRDMA_COMPL_STATUS_PHYS_BUF_LIST_TOO_LONG, 164 IRDMA_COMPL_STATUS_INVALID_VIRT_ADDRESS, 165 IRDMA_COMPL_STATUS_INVALID_REGION, 166 IRDMA_COMPL_STATUS_INVALID_WINDOW, 167 IRDMA_COMPL_STATUS_INVALID_TOTAL_LEN, 168 IRDMA_COMPL_STATUS_UNKNOWN, 169 }; 170 171 enum irdma_cmpl_notify { 172 IRDMA_CQ_COMPL_EVENT = 0, 173 IRDMA_CQ_COMPL_SOLICITED = 1, 174 }; 175 176 enum irdma_qp_caps { 177 IRDMA_WRITE_WITH_IMM = 1, 178 IRDMA_SEND_WITH_IMM = 2, 179 IRDMA_ROCE = 4, 180 IRDMA_PUSH_MODE = 8, 181 }; 182 183 struct irdma_qp_uk; 184 struct irdma_cq_uk; 185 struct irdma_qp_uk_init_info; 186 struct irdma_cq_uk_init_info; 187 188 struct irdma_sge { 189 irdma_tagged_offset tag_off; 190 u32 len; 191 irdma_stag stag; 192 }; 193 194 struct irdma_ring { 195 volatile u32 head; 196 volatile u32 tail; 197 u32 size; 198 }; 199 200 struct irdma_cqe { 201 __le64 buf[IRDMA_CQE_SIZE]; 202 }; 203 204 struct irdma_extended_cqe { 205 __le64 buf[IRDMA_EXTENDED_CQE_SIZE]; 206 }; 207 208 struct irdma_post_send { 209 irdma_sgl sg_list; 210 u32 num_sges; 211 u32 qkey; 212 u32 dest_qp; 213 u32 ah_id; 214 }; 215 216 struct irdma_post_inline_send { 217 void *data; 218 u32 len; 219 u32 qkey; 220 u32 dest_qp; 221 u32 ah_id; 222 }; 223 224 struct irdma_post_rq_info { 225 u64 wr_id; 226 irdma_sgl sg_list; 227 u32 num_sges; 228 }; 229 230 struct irdma_rdma_write { 231 irdma_sgl lo_sg_list; 232 u32 num_lo_sges; 233 struct irdma_sge rem_addr; 234 }; 235 236 struct irdma_inline_rdma_write { 237 void *data; 238 u32 len; 239 struct irdma_sge rem_addr; 240 }; 241 242 struct irdma_rdma_read { 243 irdma_sgl lo_sg_list; 244 u32 num_lo_sges; 245 struct irdma_sge rem_addr; 246 }; 247 248 struct irdma_bind_window { 249 irdma_stag mr_stag; 250 u64 bind_len; 251 void *va; 252 enum irdma_addressing_type addressing_type; 253 bool ena_reads:1; 254 bool ena_writes:1; 255 irdma_stag mw_stag; 256 bool mem_window_type_1:1; 257 }; 258 259 struct irdma_inv_local_stag { 260 irdma_stag target_stag; 261 }; 262 263 struct irdma_post_sq_info { 264 u64 wr_id; 265 u8 op_type; 266 u8 l4len; 267 bool signaled:1; 268 bool read_fence:1; 269 bool local_fence:1; 270 bool inline_data:1; 271 bool imm_data_valid:1; 272 bool push_wqe:1; 273 bool report_rtt:1; 274 bool udp_hdr:1; 275 bool defer_flag:1; 276 u32 imm_data; 277 u32 stag_to_inv; 278 union { 279 struct irdma_post_send send; 280 struct irdma_rdma_write rdma_write; 281 struct irdma_rdma_read rdma_read; 282 struct irdma_bind_window bind_window; 283 struct irdma_inv_local_stag inv_local_stag; 284 struct irdma_inline_rdma_write inline_rdma_write; 285 struct irdma_post_inline_send inline_send; 286 } op; 287 }; 288 289 struct irdma_cq_poll_info { 290 u64 wr_id; 291 irdma_qp_handle qp_handle; 292 u32 bytes_xfered; 293 u32 tcp_seq_num_rtt; 294 u32 qp_id; 295 u32 ud_src_qpn; 296 u32 imm_data; 297 irdma_stag inv_stag; /* or L_R_Key */ 298 enum irdma_cmpl_status comp_status; 299 u16 major_err; 300 u16 minor_err; 301 u16 ud_vlan; 302 u8 ud_smac[6]; 303 u8 op_type; 304 bool stag_invalid_set:1; /* or L_R_Key set */ 305 bool push_dropped:1; 306 bool error:1; 307 bool solicited_event:1; 308 bool ipv4:1; 309 bool ud_vlan_valid:1; 310 bool ud_smac_valid:1; 311 bool imm_valid:1; 312 bool signaled:1; 313 }; 314 315 int irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, 316 struct irdma_post_sq_info *info, bool post_sq); 317 int irdma_uk_inline_send(struct irdma_qp_uk *qp, 318 struct irdma_post_sq_info *info, bool post_sq); 319 int irdma_uk_mw_bind(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 320 bool post_sq); 321 int irdma_uk_post_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, 322 bool post_sq); 323 int irdma_uk_post_receive(struct irdma_qp_uk *qp, 324 struct irdma_post_rq_info *info); 325 void irdma_uk_qp_post_wr(struct irdma_qp_uk *qp); 326 int irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 327 bool inv_stag, bool post_sq); 328 int irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 329 bool post_sq); 330 int irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 331 bool post_sq); 332 int irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp, 333 struct irdma_post_sq_info *info, 334 bool post_sq); 335 336 struct irdma_wqe_uk_ops { 337 void (*iw_copy_inline_data)(u8 *dest, u8 *src, u32 len, u8 polarity); 338 u16 (*iw_inline_data_size_to_quanta)(u32 data_size); 339 void (*iw_set_fragment)(__le64 *wqe, u32 offset, struct irdma_sge *sge, 340 u8 valid); 341 void (*iw_set_mw_bind_wqe)(__le64 *wqe, 342 struct irdma_bind_window *op_info); 343 }; 344 345 int irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq, 346 struct irdma_cq_poll_info *info); 347 void irdma_uk_cq_request_notification(struct irdma_cq_uk *cq, 348 enum irdma_cmpl_notify cq_notify); 349 void irdma_uk_cq_resize(struct irdma_cq_uk *cq, void *cq_base, int size); 350 void irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *qp, u16 cnt); 351 int irdma_uk_cq_init(struct irdma_cq_uk *cq, 352 struct irdma_cq_uk_init_info *info); 353 int irdma_uk_qp_init(struct irdma_qp_uk *qp, 354 struct irdma_qp_uk_init_info *info); 355 struct irdma_sq_uk_wr_trk_info { 356 u64 wrid; 357 u32 wr_len; 358 u16 quanta; 359 u8 signaled; 360 u8 reserved[1]; 361 }; 362 363 struct irdma_qp_quanta { 364 __le64 elem[IRDMA_WQE_SIZE]; 365 }; 366 367 struct irdma_qp_uk { 368 struct irdma_qp_quanta *sq_base; 369 struct irdma_qp_quanta *rq_base; 370 struct irdma_uk_attrs *uk_attrs; 371 u32 IOMEM *wqe_alloc_db; 372 struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; 373 struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; 374 u64 *rq_wrid_array; 375 __le64 *shadow_area; 376 __le32 *push_db; 377 __le64 *push_wqe; 378 struct irdma_ring sq_ring; 379 struct irdma_ring sq_sig_ring; 380 struct irdma_ring rq_ring; 381 struct irdma_ring initial_ring; 382 u32 qp_id; 383 u32 qp_caps; 384 u32 sq_size; 385 u32 rq_size; 386 u32 max_sq_frag_cnt; 387 u32 max_rq_frag_cnt; 388 u32 max_inline_data; 389 u32 last_rx_cmpl_idx; 390 u32 last_tx_cmpl_idx; 391 struct irdma_wqe_uk_ops wqe_ops; 392 u16 conn_wqes; 393 u8 qp_type; 394 u8 swqe_polarity; 395 u8 swqe_polarity_deferred; 396 u8 rwqe_polarity; 397 u8 rq_wqe_size; 398 u8 rq_wqe_size_multiplier; 399 bool deferred_flag:1; 400 bool push_mode:1; /* whether the last post wqe was pushed */ 401 bool push_dropped:1; 402 bool first_sq_wq:1; 403 bool sq_flush_complete:1; /* Indicates flush was seen and SQ was empty after the flush */ 404 bool rq_flush_complete:1; /* Indicates flush was seen and RQ was empty after the flush */ 405 bool destroy_pending:1; /* Indicates the QP is being destroyed */ 406 void *back_qp; 407 spinlock_t *lock; 408 bool force_fence; 409 u8 dbg_rq_flushed; 410 u16 ord_cnt; 411 u8 sq_flush_seen; 412 u8 rq_flush_seen; 413 u8 rd_fence_rate; 414 }; 415 416 struct irdma_cq_uk { 417 struct irdma_cqe *cq_base; 418 u32 IOMEM *cqe_alloc_db; 419 u32 IOMEM *cq_ack_db; 420 __le64 *shadow_area; 421 u32 cq_id; 422 u32 cq_size; 423 struct irdma_ring cq_ring; 424 u8 polarity; 425 bool armed:1; 426 bool avoid_mem_cflct:1; 427 }; 428 429 struct irdma_qp_uk_init_info { 430 struct irdma_qp_quanta *sq; 431 struct irdma_qp_quanta *rq; 432 struct irdma_uk_attrs *uk_attrs; 433 u32 IOMEM *wqe_alloc_db; 434 __le64 *shadow_area; 435 struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; 436 struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; 437 u64 *rq_wrid_array; 438 u32 qp_id; 439 u32 qp_caps; 440 u32 sq_size; 441 u32 rq_size; 442 u32 max_sq_frag_cnt; 443 u32 max_rq_frag_cnt; 444 u32 max_inline_data; 445 u8 first_sq_wq; 446 u8 type; 447 u8 rd_fence_rate; 448 int abi_ver; 449 bool legacy_mode; 450 }; 451 452 struct irdma_cq_uk_init_info { 453 u32 IOMEM *cqe_alloc_db; 454 u32 IOMEM *cq_ack_db; 455 struct irdma_cqe *cq_base; 456 __le64 *shadow_area; 457 u32 cq_size; 458 u32 cq_id; 459 bool avoid_mem_cflct; 460 }; 461 462 __le64 *irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx, 463 u16 quanta, u32 total_size, 464 struct irdma_post_sq_info *info); 465 __le64 *irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx); 466 int irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq); 467 int irdma_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, bool post_sq); 468 int irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta); 469 int irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size); 470 void irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge, 471 u32 inline_data, u8 *shift); 472 int irdma_get_sqdepth(u32 max_hw_wq_quanta, u32 sq_size, u8 shift, u32 *wqdepth); 473 int irdma_get_rqdepth(u32 max_hw_rq_quanta, u32 rq_size, u8 shift, u32 *wqdepth); 474 void irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 *wqe, u16 quanta, 475 u32 wqe_idx, bool post_sq); 476 void irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx); 477 #endif /* IRDMA_USER_H */ 478