1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2026 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include "osdep.h" 36 #include "irdma_defs.h" 37 #include "irdma_user.h" 38 #include "irdma.h" 39 40 /** 41 * irdma_set_fragment - set fragment in wqe 42 * @wqe: wqe for setting fragment 43 * @offset: offset value 44 * @sge: sge length and stag 45 * @valid: The wqe valid 46 */ 47 static void 48 irdma_set_fragment(__le64 * wqe, u32 offset, struct ib_sge *sge, 49 u8 valid) 50 { 51 if (sge) { 52 set_64bit_val(wqe, offset, 53 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); 54 set_64bit_val(wqe, offset + IRDMA_BYTE_8, 55 FIELD_PREP(IRDMAQPSQ_VALID, valid) | 56 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->length) | 57 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->lkey)); 58 } else { 59 set_64bit_val(wqe, offset, 0); 60 set_64bit_val(wqe, offset + IRDMA_BYTE_8, 61 FIELD_PREP(IRDMAQPSQ_VALID, valid)); 62 } 63 } 64 65 /** 66 * irdma_set_fragment_gen_1 - set fragment in wqe 67 * @wqe: wqe for setting fragment 68 * @offset: offset value 69 * @sge: sge length and stag 70 * @valid: wqe valid flag 71 */ 72 static void 73 irdma_set_fragment_gen_1(__le64 * wqe, u32 offset, 74 struct ib_sge *sge, u8 valid) 75 { 76 if (sge) { 77 set_64bit_val(wqe, offset, 78 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); 79 set_64bit_val(wqe, offset + IRDMA_BYTE_8, 80 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, sge->length) | 81 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, sge->lkey)); 82 } else { 83 set_64bit_val(wqe, offset, 0); 84 set_64bit_val(wqe, offset + IRDMA_BYTE_8, 0); 85 } 86 } 87 88 /** 89 * irdma_nop_hdr - Format header section of noop WQE 90 * @qp: hw qp ptr 91 */ 92 static inline u64 irdma_nop_hdr(struct irdma_qp_uk *qp){ 93 return FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | 94 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, false) | 95 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 96 } 97 98 /** 99 * irdma_nop_1 - insert a NOP wqe 100 * @qp: hw qp ptr 101 */ 102 static int 103 irdma_nop_1(struct irdma_qp_uk *qp) 104 { 105 __le64 *wqe; 106 u32 wqe_idx; 107 108 if (!qp->sq_ring.head) 109 return -EINVAL; 110 111 wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 112 wqe = qp->sq_base[wqe_idx].elem; 113 114 qp->sq_wrtrk_array[wqe_idx].quanta = IRDMA_QP_WQE_MIN_QUANTA; 115 116 set_64bit_val(wqe, IRDMA_BYTE_0, 0); 117 set_64bit_val(wqe, IRDMA_BYTE_8, 0); 118 set_64bit_val(wqe, IRDMA_BYTE_16, 0); 119 120 /* make sure WQE is written before valid bit is set */ 121 irdma_wmb(); 122 123 set_64bit_val(wqe, IRDMA_BYTE_24, irdma_nop_hdr(qp)); 124 125 return 0; 126 } 127 128 /** 129 * irdma_clr_wqes - clear next 128 sq entries 130 * @qp: hw qp ptr 131 * @qp_wqe_idx: wqe_idx 132 */ 133 void 134 irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx) 135 { 136 struct irdma_qp_quanta *sq; 137 u32 wqe_idx; 138 139 if (!(qp_wqe_idx & 0x7F)) { 140 wqe_idx = (qp_wqe_idx + 128) % qp->sq_ring.size; 141 sq = qp->sq_base + wqe_idx; 142 if (wqe_idx) 143 memset(sq, qp->swqe_polarity ? 0 : 0xFF, 144 128 * sizeof(*sq)); 145 else 146 memset(sq, qp->swqe_polarity ? 0xFF : 0, 147 128 * sizeof(*sq)); 148 } 149 } 150 151 /** 152 * irdma_uk_qp_post_wr - ring doorbell 153 * @qp: hw qp ptr 154 */ 155 void 156 irdma_uk_qp_post_wr(struct irdma_qp_uk *qp) 157 { 158 u64 temp; 159 u32 hw_sq_tail; 160 u32 sw_sq_head; 161 162 /* valid bit is written and loads completed before reading shadow */ 163 irdma_mb(); 164 165 /* read the doorbell shadow area */ 166 get_64bit_val(qp->shadow_area, IRDMA_BYTE_0, &temp); 167 168 hw_sq_tail = (u32)FIELD_GET(IRDMA_QP_DBSA_HW_SQ_TAIL, temp); 169 sw_sq_head = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 170 if (sw_sq_head != qp->initial_ring.head) { 171 if (qp->push_dropped) { 172 db_wr32(qp->qp_id, qp->wqe_alloc_db); 173 qp->push_dropped = false; 174 } else if (sw_sq_head != hw_sq_tail) { 175 if (sw_sq_head > qp->initial_ring.head) { 176 if (hw_sq_tail >= qp->initial_ring.head && 177 hw_sq_tail < sw_sq_head) 178 db_wr32(qp->qp_id, qp->wqe_alloc_db); 179 } else { 180 if (hw_sq_tail >= qp->initial_ring.head || 181 hw_sq_tail < sw_sq_head) 182 db_wr32(qp->qp_id, qp->wqe_alloc_db); 183 } 184 } 185 } 186 187 qp->initial_ring.head = qp->sq_ring.head; 188 } 189 190 /** 191 * irdma_qp_ring_push_db - ring qp doorbell 192 * @qp: hw qp ptr 193 * @wqe_idx: wqe index 194 */ 195 static void 196 irdma_qp_ring_push_db(struct irdma_qp_uk *qp, u32 wqe_idx) 197 { 198 set_32bit_val(qp->push_db, 0, 199 FIELD_PREP(IRDMA_WQEALLOC_WQE_DESC_INDEX, wqe_idx >> 3) | qp->qp_id); 200 qp->initial_ring.head = qp->sq_ring.head; 201 qp->push_mode = true; 202 qp->push_dropped = false; 203 } 204 205 /** 206 * irdma_qp_push_wqe - setup push wqe and ring db 207 * @qp: hw qp ptr 208 * @wqe: wqe ptr 209 * @quanta: numbers of quanta in wqe 210 * @wqe_idx: wqe index 211 * @push_wqe: if to use push for the wqe 212 */ 213 void 214 irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 * wqe, u16 quanta, 215 u32 wqe_idx, bool push_wqe) 216 { 217 __le64 *push; 218 219 if (push_wqe) { 220 push = (__le64 *) ((uintptr_t)qp->push_wqe + 221 (wqe_idx & 0x7) * 0x20); 222 irdma_memcpy(push, wqe, quanta * IRDMA_QP_WQE_MIN_SIZE); 223 irdma_qp_ring_push_db(qp, wqe_idx); 224 qp->last_push_db = true; 225 } else if (qp->last_push_db) { 226 qp->last_push_db = false; 227 db_wr32(qp->qp_id, qp->wqe_alloc_db); 228 } else { 229 irdma_uk_qp_post_wr(qp); 230 } 231 } 232 233 /** 234 * irdma_push_ring_free - check if sq ring free to pust push wqe 235 * @qp: hw qp ptr 236 */ 237 static inline bool 238 irdma_push_ring_free(struct irdma_qp_uk *qp) 239 { 240 u32 head, tail; 241 242 head = IRDMA_RING_CURRENT_HEAD(qp->initial_ring); 243 tail = IRDMA_RING_CURRENT_TAIL(qp->sq_ring); 244 245 if (head == tail || head == (tail + 1)) 246 return true; 247 248 return false; 249 } 250 251 /** 252 * irdma_enable_push_wqe - depending on sq ring and total size 253 * @qp: hw qp ptr 254 * @total_size: total data size 255 */ 256 static inline bool 257 irdma_enable_push_wqe(struct irdma_qp_uk *qp, u32 total_size) 258 { 259 if (irdma_push_ring_free(qp) && 260 total_size <= qp->uk_attrs->max_hw_push_len) { 261 return true; 262 } 263 return false; 264 } 265 266 /** 267 * irdma_qp_get_next_send_wqe - pad with NOP if needed, return where next WR should go 268 * @qp: hw qp ptr 269 * @wqe_idx: return wqe index 270 * @quanta: (in/out) ptr to size of WR in quanta. Modified in case pad is needed 271 * @total_size: size of WR in bytes 272 * @info: info on WR 273 */ 274 __le64 * 275 irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx, 276 u16 *quanta, u32 total_size, 277 struct irdma_post_sq_info *info) 278 { 279 __le64 *wqe; 280 __le64 *wqe_0 = NULL; 281 u32 nop_wqe_idx; 282 u16 wqe_quanta = *quanta; 283 u16 avail_quanta; 284 u16 i; 285 286 avail_quanta = qp->uk_attrs->max_hw_sq_chunk - 287 (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) % 288 qp->uk_attrs->max_hw_sq_chunk); 289 290 if (*quanta <= avail_quanta) { 291 /* WR fits in current chunk */ 292 if (*quanta > IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring)) 293 return NULL; 294 } else { 295 /* Need to pad with NOP */ 296 if (*quanta + avail_quanta > 297 IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring)) 298 return NULL; 299 300 nop_wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 301 for (i = 0; i < avail_quanta; i++) { 302 irdma_nop_1(qp); 303 IRDMA_RING_MOVE_HEAD_NOCHECK(qp->sq_ring); 304 } 305 if (qp->push_db && info->push_wqe) 306 irdma_qp_push_wqe(qp, qp->sq_base[nop_wqe_idx].elem, 307 avail_quanta, nop_wqe_idx, true); 308 } 309 310 *wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 311 if (!*wqe_idx) 312 qp->swqe_polarity = !qp->swqe_polarity; 313 314 IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, *quanta); 315 316 irdma_clr_wqes(qp, *wqe_idx); 317 318 wqe = qp->sq_base[*wqe_idx].elem; 319 if (qp->uk_attrs->hw_rev == IRDMA_GEN_1 && wqe_quanta == 1 && 320 (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) & 1)) { 321 wqe_0 = qp->sq_base[IRDMA_RING_CURRENT_HEAD(qp->sq_ring)].elem; 322 wqe_0[3] = cpu_to_le64(FIELD_PREP(IRDMAQPSQ_VALID, 323 qp->swqe_polarity ? 0 : 1)); 324 } 325 qp->sq_wrtrk_array[*wqe_idx].wrid = info->wr_id; 326 qp->sq_wrtrk_array[*wqe_idx].wr_len = total_size; 327 qp->sq_wrtrk_array[*wqe_idx].quanta = wqe_quanta; 328 qp->sq_wrtrk_array[*wqe_idx].signaled = info->signaled; 329 330 return wqe; 331 } 332 333 /** 334 * irdma_qp_get_next_recv_wqe - get next qp's rcv wqe 335 * @qp: hw qp ptr 336 * @wqe_idx: return wqe index 337 */ 338 __le64 * 339 irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx) 340 { 341 __le64 *wqe; 342 int ret_code; 343 344 if (IRDMA_RING_FULL_ERR(qp->rq_ring)) 345 return NULL; 346 347 IRDMA_ATOMIC_RING_MOVE_HEAD(qp->rq_ring, *wqe_idx, ret_code); 348 if (ret_code) 349 return NULL; 350 351 if (!*wqe_idx) 352 qp->rwqe_polarity = !qp->rwqe_polarity; 353 /* rq_wqe_size_multiplier is no of 32 byte quanta in one rq wqe */ 354 wqe = qp->rq_base[*wqe_idx * qp->rq_wqe_size_multiplier].elem; 355 356 return wqe; 357 } 358 359 /** 360 * irdma_uk_rdma_write - rdma write operation 361 * @qp: hw qp ptr 362 * @info: post sq information 363 * @post_sq: flag to post sq 364 */ 365 int 366 irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 367 bool post_sq) 368 { 369 u64 hdr; 370 __le64 *wqe; 371 struct irdma_rdma_write *op_info; 372 u32 i, wqe_idx; 373 u32 total_size = 0, byte_off; 374 int ret_code; 375 u32 frag_cnt, addl_frag_cnt; 376 bool read_fence = false; 377 u16 quanta; 378 379 info->push_wqe = false; 380 381 op_info = &info->op.rdma_write; 382 if (op_info->num_lo_sges > qp->max_sq_frag_cnt) 383 return -EINVAL; 384 385 for (i = 0; i < op_info->num_lo_sges; i++) 386 total_size += op_info->lo_sg_list[i].length; 387 388 read_fence |= info->read_fence; 389 390 if (info->imm_data_valid) 391 frag_cnt = op_info->num_lo_sges + 1; 392 else 393 frag_cnt = op_info->num_lo_sges; 394 addl_frag_cnt = frag_cnt > 1 ? (frag_cnt - 1) : 0; 395 ret_code = irdma_fragcnt_to_quanta_sq(frag_cnt, &quanta); 396 if (ret_code) 397 return ret_code; 398 399 if (qp->push_db) 400 info->push_wqe = irdma_enable_push_wqe(qp, total_size); 401 402 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 403 if (!wqe) 404 return -ENOSPC; 405 406 set_64bit_val(wqe, IRDMA_BYTE_16, 407 FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.addr)); 408 409 if (info->imm_data_valid) { 410 set_64bit_val(wqe, IRDMA_BYTE_0, 411 FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); 412 i = 0; 413 } else { 414 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, 415 op_info->lo_sg_list, 416 qp->swqe_polarity); 417 i = 1; 418 } 419 420 for (byte_off = IRDMA_BYTE_32; i < op_info->num_lo_sges; i++) { 421 qp->wqe_ops.iw_set_fragment(wqe, byte_off, 422 &op_info->lo_sg_list[i], 423 qp->swqe_polarity); 424 byte_off += 16; 425 } 426 427 /* if not an odd number set valid bit in next fragment */ 428 if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(frag_cnt & 0x01) && 429 frag_cnt) { 430 qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, 431 qp->swqe_polarity); 432 if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) 433 ++addl_frag_cnt; 434 } 435 436 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.lkey) | 437 FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | 438 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, info->imm_data_valid) | 439 FIELD_PREP(IRDMAQPSQ_REPORTRTT, info->report_rtt) | 440 FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | 441 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 442 FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | 443 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 444 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 445 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 446 447 irdma_wmb(); /* make sure WQE is populated before valid bit is set */ 448 449 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 450 if (qp->push_db) 451 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, info->push_wqe); 452 else if (post_sq) 453 irdma_uk_qp_post_wr(qp); 454 455 return 0; 456 } 457 458 /** 459 * irdma_uk_rdma_read - rdma read command 460 * @qp: hw qp ptr 461 * @info: post sq information 462 * @inv_stag: flag for inv_stag 463 * @post_sq: flag to post sq 464 */ 465 int 466 irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 467 bool inv_stag, bool post_sq) 468 { 469 struct irdma_rdma_read *op_info; 470 int ret_code; 471 u32 i, byte_off, total_size = 0; 472 bool local_fence = false; 473 bool ord_fence = false; 474 u32 addl_frag_cnt; 475 __le64 *wqe; 476 u32 wqe_idx; 477 u16 quanta; 478 u64 hdr; 479 480 info->push_wqe &= qp->push_db ? true : false; 481 482 op_info = &info->op.rdma_read; 483 if (qp->max_sq_frag_cnt < op_info->num_lo_sges) 484 return -EINVAL; 485 486 for (i = 0; i < op_info->num_lo_sges; i++) 487 total_size += op_info->lo_sg_list[i].length; 488 489 ret_code = irdma_fragcnt_to_quanta_sq(op_info->num_lo_sges, &quanta); 490 if (ret_code) 491 return ret_code; 492 493 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 494 if (!wqe) 495 return -ENOSPC; 496 497 if (qp->rd_fence_rate && (qp->ord_cnt++ == qp->rd_fence_rate)) { 498 ord_fence = true; 499 qp->ord_cnt = 0; 500 } 501 502 addl_frag_cnt = op_info->num_lo_sges > 1 ? 503 (op_info->num_lo_sges - 1) : 0; 504 local_fence |= info->local_fence; 505 506 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, op_info->lo_sg_list, 507 qp->swqe_polarity); 508 for (i = 1, byte_off = IRDMA_BYTE_32; i < op_info->num_lo_sges; ++i) { 509 qp->wqe_ops.iw_set_fragment(wqe, byte_off, 510 &op_info->lo_sg_list[i], 511 qp->swqe_polarity); 512 byte_off += IRDMA_BYTE_16; 513 } 514 515 /* if not an odd number set valid bit in next fragment */ 516 if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && 517 !(op_info->num_lo_sges & 0x01) && op_info->num_lo_sges) { 518 qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, 519 qp->swqe_polarity); 520 if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) 521 ++addl_frag_cnt; 522 } 523 set_64bit_val(wqe, IRDMA_BYTE_16, 524 FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.addr)); 525 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.lkey) | 526 FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | 527 FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | 528 FIELD_PREP(IRDMAQPSQ_OPCODE, 529 (inv_stag ? IRDMAQP_OP_RDMA_READ_LOC_INV : IRDMAQP_OP_RDMA_READ)) | 530 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 531 FIELD_PREP(IRDMAQPSQ_READFENCE, 532 info->read_fence || ord_fence ? 1 : 0) | 533 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, local_fence) | 534 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 535 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 536 537 irdma_wmb(); /* make sure WQE is populated before valid bit is set */ 538 539 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 540 if (qp->push_db) 541 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, info->push_wqe); 542 else if (post_sq) 543 irdma_uk_qp_post_wr(qp); 544 545 return 0; 546 } 547 548 /** 549 * irdma_uk_send - rdma send command 550 * @qp: hw qp ptr 551 * @info: post sq information 552 * @post_sq: flag to post sq 553 */ 554 int 555 irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, 556 bool post_sq) 557 { 558 __le64 *wqe; 559 struct irdma_post_send *op_info; 560 u64 hdr; 561 u32 i, wqe_idx, total_size = 0, byte_off; 562 int ret_code; 563 u32 frag_cnt, addl_frag_cnt; 564 bool read_fence = false; 565 u16 quanta; 566 567 info->push_wqe = false; 568 569 op_info = &info->op.send; 570 if (qp->max_sq_frag_cnt < op_info->num_sges) 571 return -EINVAL; 572 573 for (i = 0; i < op_info->num_sges; i++) 574 total_size += op_info->sg_list[i].length; 575 576 if (info->imm_data_valid) 577 frag_cnt = op_info->num_sges + 1; 578 else 579 frag_cnt = op_info->num_sges; 580 ret_code = irdma_fragcnt_to_quanta_sq(frag_cnt, &quanta); 581 if (ret_code) 582 return ret_code; 583 584 if (qp->push_db) 585 info->push_wqe = irdma_enable_push_wqe(qp, total_size); 586 587 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 588 if (!wqe) 589 return -ENOSPC; 590 591 read_fence |= info->read_fence; 592 addl_frag_cnt = frag_cnt > 1 ? (frag_cnt - 1) : 0; 593 if (info->imm_data_valid) { 594 set_64bit_val(wqe, IRDMA_BYTE_0, 595 FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); 596 i = 0; 597 } else { 598 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, 599 frag_cnt ? op_info->sg_list : NULL, 600 qp->swqe_polarity); 601 i = 1; 602 } 603 604 for (byte_off = IRDMA_BYTE_32; i < op_info->num_sges; i++) { 605 qp->wqe_ops.iw_set_fragment(wqe, byte_off, &op_info->sg_list[i], 606 qp->swqe_polarity); 607 byte_off += IRDMA_BYTE_16; 608 } 609 610 /* if not an odd number set valid bit in next fragment */ 611 if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(frag_cnt & 0x01) && 612 frag_cnt) { 613 qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, 614 qp->swqe_polarity); 615 if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) 616 ++addl_frag_cnt; 617 } 618 619 set_64bit_val(wqe, IRDMA_BYTE_16, 620 FIELD_PREP(IRDMAQPSQ_DESTQKEY, op_info->qkey) | 621 FIELD_PREP(IRDMAQPSQ_DESTQPN, op_info->dest_qp)); 622 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, info->stag_to_inv) | 623 FIELD_PREP(IRDMAQPSQ_AHID, op_info->ah_id) | 624 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, 625 (info->imm_data_valid ? 1 : 0)) | 626 FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | 627 FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | 628 FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | 629 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 630 FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | 631 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 632 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 633 FIELD_PREP(IRDMAQPSQ_UDPHEADER, info->udp_hdr) | 634 FIELD_PREP(IRDMAQPSQ_L4LEN, info->l4len) | 635 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 636 637 irdma_wmb(); /* make sure WQE is populated before valid bit is set */ 638 639 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 640 if (qp->push_db) 641 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, info->push_wqe); 642 else if (post_sq) 643 irdma_uk_qp_post_wr(qp); 644 645 return 0; 646 } 647 648 /** 649 * irdma_copy_inline_data_gen_1 - Copy inline data to wqe 650 * @wqe: pointer to wqe 651 * @sge_list: table of pointers to inline data 652 * @num_sges: Total inline data length 653 * @polarity: compatibility parameter 654 */ 655 static void 656 irdma_copy_inline_data_gen_1(u8 *wqe, struct ib_sge *sge_list, 657 u32 num_sges, u8 polarity) 658 { 659 u32 quanta_bytes_remaining = 16; 660 u32 i; 661 662 for (i = 0; i < num_sges; i++) { 663 u8 *cur_sge = (u8 *)(uintptr_t)sge_list[i].addr; 664 u32 sge_len = sge_list[i].length; 665 666 while (sge_len) { 667 u32 bytes_copied; 668 669 bytes_copied = min(sge_len, quanta_bytes_remaining); 670 irdma_memcpy(wqe, cur_sge, bytes_copied); 671 wqe += bytes_copied; 672 cur_sge += bytes_copied; 673 quanta_bytes_remaining -= bytes_copied; 674 sge_len -= bytes_copied; 675 676 if (!quanta_bytes_remaining) { 677 /* Remaining inline bytes reside after hdr */ 678 wqe += 16; 679 quanta_bytes_remaining = 32; 680 } 681 } 682 } 683 } 684 685 /** 686 * irdma_inline_data_size_to_quanta_gen_1 - based on inline data, quanta 687 * @data_size: data size for inline 688 * 689 * Gets the quanta based on inline and immediate data. 690 */ 691 static inline u16 irdma_inline_data_size_to_quanta_gen_1(u32 data_size) { 692 return data_size <= 16 ? IRDMA_QP_WQE_MIN_QUANTA : 2; 693 } 694 695 /** 696 * irdma_copy_inline_data - Copy inline data to wqe 697 * @wqe: pointer to wqe 698 * @sge_list: table of pointers to inline data 699 * @num_sges: number of SGE's 700 * @polarity: polarity of wqe valid bit 701 */ 702 static void 703 irdma_copy_inline_data(u8 *wqe, struct ib_sge *sge_list, 704 u32 num_sges, u8 polarity) 705 { 706 u8 inline_valid = polarity << IRDMA_INLINE_VALID_S; 707 u32 quanta_bytes_remaining = 8; 708 u32 i; 709 bool first_quanta = true; 710 711 wqe += 8; 712 713 for (i = 0; i < num_sges; i++) { 714 u8 *cur_sge = (u8 *)(uintptr_t)sge_list[i].addr; 715 u32 sge_len = sge_list[i].length; 716 717 while (sge_len) { 718 u32 bytes_copied; 719 720 bytes_copied = min(sge_len, quanta_bytes_remaining); 721 irdma_memcpy(wqe, cur_sge, bytes_copied); 722 wqe += bytes_copied; 723 cur_sge += bytes_copied; 724 quanta_bytes_remaining -= bytes_copied; 725 sge_len -= bytes_copied; 726 727 if (!quanta_bytes_remaining) { 728 quanta_bytes_remaining = 31; 729 730 /* Remaining inline bytes reside after hdr */ 731 if (first_quanta) { 732 first_quanta = false; 733 wqe += 16; 734 } else { 735 *wqe = inline_valid; 736 wqe++; 737 } 738 } 739 } 740 } 741 if (!first_quanta && quanta_bytes_remaining < 31) 742 *(wqe + quanta_bytes_remaining) = inline_valid; 743 } 744 745 /** 746 * irdma_inline_data_size_to_quanta - based on inline data, quanta 747 * @data_size: data size for inline 748 * 749 * Gets the quanta based on inline and immediate data. 750 */ 751 static u16 irdma_inline_data_size_to_quanta(u32 data_size) { 752 if (data_size <= 8) 753 return IRDMA_QP_WQE_MIN_QUANTA; 754 else if (data_size <= 39) 755 return 2; 756 else if (data_size <= 70) 757 return 3; 758 else if (data_size <= 101) 759 return 4; 760 else if (data_size <= 132) 761 return 5; 762 else if (data_size <= 163) 763 return 6; 764 else if (data_size <= 194) 765 return 7; 766 else 767 return 8; 768 } 769 770 /** 771 * irdma_uk_inline_rdma_write - inline rdma write operation 772 * @qp: hw qp ptr 773 * @info: post sq information 774 * @post_sq: flag to post sq 775 */ 776 int 777 irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, 778 struct irdma_post_sq_info *info, bool post_sq) 779 { 780 __le64 *wqe; 781 struct irdma_rdma_write *op_info; 782 u64 hdr = 0; 783 u32 wqe_idx; 784 bool read_fence = false; 785 u16 quanta; 786 u32 i, total_size = 0; 787 788 info->push_wqe = qp->push_db ? true : false; 789 op_info = &info->op.rdma_write; 790 791 if (unlikely(qp->max_sq_frag_cnt < op_info->num_lo_sges)) 792 return -EINVAL; 793 794 for (i = 0; i < op_info->num_lo_sges; i++) 795 total_size += op_info->lo_sg_list[i].length; 796 797 if (unlikely(total_size > qp->max_inline_data)) 798 return -EINVAL; 799 800 quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(total_size); 801 802 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 803 if (!wqe) 804 return -ENOSPC; 805 806 read_fence |= info->read_fence; 807 set_64bit_val(wqe, IRDMA_BYTE_16, 808 FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.addr)); 809 810 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.lkey) | 811 FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | 812 FIELD_PREP(IRDMAQPSQ_INLINEDATALEN, total_size) | 813 FIELD_PREP(IRDMAQPSQ_REPORTRTT, info->report_rtt ? 1 : 0) | 814 FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, 1) | 815 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, info->imm_data_valid ? 1 : 0) | 816 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe ? 1 : 0) | 817 FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | 818 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 819 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 820 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 821 822 if (info->imm_data_valid) 823 set_64bit_val(wqe, IRDMA_BYTE_0, 824 FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); 825 826 qp->wqe_ops.iw_copy_inline_data((u8 *)wqe, op_info->lo_sg_list, 827 op_info->num_lo_sges, qp->swqe_polarity); 828 829 irdma_wmb(); /* make sure WQE is populated before valid bit is set */ 830 831 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 832 833 if (qp->push_db) 834 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, info->push_wqe); 835 else if (post_sq) 836 irdma_uk_qp_post_wr(qp); 837 838 return 0; 839 } 840 841 /** 842 * irdma_uk_inline_send - inline send operation 843 * @qp: hw qp ptr 844 * @info: post sq information 845 * @post_sq: flag to post sq 846 */ 847 int 848 irdma_uk_inline_send(struct irdma_qp_uk *qp, 849 struct irdma_post_sq_info *info, bool post_sq) 850 { 851 __le64 *wqe; 852 struct irdma_post_send *op_info; 853 u64 hdr; 854 u32 wqe_idx; 855 bool read_fence = false; 856 u16 quanta; 857 u32 i, total_size = 0; 858 859 info->push_wqe = qp->push_db ? true : false; 860 op_info = &info->op.send; 861 862 if (unlikely(qp->max_sq_frag_cnt < op_info->num_sges)) 863 return -EINVAL; 864 865 for (i = 0; i < op_info->num_sges; i++) 866 total_size += op_info->sg_list[i].length; 867 868 if (unlikely(total_size > qp->max_inline_data)) 869 return -EINVAL; 870 871 quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(total_size); 872 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); 873 if (!wqe) 874 return -ENOSPC; 875 876 set_64bit_val(wqe, IRDMA_BYTE_16, 877 FIELD_PREP(IRDMAQPSQ_DESTQKEY, op_info->qkey) | 878 FIELD_PREP(IRDMAQPSQ_DESTQPN, op_info->dest_qp)); 879 880 read_fence |= info->read_fence; 881 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, info->stag_to_inv) | 882 FIELD_PREP(IRDMAQPSQ_AHID, op_info->ah_id) | 883 FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | 884 FIELD_PREP(IRDMAQPSQ_INLINEDATALEN, total_size) | 885 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, 886 (info->imm_data_valid ? 1 : 0)) | 887 FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | 888 FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, 1) | 889 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 890 FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | 891 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 892 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 893 FIELD_PREP(IRDMAQPSQ_UDPHEADER, info->udp_hdr) | 894 FIELD_PREP(IRDMAQPSQ_L4LEN, info->l4len) | 895 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 896 897 if (info->imm_data_valid) 898 set_64bit_val(wqe, IRDMA_BYTE_0, 899 FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); 900 qp->wqe_ops.iw_copy_inline_data((u8 *)wqe, op_info->sg_list, 901 op_info->num_sges, qp->swqe_polarity); 902 903 irdma_wmb(); /* make sure WQE is populated before valid bit is set */ 904 905 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 906 907 if (qp->push_db) 908 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, info->push_wqe); 909 else if (post_sq) 910 irdma_uk_qp_post_wr(qp); 911 912 return 0; 913 } 914 915 /** 916 * irdma_uk_stag_local_invalidate - stag invalidate operation 917 * @qp: hw qp ptr 918 * @info: post sq information 919 * @post_sq: flag to post sq 920 */ 921 int 922 irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp, 923 struct irdma_post_sq_info *info, 924 bool post_sq) 925 { 926 __le64 *wqe; 927 struct irdma_inv_local_stag *op_info; 928 u64 hdr; 929 u32 wqe_idx; 930 bool local_fence = false; 931 struct ib_sge sge = {0}; 932 u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; 933 934 info->push_wqe = qp->push_db ? true : false; 935 op_info = &info->op.inv_local_stag; 936 local_fence = info->local_fence; 937 938 wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, 0, info); 939 if (!wqe) 940 return -ENOSPC; 941 942 sge.lkey = op_info->target_stag; 943 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, &sge, 0); 944 945 set_64bit_val(wqe, IRDMA_BYTE_16, 0); 946 947 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMA_OP_TYPE_INV_STAG) | 948 FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | 949 FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | 950 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, local_fence) | 951 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 952 FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); 953 954 irdma_wmb(); /* make sure WQE is populated before valid bit is set */ 955 956 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 957 958 if (qp->push_db) 959 irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, info->push_wqe); 960 else if (post_sq) 961 irdma_uk_qp_post_wr(qp); 962 963 return 0; 964 } 965 966 /** 967 * irdma_uk_post_receive - post receive wqe 968 * @qp: hw qp ptr 969 * @info: post rq information 970 */ 971 int 972 irdma_uk_post_receive(struct irdma_qp_uk *qp, 973 struct irdma_post_rq_info *info) 974 { 975 u32 wqe_idx, i, byte_off; 976 u32 addl_frag_cnt; 977 __le64 *wqe; 978 u64 hdr; 979 980 if (qp->max_rq_frag_cnt < info->num_sges) 981 return -EINVAL; 982 983 wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx); 984 if (!wqe) 985 return -ENOSPC; 986 987 qp->rq_wrid_array[wqe_idx] = info->wr_id; 988 addl_frag_cnt = info->num_sges > 1 ? (info->num_sges - 1) : 0; 989 qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, info->sg_list, 990 qp->rwqe_polarity); 991 992 for (i = 1, byte_off = IRDMA_BYTE_32; i < info->num_sges; i++) { 993 qp->wqe_ops.iw_set_fragment(wqe, byte_off, &info->sg_list[i], 994 qp->rwqe_polarity); 995 byte_off += 16; 996 } 997 998 /* if not an odd number set valid bit in next fragment */ 999 if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(info->num_sges & 0x01) && 1000 info->num_sges) { 1001 qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, 1002 qp->rwqe_polarity); 1003 if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) 1004 ++addl_frag_cnt; 1005 } 1006 1007 set_64bit_val(wqe, IRDMA_BYTE_16, 0); 1008 hdr = FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | 1009 FIELD_PREP(IRDMAQPSQ_VALID, qp->rwqe_polarity); 1010 1011 irdma_wmb(); /* make sure WQE is populated before valid bit is set */ 1012 1013 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 1014 1015 return 0; 1016 } 1017 1018 /** 1019 * irdma_uk_cq_resize - reset the cq buffer info 1020 * @cq: cq to resize 1021 * @cq_base: new cq buffer addr 1022 * @cq_size: number of cqes 1023 */ 1024 void 1025 irdma_uk_cq_resize(struct irdma_cq_uk *cq, void *cq_base, int cq_size) 1026 { 1027 cq->cq_base = cq_base; 1028 cq->cq_size = cq_size; 1029 IRDMA_RING_INIT(cq->cq_ring, cq->cq_size); 1030 cq->polarity = 1; 1031 } 1032 1033 /** 1034 * irdma_uk_cq_set_resized_cnt - record the count of the resized buffers 1035 * @cq: cq to resize 1036 * @cq_cnt: the count of the resized cq buffers 1037 */ 1038 void 1039 irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *cq, u16 cq_cnt) 1040 { 1041 u64 temp_val; 1042 u16 sw_cq_sel; 1043 u8 arm_next_se; 1044 u8 arm_next; 1045 u8 arm_seq_num; 1046 1047 get_64bit_val(cq->shadow_area, 32, &temp_val); 1048 1049 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); 1050 sw_cq_sel += cq_cnt; 1051 1052 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); 1053 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); 1054 arm_next = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT, temp_val); 1055 1056 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | 1057 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | 1058 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | 1059 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, arm_next); 1060 1061 set_64bit_val(cq->shadow_area, 32, temp_val); 1062 } 1063 1064 /** 1065 * irdma_uk_cq_request_notification - cq notification request (door bell) 1066 * @cq: hw cq 1067 * @cq_notify: notification type 1068 */ 1069 void 1070 irdma_uk_cq_request_notification(struct irdma_cq_uk *cq, 1071 enum irdma_cmpl_notify cq_notify) 1072 { 1073 u64 temp_val; 1074 u16 sw_cq_sel; 1075 u8 arm_next_se = 0; 1076 u8 arm_next = 0; 1077 u8 arm_seq_num; 1078 1079 get_64bit_val(cq->shadow_area, IRDMA_BYTE_32, &temp_val); 1080 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); 1081 arm_seq_num++; 1082 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); 1083 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); 1084 arm_next_se |= 1; 1085 if (cq_notify == IRDMA_CQ_COMPL_EVENT) 1086 arm_next = 1; 1087 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | 1088 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | 1089 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | 1090 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, arm_next); 1091 1092 set_64bit_val(cq->shadow_area, IRDMA_BYTE_32, temp_val); 1093 1094 irdma_wmb(); /* make sure WQE is populated before valid bit is set */ 1095 1096 db_wr32(cq->cq_id, cq->cqe_alloc_db); 1097 } 1098 1099 static int 1100 irdma_check_rq_cqe(struct irdma_qp_uk *qp, u32 *array_idx) 1101 { 1102 u32 exp_idx = (qp->last_rx_cmpl_idx + 1) % qp->rq_size; 1103 1104 if (*array_idx != exp_idx) { 1105 1106 *array_idx = exp_idx; 1107 qp->last_rx_cmpl_idx = exp_idx; 1108 1109 return -1; 1110 } 1111 1112 qp->last_rx_cmpl_idx = *array_idx; 1113 1114 return 0; 1115 } 1116 1117 /** 1118 * irdma_detect_unsignaled_cmpls - check if unsignaled cmpl is to be reported 1119 * @cq: hw cq 1120 * @qp: hw qp 1121 * @info: cq poll information collected 1122 * @wge_idx: index of the WR in SQ ring 1123 */ 1124 static int 1125 irdma_detect_unsignaled_cmpls(struct irdma_cq_uk *cq, 1126 struct irdma_qp_uk *qp, 1127 struct irdma_cq_poll_info *info, 1128 u32 wqe_idx) 1129 { 1130 u64 qword0, qword1, qword2, qword3; 1131 __le64 *cqe, *wqe; 1132 int i; 1133 u32 widx; 1134 1135 if (qp->sq_wrtrk_array[wqe_idx].signaled == 0) { 1136 cqe = IRDMA_GET_CURRENT_CQ_ELEM(cq); 1137 irdma_pr_err("%p %d %d\n", cqe, cq->cq_ring.head, wqe_idx); 1138 for (i = -10; i <= 10; i++) { 1139 IRDMA_GET_CQ_ELEM_AT_OFFSET(cq, i + cq->cq_ring.size, cqe); 1140 get_64bit_val(cqe, IRDMA_BYTE_0, &qword0); 1141 get_64bit_val(cqe, IRDMA_BYTE_8, &qword1); 1142 get_64bit_val(cqe, IRDMA_BYTE_16, &qword2); 1143 get_64bit_val(cqe, IRDMA_BYTE_24, &qword3); 1144 widx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); 1145 irdma_pr_err("%d %04x %p %016lx %016lx %016lx %016lx ", 1146 i, widx, cqe, qword0, qword1, qword2, qword3); 1147 if ((u8)FIELD_GET(IRDMA_CQ_SQ, qword3)) { 1148 irdma_pr_err("%lx %x %x %x ", 1149 qp->sq_wrtrk_array[widx].wrid, qp->sq_wrtrk_array[widx].wr_len, 1150 qp->sq_wrtrk_array[widx].quanta, qp->sq_wrtrk_array[widx].signaled); 1151 wqe = qp->sq_base[widx].elem; 1152 get_64bit_val(wqe, IRDMA_BYTE_0, &qword0); 1153 get_64bit_val(wqe, IRDMA_BYTE_8, &qword1); 1154 get_64bit_val(wqe, IRDMA_BYTE_16, &qword2); 1155 get_64bit_val(wqe, IRDMA_BYTE_24, &qword3); 1156 1157 irdma_pr_err("%016lx %016lx %016lx %016lx \n", 1158 qword0, qword1, qword2, qword3); 1159 } else { 1160 irdma_pr_err("\n"); 1161 } 1162 } 1163 return -ENOENT; 1164 } 1165 1166 return 0; 1167 } 1168 1169 /** 1170 * irdma_uk_cq_empty - Check if CQ is empty 1171 * @cq: hw cq 1172 */ 1173 bool 1174 irdma_uk_cq_empty(struct irdma_cq_uk *cq) 1175 { 1176 __le64 *cqe; 1177 u8 polarity; 1178 u64 qword3; 1179 1180 if (cq->avoid_mem_cflct) 1181 cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(cq); 1182 else 1183 cqe = IRDMA_GET_CURRENT_CQ_ELEM(cq); 1184 1185 get_64bit_val(cqe, 24, &qword3); 1186 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); 1187 1188 return polarity != cq->polarity; 1189 } 1190 1191 /** 1192 * irdma_uk_cq_poll_cmpl - get cq completion info 1193 * @cq: hw cq 1194 * @info: cq poll information returned 1195 */ 1196 int 1197 irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq, 1198 struct irdma_cq_poll_info *info) 1199 { 1200 u64 comp_ctx, qword0, qword2, qword3; 1201 __le64 *cqe; 1202 struct irdma_qp_uk *qp; 1203 struct irdma_ring *pring = NULL; 1204 u32 wqe_idx; 1205 int ret_code; 1206 bool move_cq_head = true; 1207 u8 polarity; 1208 bool ext_valid; 1209 __le64 *ext_cqe; 1210 unsigned long flags; 1211 1212 if (cq->avoid_mem_cflct) 1213 cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(cq); 1214 else 1215 cqe = IRDMA_GET_CURRENT_CQ_ELEM(cq); 1216 1217 get_64bit_val(cqe, IRDMA_BYTE_24, &qword3); 1218 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); 1219 if (polarity != cq->polarity) 1220 return -ENOENT; 1221 1222 /* Ensure CQE contents are read after valid bit is checked */ 1223 rmb(); 1224 1225 ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); 1226 if (ext_valid) { 1227 u64 qword6, qword7; 1228 u32 peek_head; 1229 1230 if (cq->avoid_mem_cflct) { 1231 ext_cqe = (__le64 *) ((u8 *)cqe + 32); 1232 get_64bit_val(ext_cqe, IRDMA_BYTE_24, &qword7); 1233 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); 1234 } else { 1235 peek_head = (cq->cq_ring.head + 1) % cq->cq_ring.size; 1236 ext_cqe = cq->cq_base[peek_head].buf; 1237 get_64bit_val(ext_cqe, IRDMA_BYTE_24, &qword7); 1238 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); 1239 if (!peek_head) 1240 polarity ^= 1; 1241 } 1242 if (polarity != cq->polarity) 1243 return -ENOENT; 1244 1245 /* Ensure ext CQE contents are read after ext valid bit is checked */ 1246 rmb(); 1247 1248 info->imm_valid = (bool)FIELD_GET(IRDMA_CQ_IMMVALID, qword7); 1249 if (info->imm_valid) { 1250 u64 qword4; 1251 1252 get_64bit_val(ext_cqe, IRDMA_BYTE_0, &qword4); 1253 info->imm_data = (u32)FIELD_GET(IRDMA_CQ_IMMDATALOW32, qword4); 1254 } 1255 info->ud_smac_valid = (bool)FIELD_GET(IRDMA_CQ_UDSMACVALID, qword7); 1256 info->ud_vlan_valid = (bool)FIELD_GET(IRDMA_CQ_UDVLANVALID, qword7); 1257 if (info->ud_smac_valid || info->ud_vlan_valid) { 1258 get_64bit_val(ext_cqe, IRDMA_BYTE_16, &qword6); 1259 if (info->ud_vlan_valid) 1260 info->ud_vlan = (u16)FIELD_GET(IRDMA_CQ_UDVLAN, qword6); 1261 if (info->ud_smac_valid) { 1262 info->ud_smac[5] = qword6 & 0xFF; 1263 info->ud_smac[4] = (qword6 >> 8) & 0xFF; 1264 info->ud_smac[3] = (qword6 >> 16) & 0xFF; 1265 info->ud_smac[2] = (qword6 >> 24) & 0xFF; 1266 info->ud_smac[1] = (qword6 >> 32) & 0xFF; 1267 info->ud_smac[0] = (qword6 >> 40) & 0xFF; 1268 } 1269 } 1270 } else { 1271 info->imm_valid = false; 1272 info->ud_smac_valid = false; 1273 info->ud_vlan_valid = false; 1274 } 1275 1276 info->q_type = (u8)FIELD_GET(IRDMA_CQ_SQ, qword3); 1277 info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); 1278 info->push_dropped = (bool)FIELD_GET(IRDMACQ_PSHDROP, qword3); 1279 info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); 1280 get_64bit_val(cqe, IRDMA_BYTE_8, &comp_ctx); 1281 qp = (struct irdma_qp_uk *)(irdma_uintptr) comp_ctx; 1282 if (!qp || qp->destroy_pending) { 1283 ret_code = -EFAULT; 1284 goto exit; 1285 } 1286 if (info->error) { 1287 info->major_err = FIELD_GET(IRDMA_CQ_MAJERR, qword3); 1288 info->minor_err = FIELD_GET(IRDMA_CQ_MINERR, qword3); 1289 switch (info->major_err) { 1290 case IRDMA_FLUSH_MAJOR_ERR: 1291 /* Set the min error to standard flush error code for remaining cqes */ 1292 if (info->minor_err != FLUSH_GENERAL_ERR) { 1293 qword3 &= ~IRDMA_CQ_MINERR; 1294 qword3 |= FIELD_PREP(IRDMA_CQ_MINERR, FLUSH_GENERAL_ERR); 1295 set_64bit_val(cqe, IRDMA_BYTE_24, qword3); 1296 } 1297 info->comp_status = IRDMA_COMPL_STATUS_FLUSHED; 1298 break; 1299 default: 1300 info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; 1301 break; 1302 } 1303 } else { 1304 info->comp_status = IRDMA_COMPL_STATUS_SUCCESS; 1305 } 1306 1307 get_64bit_val(cqe, IRDMA_BYTE_0, &qword0); 1308 get_64bit_val(cqe, IRDMA_BYTE_16, &qword2); 1309 1310 info->qp_id = (u32)FIELD_GET(IRDMACQ_QPID, qword2); 1311 info->ud_src_qpn = (u32)FIELD_GET(IRDMACQ_UDSRCQPN, qword2); 1312 1313 info->solicited_event = (bool)FIELD_GET(IRDMACQ_SOEVENT, qword3); 1314 wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); 1315 info->qp_handle = (irdma_qp_handle) (irdma_uintptr) qp; 1316 info->op_type = (u8)FIELD_GET(IRDMACQ_OP, qword3); 1317 1318 if (info->q_type == IRDMA_CQE_QTYPE_RQ) { 1319 u32 array_idx; 1320 1321 array_idx = wqe_idx / qp->rq_wqe_size_multiplier; 1322 info->bytes_xfered = (u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); 1323 info->signaled = 1; 1324 1325 if (qword3 & IRDMACQ_STAG) { 1326 info->stag_invalid_set = true; 1327 info->inv_stag = (u32)FIELD_GET(IRDMACQ_INVSTAG, qword2); 1328 } else { 1329 info->stag_invalid_set = false; 1330 } 1331 1332 if (info->comp_status == IRDMA_COMPL_STATUS_FLUSHED || 1333 info->comp_status == IRDMA_COMPL_STATUS_UNKNOWN) { 1334 spin_lock_irqsave(qp->lock, flags); 1335 if (!IRDMA_RING_MORE_WORK(qp->rq_ring)) { 1336 ret_code = -ENOENT; 1337 spin_unlock_irqrestore(qp->lock, flags); 1338 goto exit; 1339 } 1340 1341 info->wr_id = qp->rq_wrid_array[qp->rq_ring.tail]; 1342 IRDMA_RING_SET_TAIL(qp->rq_ring, qp->rq_ring.tail + 1); 1343 if (!IRDMA_RING_MORE_WORK(qp->rq_ring)) 1344 qp->rq_flush_complete = true; 1345 else 1346 move_cq_head = false; 1347 spin_unlock_irqrestore(qp->lock, flags); 1348 } else { 1349 info->wr_id = qp->rq_wrid_array[array_idx]; 1350 if (irdma_check_rq_cqe(qp, &array_idx)) { 1351 info->wr_id = qp->rq_wrid_array[array_idx]; 1352 info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; 1353 IRDMA_RING_SET_TAIL(qp->rq_ring, array_idx + 1); 1354 return 0; 1355 } 1356 IRDMA_RING_SET_TAIL(qp->rq_ring, array_idx + 1); 1357 } 1358 pring = &qp->rq_ring; 1359 } else { /* q_type is IRDMA_CQE_QTYPE_SQ */ 1360 if (qp->first_sq_wq) { 1361 if (wqe_idx + 1 >= qp->conn_wqes) 1362 qp->first_sq_wq = false; 1363 1364 if (wqe_idx < qp->conn_wqes && qp->sq_ring.head == qp->sq_ring.tail) { 1365 IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); 1366 IRDMA_RING_MOVE_TAIL(cq->cq_ring); 1367 set_64bit_val(cq->shadow_area, IRDMA_BYTE_0, 1368 IRDMA_RING_CURRENT_HEAD(cq->cq_ring)); 1369 memset(info, 0, sizeof(*info)); 1370 return irdma_uk_cq_poll_cmpl(cq, info); 1371 } 1372 } 1373 /* cease posting push mode on push drop */ 1374 if (info->push_dropped) { 1375 qp->push_mode = false; 1376 qp->push_dropped = true; 1377 } 1378 if (info->comp_status != IRDMA_COMPL_STATUS_FLUSHED) { 1379 info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid; 1380 info->signaled = qp->sq_wrtrk_array[wqe_idx].signaled; 1381 if (!info->comp_status) 1382 info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len; 1383 ret_code = irdma_detect_unsignaled_cmpls(cq, qp, info, wqe_idx); 1384 if (ret_code != 0) 1385 goto exit; 1386 info->op_type = (u8)FIELD_GET(IRDMACQ_OP, qword3); 1387 IRDMA_RING_SET_TAIL(qp->sq_ring, 1388 wqe_idx + qp->sq_wrtrk_array[wqe_idx].quanta); 1389 } else { 1390 spin_lock_irqsave(qp->lock, flags); 1391 if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) { 1392 spin_unlock_irqrestore(qp->lock, flags); 1393 ret_code = -ENOENT; 1394 goto exit; 1395 } 1396 1397 do { 1398 __le64 *sw_wqe; 1399 u64 wqe_qword; 1400 u32 tail; 1401 1402 tail = qp->sq_ring.tail; 1403 sw_wqe = qp->sq_base[tail].elem; 1404 get_64bit_val(sw_wqe, IRDMA_BYTE_24, 1405 &wqe_qword); 1406 info->op_type = (u8)FIELD_GET(IRDMAQPSQ_OPCODE, 1407 wqe_qword); 1408 IRDMA_RING_SET_TAIL(qp->sq_ring, 1409 tail + qp->sq_wrtrk_array[tail].quanta); 1410 if (info->op_type != IRDMAQP_OP_NOP) { 1411 info->wr_id = qp->sq_wrtrk_array[tail].wrid; 1412 info->signaled = qp->sq_wrtrk_array[tail].signaled; 1413 info->bytes_xfered = qp->sq_wrtrk_array[tail].wr_len; 1414 break; 1415 } 1416 } while (1); 1417 1418 if (info->op_type == IRDMA_OP_TYPE_BIND_MW && 1419 info->minor_err == FLUSH_PROT_ERR) 1420 info->minor_err = FLUSH_MW_BIND_ERR; 1421 if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) 1422 qp->sq_flush_complete = true; 1423 spin_unlock_irqrestore(qp->lock, flags); 1424 } 1425 pring = &qp->sq_ring; 1426 } 1427 1428 ret_code = 0; 1429 1430 exit: 1431 if (!ret_code && info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) { 1432 if (pring && IRDMA_RING_MORE_WORK(*pring)) 1433 move_cq_head = false; 1434 } 1435 1436 if (move_cq_head) { 1437 IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); 1438 if (!IRDMA_RING_CURRENT_HEAD(cq->cq_ring)) 1439 cq->polarity ^= 1; 1440 1441 if (ext_valid && !cq->avoid_mem_cflct) { 1442 IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); 1443 if (!IRDMA_RING_CURRENT_HEAD(cq->cq_ring)) 1444 cq->polarity ^= 1; 1445 } 1446 1447 IRDMA_RING_MOVE_TAIL(cq->cq_ring); 1448 if (!cq->avoid_mem_cflct && ext_valid) 1449 IRDMA_RING_MOVE_TAIL(cq->cq_ring); 1450 if (IRDMA_RING_CURRENT_HEAD(cq->cq_ring) & 0x3F || irdma_uk_cq_empty(cq)) 1451 set_64bit_val(cq->shadow_area, IRDMA_BYTE_0, 1452 IRDMA_RING_CURRENT_HEAD(cq->cq_ring)); 1453 } else { 1454 qword3 &= ~IRDMA_CQ_WQEIDX; 1455 qword3 |= FIELD_PREP(IRDMA_CQ_WQEIDX, pring->tail); 1456 set_64bit_val(cqe, IRDMA_BYTE_24, qword3); 1457 } 1458 1459 return ret_code; 1460 } 1461 1462 /** 1463 * irdma_round_up_wq - return round up qp wq depth 1464 * @wqdepth: wq depth in quanta to round up 1465 */ 1466 static int 1467 irdma_round_up_wq(u32 wqdepth) 1468 { 1469 int scount = 1; 1470 1471 for (wqdepth--; scount <= 16; scount *= 2) 1472 wqdepth |= wqdepth >> scount; 1473 1474 return ++wqdepth; 1475 } 1476 1477 /** 1478 * irdma_get_wqe_shift - get shift count for maximum wqe size 1479 * @uk_attrs: qp HW attributes 1480 * @sge: Maximum Scatter Gather Elements wqe 1481 * @inline_data: Maximum inline data size 1482 * @shift: Returns the shift needed based on sge 1483 * 1484 * Shift can be used to left shift the wqe size based on number of SGEs and inlind data size. 1485 * For 1 SGE or inline data <= 8, shift = 0 (wqe size of 32 1486 * bytes). For 2 or 3 SGEs or inline data <= 39, shift = 1 (wqe 1487 * size of 64 bytes). 1488 * For 4-7 SGE's and inline <= 101 Shift of 2 otherwise (wqe 1489 * size of 256 bytes). 1490 */ 1491 void 1492 irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge, 1493 u32 inline_data, u8 *shift) 1494 { 1495 *shift = 0; 1496 if (uk_attrs->hw_rev >= IRDMA_GEN_2) { 1497 if (sge > 1 || inline_data > 8) { 1498 if (sge < 4 && inline_data <= 39) 1499 *shift = 1; 1500 else if (sge < 8 && inline_data <= 101) 1501 *shift = 2; 1502 else 1503 *shift = 3; 1504 } 1505 } else if (sge > 1 || inline_data > 16) { 1506 *shift = (sge < 4 && inline_data <= 48) ? 1 : 2; 1507 } 1508 } 1509 1510 /* 1511 * irdma_get_sqdepth - get SQ depth (quanta) @uk_attrs: qp HW attributes @sq_size: SQ size @shift: shift which 1512 * determines size of WQE @sqdepth: depth of SQ 1513 */ 1514 int 1515 irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, u32 sq_size, u8 shift, u32 *sqdepth) 1516 { 1517 u32 min_hw_quanta = (u32)uk_attrs->min_hw_wq_size << shift; 1518 u64 hw_quanta = 1519 irdma_round_up_wq(((u64)sq_size << shift) + IRDMA_SQ_RSVD); 1520 1521 if (hw_quanta < min_hw_quanta) 1522 hw_quanta = min_hw_quanta; 1523 else if (hw_quanta > uk_attrs->max_hw_wq_quanta) 1524 return -EINVAL; 1525 1526 *sqdepth = hw_quanta; 1527 return 0; 1528 } 1529 1530 /* 1531 * irdma_get_rqdepth - get RQ depth (quanta) @uk_attrs: qp HW attributes @rq_size: SRQ size @shift: shift which 1532 * determines size of WQE @rqdepth: depth of RQ/SRQ 1533 */ 1534 int 1535 irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, u32 rq_size, u8 shift, u32 *rqdepth) 1536 { 1537 u32 min_hw_quanta = (u32)uk_attrs->min_hw_wq_size << shift; 1538 u64 hw_quanta = 1539 irdma_round_up_wq(((u64)rq_size << shift) + IRDMA_RQ_RSVD); 1540 1541 if (hw_quanta < min_hw_quanta) 1542 hw_quanta = min_hw_quanta; 1543 else if (hw_quanta > uk_attrs->max_hw_rq_quanta) 1544 return -EINVAL; 1545 1546 *rqdepth = hw_quanta; 1547 return 0; 1548 } 1549 1550 static const struct irdma_wqe_uk_ops iw_wqe_uk_ops = { 1551 .iw_copy_inline_data = irdma_copy_inline_data, 1552 .iw_inline_data_size_to_quanta = irdma_inline_data_size_to_quanta, 1553 .iw_set_fragment = irdma_set_fragment, 1554 }; 1555 1556 static const struct irdma_wqe_uk_ops iw_wqe_uk_ops_gen_1 = { 1557 .iw_copy_inline_data = irdma_copy_inline_data_gen_1, 1558 .iw_inline_data_size_to_quanta = irdma_inline_data_size_to_quanta_gen_1, 1559 .iw_set_fragment = irdma_set_fragment_gen_1, 1560 }; 1561 1562 /** 1563 * irdma_setup_connection_wqes - setup WQEs necessary to complete 1564 * connection. 1565 * @qp: hw qp (user and kernel) 1566 * @info: qp initialization info 1567 */ 1568 static void 1569 irdma_setup_connection_wqes(struct irdma_qp_uk *qp, 1570 struct irdma_qp_uk_init_info *info) 1571 { 1572 u16 move_cnt = 1; 1573 1574 if (info->start_wqe_idx) 1575 move_cnt = info->start_wqe_idx; 1576 else if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_RTS_AE) 1577 move_cnt = 3; 1578 qp->conn_wqes = move_cnt; 1579 IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, move_cnt); 1580 IRDMA_RING_MOVE_TAIL_BY_COUNT(qp->sq_ring, move_cnt); 1581 IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->initial_ring, move_cnt); 1582 } 1583 1584 /** 1585 * irdma_uk_calc_shift_wq - calculate WQE shift for both SQ and RQ 1586 * @ukinfo: qp initialization info 1587 * @sq_shift: Returns shift of SQ 1588 * @rq_shift: Returns shift of RQ 1589 */ 1590 void 1591 irdma_uk_calc_shift_wq(struct irdma_qp_uk_init_info *ukinfo, u8 *sq_shift, 1592 u8 *rq_shift) 1593 { 1594 bool imm_support = ukinfo->uk_attrs->hw_rev >= IRDMA_GEN_2 ? true : false; 1595 1596 irdma_get_wqe_shift(ukinfo->uk_attrs, 1597 imm_support ? ukinfo->max_sq_frag_cnt + 1 : 1598 ukinfo->max_sq_frag_cnt, 1599 ukinfo->max_inline_data, sq_shift); 1600 1601 irdma_get_wqe_shift(ukinfo->uk_attrs, ukinfo->max_rq_frag_cnt, 0, 1602 rq_shift); 1603 1604 if (ukinfo->uk_attrs->hw_rev == IRDMA_GEN_1) { 1605 if (ukinfo->abi_ver > 4) 1606 *rq_shift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1; 1607 } 1608 } 1609 1610 /** 1611 * irdma_uk_calc_depth_shift_sq - calculate depth and shift for SQ size. 1612 * @ukinfo: qp initialization info 1613 * @sq_depth: Returns depth of SQ 1614 * @sq_shift: Returns shift of SQ 1615 */ 1616 int 1617 irdma_uk_calc_depth_shift_sq(struct irdma_qp_uk_init_info *ukinfo, 1618 u32 *sq_depth, u8 *sq_shift) 1619 { 1620 bool imm_support = ukinfo->uk_attrs->hw_rev >= IRDMA_GEN_2 ? true : false; 1621 int status; 1622 1623 irdma_get_wqe_shift(ukinfo->uk_attrs, 1624 imm_support ? ukinfo->max_sq_frag_cnt + 1 : 1625 ukinfo->max_sq_frag_cnt, 1626 ukinfo->max_inline_data, sq_shift); 1627 status = irdma_get_sqdepth(ukinfo->uk_attrs, ukinfo->sq_size, 1628 *sq_shift, sq_depth); 1629 1630 return status; 1631 } 1632 1633 /** 1634 * irdma_uk_calc_depth_shift_rq - calculate depth and shift for RQ size. 1635 * @ukinfo: qp initialization info 1636 * @rq_depth: Returns depth of RQ 1637 * @rq_shift: Returns shift of RQ 1638 */ 1639 int 1640 irdma_uk_calc_depth_shift_rq(struct irdma_qp_uk_init_info *ukinfo, 1641 u32 *rq_depth, u8 *rq_shift) 1642 { 1643 int status; 1644 1645 irdma_get_wqe_shift(ukinfo->uk_attrs, ukinfo->max_rq_frag_cnt, 0, 1646 rq_shift); 1647 1648 if (ukinfo->uk_attrs->hw_rev == IRDMA_GEN_1) { 1649 if (ukinfo->abi_ver > 4) 1650 *rq_shift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1; 1651 } 1652 1653 status = irdma_get_rqdepth(ukinfo->uk_attrs, ukinfo->rq_size, 1654 *rq_shift, rq_depth); 1655 1656 return status; 1657 } 1658 1659 /** 1660 * irdma_uk_qp_init - initialize shared qp 1661 * @qp: hw qp (user and kernel) 1662 * @info: qp initialization info 1663 * 1664 * initializes the vars used in both user and kernel mode. 1665 * size of the wqe depends on numbers of max. fragements 1666 * allowed. Then size of wqe * the number of wqes should be the 1667 * amount of memory allocated for sq and rq. 1668 */ 1669 int 1670 irdma_uk_qp_init(struct irdma_qp_uk *qp, struct irdma_qp_uk_init_info *info) 1671 { 1672 int ret_code = 0; 1673 u32 sq_ring_size; 1674 1675 qp->uk_attrs = info->uk_attrs; 1676 if (info->max_sq_frag_cnt > qp->uk_attrs->max_hw_wq_frags || 1677 info->max_rq_frag_cnt > qp->uk_attrs->max_hw_wq_frags) 1678 return -EINVAL; 1679 1680 qp->qp_caps = info->qp_caps; 1681 qp->sq_base = info->sq; 1682 qp->rq_base = info->rq; 1683 qp->qp_type = info->type ? info->type : IRDMA_QP_TYPE_IWARP; 1684 qp->shadow_area = info->shadow_area; 1685 qp->sq_wrtrk_array = info->sq_wrtrk_array; 1686 1687 qp->rq_wrid_array = info->rq_wrid_array; 1688 qp->wqe_alloc_db = info->wqe_alloc_db; 1689 qp->last_rx_cmpl_idx = 0xffffffff; 1690 qp->rd_fence_rate = info->rd_fence_rate; 1691 qp->qp_id = info->qp_id; 1692 qp->sq_size = info->sq_size; 1693 qp->push_mode = false; 1694 qp->max_sq_frag_cnt = info->max_sq_frag_cnt; 1695 sq_ring_size = qp->sq_size << info->sq_shift; 1696 IRDMA_RING_INIT(qp->sq_ring, sq_ring_size); 1697 IRDMA_RING_INIT(qp->initial_ring, sq_ring_size); 1698 if (info->first_sq_wq) { 1699 irdma_setup_connection_wqes(qp, info); 1700 qp->swqe_polarity = 1; 1701 qp->first_sq_wq = true; 1702 } else { 1703 qp->swqe_polarity = 0; 1704 } 1705 qp->swqe_polarity_deferred = 1; 1706 qp->rwqe_polarity = 0; 1707 qp->rq_size = info->rq_size; 1708 qp->max_rq_frag_cnt = info->max_rq_frag_cnt; 1709 qp->max_inline_data = info->max_inline_data; 1710 qp->rq_wqe_size = info->rq_shift; 1711 IRDMA_RING_INIT(qp->rq_ring, qp->rq_size); 1712 qp->rq_wqe_size_multiplier = 1 << info->rq_shift; 1713 if (qp->uk_attrs->hw_rev == IRDMA_GEN_1) 1714 qp->wqe_ops = iw_wqe_uk_ops_gen_1; 1715 else 1716 qp->wqe_ops = iw_wqe_uk_ops; 1717 qp->start_wqe_idx = info->start_wqe_idx; 1718 1719 return ret_code; 1720 } 1721 1722 /** 1723 * irdma_uk_cq_init - initialize shared cq (user and kernel) 1724 * @cq: hw cq 1725 * @info: hw cq initialization info 1726 */ 1727 int 1728 irdma_uk_cq_init(struct irdma_cq_uk *cq, struct irdma_cq_uk_init_info *info) 1729 { 1730 cq->cq_base = info->cq_base; 1731 cq->cq_id = info->cq_id; 1732 cq->cq_size = info->cq_size; 1733 cq->cqe_alloc_db = info->cqe_alloc_db; 1734 cq->cq_ack_db = info->cq_ack_db; 1735 cq->shadow_area = info->shadow_area; 1736 cq->avoid_mem_cflct = info->avoid_mem_cflct; 1737 IRDMA_RING_INIT(cq->cq_ring, cq->cq_size); 1738 cq->polarity = 1; 1739 1740 return 0; 1741 } 1742 1743 /** 1744 * irdma_uk_clean_cq - clean cq entries 1745 * @q: completion context 1746 * @cq: cq to clean 1747 */ 1748 int 1749 irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq) 1750 { 1751 __le64 *cqe; 1752 u64 qword3, comp_ctx; 1753 u32 cq_head; 1754 u8 polarity, temp; 1755 1756 cq_head = cq->cq_ring.head; 1757 temp = cq->polarity; 1758 do { 1759 if (cq->avoid_mem_cflct) 1760 cqe = ((struct irdma_extended_cqe *)(cq->cq_base))[cq_head].buf; 1761 else 1762 cqe = cq->cq_base[cq_head].buf; 1763 get_64bit_val(cqe, IRDMA_BYTE_24, &qword3); 1764 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); 1765 1766 if (polarity != temp) 1767 break; 1768 1769 /* Ensure CQE contents are read after valid bit is checked */ 1770 rmb(); 1771 1772 get_64bit_val(cqe, IRDMA_BYTE_8, &comp_ctx); 1773 if ((void *)(irdma_uintptr) comp_ctx == q) 1774 set_64bit_val(cqe, IRDMA_BYTE_8, 0); 1775 1776 cq_head = (cq_head + 1) % cq->cq_ring.size; 1777 if (!cq_head) 1778 temp ^= 1; 1779 } while (true); 1780 return 0; 1781 } 1782 1783 /** 1784 * irdma_fragcnt_to_quanta_sq - calculate quanta based on fragment count for SQ 1785 * @frag_cnt: number of fragments 1786 * @quanta: quanta for frag_cnt 1787 */ 1788 int 1789 irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta) 1790 { 1791 switch (frag_cnt) { 1792 case 0: 1793 case 1: 1794 *quanta = IRDMA_QP_WQE_MIN_QUANTA; 1795 break; 1796 case 2: 1797 case 3: 1798 *quanta = 2; 1799 break; 1800 case 4: 1801 case 5: 1802 *quanta = 3; 1803 break; 1804 case 6: 1805 case 7: 1806 *quanta = 4; 1807 break; 1808 case 8: 1809 case 9: 1810 *quanta = 5; 1811 break; 1812 case 10: 1813 case 11: 1814 *quanta = 6; 1815 break; 1816 case 12: 1817 case 13: 1818 *quanta = 7; 1819 break; 1820 case 14: 1821 case 15: /* when immediate data is present */ 1822 *quanta = 8; 1823 break; 1824 default: 1825 return -EINVAL; 1826 } 1827 1828 return 0; 1829 } 1830 1831 /** 1832 * irdma_fragcnt_to_wqesize_rq - calculate wqe size based on fragment count for RQ 1833 * @frag_cnt: number of fragments 1834 * @wqe_size: size in bytes given frag_cnt 1835 */ 1836 int 1837 irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size) 1838 { 1839 switch (frag_cnt) { 1840 case 0: 1841 case 1: 1842 *wqe_size = 32; 1843 break; 1844 case 2: 1845 case 3: 1846 *wqe_size = 64; 1847 break; 1848 case 4: 1849 case 5: 1850 case 6: 1851 case 7: 1852 *wqe_size = 128; 1853 break; 1854 case 8: 1855 case 9: 1856 case 10: 1857 case 11: 1858 case 12: 1859 case 13: 1860 case 14: 1861 *wqe_size = 256; 1862 break; 1863 default: 1864 return -EINVAL; 1865 } 1866 1867 return 0; 1868 } 1869