1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2023 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include "osdep.h" 36 #include "irdma_hmc.h" 37 #include "irdma_defs.h" 38 #include "irdma_type.h" 39 #include "irdma_protos.h" 40 #include "irdma_puda.h" 41 #include "irdma_ws.h" 42 43 static void 44 irdma_ieq_receive(struct irdma_sc_vsi *vsi, 45 struct irdma_puda_buf *buf); 46 static void irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid); 47 static void 48 irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, 49 struct irdma_puda_buf *buf, u32 wqe_idx); 50 /** 51 * irdma_puda_get_listbuf - get buffer from puda list 52 * @list: list to use for buffers (ILQ or IEQ) 53 */ 54 static struct irdma_puda_buf * 55 irdma_puda_get_listbuf(struct list_head *list) 56 { 57 struct irdma_puda_buf *buf = NULL; 58 59 if (!list_empty(list)) { 60 buf = (struct irdma_puda_buf *)(list)->next; 61 list_del((struct list_head *)&buf->list); 62 } 63 64 return buf; 65 } 66 67 /** 68 * irdma_puda_get_bufpool - return buffer from resource 69 * @rsrc: resource to use for buffer 70 */ 71 struct irdma_puda_buf * 72 irdma_puda_get_bufpool(struct irdma_puda_rsrc *rsrc) 73 { 74 struct irdma_puda_buf *buf = NULL; 75 struct list_head *list = &rsrc->bufpool; 76 unsigned long flags; 77 78 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 79 buf = irdma_puda_get_listbuf(list); 80 if (buf) { 81 rsrc->avail_buf_count--; 82 buf->vsi = rsrc->vsi; 83 } else { 84 rsrc->stats_buf_alloc_fail++; 85 } 86 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 87 88 return buf; 89 } 90 91 /** 92 * irdma_puda_ret_bufpool - return buffer to rsrc list 93 * @rsrc: resource to use for buffer 94 * @buf: buffer to return to resource 95 */ 96 void 97 irdma_puda_ret_bufpool(struct irdma_puda_rsrc *rsrc, 98 struct irdma_puda_buf *buf) 99 { 100 unsigned long flags; 101 102 buf->do_lpb = false; 103 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 104 list_add(&buf->list, &rsrc->bufpool); 105 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 106 rsrc->avail_buf_count++; 107 } 108 109 /** 110 * irdma_puda_post_recvbuf - set wqe for rcv buffer 111 * @rsrc: resource ptr 112 * @wqe_idx: wqe index to use 113 * @buf: puda buffer for rcv q 114 * @initial: flag if during init time 115 */ 116 static void 117 irdma_puda_post_recvbuf(struct irdma_puda_rsrc *rsrc, u32 wqe_idx, 118 struct irdma_puda_buf *buf, bool initial) 119 { 120 __le64 *wqe; 121 struct irdma_sc_qp *qp = &rsrc->qp; 122 u64 offset24 = 0; 123 124 /* Synch buffer for use by device */ 125 dma_sync_single_for_device(hw_to_dev(rsrc->dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 126 qp->qp_uk.rq_wrid_array[wqe_idx] = (uintptr_t)buf; 127 wqe = qp->qp_uk.rq_base[wqe_idx].elem; 128 if (!initial) 129 get_64bit_val(wqe, IRDMA_BYTE_24, &offset24); 130 131 offset24 = (offset24) ? 0 : FIELD_PREP(IRDMAQPSQ_VALID, 1); 132 133 set_64bit_val(wqe, IRDMA_BYTE_16, 0); 134 set_64bit_val(wqe, 0, buf->mem.pa); 135 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 136 set_64bit_val(wqe, IRDMA_BYTE_8, 137 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, buf->mem.size)); 138 } else { 139 set_64bit_val(wqe, IRDMA_BYTE_8, 140 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, buf->mem.size) | 141 offset24); 142 } 143 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 144 145 set_64bit_val(wqe, IRDMA_BYTE_24, offset24); 146 } 147 148 /** 149 * irdma_puda_replenish_rq - post rcv buffers 150 * @rsrc: resource to use for buffer 151 * @initial: flag if during init time 152 */ 153 static int 154 irdma_puda_replenish_rq(struct irdma_puda_rsrc *rsrc, bool initial) 155 { 156 u32 i; 157 u32 invalid_cnt = rsrc->rxq_invalid_cnt; 158 struct irdma_puda_buf *buf = NULL; 159 160 for (i = 0; i < invalid_cnt; i++) { 161 buf = irdma_puda_get_bufpool(rsrc); 162 if (!buf) 163 return -ENOBUFS; 164 irdma_puda_post_recvbuf(rsrc, rsrc->rx_wqe_idx, buf, initial); 165 rsrc->rx_wqe_idx = ((rsrc->rx_wqe_idx + 1) % rsrc->rq_size); 166 rsrc->rxq_invalid_cnt--; 167 } 168 169 return 0; 170 } 171 172 /** 173 * irdma_puda_alloc_buf - allocate mem for buffer 174 * @dev: iwarp device 175 * @len: length of buffer 176 */ 177 static struct irdma_puda_buf * 178 irdma_puda_alloc_buf(struct irdma_sc_dev *dev, 179 u32 len) 180 { 181 struct irdma_puda_buf *buf; 182 struct irdma_virt_mem buf_mem; 183 184 buf_mem.size = sizeof(struct irdma_puda_buf); 185 buf_mem.va = kzalloc(buf_mem.size, GFP_KERNEL); 186 if (!buf_mem.va) 187 return NULL; 188 189 buf = buf_mem.va; 190 buf->mem.size = len; 191 buf->mem.va = kzalloc(buf->mem.size, GFP_KERNEL); 192 if (!buf->mem.va) 193 goto free_virt; 194 buf->mem.pa = dma_map_single(hw_to_dev(dev->hw), buf->mem.va, buf->mem.size, DMA_BIDIRECTIONAL); 195 if (dma_mapping_error(hw_to_dev(dev->hw), buf->mem.pa)) { 196 kfree(buf->mem.va); 197 goto free_virt; 198 } 199 200 buf->buf_mem.va = buf_mem.va; 201 buf->buf_mem.size = buf_mem.size; 202 203 return buf; 204 205 free_virt: 206 kfree(buf_mem.va); 207 return NULL; 208 } 209 210 /** 211 * irdma_puda_dele_buf - delete buffer back to system 212 * @dev: iwarp device 213 * @buf: buffer to free 214 */ 215 static void 216 irdma_puda_dele_buf(struct irdma_sc_dev *dev, 217 struct irdma_puda_buf *buf) 218 { 219 if (!buf->virtdma) { 220 irdma_free_dma_mem(dev->hw, &buf->mem); 221 kfree(buf->buf_mem.va); 222 } 223 } 224 225 /** 226 * irdma_puda_get_next_send_wqe - return next wqe for processing 227 * @qp: puda qp for wqe 228 * @wqe_idx: wqe index for caller 229 */ 230 static __le64 * irdma_puda_get_next_send_wqe(struct irdma_qp_uk *qp, 231 u32 *wqe_idx){ 232 int ret_code = 0; 233 234 *wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 235 if (!*wqe_idx) 236 qp->swqe_polarity = !qp->swqe_polarity; 237 IRDMA_RING_MOVE_HEAD(qp->sq_ring, ret_code); 238 if (ret_code) 239 return NULL; 240 241 return qp->sq_base[*wqe_idx].elem; 242 } 243 244 /** 245 * irdma_puda_poll_info - poll cq for completion 246 * @cq: cq for poll 247 * @info: info return for successful completion 248 */ 249 static int 250 irdma_puda_poll_info(struct irdma_sc_cq *cq, 251 struct irdma_puda_cmpl_info *info) 252 { 253 struct irdma_cq_uk *cq_uk = &cq->cq_uk; 254 u64 qword0, qword2, qword3, qword6; 255 __le64 *cqe; 256 __le64 *ext_cqe = NULL; 257 u64 qword7 = 0; 258 u64 comp_ctx; 259 bool valid_bit; 260 bool ext_valid = 0; 261 u32 major_err, minor_err; 262 u32 peek_head; 263 bool error; 264 u8 polarity; 265 266 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&cq->cq_uk); 267 get_64bit_val(cqe, IRDMA_BYTE_24, &qword3); 268 valid_bit = (bool)FIELD_GET(IRDMA_CQ_VALID, qword3); 269 if (valid_bit != cq_uk->polarity) 270 return -ENOENT; 271 272 /* Ensure CQE contents are read after valid bit is checked */ 273 rmb(); 274 275 if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 276 ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); 277 278 if (ext_valid) { 279 peek_head = (cq_uk->cq_ring.head + 1) % cq_uk->cq_ring.size; 280 ext_cqe = cq_uk->cq_base[peek_head].buf; 281 get_64bit_val(ext_cqe, IRDMA_BYTE_24, &qword7); 282 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); 283 if (!peek_head) 284 polarity ^= 1; 285 if (polarity != cq_uk->polarity) 286 return -ENOENT; 287 288 /* Ensure ext CQE contents are read after ext valid bit is checked */ 289 rmb(); 290 291 IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); 292 if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) 293 cq_uk->polarity = !cq_uk->polarity; 294 /* update cq tail in cq shadow memory also */ 295 IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); 296 } 297 298 irdma_debug_buf(cq->dev, IRDMA_DEBUG_PUDA, "PUDA CQE", cqe, 32); 299 if (ext_valid) 300 irdma_debug_buf(cq->dev, IRDMA_DEBUG_PUDA, "PUDA EXT-CQE", 301 ext_cqe, 32); 302 303 error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); 304 if (error) { 305 irdma_debug(cq->dev, IRDMA_DEBUG_PUDA, "receive error\n"); 306 major_err = (u32)(FIELD_GET(IRDMA_CQ_MAJERR, qword3)); 307 minor_err = (u32)(FIELD_GET(IRDMA_CQ_MINERR, qword3)); 308 info->compl_error = major_err << 16 | minor_err; 309 return -EIO; 310 } 311 312 get_64bit_val(cqe, IRDMA_BYTE_0, &qword0); 313 get_64bit_val(cqe, IRDMA_BYTE_16, &qword2); 314 315 info->q_type = (u8)FIELD_GET(IRDMA_CQ_SQ, qword3); 316 info->qp_id = (u32)FIELD_GET(IRDMACQ_QPID, qword2); 317 if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 318 info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); 319 320 get_64bit_val(cqe, IRDMA_BYTE_8, &comp_ctx); 321 info->qp = (struct irdma_qp_uk *)(irdma_uintptr) comp_ctx; 322 info->wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); 323 324 if (info->q_type == IRDMA_CQE_QTYPE_RQ) { 325 if (ext_valid) { 326 info->vlan_valid = (bool)FIELD_GET(IRDMA_CQ_UDVLANVALID, qword7); 327 if (info->vlan_valid) { 328 get_64bit_val(ext_cqe, IRDMA_BYTE_16, &qword6); 329 info->vlan = (u16)FIELD_GET(IRDMA_CQ_UDVLAN, qword6); 330 } 331 info->smac_valid = (bool)FIELD_GET(IRDMA_CQ_UDSMACVALID, qword7); 332 if (info->smac_valid) { 333 get_64bit_val(ext_cqe, IRDMA_BYTE_16, &qword6); 334 info->smac[0] = (u8)((qword6 >> 40) & 0xFF); 335 info->smac[1] = (u8)((qword6 >> 32) & 0xFF); 336 info->smac[2] = (u8)((qword6 >> 24) & 0xFF); 337 info->smac[3] = (u8)((qword6 >> 16) & 0xFF); 338 info->smac[4] = (u8)((qword6 >> 8) & 0xFF); 339 info->smac[5] = (u8)(qword6 & 0xFF); 340 } 341 } 342 343 if (cq->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 344 info->vlan_valid = (bool)FIELD_GET(IRDMA_VLAN_TAG_VALID, qword3); 345 info->l4proto = (u8)FIELD_GET(IRDMA_UDA_L4PROTO, qword2); 346 info->l3proto = (u8)FIELD_GET(IRDMA_UDA_L3PROTO, qword2); 347 } 348 349 info->payload_len = (u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); 350 } 351 352 return 0; 353 } 354 355 /** 356 * irdma_puda_poll_cmpl - processes completion for cq 357 * @dev: iwarp device 358 * @cq: cq getting interrupt 359 * @compl_err: return any completion err 360 */ 361 int 362 irdma_puda_poll_cmpl(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq, 363 u32 *compl_err) 364 { 365 struct irdma_qp_uk *qp; 366 struct irdma_cq_uk *cq_uk = &cq->cq_uk; 367 struct irdma_puda_cmpl_info info = {0}; 368 int ret = 0; 369 struct irdma_puda_buf *buf; 370 struct irdma_puda_rsrc *rsrc; 371 u8 cq_type = cq->cq_type; 372 unsigned long flags; 373 374 if (cq_type == IRDMA_CQ_TYPE_ILQ || cq_type == IRDMA_CQ_TYPE_IEQ) { 375 rsrc = (cq_type == IRDMA_CQ_TYPE_ILQ) ? cq->vsi->ilq : 376 cq->vsi->ieq; 377 } else { 378 irdma_debug(dev, IRDMA_DEBUG_PUDA, "qp_type error\n"); 379 return -EFAULT; 380 } 381 382 ret = irdma_puda_poll_info(cq, &info); 383 *compl_err = info.compl_error; 384 if (ret == -ENOENT) 385 return ret; 386 if (ret) 387 goto done; 388 389 qp = info.qp; 390 if (!qp || !rsrc) { 391 ret = -EFAULT; 392 goto done; 393 } 394 395 if (qp->qp_id != rsrc->qp_id) { 396 ret = -EFAULT; 397 goto done; 398 } 399 400 if (info.q_type == IRDMA_CQE_QTYPE_RQ) { 401 buf = (struct irdma_puda_buf *)(uintptr_t) 402 qp->rq_wrid_array[info.wqe_idx]; 403 404 /* reusing so synch the buffer for CPU use */ 405 dma_sync_single_for_cpu(hw_to_dev(dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 406 /* Get all the tcpip information in the buf header */ 407 ret = irdma_puda_get_tcpip_info(&info, buf); 408 if (ret) { 409 rsrc->stats_rcvd_pkt_err++; 410 if (cq_type == IRDMA_CQ_TYPE_ILQ) { 411 irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, 412 info.wqe_idx); 413 } else { 414 irdma_puda_ret_bufpool(rsrc, buf); 415 irdma_puda_replenish_rq(rsrc, false); 416 } 417 goto done; 418 } 419 420 rsrc->stats_pkt_rcvd++; 421 rsrc->compl_rxwqe_idx = info.wqe_idx; 422 irdma_debug(dev, IRDMA_DEBUG_PUDA, "RQ completion\n"); 423 rsrc->receive(rsrc->vsi, buf); 424 if (cq_type == IRDMA_CQ_TYPE_ILQ) 425 irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, info.wqe_idx); 426 else 427 irdma_puda_replenish_rq(rsrc, false); 428 429 } else { 430 irdma_debug(dev, IRDMA_DEBUG_PUDA, "SQ completion\n"); 431 buf = (struct irdma_puda_buf *)(uintptr_t) 432 qp->sq_wrtrk_array[info.wqe_idx].wrid; 433 434 /* reusing so synch the buffer for CPU use */ 435 dma_sync_single_for_cpu(hw_to_dev(dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 436 IRDMA_RING_SET_TAIL(qp->sq_ring, info.wqe_idx); 437 rsrc->xmit_complete(rsrc->vsi, buf); 438 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 439 rsrc->tx_wqe_avail_cnt++; 440 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 441 if (!list_empty(&rsrc->txpend)) 442 irdma_puda_send_buf(rsrc, NULL); 443 } 444 445 done: 446 IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); 447 if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) 448 cq_uk->polarity = !cq_uk->polarity; 449 /* update cq tail in cq shadow memory also */ 450 IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); 451 set_64bit_val(cq_uk->shadow_area, IRDMA_BYTE_0, 452 IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)); 453 454 return ret; 455 } 456 457 /** 458 * irdma_puda_send - complete send wqe for transmit 459 * @qp: puda qp for send 460 * @info: buffer information for transmit 461 */ 462 int 463 irdma_puda_send(struct irdma_sc_qp *qp, struct irdma_puda_send_info *info) 464 { 465 __le64 *wqe; 466 u32 iplen, l4len; 467 u64 hdr[2]; 468 u32 wqe_idx; 469 u8 iipt; 470 471 /* number of 32 bits DWORDS in header */ 472 l4len = info->tcplen >> 2; 473 if (info->ipv4) { 474 iipt = 3; 475 iplen = 5; 476 } else { 477 iipt = 1; 478 iplen = 10; 479 } 480 481 wqe = irdma_puda_get_next_send_wqe(&qp->qp_uk, &wqe_idx); 482 if (!wqe) 483 return -ENOSPC; 484 485 qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid = (uintptr_t)info->scratch; 486 /* Third line of WQE descriptor */ 487 /* maclen is in words */ 488 489 if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 490 hdr[0] = 0; /* Dest_QPN and Dest_QKey only for UD */ 491 hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | 492 FIELD_PREP(IRDMA_UDA_QPSQ_L4LEN, l4len) | 493 FIELD_PREP(IRDMAQPSQ_AHID, info->ah_id) | 494 FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | 495 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, 496 qp->qp_uk.swqe_polarity); 497 498 /* Forth line of WQE descriptor */ 499 500 set_64bit_val(wqe, IRDMA_BYTE_0, info->paddr); 501 set_64bit_val(wqe, IRDMA_BYTE_8, 502 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, info->len) | 503 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity)); 504 } else { 505 hdr[0] = FIELD_PREP(IRDMA_UDA_QPSQ_MACLEN, info->maclen >> 1) | 506 FIELD_PREP(IRDMA_UDA_QPSQ_IPLEN, iplen) | 507 FIELD_PREP(IRDMA_UDA_QPSQ_L4T, 1) | 508 FIELD_PREP(IRDMA_UDA_QPSQ_IIPT, iipt) | 509 FIELD_PREP(IRDMA_GEN1_UDA_QPSQ_L4LEN, l4len); 510 511 hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | 512 FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | 513 FIELD_PREP(IRDMA_UDA_QPSQ_DOLOOPBACK, info->do_lpb) | 514 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity); 515 516 /* Forth line of WQE descriptor */ 517 518 set_64bit_val(wqe, IRDMA_BYTE_0, info->paddr); 519 set_64bit_val(wqe, IRDMA_BYTE_8, 520 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, info->len)); 521 } 522 523 set_64bit_val(wqe, IRDMA_BYTE_16, hdr[0]); 524 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 525 526 set_64bit_val(wqe, IRDMA_BYTE_24, hdr[1]); 527 528 irdma_debug_buf(qp->dev, IRDMA_DEBUG_PUDA, "PUDA SEND WQE", wqe, 32); 529 irdma_uk_qp_post_wr(&qp->qp_uk); 530 return 0; 531 } 532 533 /** 534 * irdma_puda_send_buf - transmit puda buffer 535 * @rsrc: resource to use for buffer 536 * @buf: puda buffer to transmit 537 */ 538 void 539 irdma_puda_send_buf(struct irdma_puda_rsrc *rsrc, 540 struct irdma_puda_buf *buf) 541 { 542 struct irdma_puda_send_info info; 543 int ret = 0; 544 unsigned long flags; 545 546 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 547 /* 548 * if no wqe available or not from a completion and we have pending buffers, we must queue new buffer 549 */ 550 if (!rsrc->tx_wqe_avail_cnt || (buf && !list_empty(&rsrc->txpend))) { 551 list_add_tail(&buf->list, &rsrc->txpend); 552 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 553 rsrc->stats_sent_pkt_q++; 554 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 555 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 556 "adding to txpend\n"); 557 return; 558 } 559 rsrc->tx_wqe_avail_cnt--; 560 /* 561 * if we are coming from a completion and have pending buffers then Get one from pending list 562 */ 563 if (!buf) { 564 buf = irdma_puda_get_listbuf(&rsrc->txpend); 565 if (!buf) 566 goto done; 567 } 568 569 info.scratch = buf; 570 info.paddr = buf->mem.pa; 571 info.len = buf->totallen; 572 info.tcplen = buf->tcphlen; 573 info.ipv4 = buf->ipv4; 574 575 if (rsrc->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 576 info.ah_id = buf->ah_id; 577 } else { 578 info.maclen = buf->maclen; 579 info.do_lpb = buf->do_lpb; 580 } 581 582 /* Synch buffer for use by device */ 583 dma_sync_single_for_cpu(hw_to_dev(rsrc->dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 584 ret = irdma_puda_send(&rsrc->qp, &info); 585 if (ret) { 586 rsrc->tx_wqe_avail_cnt++; 587 rsrc->stats_sent_pkt_q++; 588 list_add(&buf->list, &rsrc->txpend); 589 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 590 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 591 "adding to puda_send\n"); 592 } else { 593 rsrc->stats_pkt_sent++; 594 } 595 done: 596 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 597 } 598 599 /** 600 * irdma_puda_qp_setctx - during init, set qp's context 601 * @rsrc: qp's resource 602 */ 603 static void 604 irdma_puda_qp_setctx(struct irdma_puda_rsrc *rsrc) 605 { 606 struct irdma_sc_qp *qp = &rsrc->qp; 607 __le64 *qp_ctx = qp->hw_host_ctx; 608 609 set_64bit_val(qp_ctx, IRDMA_BYTE_8, qp->sq_pa); 610 set_64bit_val(qp_ctx, IRDMA_BYTE_16, qp->rq_pa); 611 set_64bit_val(qp_ctx, IRDMA_BYTE_24, 612 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 613 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size)); 614 set_64bit_val(qp_ctx, IRDMA_BYTE_48, 615 FIELD_PREP(IRDMAQPC_SNDMSS, rsrc->buf_size)); 616 set_64bit_val(qp_ctx, IRDMA_BYTE_56, 0); 617 if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 618 set_64bit_val(qp_ctx, IRDMA_BYTE_64, 1); 619 set_64bit_val(qp_ctx, IRDMA_BYTE_136, 620 FIELD_PREP(IRDMAQPC_TXCQNUM, rsrc->cq_id) | 621 FIELD_PREP(IRDMAQPC_RXCQNUM, rsrc->cq_id)); 622 set_64bit_val(qp_ctx, IRDMA_BYTE_144, 623 FIELD_PREP(IRDMAQPC_STAT_INDEX, rsrc->stats_idx)); 624 set_64bit_val(qp_ctx, IRDMA_BYTE_160, 625 FIELD_PREP(IRDMAQPC_PRIVEN, 1) | 626 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, rsrc->stats_idx_valid)); 627 set_64bit_val(qp_ctx, IRDMA_BYTE_168, 628 FIELD_PREP(IRDMAQPC_QPCOMPCTX, (uintptr_t)qp)); 629 set_64bit_val(qp_ctx, IRDMA_BYTE_176, 630 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 631 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 632 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 633 634 irdma_debug_buf(rsrc->dev, IRDMA_DEBUG_PUDA, "PUDA QP CONTEXT", qp_ctx, 635 IRDMA_QP_CTX_SIZE); 636 } 637 638 /** 639 * irdma_puda_qp_wqe - setup wqe for qp create 640 * @dev: Device 641 * @qp: Resource qp 642 */ 643 static int 644 irdma_puda_qp_wqe(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp) 645 { 646 struct irdma_sc_cqp *cqp; 647 __le64 *wqe; 648 u64 hdr; 649 struct irdma_ccq_cqe_info compl_info; 650 int status = 0; 651 652 cqp = dev->cqp; 653 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); 654 if (!wqe) 655 return -ENOSPC; 656 657 set_64bit_val(wqe, IRDMA_BYTE_16, qp->hw_host_ctx_pa); 658 set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa); 659 660 hdr = qp->qp_uk.qp_id | 661 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | 662 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, IRDMA_QP_TYPE_UDA) | 663 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, 1) | 664 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, 2) | 665 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 666 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 667 668 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 669 670 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_PUDA, "PUDA QP CREATE", wqe, 40); 671 irdma_sc_cqp_post_sq(cqp); 672 status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_QP, 673 &compl_info); 674 675 return status; 676 } 677 678 /** 679 * irdma_puda_qp_create - create qp for resource 680 * @rsrc: resource to use for buffer 681 */ 682 static int 683 irdma_puda_qp_create(struct irdma_puda_rsrc *rsrc) 684 { 685 struct irdma_sc_qp *qp = &rsrc->qp; 686 struct irdma_qp_uk *ukqp = &qp->qp_uk; 687 int ret = 0; 688 u32 sq_size, rq_size; 689 struct irdma_dma_mem *mem; 690 691 sq_size = rsrc->sq_size * IRDMA_QP_WQE_MIN_SIZE; 692 rq_size = rsrc->rq_size * IRDMA_QP_WQE_MIN_SIZE; 693 rsrc->qpmem.size = (sq_size + rq_size + (IRDMA_SHADOW_AREA_SIZE << 3) + 694 IRDMA_QP_CTX_SIZE); 695 rsrc->qpmem.va = irdma_allocate_dma_mem(rsrc->dev->hw, &rsrc->qpmem, 696 rsrc->qpmem.size, IRDMA_HW_PAGE_SIZE); 697 if (!rsrc->qpmem.va) 698 return -ENOMEM; 699 700 mem = &rsrc->qpmem; 701 memset(mem->va, 0, rsrc->qpmem.size); 702 qp->hw_sq_size = irdma_get_encoded_wqe_size(rsrc->sq_size, IRDMA_QUEUE_TYPE_SQ_RQ); 703 qp->hw_rq_size = irdma_get_encoded_wqe_size(rsrc->rq_size, IRDMA_QUEUE_TYPE_SQ_RQ); 704 qp->pd = &rsrc->sc_pd; 705 qp->qp_uk.qp_type = IRDMA_QP_TYPE_UDA; 706 qp->dev = rsrc->dev; 707 qp->qp_uk.back_qp = rsrc; 708 qp->sq_pa = mem->pa; 709 qp->rq_pa = qp->sq_pa + sq_size; 710 qp->vsi = rsrc->vsi; 711 ukqp->sq_base = mem->va; 712 ukqp->rq_base = &ukqp->sq_base[rsrc->sq_size]; 713 ukqp->shadow_area = ukqp->rq_base[rsrc->rq_size].elem; 714 ukqp->uk_attrs = &qp->dev->hw_attrs.uk_attrs; 715 qp->shadow_area_pa = qp->rq_pa + rq_size; 716 qp->hw_host_ctx = ukqp->shadow_area + IRDMA_SHADOW_AREA_SIZE; 717 qp->hw_host_ctx_pa = qp->shadow_area_pa + (IRDMA_SHADOW_AREA_SIZE << 3); 718 qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; 719 ukqp->qp_id = rsrc->qp_id; 720 ukqp->sq_wrtrk_array = rsrc->sq_wrtrk_array; 721 ukqp->rq_wrid_array = rsrc->rq_wrid_array; 722 ukqp->sq_size = rsrc->sq_size; 723 ukqp->rq_size = rsrc->rq_size; 724 725 IRDMA_RING_INIT(ukqp->sq_ring, ukqp->sq_size); 726 IRDMA_RING_INIT(ukqp->initial_ring, ukqp->sq_size); 727 IRDMA_RING_INIT(ukqp->rq_ring, ukqp->rq_size); 728 ukqp->wqe_alloc_db = qp->pd->dev->wqe_alloc_db; 729 730 ret = rsrc->dev->ws_add(qp->vsi, qp->user_pri); 731 if (ret) { 732 irdma_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem); 733 return ret; 734 } 735 736 irdma_qp_add_qos(qp); 737 irdma_puda_qp_setctx(rsrc); 738 739 if (rsrc->dev->ceq_valid) 740 ret = irdma_cqp_qp_create_cmd(rsrc->dev, qp); 741 else 742 ret = irdma_puda_qp_wqe(rsrc->dev, qp); 743 if (ret) { 744 irdma_qp_rem_qos(qp); 745 rsrc->dev->ws_remove(qp->vsi, qp->user_pri); 746 irdma_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem); 747 } 748 749 return ret; 750 } 751 752 /** 753 * irdma_puda_cq_wqe - setup wqe for CQ create 754 * @dev: Device 755 * @cq: resource for cq 756 */ 757 static int 758 irdma_puda_cq_wqe(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq) 759 { 760 __le64 *wqe; 761 struct irdma_sc_cqp *cqp; 762 u64 hdr; 763 struct irdma_ccq_cqe_info compl_info; 764 int status = 0; 765 766 cqp = dev->cqp; 767 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); 768 if (!wqe) 769 return -ENOSPC; 770 771 set_64bit_val(wqe, IRDMA_BYTE_0, cq->cq_uk.cq_size); 772 set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1)); 773 set_64bit_val(wqe, IRDMA_BYTE_16, 774 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold)); 775 set_64bit_val(wqe, IRDMA_BYTE_32, cq->cq_pa); 776 set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa); 777 set_64bit_val(wqe, IRDMA_BYTE_56, 778 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 779 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 780 781 hdr = cq->cq_uk.cq_id | 782 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | 783 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, 1) | 784 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, 1) | 785 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, 1) | 786 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 787 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 788 789 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 790 791 irdma_debug_buf(dev, IRDMA_DEBUG_PUDA, "PUDA CREATE CQ", wqe, 792 IRDMA_CQP_WQE_SIZE * 8); 793 irdma_sc_cqp_post_sq(dev->cqp); 794 status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_CQ, 795 &compl_info); 796 if (!status) { 797 struct irdma_sc_ceq *ceq = dev->ceq[0]; 798 799 if (ceq && ceq->reg_cq) 800 status = irdma_sc_add_cq_ctx(ceq, cq); 801 } 802 803 return status; 804 } 805 806 /** 807 * irdma_puda_cq_create - create cq for resource 808 * @rsrc: resource for which cq to create 809 */ 810 static int 811 irdma_puda_cq_create(struct irdma_puda_rsrc *rsrc) 812 { 813 struct irdma_sc_dev *dev = rsrc->dev; 814 struct irdma_sc_cq *cq = &rsrc->cq; 815 int ret = 0; 816 u32 cqsize; 817 struct irdma_dma_mem *mem; 818 struct irdma_cq_init_info info = {0}; 819 struct irdma_cq_uk_init_info *init_info = &info.cq_uk_init_info; 820 821 cq->vsi = rsrc->vsi; 822 cqsize = rsrc->cq_size * (sizeof(struct irdma_cqe)); 823 rsrc->cqmem.size = cqsize + sizeof(struct irdma_cq_shadow_area); 824 rsrc->cqmem.va = irdma_allocate_dma_mem(dev->hw, &rsrc->cqmem, 825 rsrc->cqmem.size, 826 IRDMA_CQ0_ALIGNMENT); 827 if (!rsrc->cqmem.va) 828 return -ENOMEM; 829 830 mem = &rsrc->cqmem; 831 info.dev = dev; 832 info.type = (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) ? 833 IRDMA_CQ_TYPE_ILQ : IRDMA_CQ_TYPE_IEQ; 834 info.shadow_read_threshold = rsrc->cq_size >> 2; 835 info.cq_base_pa = mem->pa; 836 info.shadow_area_pa = mem->pa + cqsize; 837 init_info->cq_base = mem->va; 838 init_info->shadow_area = (__le64 *) ((u8 *)mem->va + cqsize); 839 init_info->cq_size = rsrc->cq_size; 840 init_info->cq_id = rsrc->cq_id; 841 info.ceqe_mask = true; 842 info.ceq_id_valid = true; 843 info.vsi = rsrc->vsi; 844 845 ret = irdma_sc_cq_init(cq, &info); 846 if (ret) 847 goto error; 848 849 if (rsrc->dev->ceq_valid) 850 ret = irdma_cqp_cq_create_cmd(dev, cq); 851 else 852 ret = irdma_puda_cq_wqe(dev, cq); 853 error: 854 if (ret) 855 irdma_free_dma_mem(dev->hw, &rsrc->cqmem); 856 857 return ret; 858 } 859 860 /** 861 * irdma_puda_free_qp - free qp for resource 862 * @rsrc: resource for which qp to free 863 */ 864 static void 865 irdma_puda_free_qp(struct irdma_puda_rsrc *rsrc) 866 { 867 int ret; 868 struct irdma_ccq_cqe_info compl_info; 869 struct irdma_sc_dev *dev = rsrc->dev; 870 871 if (rsrc->dev->ceq_valid) { 872 irdma_cqp_qp_destroy_cmd(dev, &rsrc->qp); 873 rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); 874 return; 875 } 876 877 ret = irdma_sc_qp_destroy(&rsrc->qp, 0, false, true, true); 878 if (ret) 879 irdma_debug(dev, IRDMA_DEBUG_PUDA, 880 "error puda qp destroy wqe, status = %d\n", ret); 881 if (!ret) { 882 ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_QP, 883 &compl_info); 884 if (ret) 885 irdma_debug(dev, IRDMA_DEBUG_PUDA, 886 "error puda qp destroy failed, status = %d\n", 887 ret); 888 } 889 rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); 890 } 891 892 /** 893 * irdma_puda_free_cq - free cq for resource 894 * @rsrc: resource for which cq to free 895 */ 896 static void 897 irdma_puda_free_cq(struct irdma_puda_rsrc *rsrc) 898 { 899 int ret; 900 struct irdma_ccq_cqe_info compl_info; 901 struct irdma_sc_dev *dev = rsrc->dev; 902 903 if (rsrc->dev->ceq_valid) { 904 irdma_cqp_cq_destroy_cmd(dev, &rsrc->cq); 905 return; 906 } 907 908 ret = irdma_sc_cq_destroy(&rsrc->cq, 0, true); 909 if (ret) 910 irdma_debug(dev, IRDMA_DEBUG_PUDA, "error ieq cq destroy\n"); 911 if (!ret) { 912 ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_CQ, 913 &compl_info); 914 if (ret) 915 irdma_debug(dev, IRDMA_DEBUG_PUDA, 916 "error ieq qp destroy done\n"); 917 } 918 } 919 920 /** 921 * irdma_puda_dele_rsrc - delete all resources during close 922 * @vsi: VSI structure of device 923 * @type: type of resource to dele 924 * @reset: true if reset chip 925 */ 926 void 927 irdma_puda_dele_rsrc(struct irdma_sc_vsi *vsi, enum puda_rsrc_type type, 928 bool reset) 929 { 930 struct irdma_sc_dev *dev = vsi->dev; 931 struct irdma_puda_rsrc *rsrc; 932 struct irdma_puda_buf *buf = NULL; 933 struct irdma_puda_buf *nextbuf = NULL; 934 struct irdma_virt_mem *vmem; 935 struct irdma_sc_ceq *ceq; 936 937 ceq = vsi->dev->ceq[0]; 938 switch (type) { 939 case IRDMA_PUDA_RSRC_TYPE_ILQ: 940 rsrc = vsi->ilq; 941 vmem = &vsi->ilq_mem; 942 vsi->ilq = NULL; 943 if (ceq && ceq->reg_cq) 944 irdma_sc_remove_cq_ctx(ceq, &rsrc->cq); 945 break; 946 case IRDMA_PUDA_RSRC_TYPE_IEQ: 947 rsrc = vsi->ieq; 948 vmem = &vsi->ieq_mem; 949 vsi->ieq = NULL; 950 if (ceq && ceq->reg_cq) 951 irdma_sc_remove_cq_ctx(ceq, &rsrc->cq); 952 break; 953 default: 954 irdma_debug(dev, IRDMA_DEBUG_PUDA, 955 "error resource type = 0x%x\n", type); 956 return; 957 } 958 959 spin_lock_destroy(&rsrc->bufpool_lock); 960 switch (rsrc->cmpl) { 961 case PUDA_HASH_CRC_COMPLETE: 962 irdma_free_hash_desc(rsrc->hash_desc); 963 /* fallthrough */ 964 case PUDA_QP_CREATED: 965 irdma_qp_rem_qos(&rsrc->qp); 966 967 if (!reset) 968 irdma_puda_free_qp(rsrc); 969 970 irdma_free_dma_mem(dev->hw, &rsrc->qpmem); 971 /* fallthrough */ 972 case PUDA_CQ_CREATED: 973 if (!reset) 974 irdma_puda_free_cq(rsrc); 975 976 irdma_free_dma_mem(dev->hw, &rsrc->cqmem); 977 break; 978 default: 979 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 980 "error no resources\n"); 981 break; 982 } 983 /* Free all allocated puda buffers for both tx and rx */ 984 buf = rsrc->alloclist; 985 while (buf) { 986 nextbuf = buf->next; 987 irdma_puda_dele_buf(dev, buf); 988 buf = nextbuf; 989 rsrc->alloc_buf_count--; 990 } 991 992 kfree(vmem->va); 993 } 994 995 /** 996 * irdma_puda_allocbufs - allocate buffers for resource 997 * @rsrc: resource for buffer allocation 998 * @count: number of buffers to create 999 */ 1000 static int 1001 irdma_puda_allocbufs(struct irdma_puda_rsrc *rsrc, u32 count) 1002 { 1003 u32 i; 1004 struct irdma_puda_buf *buf; 1005 struct irdma_puda_buf *nextbuf; 1006 struct irdma_virt_mem buf_mem; 1007 struct irdma_dma_mem *dma_mem; 1008 bool virtdma = false; 1009 unsigned long flags; 1010 1011 buf_mem.size = count * sizeof(struct irdma_puda_buf); 1012 buf_mem.va = kzalloc(buf_mem.size, GFP_KERNEL); 1013 if (!buf_mem.va) { 1014 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 1015 "error virt_mem for buf\n"); 1016 rsrc->stats_buf_alloc_fail++; 1017 goto trysmall; 1018 } 1019 1020 /* 1021 * Allocate the large dma chunk and setup dma attributes into first puda buffer. This is required during free 1022 */ 1023 buf = (struct irdma_puda_buf *)buf_mem.va; 1024 buf->mem.va = irdma_allocate_dma_mem(rsrc->dev->hw, &buf->mem, 1025 rsrc->buf_size * count, 1); 1026 if (!buf->mem.va) { 1027 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 1028 "error dma_mem for buf\n"); 1029 kfree(buf_mem.va); 1030 rsrc->stats_buf_alloc_fail++; 1031 goto trysmall; 1032 } 1033 1034 /* 1035 * dma_mem points to start of the large DMA chunk 1036 */ 1037 dma_mem = &buf->mem; 1038 1039 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 1040 for (i = 0; i < count; i++) { 1041 buf = ((struct irdma_puda_buf *)buf_mem.va) + i; 1042 1043 buf->mem.va = (char *)dma_mem->va + (i * rsrc->buf_size); 1044 buf->mem.pa = dma_mem->pa + (i * rsrc->buf_size); 1045 buf->mem.size = rsrc->buf_size; 1046 buf->virtdma = virtdma; 1047 virtdma = true; 1048 1049 buf->buf_mem.va = buf_mem.va; 1050 buf->buf_mem.size = buf_mem.size; 1051 1052 list_add(&buf->list, &rsrc->bufpool); 1053 rsrc->alloc_buf_count++; 1054 if (!rsrc->alloclist) { 1055 rsrc->alloclist = buf; 1056 } else { 1057 nextbuf = rsrc->alloclist; 1058 rsrc->alloclist = buf; 1059 buf->next = nextbuf; 1060 } 1061 } 1062 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 1063 1064 rsrc->avail_buf_count = rsrc->alloc_buf_count; 1065 return 0; 1066 trysmall: 1067 for (i = 0; i < count; i++) { 1068 buf = irdma_puda_alloc_buf(rsrc->dev, rsrc->buf_size); 1069 if (!buf) { 1070 rsrc->stats_buf_alloc_fail++; 1071 return -ENOMEM; 1072 } 1073 irdma_puda_ret_bufpool(rsrc, buf); 1074 rsrc->alloc_buf_count++; 1075 if (!rsrc->alloclist) { 1076 rsrc->alloclist = buf; 1077 } else { 1078 nextbuf = rsrc->alloclist; 1079 rsrc->alloclist = buf; 1080 buf->next = nextbuf; 1081 } 1082 } 1083 1084 rsrc->avail_buf_count = rsrc->alloc_buf_count; 1085 1086 return 0; 1087 } 1088 1089 /** 1090 * irdma_puda_create_rsrc - create resource (ilq or ieq) 1091 * @vsi: sc VSI struct 1092 * @info: resource information 1093 */ 1094 int 1095 irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi, 1096 struct irdma_puda_rsrc_info *info) 1097 { 1098 struct irdma_sc_dev *dev = vsi->dev; 1099 int ret = 0; 1100 struct irdma_puda_rsrc *rsrc; 1101 u32 pudasize; 1102 u32 sqwridsize, rqwridsize; 1103 struct irdma_virt_mem *vmem; 1104 1105 info->count = 1; 1106 pudasize = sizeof(struct irdma_puda_rsrc); 1107 sqwridsize = info->sq_size * sizeof(struct irdma_sq_uk_wr_trk_info); 1108 rqwridsize = info->rq_size * 8; 1109 switch (info->type) { 1110 case IRDMA_PUDA_RSRC_TYPE_ILQ: 1111 vmem = &vsi->ilq_mem; 1112 break; 1113 case IRDMA_PUDA_RSRC_TYPE_IEQ: 1114 vmem = &vsi->ieq_mem; 1115 break; 1116 default: 1117 return -EOPNOTSUPP; 1118 } 1119 vmem->size = pudasize + sqwridsize + rqwridsize; 1120 vmem->va = kzalloc(vmem->size, GFP_KERNEL); 1121 if (!vmem->va) 1122 return -ENOMEM; 1123 1124 rsrc = vmem->va; 1125 spin_lock_init(&rsrc->bufpool_lock); 1126 switch (info->type) { 1127 case IRDMA_PUDA_RSRC_TYPE_ILQ: 1128 vsi->ilq = vmem->va; 1129 vsi->ilq_count = info->count; 1130 rsrc->receive = info->receive; 1131 rsrc->xmit_complete = info->xmit_complete; 1132 break; 1133 case IRDMA_PUDA_RSRC_TYPE_IEQ: 1134 vsi->ieq_count = info->count; 1135 vsi->ieq = vmem->va; 1136 rsrc->receive = irdma_ieq_receive; 1137 rsrc->xmit_complete = irdma_ieq_tx_compl; 1138 break; 1139 default: 1140 return -EOPNOTSUPP; 1141 } 1142 1143 rsrc->type = info->type; 1144 rsrc->sq_wrtrk_array = (struct irdma_sq_uk_wr_trk_info *) 1145 ((u8 *)vmem->va + pudasize); 1146 rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize); 1147 /* Initialize all ieq lists */ 1148 INIT_LIST_HEAD(&rsrc->bufpool); 1149 INIT_LIST_HEAD(&rsrc->txpend); 1150 1151 rsrc->tx_wqe_avail_cnt = info->sq_size - 1; 1152 irdma_sc_pd_init(dev, &rsrc->sc_pd, info->pd_id, info->abi_ver); 1153 rsrc->qp_id = info->qp_id; 1154 rsrc->cq_id = info->cq_id; 1155 rsrc->sq_size = info->sq_size; 1156 rsrc->rq_size = info->rq_size; 1157 rsrc->cq_size = info->rq_size + info->sq_size; 1158 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1159 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 1160 rsrc->cq_size += info->rq_size; 1161 } 1162 rsrc->buf_size = info->buf_size; 1163 rsrc->dev = dev; 1164 rsrc->vsi = vsi; 1165 rsrc->stats_idx = info->stats_idx; 1166 rsrc->stats_idx_valid = info->stats_idx_valid; 1167 1168 ret = irdma_puda_cq_create(rsrc); 1169 if (!ret) { 1170 rsrc->cmpl = PUDA_CQ_CREATED; 1171 ret = irdma_puda_qp_create(rsrc); 1172 } 1173 if (ret) { 1174 irdma_debug(dev, IRDMA_DEBUG_PUDA, 1175 "error qp_create type=%d, status=%d\n", rsrc->type, 1176 ret); 1177 goto error; 1178 } 1179 rsrc->cmpl = PUDA_QP_CREATED; 1180 1181 ret = irdma_puda_allocbufs(rsrc, info->tx_buf_cnt + info->rq_size); 1182 if (ret) { 1183 irdma_debug(dev, IRDMA_DEBUG_PUDA, "error alloc_buf\n"); 1184 goto error; 1185 } 1186 1187 rsrc->rxq_invalid_cnt = info->rq_size; 1188 ret = irdma_puda_replenish_rq(rsrc, true); 1189 if (ret) 1190 goto error; 1191 1192 if (info->type == IRDMA_PUDA_RSRC_TYPE_IEQ) { 1193 if (!irdma_init_hash_desc(&rsrc->hash_desc)) { 1194 rsrc->check_crc = true; 1195 rsrc->cmpl = PUDA_HASH_CRC_COMPLETE; 1196 ret = 0; 1197 } 1198 } 1199 1200 irdma_sc_ccq_arm(&rsrc->cq); 1201 return ret; 1202 1203 error: 1204 irdma_puda_dele_rsrc(vsi, info->type, false); 1205 1206 return ret; 1207 } 1208 1209 /** 1210 * irdma_ilq_putback_rcvbuf - ilq buffer to put back on rq 1211 * @qp: ilq's qp resource 1212 * @buf: puda buffer for rcv q 1213 * @wqe_idx: wqe index of completed rcvbuf 1214 */ 1215 static void 1216 irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, 1217 struct irdma_puda_buf *buf, u32 wqe_idx) 1218 { 1219 __le64 *wqe; 1220 u64 offset8, offset24; 1221 1222 /* Synch buffer for use by device */ 1223 dma_sync_single_for_device(hw_to_dev(qp->dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 1224 wqe = qp->qp_uk.rq_base[wqe_idx].elem; 1225 get_64bit_val(wqe, IRDMA_BYTE_24, &offset24); 1226 if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1227 get_64bit_val(wqe, IRDMA_BYTE_8, &offset8); 1228 if (offset24) 1229 offset8 &= ~FIELD_PREP(IRDMAQPSQ_VALID, 1); 1230 else 1231 offset8 |= FIELD_PREP(IRDMAQPSQ_VALID, 1); 1232 set_64bit_val(wqe, IRDMA_BYTE_8, offset8); 1233 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 1234 } 1235 if (offset24) 1236 offset24 = 0; 1237 else 1238 offset24 = FIELD_PREP(IRDMAQPSQ_VALID, 1); 1239 1240 set_64bit_val(wqe, IRDMA_BYTE_24, offset24); 1241 } 1242 1243 /** 1244 * irdma_ieq_get_fpdu_len - get length of fpdu with or without marker 1245 * @pfpdu: pointer to fpdu 1246 * @datap: pointer to data in the buffer 1247 * @rcv_seq: seqnum of the data buffer 1248 */ 1249 static u16 irdma_ieq_get_fpdu_len(struct irdma_pfpdu *pfpdu, u8 *datap, 1250 u32 rcv_seq){ 1251 u32 marker_seq, end_seq, blk_start; 1252 u8 marker_len = pfpdu->marker_len; 1253 u16 total_len = 0; 1254 u16 fpdu_len; 1255 1256 blk_start = (pfpdu->rcv_start_seq - rcv_seq) & (IRDMA_MRK_BLK_SZ - 1); 1257 if (!blk_start) { 1258 total_len = marker_len; 1259 marker_seq = rcv_seq + IRDMA_MRK_BLK_SZ; 1260 if (marker_len && *(u32 *)datap) 1261 return 0; 1262 } else { 1263 marker_seq = rcv_seq + blk_start; 1264 } 1265 1266 datap += total_len; 1267 fpdu_len = IRDMA_NTOHS(*(__be16 *) datap); 1268 fpdu_len += IRDMA_IEQ_MPA_FRAMING; 1269 fpdu_len = (fpdu_len + 3) & 0xfffc; 1270 1271 if (fpdu_len > pfpdu->max_fpdu_data) 1272 return 0; 1273 1274 total_len += fpdu_len; 1275 end_seq = rcv_seq + total_len; 1276 while ((int)(marker_seq - end_seq) < 0) { 1277 total_len += marker_len; 1278 end_seq += marker_len; 1279 marker_seq += IRDMA_MRK_BLK_SZ; 1280 } 1281 1282 return total_len; 1283 } 1284 1285 /** 1286 * irdma_ieq_copy_to_txbuf - copydata from rcv buf to tx buf 1287 * @buf: rcv buffer with partial 1288 * @txbuf: tx buffer for sending back 1289 * @buf_offset: rcv buffer offset to copy from 1290 * @txbuf_offset: at offset in tx buf to copy 1291 * @len: length of data to copy 1292 */ 1293 static void 1294 irdma_ieq_copy_to_txbuf(struct irdma_puda_buf *buf, 1295 struct irdma_puda_buf *txbuf, 1296 u16 buf_offset, u32 txbuf_offset, u32 len) 1297 { 1298 void *mem1 = (u8 *)buf->mem.va + buf_offset; 1299 void *mem2 = (u8 *)txbuf->mem.va + txbuf_offset; 1300 1301 irdma_memcpy(mem2, mem1, len); 1302 } 1303 1304 /** 1305 * irdma_ieq_setup_tx_buf - setup tx buffer for partial handling 1306 * @buf: reeive buffer with partial 1307 * @txbuf: buffer to prepare 1308 */ 1309 static void 1310 irdma_ieq_setup_tx_buf(struct irdma_puda_buf *buf, 1311 struct irdma_puda_buf *txbuf) 1312 { 1313 txbuf->tcphlen = buf->tcphlen; 1314 txbuf->ipv4 = buf->ipv4; 1315 1316 if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1317 txbuf->hdrlen = txbuf->tcphlen; 1318 irdma_ieq_copy_to_txbuf(buf, txbuf, IRDMA_TCP_OFFSET, 0, 1319 txbuf->hdrlen); 1320 } else { 1321 txbuf->maclen = buf->maclen; 1322 txbuf->hdrlen = buf->hdrlen; 1323 irdma_ieq_copy_to_txbuf(buf, txbuf, 0, 0, buf->hdrlen); 1324 } 1325 } 1326 1327 /** 1328 * irdma_ieq_check_first_buf - check if rcv buffer's seq is in range 1329 * @buf: receive exception buffer 1330 * @fps: first partial sequence number 1331 */ 1332 static void 1333 irdma_ieq_check_first_buf(struct irdma_puda_buf *buf, u32 fps) 1334 { 1335 u32 offset; 1336 1337 if (buf->seqnum < fps) { 1338 offset = fps - buf->seqnum; 1339 if (offset > buf->datalen) 1340 return; 1341 buf->data += offset; 1342 buf->datalen -= (u16)offset; 1343 buf->seqnum = fps; 1344 } 1345 } 1346 1347 /** 1348 * irdma_ieq_compl_pfpdu - write txbuf with full fpdu 1349 * @ieq: ieq resource 1350 * @rxlist: ieq's received buffer list 1351 * @pbufl: temporary list for buffers for fpddu 1352 * @txbuf: tx buffer for fpdu 1353 * @fpdu_len: total length of fpdu 1354 */ 1355 static void 1356 irdma_ieq_compl_pfpdu(struct irdma_puda_rsrc *ieq, 1357 struct list_head *rxlist, 1358 struct list_head *pbufl, 1359 struct irdma_puda_buf *txbuf, u16 fpdu_len) 1360 { 1361 struct irdma_puda_buf *buf; 1362 u32 nextseqnum; 1363 u16 txoffset, bufoffset; 1364 1365 buf = irdma_puda_get_listbuf(pbufl); 1366 if (!buf) 1367 return; 1368 1369 nextseqnum = buf->seqnum + fpdu_len; 1370 irdma_ieq_setup_tx_buf(buf, txbuf); 1371 if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1372 txoffset = txbuf->hdrlen; 1373 txbuf->totallen = txbuf->hdrlen + fpdu_len; 1374 txbuf->data = (u8 *)txbuf->mem.va + txoffset; 1375 } else { 1376 txoffset = buf->hdrlen; 1377 txbuf->totallen = buf->hdrlen + fpdu_len; 1378 txbuf->data = (u8 *)txbuf->mem.va + buf->hdrlen; 1379 } 1380 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); 1381 1382 do { 1383 if (buf->datalen >= fpdu_len) { 1384 /* copied full fpdu */ 1385 irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, 1386 fpdu_len); 1387 buf->datalen -= fpdu_len; 1388 buf->data += fpdu_len; 1389 buf->seqnum = nextseqnum; 1390 break; 1391 } 1392 /* copy partial fpdu */ 1393 irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, 1394 buf->datalen); 1395 txoffset += buf->datalen; 1396 fpdu_len -= buf->datalen; 1397 irdma_puda_ret_bufpool(ieq, buf); 1398 buf = irdma_puda_get_listbuf(pbufl); 1399 if (!buf) 1400 return; 1401 1402 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); 1403 } while (1); 1404 1405 /* last buffer on the list */ 1406 if (buf->datalen) 1407 list_add(&buf->list, rxlist); 1408 else 1409 irdma_puda_ret_bufpool(ieq, buf); 1410 } 1411 1412 /** 1413 * irdma_ieq_create_pbufl - create buffer list for single fpdu 1414 * @pfpdu: pointer to fpdu 1415 * @rxlist: resource list for receive ieq buffes 1416 * @pbufl: temp. list for buffers for fpddu 1417 * @buf: first receive buffer 1418 * @fpdu_len: total length of fpdu 1419 */ 1420 static int 1421 irdma_ieq_create_pbufl(struct irdma_pfpdu *pfpdu, 1422 struct list_head *rxlist, 1423 struct list_head *pbufl, 1424 struct irdma_puda_buf *buf, u16 fpdu_len) 1425 { 1426 int status = 0; 1427 struct irdma_puda_buf *nextbuf; 1428 u32 nextseqnum; 1429 u16 plen = fpdu_len - buf->datalen; 1430 bool done = false; 1431 1432 nextseqnum = buf->seqnum + buf->datalen; 1433 do { 1434 nextbuf = irdma_puda_get_listbuf(rxlist); 1435 if (!nextbuf) { 1436 status = -ENOBUFS; 1437 break; 1438 } 1439 list_add_tail(&nextbuf->list, pbufl); 1440 if (nextbuf->seqnum != nextseqnum) { 1441 pfpdu->bad_seq_num++; 1442 status = -ERANGE; 1443 break; 1444 } 1445 if (nextbuf->datalen >= plen) { 1446 done = true; 1447 } else { 1448 plen -= nextbuf->datalen; 1449 nextseqnum = nextbuf->seqnum + nextbuf->datalen; 1450 } 1451 1452 } while (!done); 1453 1454 return status; 1455 } 1456 1457 /** 1458 * irdma_ieq_handle_partial - process partial fpdu buffer 1459 * @ieq: ieq resource 1460 * @pfpdu: partial management per user qp 1461 * @buf: receive buffer 1462 * @fpdu_len: fpdu len in the buffer 1463 */ 1464 static int 1465 irdma_ieq_handle_partial(struct irdma_puda_rsrc *ieq, 1466 struct irdma_pfpdu *pfpdu, 1467 struct irdma_puda_buf *buf, u16 fpdu_len) 1468 { 1469 int status = 0; 1470 u8 *crcptr; 1471 u32 mpacrc; 1472 u32 seqnum = buf->seqnum; 1473 struct list_head pbufl; /* partial buffer list */ 1474 struct irdma_puda_buf *txbuf = NULL; 1475 struct list_head *rxlist = &pfpdu->rxlist; 1476 1477 ieq->partials_handled++; 1478 1479 INIT_LIST_HEAD(&pbufl); 1480 list_add(&buf->list, &pbufl); 1481 1482 status = irdma_ieq_create_pbufl(pfpdu, rxlist, &pbufl, buf, fpdu_len); 1483 if (status) 1484 goto error; 1485 1486 txbuf = irdma_puda_get_bufpool(ieq); 1487 if (!txbuf) { 1488 pfpdu->no_tx_bufs++; 1489 status = -ENOBUFS; 1490 goto error; 1491 } 1492 1493 irdma_ieq_compl_pfpdu(ieq, rxlist, &pbufl, txbuf, fpdu_len); 1494 irdma_ieq_update_tcpip_info(txbuf, fpdu_len, seqnum); 1495 1496 crcptr = txbuf->data + fpdu_len - 4; 1497 mpacrc = *(u32 *)crcptr; 1498 if (ieq->check_crc) { 1499 status = irdma_ieq_check_mpacrc(ieq->hash_desc, txbuf->data, 1500 (fpdu_len - 4), mpacrc); 1501 if (status) { 1502 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1503 "error bad crc\n"); 1504 pfpdu->mpa_crc_err = true; 1505 goto error; 1506 } 1507 } 1508 1509 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "IEQ TX BUFFER", 1510 txbuf->mem.va, txbuf->totallen); 1511 if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 1512 txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; 1513 txbuf->do_lpb = true; 1514 irdma_puda_send_buf(ieq, txbuf); 1515 pfpdu->rcv_nxt = seqnum + fpdu_len; 1516 return status; 1517 1518 error: 1519 while (!list_empty(&pbufl)) { 1520 buf = (struct irdma_puda_buf *)(&pbufl)->prev; 1521 list_move(&buf->list, rxlist); 1522 } 1523 if (txbuf) 1524 irdma_puda_ret_bufpool(ieq, txbuf); 1525 1526 return status; 1527 } 1528 1529 /** 1530 * irdma_ieq_process_buf - process buffer rcvd for ieq 1531 * @ieq: ieq resource 1532 * @pfpdu: partial management per user qp 1533 * @buf: receive buffer 1534 */ 1535 static int 1536 irdma_ieq_process_buf(struct irdma_puda_rsrc *ieq, 1537 struct irdma_pfpdu *pfpdu, 1538 struct irdma_puda_buf *buf) 1539 { 1540 u16 fpdu_len = 0; 1541 u16 datalen = buf->datalen; 1542 u8 *datap = buf->data; 1543 u8 *crcptr; 1544 u16 ioffset = 0; 1545 u32 mpacrc; 1546 u32 seqnum = buf->seqnum; 1547 u16 len = 0; 1548 u16 full = 0; 1549 bool partial = false; 1550 struct irdma_puda_buf *txbuf; 1551 struct list_head *rxlist = &pfpdu->rxlist; 1552 int ret = 0; 1553 1554 ioffset = (u16)(buf->data - (u8 *)buf->mem.va); 1555 while (datalen) { 1556 fpdu_len = irdma_ieq_get_fpdu_len(pfpdu, datap, buf->seqnum); 1557 if (!fpdu_len) { 1558 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1559 "error bad fpdu len\n"); 1560 list_add(&buf->list, rxlist); 1561 pfpdu->mpa_crc_err = true; 1562 return -EINVAL; 1563 } 1564 1565 if (datalen < fpdu_len) { 1566 partial = true; 1567 break; 1568 } 1569 crcptr = datap + fpdu_len - 4; 1570 mpacrc = *(u32 *)crcptr; 1571 if (ieq->check_crc) 1572 ret = irdma_ieq_check_mpacrc(ieq->hash_desc, datap, 1573 fpdu_len - 4, mpacrc); 1574 if (ret) { 1575 list_add(&buf->list, rxlist); 1576 irdma_debug(ieq->dev, IRDMA_DEBUG_ERR, 1577 "IRDMA_ERR_MPA_CRC\n"); 1578 pfpdu->mpa_crc_err = true; 1579 return ret; 1580 } 1581 full++; 1582 pfpdu->fpdu_processed++; 1583 ieq->fpdu_processed++; 1584 datap += fpdu_len; 1585 len += fpdu_len; 1586 datalen -= fpdu_len; 1587 } 1588 if (full) { 1589 /* copy full pdu's in the txbuf and send them out */ 1590 txbuf = irdma_puda_get_bufpool(ieq); 1591 if (!txbuf) { 1592 pfpdu->no_tx_bufs++; 1593 list_add(&buf->list, rxlist); 1594 return -ENOBUFS; 1595 } 1596 /* modify txbuf's buffer header */ 1597 irdma_ieq_setup_tx_buf(buf, txbuf); 1598 /* copy full fpdu's to new buffer */ 1599 if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1600 irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, 1601 txbuf->hdrlen, len); 1602 txbuf->totallen = txbuf->hdrlen + len; 1603 txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; 1604 } else { 1605 irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, 1606 buf->hdrlen, len); 1607 txbuf->totallen = buf->hdrlen + len; 1608 } 1609 irdma_ieq_update_tcpip_info(txbuf, len, buf->seqnum); 1610 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "IEQ TX BUFFER", 1611 txbuf->mem.va, txbuf->totallen); 1612 txbuf->do_lpb = true; 1613 irdma_puda_send_buf(ieq, txbuf); 1614 1615 if (!datalen) { 1616 pfpdu->rcv_nxt = buf->seqnum + len; 1617 irdma_puda_ret_bufpool(ieq, buf); 1618 return 0; 1619 } 1620 buf->data = datap; 1621 buf->seqnum = seqnum + len; 1622 buf->datalen = datalen; 1623 pfpdu->rcv_nxt = buf->seqnum; 1624 } 1625 if (partial) 1626 return irdma_ieq_handle_partial(ieq, pfpdu, buf, fpdu_len); 1627 1628 return 0; 1629 } 1630 1631 /** 1632 * irdma_ieq_process_fpdus - process fpdu's buffers on its list 1633 * @qp: qp for which partial fpdus 1634 * @ieq: ieq resource 1635 */ 1636 void 1637 irdma_ieq_process_fpdus(struct irdma_sc_qp *qp, 1638 struct irdma_puda_rsrc *ieq) 1639 { 1640 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1641 struct list_head *rxlist = &pfpdu->rxlist; 1642 struct irdma_puda_buf *buf; 1643 int status; 1644 1645 do { 1646 if (list_empty(rxlist)) 1647 break; 1648 buf = irdma_puda_get_listbuf(rxlist); 1649 if (!buf) { 1650 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1651 "error no buf\n"); 1652 break; 1653 } 1654 if (buf->seqnum != pfpdu->rcv_nxt) { 1655 /* This could be out of order or missing packet */ 1656 pfpdu->out_of_order++; 1657 list_add(&buf->list, rxlist); 1658 break; 1659 } 1660 /* keep processing buffers from the head of the list */ 1661 status = irdma_ieq_process_buf(ieq, pfpdu, buf); 1662 if (status && pfpdu->mpa_crc_err) { 1663 while (!list_empty(rxlist)) { 1664 buf = irdma_puda_get_listbuf(rxlist); 1665 irdma_puda_ret_bufpool(ieq, buf); 1666 pfpdu->crc_err++; 1667 ieq->crc_err++; 1668 } 1669 /* create CQP for AE */ 1670 irdma_ieq_mpa_crc_ae(ieq->dev, qp); 1671 } 1672 } while (!status); 1673 } 1674 1675 /** 1676 * irdma_ieq_create_ah - create an address handle for IEQ 1677 * @qp: qp pointer 1678 * @buf: buf received on IEQ used to create AH 1679 */ 1680 static int 1681 irdma_ieq_create_ah(struct irdma_sc_qp *qp, struct irdma_puda_buf *buf) 1682 { 1683 struct irdma_ah_info ah_info = {0}; 1684 1685 qp->pfpdu.ah_buf = buf; 1686 irdma_puda_ieq_get_ah_info(qp, &ah_info); 1687 return irdma_puda_create_ah(qp->vsi->dev, &ah_info, false, 1688 IRDMA_PUDA_RSRC_TYPE_IEQ, qp, 1689 &qp->pfpdu.ah); 1690 } 1691 1692 /** 1693 * irdma_ieq_handle_exception - handle qp's exception 1694 * @ieq: ieq resource 1695 * @qp: qp receiving excpetion 1696 * @buf: receive buffer 1697 */ 1698 static void 1699 irdma_ieq_handle_exception(struct irdma_puda_rsrc *ieq, 1700 struct irdma_sc_qp *qp, 1701 struct irdma_puda_buf *buf) 1702 { 1703 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1704 u32 *hw_host_ctx = (u32 *)qp->hw_host_ctx; 1705 u32 rcv_wnd = hw_host_ctx[23]; 1706 /* first partial seq # in q2 */ 1707 u32 fps = *(u32 *)(qp->q2_buf + Q2_FPSN_OFFSET); 1708 struct list_head *rxlist = &pfpdu->rxlist; 1709 struct list_head *plist; 1710 struct irdma_puda_buf *tmpbuf = NULL; 1711 unsigned long flags = 0; 1712 u8 hw_rev = qp->dev->hw_attrs.uk_attrs.hw_rev; 1713 1714 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "IEQ RX BUFFER", buf->mem.va, 1715 buf->totallen); 1716 1717 spin_lock_irqsave(&pfpdu->lock, flags); 1718 pfpdu->total_ieq_bufs++; 1719 if (pfpdu->mpa_crc_err) { 1720 pfpdu->crc_err++; 1721 goto error; 1722 } 1723 if (pfpdu->mode && fps != pfpdu->fps) { 1724 /* clean up qp as it is new partial sequence */ 1725 irdma_ieq_cleanup_qp(ieq, qp); 1726 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1727 "restarting new partial\n"); 1728 pfpdu->mode = false; 1729 } 1730 1731 if (!pfpdu->mode) { 1732 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "Q2 BUFFER", 1733 (u64 *)qp->q2_buf, 128); 1734 /* First_Partial_Sequence_Number check */ 1735 pfpdu->rcv_nxt = fps; 1736 pfpdu->fps = fps; 1737 pfpdu->mode = true; 1738 pfpdu->max_fpdu_data = (buf->ipv4) ? 1739 (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV4) : 1740 (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV6); 1741 pfpdu->pmode_count++; 1742 ieq->pmode_count++; 1743 INIT_LIST_HEAD(rxlist); 1744 irdma_ieq_check_first_buf(buf, fps); 1745 } 1746 1747 if (!(rcv_wnd >= (buf->seqnum - pfpdu->rcv_nxt))) { 1748 pfpdu->bad_seq_num++; 1749 ieq->bad_seq_num++; 1750 goto error; 1751 } 1752 1753 if (!list_empty(rxlist)) { 1754 tmpbuf = (struct irdma_puda_buf *)(rxlist)->next; 1755 while ((struct list_head *)tmpbuf != rxlist) { 1756 if (buf->seqnum == tmpbuf->seqnum) 1757 goto error; 1758 if ((int)(buf->seqnum - tmpbuf->seqnum) < 0) 1759 break; 1760 plist = &tmpbuf->list; 1761 tmpbuf = (struct irdma_puda_buf *)(plist)->next; 1762 } 1763 /* Insert buf before tmpbuf */ 1764 list_add_tail(&buf->list, &tmpbuf->list); 1765 } else { 1766 list_add_tail(&buf->list, rxlist); 1767 } 1768 pfpdu->nextseqnum = buf->seqnum + buf->datalen; 1769 pfpdu->lastrcv_buf = buf; 1770 if (hw_rev >= IRDMA_GEN_2 && !pfpdu->ah) { 1771 irdma_ieq_create_ah(qp, buf); 1772 if (!pfpdu->ah) 1773 goto error; 1774 goto exit; 1775 } 1776 if (hw_rev == IRDMA_GEN_1) 1777 irdma_ieq_process_fpdus(qp, ieq); 1778 else if (pfpdu->ah && pfpdu->ah->ah_info.ah_valid) 1779 irdma_ieq_process_fpdus(qp, ieq); 1780 exit: 1781 spin_unlock_irqrestore(&pfpdu->lock, flags); 1782 1783 return; 1784 1785 error: 1786 irdma_puda_ret_bufpool(ieq, buf); 1787 spin_unlock_irqrestore(&pfpdu->lock, flags); 1788 } 1789 1790 /** 1791 * irdma_ieq_receive - received exception buffer 1792 * @vsi: VSI of device 1793 * @buf: exception buffer received 1794 */ 1795 static void 1796 irdma_ieq_receive(struct irdma_sc_vsi *vsi, 1797 struct irdma_puda_buf *buf) 1798 { 1799 struct irdma_puda_rsrc *ieq = vsi->ieq; 1800 struct irdma_sc_qp *qp = NULL; 1801 u32 wqe_idx = ieq->compl_rxwqe_idx; 1802 1803 qp = irdma_ieq_get_qp(vsi->dev, buf); 1804 if (!qp) { 1805 ieq->stats_bad_qp_id++; 1806 irdma_puda_ret_bufpool(ieq, buf); 1807 } else { 1808 irdma_ieq_handle_exception(ieq, qp, buf); 1809 } 1810 /* 1811 * ieq->rx_wqe_idx is used by irdma_puda_replenish_rq() on which wqe_idx to start replenish rq 1812 */ 1813 if (!ieq->rxq_invalid_cnt) 1814 ieq->rx_wqe_idx = wqe_idx; 1815 ieq->rxq_invalid_cnt++; 1816 } 1817 1818 /** 1819 * irdma_ieq_tx_compl - put back after sending completed exception buffer 1820 * @vsi: sc VSI struct 1821 * @sqwrid: pointer to puda buffer 1822 */ 1823 static void 1824 irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid) 1825 { 1826 struct irdma_puda_rsrc *ieq = vsi->ieq; 1827 struct irdma_puda_buf *buf = sqwrid; 1828 1829 irdma_puda_ret_bufpool(ieq, buf); 1830 } 1831 1832 /** 1833 * irdma_ieq_cleanup_qp - qp is being destroyed 1834 * @ieq: ieq resource 1835 * @qp: all pending fpdu buffers 1836 */ 1837 void 1838 irdma_ieq_cleanup_qp(struct irdma_puda_rsrc *ieq, struct irdma_sc_qp *qp) 1839 { 1840 struct irdma_puda_buf *buf; 1841 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1842 struct list_head *rxlist = &pfpdu->rxlist; 1843 1844 if (qp->pfpdu.ah) { 1845 irdma_puda_free_ah(ieq->dev, qp->pfpdu.ah); 1846 qp->pfpdu.ah = NULL; 1847 qp->pfpdu.ah_buf = NULL; 1848 } 1849 1850 if (!pfpdu->mode) 1851 return; 1852 1853 while (!list_empty(rxlist)) { 1854 buf = irdma_puda_get_listbuf(rxlist); 1855 irdma_puda_ret_bufpool(ieq, buf); 1856 } 1857 } 1858