1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #include "osdep.h" 37 #include "irdma_hmc.h" 38 #include "irdma_defs.h" 39 #include "irdma_type.h" 40 #include "irdma_protos.h" 41 #include "irdma_puda.h" 42 #include "irdma_ws.h" 43 44 static void 45 irdma_ieq_receive(struct irdma_sc_vsi *vsi, 46 struct irdma_puda_buf *buf); 47 static void irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid); 48 static void 49 irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, 50 struct irdma_puda_buf *buf, u32 wqe_idx); 51 /** 52 * irdma_puda_get_listbuf - get buffer from puda list 53 * @list: list to use for buffers (ILQ or IEQ) 54 */ 55 static struct irdma_puda_buf * 56 irdma_puda_get_listbuf(struct list_head *list) 57 { 58 struct irdma_puda_buf *buf = NULL; 59 60 if (!list_empty(list)) { 61 buf = (struct irdma_puda_buf *)(list)->next; 62 list_del((struct list_head *)&buf->list); 63 } 64 65 return buf; 66 } 67 68 /** 69 * irdma_puda_get_bufpool - return buffer from resource 70 * @rsrc: resource to use for buffer 71 */ 72 struct irdma_puda_buf * 73 irdma_puda_get_bufpool(struct irdma_puda_rsrc *rsrc) 74 { 75 struct irdma_puda_buf *buf = NULL; 76 struct list_head *list = &rsrc->bufpool; 77 unsigned long flags; 78 79 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 80 buf = irdma_puda_get_listbuf(list); 81 if (buf) { 82 rsrc->avail_buf_count--; 83 buf->vsi = rsrc->vsi; 84 } else { 85 rsrc->stats_buf_alloc_fail++; 86 } 87 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 88 89 return buf; 90 } 91 92 /** 93 * irdma_puda_ret_bufpool - return buffer to rsrc list 94 * @rsrc: resource to use for buffer 95 * @buf: buffer to return to resource 96 */ 97 void 98 irdma_puda_ret_bufpool(struct irdma_puda_rsrc *rsrc, 99 struct irdma_puda_buf *buf) 100 { 101 unsigned long flags; 102 103 buf->do_lpb = false; 104 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 105 list_add(&buf->list, &rsrc->bufpool); 106 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 107 rsrc->avail_buf_count++; 108 } 109 110 /** 111 * irdma_puda_post_recvbuf - set wqe for rcv buffer 112 * @rsrc: resource ptr 113 * @wqe_idx: wqe index to use 114 * @buf: puda buffer for rcv q 115 * @initial: flag if during init time 116 */ 117 static void 118 irdma_puda_post_recvbuf(struct irdma_puda_rsrc *rsrc, u32 wqe_idx, 119 struct irdma_puda_buf *buf, bool initial) 120 { 121 __le64 *wqe; 122 struct irdma_sc_qp *qp = &rsrc->qp; 123 u64 offset24 = 0; 124 125 /* Synch buffer for use by device */ 126 dma_sync_single_for_device(hw_to_dev(rsrc->dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 127 qp->qp_uk.rq_wrid_array[wqe_idx] = (uintptr_t)buf; 128 wqe = qp->qp_uk.rq_base[wqe_idx].elem; 129 if (!initial) 130 get_64bit_val(wqe, IRDMA_BYTE_24, &offset24); 131 132 offset24 = (offset24) ? 0 : FIELD_PREP(IRDMAQPSQ_VALID, 1); 133 134 set_64bit_val(wqe, IRDMA_BYTE_16, 0); 135 set_64bit_val(wqe, 0, buf->mem.pa); 136 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 137 set_64bit_val(wqe, IRDMA_BYTE_8, 138 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, buf->mem.size)); 139 } else { 140 set_64bit_val(wqe, IRDMA_BYTE_8, 141 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, buf->mem.size) | 142 offset24); 143 } 144 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 145 146 set_64bit_val(wqe, IRDMA_BYTE_24, offset24); 147 } 148 149 /** 150 * irdma_puda_replenish_rq - post rcv buffers 151 * @rsrc: resource to use for buffer 152 * @initial: flag if during init time 153 */ 154 static int 155 irdma_puda_replenish_rq(struct irdma_puda_rsrc *rsrc, bool initial) 156 { 157 u32 i; 158 u32 invalid_cnt = rsrc->rxq_invalid_cnt; 159 struct irdma_puda_buf *buf = NULL; 160 161 for (i = 0; i < invalid_cnt; i++) { 162 buf = irdma_puda_get_bufpool(rsrc); 163 if (!buf) 164 return -ENOBUFS; 165 irdma_puda_post_recvbuf(rsrc, rsrc->rx_wqe_idx, buf, initial); 166 rsrc->rx_wqe_idx = ((rsrc->rx_wqe_idx + 1) % rsrc->rq_size); 167 rsrc->rxq_invalid_cnt--; 168 } 169 170 return 0; 171 } 172 173 /** 174 * irdma_puda_alloc_buf - allocate mem for buffer 175 * @dev: iwarp device 176 * @len: length of buffer 177 */ 178 static struct irdma_puda_buf * 179 irdma_puda_alloc_buf(struct irdma_sc_dev *dev, 180 u32 len) 181 { 182 struct irdma_puda_buf *buf; 183 struct irdma_virt_mem buf_mem; 184 185 buf_mem.size = sizeof(struct irdma_puda_buf); 186 buf_mem.va = kzalloc(buf_mem.size, GFP_KERNEL); 187 if (!buf_mem.va) 188 return NULL; 189 190 buf = buf_mem.va; 191 buf->mem.size = len; 192 buf->mem.va = kzalloc(buf->mem.size, GFP_KERNEL); 193 if (!buf->mem.va) 194 goto free_virt; 195 buf->mem.pa = dma_map_single(hw_to_dev(dev->hw), buf->mem.va, buf->mem.size, DMA_BIDIRECTIONAL); 196 if (dma_mapping_error(hw_to_dev(dev->hw), buf->mem.pa)) { 197 kfree(buf->mem.va); 198 goto free_virt; 199 } 200 201 buf->buf_mem.va = buf_mem.va; 202 buf->buf_mem.size = buf_mem.size; 203 204 return buf; 205 206 free_virt: 207 kfree(buf_mem.va); 208 return NULL; 209 } 210 211 /** 212 * irdma_puda_dele_buf - delete buffer back to system 213 * @dev: iwarp device 214 * @buf: buffer to free 215 */ 216 static void 217 irdma_puda_dele_buf(struct irdma_sc_dev *dev, 218 struct irdma_puda_buf *buf) 219 { 220 if (!buf->virtdma) { 221 irdma_free_dma_mem(dev->hw, &buf->mem); 222 kfree(buf->buf_mem.va); 223 } 224 } 225 226 /** 227 * irdma_puda_get_next_send_wqe - return next wqe for processing 228 * @qp: puda qp for wqe 229 * @wqe_idx: wqe index for caller 230 */ 231 static __le64 * irdma_puda_get_next_send_wqe(struct irdma_qp_uk *qp, 232 u32 *wqe_idx){ 233 int ret_code = 0; 234 235 *wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 236 if (!*wqe_idx) 237 qp->swqe_polarity = !qp->swqe_polarity; 238 IRDMA_RING_MOVE_HEAD(qp->sq_ring, ret_code); 239 if (ret_code) 240 return NULL; 241 242 return qp->sq_base[*wqe_idx].elem; 243 } 244 245 /** 246 * irdma_puda_poll_info - poll cq for completion 247 * @cq: cq for poll 248 * @info: info return for successful completion 249 */ 250 static int 251 irdma_puda_poll_info(struct irdma_sc_cq *cq, 252 struct irdma_puda_cmpl_info *info) 253 { 254 struct irdma_cq_uk *cq_uk = &cq->cq_uk; 255 u64 qword0, qword2, qword3, qword6; 256 __le64 *cqe; 257 __le64 *ext_cqe = NULL; 258 u64 qword7 = 0; 259 u64 comp_ctx; 260 bool valid_bit; 261 bool ext_valid = 0; 262 u32 major_err, minor_err; 263 u32 peek_head; 264 bool error; 265 u8 polarity; 266 267 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&cq->cq_uk); 268 get_64bit_val(cqe, IRDMA_BYTE_24, &qword3); 269 valid_bit = (bool)FIELD_GET(IRDMA_CQ_VALID, qword3); 270 if (valid_bit != cq_uk->polarity) 271 return -ENOENT; 272 273 if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 274 ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); 275 276 if (ext_valid) { 277 peek_head = (cq_uk->cq_ring.head + 1) % cq_uk->cq_ring.size; 278 ext_cqe = cq_uk->cq_base[peek_head].buf; 279 get_64bit_val(ext_cqe, IRDMA_BYTE_24, &qword7); 280 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); 281 if (!peek_head) 282 polarity ^= 1; 283 if (polarity != cq_uk->polarity) 284 return -ENOENT; 285 286 IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); 287 if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) 288 cq_uk->polarity = !cq_uk->polarity; 289 /* update cq tail in cq shadow memory also */ 290 IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); 291 } 292 293 irdma_debug_buf(cq->dev, IRDMA_DEBUG_PUDA, "PUDA CQE", cqe, 32); 294 if (ext_valid) 295 irdma_debug_buf(cq->dev, IRDMA_DEBUG_PUDA, "PUDA EXT-CQE", 296 ext_cqe, 32); 297 298 error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); 299 if (error) { 300 irdma_debug(cq->dev, IRDMA_DEBUG_PUDA, "receive error\n"); 301 major_err = (u32)(FIELD_GET(IRDMA_CQ_MAJERR, qword3)); 302 minor_err = (u32)(FIELD_GET(IRDMA_CQ_MINERR, qword3)); 303 info->compl_error = major_err << 16 | minor_err; 304 return -EIO; 305 } 306 307 get_64bit_val(cqe, IRDMA_BYTE_0, &qword0); 308 get_64bit_val(cqe, IRDMA_BYTE_16, &qword2); 309 310 info->q_type = (u8)FIELD_GET(IRDMA_CQ_SQ, qword3); 311 info->qp_id = (u32)FIELD_GET(IRDMACQ_QPID, qword2); 312 if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 313 info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); 314 315 get_64bit_val(cqe, IRDMA_BYTE_8, &comp_ctx); 316 info->qp = (struct irdma_qp_uk *)(irdma_uintptr) comp_ctx; 317 info->wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); 318 319 if (info->q_type == IRDMA_CQE_QTYPE_RQ) { 320 if (ext_valid) { 321 info->vlan_valid = (bool)FIELD_GET(IRDMA_CQ_UDVLANVALID, qword7); 322 if (info->vlan_valid) { 323 get_64bit_val(ext_cqe, IRDMA_BYTE_16, &qword6); 324 info->vlan = (u16)FIELD_GET(IRDMA_CQ_UDVLAN, qword6); 325 } 326 info->smac_valid = (bool)FIELD_GET(IRDMA_CQ_UDSMACVALID, qword7); 327 if (info->smac_valid) { 328 get_64bit_val(ext_cqe, IRDMA_BYTE_16, &qword6); 329 info->smac[0] = (u8)((qword6 >> 40) & 0xFF); 330 info->smac[1] = (u8)((qword6 >> 32) & 0xFF); 331 info->smac[2] = (u8)((qword6 >> 24) & 0xFF); 332 info->smac[3] = (u8)((qword6 >> 16) & 0xFF); 333 info->smac[4] = (u8)((qword6 >> 8) & 0xFF); 334 info->smac[5] = (u8)(qword6 & 0xFF); 335 } 336 } 337 338 if (cq->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 339 info->vlan_valid = (bool)FIELD_GET(IRDMA_VLAN_TAG_VALID, qword3); 340 info->l4proto = (u8)FIELD_GET(IRDMA_UDA_L4PROTO, qword2); 341 info->l3proto = (u8)FIELD_GET(IRDMA_UDA_L3PROTO, qword2); 342 } 343 344 info->payload_len = (u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); 345 } 346 347 return 0; 348 } 349 350 /** 351 * irdma_puda_poll_cmpl - processes completion for cq 352 * @dev: iwarp device 353 * @cq: cq getting interrupt 354 * @compl_err: return any completion err 355 */ 356 int 357 irdma_puda_poll_cmpl(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq, 358 u32 *compl_err) 359 { 360 struct irdma_qp_uk *qp; 361 struct irdma_cq_uk *cq_uk = &cq->cq_uk; 362 struct irdma_puda_cmpl_info info = {0}; 363 int ret = 0; 364 struct irdma_puda_buf *buf; 365 struct irdma_puda_rsrc *rsrc; 366 u8 cq_type = cq->cq_type; 367 unsigned long flags; 368 369 if (cq_type == IRDMA_CQ_TYPE_ILQ || cq_type == IRDMA_CQ_TYPE_IEQ) { 370 rsrc = (cq_type == IRDMA_CQ_TYPE_ILQ) ? cq->vsi->ilq : 371 cq->vsi->ieq; 372 } else { 373 irdma_debug(dev, IRDMA_DEBUG_PUDA, "qp_type error\n"); 374 return -EFAULT; 375 } 376 377 ret = irdma_puda_poll_info(cq, &info); 378 *compl_err = info.compl_error; 379 if (ret == -ENOENT) 380 return ret; 381 if (ret) 382 goto done; 383 384 qp = info.qp; 385 if (!qp || !rsrc) { 386 ret = -EFAULT; 387 goto done; 388 } 389 390 if (qp->qp_id != rsrc->qp_id) { 391 ret = -EFAULT; 392 goto done; 393 } 394 395 if (info.q_type == IRDMA_CQE_QTYPE_RQ) { 396 buf = (struct irdma_puda_buf *)(uintptr_t) 397 qp->rq_wrid_array[info.wqe_idx]; 398 399 /* reusing so synch the buffer for CPU use */ 400 dma_sync_single_for_cpu(hw_to_dev(dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 401 /* Get all the tcpip information in the buf header */ 402 ret = irdma_puda_get_tcpip_info(&info, buf); 403 if (ret) { 404 rsrc->stats_rcvd_pkt_err++; 405 if (cq_type == IRDMA_CQ_TYPE_ILQ) { 406 irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, 407 info.wqe_idx); 408 } else { 409 irdma_puda_ret_bufpool(rsrc, buf); 410 irdma_puda_replenish_rq(rsrc, false); 411 } 412 goto done; 413 } 414 415 rsrc->stats_pkt_rcvd++; 416 rsrc->compl_rxwqe_idx = info.wqe_idx; 417 irdma_debug(dev, IRDMA_DEBUG_PUDA, "RQ completion\n"); 418 rsrc->receive(rsrc->vsi, buf); 419 if (cq_type == IRDMA_CQ_TYPE_ILQ) 420 irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, info.wqe_idx); 421 else 422 irdma_puda_replenish_rq(rsrc, false); 423 424 } else { 425 irdma_debug(dev, IRDMA_DEBUG_PUDA, "SQ completion\n"); 426 buf = (struct irdma_puda_buf *)(uintptr_t) 427 qp->sq_wrtrk_array[info.wqe_idx].wrid; 428 429 /* reusing so synch the buffer for CPU use */ 430 dma_sync_single_for_cpu(hw_to_dev(dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 431 IRDMA_RING_SET_TAIL(qp->sq_ring, info.wqe_idx); 432 rsrc->xmit_complete(rsrc->vsi, buf); 433 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 434 rsrc->tx_wqe_avail_cnt++; 435 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 436 if (!list_empty(&rsrc->txpend)) 437 irdma_puda_send_buf(rsrc, NULL); 438 } 439 440 done: 441 IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); 442 if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) 443 cq_uk->polarity = !cq_uk->polarity; 444 /* update cq tail in cq shadow memory also */ 445 IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); 446 set_64bit_val(cq_uk->shadow_area, IRDMA_BYTE_0, 447 IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)); 448 449 return ret; 450 } 451 452 /** 453 * irdma_puda_send - complete send wqe for transmit 454 * @qp: puda qp for send 455 * @info: buffer information for transmit 456 */ 457 int 458 irdma_puda_send(struct irdma_sc_qp *qp, struct irdma_puda_send_info *info) 459 { 460 __le64 *wqe; 461 u32 iplen, l4len; 462 u64 hdr[2]; 463 u32 wqe_idx; 464 u8 iipt; 465 466 /* number of 32 bits DWORDS in header */ 467 l4len = info->tcplen >> 2; 468 if (info->ipv4) { 469 iipt = 3; 470 iplen = 5; 471 } else { 472 iipt = 1; 473 iplen = 10; 474 } 475 476 wqe = irdma_puda_get_next_send_wqe(&qp->qp_uk, &wqe_idx); 477 if (!wqe) 478 return -ENOSPC; 479 480 qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid = (uintptr_t)info->scratch; 481 /* Third line of WQE descriptor */ 482 /* maclen is in words */ 483 484 if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 485 hdr[0] = 0; /* Dest_QPN and Dest_QKey only for UD */ 486 hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | 487 FIELD_PREP(IRDMA_UDA_QPSQ_L4LEN, l4len) | 488 FIELD_PREP(IRDMAQPSQ_AHID, info->ah_id) | 489 FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | 490 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, 491 qp->qp_uk.swqe_polarity); 492 493 /* Forth line of WQE descriptor */ 494 495 set_64bit_val(wqe, IRDMA_BYTE_0, info->paddr); 496 set_64bit_val(wqe, IRDMA_BYTE_8, 497 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, info->len) | 498 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity)); 499 } else { 500 hdr[0] = FIELD_PREP(IRDMA_UDA_QPSQ_MACLEN, info->maclen >> 1) | 501 FIELD_PREP(IRDMA_UDA_QPSQ_IPLEN, iplen) | 502 FIELD_PREP(IRDMA_UDA_QPSQ_L4T, 1) | 503 FIELD_PREP(IRDMA_UDA_QPSQ_IIPT, iipt) | 504 FIELD_PREP(IRDMA_GEN1_UDA_QPSQ_L4LEN, l4len); 505 506 hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | 507 FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | 508 FIELD_PREP(IRDMA_UDA_QPSQ_DOLOOPBACK, info->do_lpb) | 509 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity); 510 511 /* Forth line of WQE descriptor */ 512 513 set_64bit_val(wqe, IRDMA_BYTE_0, info->paddr); 514 set_64bit_val(wqe, IRDMA_BYTE_8, 515 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, info->len)); 516 } 517 518 set_64bit_val(wqe, IRDMA_BYTE_16, hdr[0]); 519 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 520 521 set_64bit_val(wqe, IRDMA_BYTE_24, hdr[1]); 522 523 irdma_debug_buf(qp->dev, IRDMA_DEBUG_PUDA, "PUDA SEND WQE", wqe, 32); 524 irdma_uk_qp_post_wr(&qp->qp_uk); 525 return 0; 526 } 527 528 /** 529 * irdma_puda_send_buf - transmit puda buffer 530 * @rsrc: resource to use for buffer 531 * @buf: puda buffer to transmit 532 */ 533 void 534 irdma_puda_send_buf(struct irdma_puda_rsrc *rsrc, 535 struct irdma_puda_buf *buf) 536 { 537 struct irdma_puda_send_info info; 538 int ret = 0; 539 unsigned long flags; 540 541 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 542 /* 543 * if no wqe available or not from a completion and we have pending buffers, we must queue new buffer 544 */ 545 if (!rsrc->tx_wqe_avail_cnt || (buf && !list_empty(&rsrc->txpend))) { 546 list_add_tail(&buf->list, &rsrc->txpend); 547 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 548 rsrc->stats_sent_pkt_q++; 549 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 550 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 551 "adding to txpend\n"); 552 return; 553 } 554 rsrc->tx_wqe_avail_cnt--; 555 /* 556 * if we are coming from a completion and have pending buffers then Get one from pending list 557 */ 558 if (!buf) { 559 buf = irdma_puda_get_listbuf(&rsrc->txpend); 560 if (!buf) 561 goto done; 562 } 563 564 info.scratch = buf; 565 info.paddr = buf->mem.pa; 566 info.len = buf->totallen; 567 info.tcplen = buf->tcphlen; 568 info.ipv4 = buf->ipv4; 569 570 if (rsrc->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 571 info.ah_id = buf->ah_id; 572 } else { 573 info.maclen = buf->maclen; 574 info.do_lpb = buf->do_lpb; 575 } 576 577 /* Synch buffer for use by device */ 578 dma_sync_single_for_cpu(hw_to_dev(rsrc->dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 579 ret = irdma_puda_send(&rsrc->qp, &info); 580 if (ret) { 581 rsrc->tx_wqe_avail_cnt++; 582 rsrc->stats_sent_pkt_q++; 583 list_add(&buf->list, &rsrc->txpend); 584 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 585 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 586 "adding to puda_send\n"); 587 } else { 588 rsrc->stats_pkt_sent++; 589 } 590 done: 591 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 592 } 593 594 /** 595 * irdma_puda_qp_setctx - during init, set qp's context 596 * @rsrc: qp's resource 597 */ 598 static void 599 irdma_puda_qp_setctx(struct irdma_puda_rsrc *rsrc) 600 { 601 struct irdma_sc_qp *qp = &rsrc->qp; 602 __le64 *qp_ctx = qp->hw_host_ctx; 603 604 set_64bit_val(qp_ctx, IRDMA_BYTE_8, qp->sq_pa); 605 set_64bit_val(qp_ctx, IRDMA_BYTE_16, qp->rq_pa); 606 set_64bit_val(qp_ctx, IRDMA_BYTE_24, 607 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 608 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size)); 609 set_64bit_val(qp_ctx, IRDMA_BYTE_48, 610 FIELD_PREP(IRDMAQPC_SNDMSS, rsrc->buf_size)); 611 set_64bit_val(qp_ctx, IRDMA_BYTE_56, 0); 612 if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 613 set_64bit_val(qp_ctx, IRDMA_BYTE_64, 1); 614 set_64bit_val(qp_ctx, IRDMA_BYTE_136, 615 FIELD_PREP(IRDMAQPC_TXCQNUM, rsrc->cq_id) | 616 FIELD_PREP(IRDMAQPC_RXCQNUM, rsrc->cq_id)); 617 set_64bit_val(qp_ctx, IRDMA_BYTE_144, 618 FIELD_PREP(IRDMAQPC_STAT_INDEX, rsrc->stats_idx)); 619 set_64bit_val(qp_ctx, IRDMA_BYTE_160, 620 FIELD_PREP(IRDMAQPC_PRIVEN, 1) | 621 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, rsrc->stats_idx_valid)); 622 set_64bit_val(qp_ctx, IRDMA_BYTE_168, 623 FIELD_PREP(IRDMAQPC_QPCOMPCTX, (uintptr_t)qp)); 624 set_64bit_val(qp_ctx, IRDMA_BYTE_176, 625 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 626 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 627 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 628 629 irdma_debug_buf(rsrc->dev, IRDMA_DEBUG_PUDA, "PUDA QP CONTEXT", qp_ctx, 630 IRDMA_QP_CTX_SIZE); 631 } 632 633 /** 634 * irdma_puda_qp_wqe - setup wqe for qp create 635 * @dev: Device 636 * @qp: Resource qp 637 */ 638 static int 639 irdma_puda_qp_wqe(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp) 640 { 641 struct irdma_sc_cqp *cqp; 642 __le64 *wqe; 643 u64 hdr; 644 struct irdma_ccq_cqe_info compl_info; 645 int status = 0; 646 647 cqp = dev->cqp; 648 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); 649 if (!wqe) 650 return -ENOSPC; 651 652 set_64bit_val(wqe, IRDMA_BYTE_16, qp->hw_host_ctx_pa); 653 set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa); 654 655 hdr = qp->qp_uk.qp_id | 656 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | 657 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, IRDMA_QP_TYPE_UDA) | 658 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, 1) | 659 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, 2) | 660 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 661 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 662 663 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 664 665 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_PUDA, "PUDA QP CREATE", wqe, 40); 666 irdma_sc_cqp_post_sq(cqp); 667 status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_QP, 668 &compl_info); 669 670 return status; 671 } 672 673 /** 674 * irdma_puda_qp_create - create qp for resource 675 * @rsrc: resource to use for buffer 676 */ 677 static int 678 irdma_puda_qp_create(struct irdma_puda_rsrc *rsrc) 679 { 680 struct irdma_sc_qp *qp = &rsrc->qp; 681 struct irdma_qp_uk *ukqp = &qp->qp_uk; 682 int ret = 0; 683 u32 sq_size, rq_size; 684 struct irdma_dma_mem *mem; 685 686 sq_size = rsrc->sq_size * IRDMA_QP_WQE_MIN_SIZE; 687 rq_size = rsrc->rq_size * IRDMA_QP_WQE_MIN_SIZE; 688 rsrc->qpmem.size = (sq_size + rq_size + (IRDMA_SHADOW_AREA_SIZE << 3) + 689 IRDMA_QP_CTX_SIZE); 690 rsrc->qpmem.va = irdma_allocate_dma_mem(rsrc->dev->hw, &rsrc->qpmem, 691 rsrc->qpmem.size, IRDMA_HW_PAGE_SIZE); 692 if (!rsrc->qpmem.va) 693 return -ENOMEM; 694 695 mem = &rsrc->qpmem; 696 memset(mem->va, 0, rsrc->qpmem.size); 697 qp->hw_sq_size = irdma_get_encoded_wqe_size(rsrc->sq_size, IRDMA_QUEUE_TYPE_SQ_RQ); 698 qp->hw_rq_size = irdma_get_encoded_wqe_size(rsrc->rq_size, IRDMA_QUEUE_TYPE_SQ_RQ); 699 qp->pd = &rsrc->sc_pd; 700 qp->qp_uk.qp_type = IRDMA_QP_TYPE_UDA; 701 qp->dev = rsrc->dev; 702 qp->qp_uk.back_qp = rsrc; 703 qp->sq_pa = mem->pa; 704 qp->rq_pa = qp->sq_pa + sq_size; 705 qp->vsi = rsrc->vsi; 706 ukqp->sq_base = mem->va; 707 ukqp->rq_base = &ukqp->sq_base[rsrc->sq_size]; 708 ukqp->shadow_area = ukqp->rq_base[rsrc->rq_size].elem; 709 ukqp->uk_attrs = &qp->dev->hw_attrs.uk_attrs; 710 qp->shadow_area_pa = qp->rq_pa + rq_size; 711 qp->hw_host_ctx = ukqp->shadow_area + IRDMA_SHADOW_AREA_SIZE; 712 qp->hw_host_ctx_pa = qp->shadow_area_pa + (IRDMA_SHADOW_AREA_SIZE << 3); 713 qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; 714 ukqp->qp_id = rsrc->qp_id; 715 ukqp->sq_wrtrk_array = rsrc->sq_wrtrk_array; 716 ukqp->rq_wrid_array = rsrc->rq_wrid_array; 717 ukqp->sq_size = rsrc->sq_size; 718 ukqp->rq_size = rsrc->rq_size; 719 720 IRDMA_RING_INIT(ukqp->sq_ring, ukqp->sq_size); 721 IRDMA_RING_INIT(ukqp->initial_ring, ukqp->sq_size); 722 IRDMA_RING_INIT(ukqp->rq_ring, ukqp->rq_size); 723 ukqp->wqe_alloc_db = qp->pd->dev->wqe_alloc_db; 724 725 ret = rsrc->dev->ws_add(qp->vsi, qp->user_pri); 726 if (ret) { 727 irdma_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem); 728 return ret; 729 } 730 731 irdma_qp_add_qos(qp); 732 irdma_puda_qp_setctx(rsrc); 733 734 if (rsrc->dev->ceq_valid) 735 ret = irdma_cqp_qp_create_cmd(rsrc->dev, qp); 736 else 737 ret = irdma_puda_qp_wqe(rsrc->dev, qp); 738 if (ret) { 739 irdma_qp_rem_qos(qp); 740 rsrc->dev->ws_remove(qp->vsi, qp->user_pri); 741 irdma_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem); 742 } 743 744 return ret; 745 } 746 747 /** 748 * irdma_puda_cq_wqe - setup wqe for CQ create 749 * @dev: Device 750 * @cq: resource for cq 751 */ 752 static int 753 irdma_puda_cq_wqe(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq) 754 { 755 __le64 *wqe; 756 struct irdma_sc_cqp *cqp; 757 u64 hdr; 758 struct irdma_ccq_cqe_info compl_info; 759 int status = 0; 760 761 cqp = dev->cqp; 762 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); 763 if (!wqe) 764 return -ENOSPC; 765 766 set_64bit_val(wqe, IRDMA_BYTE_0, cq->cq_uk.cq_size); 767 set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1)); 768 set_64bit_val(wqe, IRDMA_BYTE_16, 769 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold)); 770 set_64bit_val(wqe, IRDMA_BYTE_32, cq->cq_pa); 771 set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa); 772 set_64bit_val(wqe, IRDMA_BYTE_56, 773 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 774 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 775 776 hdr = cq->cq_uk.cq_id | 777 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | 778 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, 1) | 779 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, 1) | 780 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, 1) | 781 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 782 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 783 784 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 785 786 irdma_debug_buf(dev, IRDMA_DEBUG_PUDA, "PUDA CREATE CQ", wqe, 787 IRDMA_CQP_WQE_SIZE * 8); 788 irdma_sc_cqp_post_sq(dev->cqp); 789 status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_CQ, 790 &compl_info); 791 if (!status) { 792 struct irdma_sc_ceq *ceq = dev->ceq[0]; 793 794 if (ceq && ceq->reg_cq) 795 status = irdma_sc_add_cq_ctx(ceq, cq); 796 } 797 798 return status; 799 } 800 801 /** 802 * irdma_puda_cq_create - create cq for resource 803 * @rsrc: resource for which cq to create 804 */ 805 static int 806 irdma_puda_cq_create(struct irdma_puda_rsrc *rsrc) 807 { 808 struct irdma_sc_dev *dev = rsrc->dev; 809 struct irdma_sc_cq *cq = &rsrc->cq; 810 int ret = 0; 811 u32 cqsize; 812 struct irdma_dma_mem *mem; 813 struct irdma_cq_init_info info = {0}; 814 struct irdma_cq_uk_init_info *init_info = &info.cq_uk_init_info; 815 816 cq->vsi = rsrc->vsi; 817 cqsize = rsrc->cq_size * (sizeof(struct irdma_cqe)); 818 rsrc->cqmem.size = cqsize + sizeof(struct irdma_cq_shadow_area); 819 rsrc->cqmem.va = irdma_allocate_dma_mem(dev->hw, &rsrc->cqmem, 820 rsrc->cqmem.size, 821 IRDMA_CQ0_ALIGNMENT); 822 if (!rsrc->cqmem.va) 823 return -ENOMEM; 824 825 mem = &rsrc->cqmem; 826 info.dev = dev; 827 info.type = (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) ? 828 IRDMA_CQ_TYPE_ILQ : IRDMA_CQ_TYPE_IEQ; 829 info.shadow_read_threshold = rsrc->cq_size >> 2; 830 info.cq_base_pa = mem->pa; 831 info.shadow_area_pa = mem->pa + cqsize; 832 init_info->cq_base = mem->va; 833 init_info->shadow_area = (__le64 *) ((u8 *)mem->va + cqsize); 834 init_info->cq_size = rsrc->cq_size; 835 init_info->cq_id = rsrc->cq_id; 836 info.ceqe_mask = true; 837 info.ceq_id_valid = true; 838 info.vsi = rsrc->vsi; 839 840 ret = irdma_sc_cq_init(cq, &info); 841 if (ret) 842 goto error; 843 844 if (rsrc->dev->ceq_valid) 845 ret = irdma_cqp_cq_create_cmd(dev, cq); 846 else 847 ret = irdma_puda_cq_wqe(dev, cq); 848 error: 849 if (ret) 850 irdma_free_dma_mem(dev->hw, &rsrc->cqmem); 851 852 return ret; 853 } 854 855 /** 856 * irdma_puda_free_qp - free qp for resource 857 * @rsrc: resource for which qp to free 858 */ 859 static void 860 irdma_puda_free_qp(struct irdma_puda_rsrc *rsrc) 861 { 862 int ret; 863 struct irdma_ccq_cqe_info compl_info; 864 struct irdma_sc_dev *dev = rsrc->dev; 865 866 if (rsrc->dev->ceq_valid) { 867 irdma_cqp_qp_destroy_cmd(dev, &rsrc->qp); 868 rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); 869 return; 870 } 871 872 ret = irdma_sc_qp_destroy(&rsrc->qp, 0, false, true, true); 873 if (ret) 874 irdma_debug(dev, IRDMA_DEBUG_PUDA, 875 "error puda qp destroy wqe, status = %d\n", ret); 876 if (!ret) { 877 ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_QP, 878 &compl_info); 879 if (ret) 880 irdma_debug(dev, IRDMA_DEBUG_PUDA, 881 "error puda qp destroy failed, status = %d\n", 882 ret); 883 } 884 rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); 885 } 886 887 /** 888 * irdma_puda_free_cq - free cq for resource 889 * @rsrc: resource for which cq to free 890 */ 891 static void 892 irdma_puda_free_cq(struct irdma_puda_rsrc *rsrc) 893 { 894 int ret; 895 struct irdma_ccq_cqe_info compl_info; 896 struct irdma_sc_dev *dev = rsrc->dev; 897 898 if (rsrc->dev->ceq_valid) { 899 irdma_cqp_cq_destroy_cmd(dev, &rsrc->cq); 900 return; 901 } 902 903 ret = irdma_sc_cq_destroy(&rsrc->cq, 0, true); 904 if (ret) 905 irdma_debug(dev, IRDMA_DEBUG_PUDA, "error ieq cq destroy\n"); 906 if (!ret) { 907 ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_CQ, 908 &compl_info); 909 if (ret) 910 irdma_debug(dev, IRDMA_DEBUG_PUDA, 911 "error ieq qp destroy done\n"); 912 } 913 } 914 915 /** 916 * irdma_puda_dele_rsrc - delete all resources during close 917 * @vsi: VSI structure of device 918 * @type: type of resource to dele 919 * @reset: true if reset chip 920 */ 921 void 922 irdma_puda_dele_rsrc(struct irdma_sc_vsi *vsi, enum puda_rsrc_type type, 923 bool reset) 924 { 925 struct irdma_sc_dev *dev = vsi->dev; 926 struct irdma_puda_rsrc *rsrc; 927 struct irdma_puda_buf *buf = NULL; 928 struct irdma_puda_buf *nextbuf = NULL; 929 struct irdma_virt_mem *vmem; 930 struct irdma_sc_ceq *ceq; 931 932 ceq = vsi->dev->ceq[0]; 933 switch (type) { 934 case IRDMA_PUDA_RSRC_TYPE_ILQ: 935 rsrc = vsi->ilq; 936 vmem = &vsi->ilq_mem; 937 vsi->ilq = NULL; 938 if (ceq && ceq->reg_cq) 939 irdma_sc_remove_cq_ctx(ceq, &rsrc->cq); 940 break; 941 case IRDMA_PUDA_RSRC_TYPE_IEQ: 942 rsrc = vsi->ieq; 943 vmem = &vsi->ieq_mem; 944 vsi->ieq = NULL; 945 if (ceq && ceq->reg_cq) 946 irdma_sc_remove_cq_ctx(ceq, &rsrc->cq); 947 break; 948 default: 949 irdma_debug(dev, IRDMA_DEBUG_PUDA, 950 "error resource type = 0x%x\n", type); 951 return; 952 } 953 954 spin_lock_destroy(&rsrc->bufpool_lock); 955 switch (rsrc->cmpl) { 956 case PUDA_HASH_CRC_COMPLETE: 957 irdma_free_hash_desc(rsrc->hash_desc); 958 /* fallthrough */ 959 case PUDA_QP_CREATED: 960 irdma_qp_rem_qos(&rsrc->qp); 961 962 if (!reset) 963 irdma_puda_free_qp(rsrc); 964 965 irdma_free_dma_mem(dev->hw, &rsrc->qpmem); 966 /* fallthrough */ 967 case PUDA_CQ_CREATED: 968 if (!reset) 969 irdma_puda_free_cq(rsrc); 970 971 irdma_free_dma_mem(dev->hw, &rsrc->cqmem); 972 break; 973 default: 974 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 975 "error no resources\n"); 976 break; 977 } 978 /* Free all allocated puda buffers for both tx and rx */ 979 buf = rsrc->alloclist; 980 while (buf) { 981 nextbuf = buf->next; 982 irdma_puda_dele_buf(dev, buf); 983 buf = nextbuf; 984 rsrc->alloc_buf_count--; 985 } 986 987 kfree(vmem->va); 988 } 989 990 /** 991 * irdma_puda_allocbufs - allocate buffers for resource 992 * @rsrc: resource for buffer allocation 993 * @count: number of buffers to create 994 */ 995 static int 996 irdma_puda_allocbufs(struct irdma_puda_rsrc *rsrc, u32 count) 997 { 998 u32 i; 999 struct irdma_puda_buf *buf; 1000 struct irdma_puda_buf *nextbuf; 1001 struct irdma_virt_mem buf_mem; 1002 struct irdma_dma_mem *dma_mem; 1003 bool virtdma = false; 1004 unsigned long flags; 1005 1006 buf_mem.size = count * sizeof(struct irdma_puda_buf); 1007 buf_mem.va = kzalloc(buf_mem.size, GFP_KERNEL); 1008 if (!buf_mem.va) { 1009 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 1010 "error virt_mem for buf\n"); 1011 rsrc->stats_buf_alloc_fail++; 1012 goto trysmall; 1013 } 1014 1015 /* 1016 * Allocate the large dma chunk and setup dma attributes into first puda buffer. This is required during free 1017 */ 1018 buf = (struct irdma_puda_buf *)buf_mem.va; 1019 buf->mem.va = irdma_allocate_dma_mem(rsrc->dev->hw, &buf->mem, 1020 rsrc->buf_size * count, 1); 1021 if (!buf->mem.va) { 1022 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 1023 "error dma_mem for buf\n"); 1024 kfree(buf_mem.va); 1025 rsrc->stats_buf_alloc_fail++; 1026 goto trysmall; 1027 } 1028 1029 /* 1030 * dma_mem points to start of the large DMA chunk 1031 */ 1032 dma_mem = &buf->mem; 1033 1034 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 1035 for (i = 0; i < count; i++) { 1036 buf = ((struct irdma_puda_buf *)buf_mem.va) + i; 1037 1038 buf->mem.va = (char *)dma_mem->va + (i * rsrc->buf_size); 1039 buf->mem.pa = dma_mem->pa + (i * rsrc->buf_size); 1040 buf->mem.size = rsrc->buf_size; 1041 buf->virtdma = virtdma; 1042 virtdma = true; 1043 1044 buf->buf_mem.va = buf_mem.va; 1045 buf->buf_mem.size = buf_mem.size; 1046 1047 list_add(&buf->list, &rsrc->bufpool); 1048 rsrc->alloc_buf_count++; 1049 if (!rsrc->alloclist) { 1050 rsrc->alloclist = buf; 1051 } else { 1052 nextbuf = rsrc->alloclist; 1053 rsrc->alloclist = buf; 1054 buf->next = nextbuf; 1055 } 1056 } 1057 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 1058 1059 rsrc->avail_buf_count = rsrc->alloc_buf_count; 1060 return 0; 1061 trysmall: 1062 for (i = 0; i < count; i++) { 1063 buf = irdma_puda_alloc_buf(rsrc->dev, rsrc->buf_size); 1064 if (!buf) { 1065 rsrc->stats_buf_alloc_fail++; 1066 return -ENOMEM; 1067 } 1068 irdma_puda_ret_bufpool(rsrc, buf); 1069 rsrc->alloc_buf_count++; 1070 if (!rsrc->alloclist) { 1071 rsrc->alloclist = buf; 1072 } else { 1073 nextbuf = rsrc->alloclist; 1074 rsrc->alloclist = buf; 1075 buf->next = nextbuf; 1076 } 1077 } 1078 1079 rsrc->avail_buf_count = rsrc->alloc_buf_count; 1080 1081 return 0; 1082 } 1083 1084 /** 1085 * irdma_puda_create_rsrc - create resource (ilq or ieq) 1086 * @vsi: sc VSI struct 1087 * @info: resource information 1088 */ 1089 int 1090 irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi, 1091 struct irdma_puda_rsrc_info *info) 1092 { 1093 struct irdma_sc_dev *dev = vsi->dev; 1094 int ret = 0; 1095 struct irdma_puda_rsrc *rsrc; 1096 u32 pudasize; 1097 u32 sqwridsize, rqwridsize; 1098 struct irdma_virt_mem *vmem; 1099 1100 info->count = 1; 1101 pudasize = sizeof(struct irdma_puda_rsrc); 1102 sqwridsize = info->sq_size * sizeof(struct irdma_sq_uk_wr_trk_info); 1103 rqwridsize = info->rq_size * 8; 1104 switch (info->type) { 1105 case IRDMA_PUDA_RSRC_TYPE_ILQ: 1106 vmem = &vsi->ilq_mem; 1107 break; 1108 case IRDMA_PUDA_RSRC_TYPE_IEQ: 1109 vmem = &vsi->ieq_mem; 1110 break; 1111 default: 1112 return -EOPNOTSUPP; 1113 } 1114 vmem->size = pudasize + sqwridsize + rqwridsize; 1115 vmem->va = kzalloc(vmem->size, GFP_KERNEL); 1116 if (!vmem->va) 1117 return -ENOMEM; 1118 1119 rsrc = vmem->va; 1120 spin_lock_init(&rsrc->bufpool_lock); 1121 switch (info->type) { 1122 case IRDMA_PUDA_RSRC_TYPE_ILQ: 1123 vsi->ilq = vmem->va; 1124 vsi->ilq_count = info->count; 1125 rsrc->receive = info->receive; 1126 rsrc->xmit_complete = info->xmit_complete; 1127 break; 1128 case IRDMA_PUDA_RSRC_TYPE_IEQ: 1129 vsi->ieq_count = info->count; 1130 vsi->ieq = vmem->va; 1131 rsrc->receive = irdma_ieq_receive; 1132 rsrc->xmit_complete = irdma_ieq_tx_compl; 1133 break; 1134 default: 1135 return -EOPNOTSUPP; 1136 } 1137 1138 rsrc->type = info->type; 1139 rsrc->sq_wrtrk_array = (struct irdma_sq_uk_wr_trk_info *) 1140 ((u8 *)vmem->va + pudasize); 1141 rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize); 1142 /* Initialize all ieq lists */ 1143 INIT_LIST_HEAD(&rsrc->bufpool); 1144 INIT_LIST_HEAD(&rsrc->txpend); 1145 1146 rsrc->tx_wqe_avail_cnt = info->sq_size - 1; 1147 irdma_sc_pd_init(dev, &rsrc->sc_pd, info->pd_id, info->abi_ver); 1148 rsrc->qp_id = info->qp_id; 1149 rsrc->cq_id = info->cq_id; 1150 rsrc->sq_size = info->sq_size; 1151 rsrc->rq_size = info->rq_size; 1152 rsrc->cq_size = info->rq_size + info->sq_size; 1153 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1154 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 1155 rsrc->cq_size += info->rq_size; 1156 } 1157 rsrc->buf_size = info->buf_size; 1158 rsrc->dev = dev; 1159 rsrc->vsi = vsi; 1160 rsrc->stats_idx = info->stats_idx; 1161 rsrc->stats_idx_valid = info->stats_idx_valid; 1162 1163 ret = irdma_puda_cq_create(rsrc); 1164 if (!ret) { 1165 rsrc->cmpl = PUDA_CQ_CREATED; 1166 ret = irdma_puda_qp_create(rsrc); 1167 } 1168 if (ret) { 1169 irdma_debug(dev, IRDMA_DEBUG_PUDA, 1170 "error qp_create type=%d, status=%d\n", rsrc->type, 1171 ret); 1172 goto error; 1173 } 1174 rsrc->cmpl = PUDA_QP_CREATED; 1175 1176 ret = irdma_puda_allocbufs(rsrc, info->tx_buf_cnt + info->rq_size); 1177 if (ret) { 1178 irdma_debug(dev, IRDMA_DEBUG_PUDA, "error alloc_buf\n"); 1179 goto error; 1180 } 1181 1182 rsrc->rxq_invalid_cnt = info->rq_size; 1183 ret = irdma_puda_replenish_rq(rsrc, true); 1184 if (ret) 1185 goto error; 1186 1187 if (info->type == IRDMA_PUDA_RSRC_TYPE_IEQ) { 1188 if (!irdma_init_hash_desc(&rsrc->hash_desc)) { 1189 rsrc->check_crc = true; 1190 rsrc->cmpl = PUDA_HASH_CRC_COMPLETE; 1191 ret = 0; 1192 } 1193 } 1194 1195 irdma_sc_ccq_arm(&rsrc->cq); 1196 return ret; 1197 1198 error: 1199 irdma_puda_dele_rsrc(vsi, info->type, false); 1200 1201 return ret; 1202 } 1203 1204 /** 1205 * irdma_ilq_putback_rcvbuf - ilq buffer to put back on rq 1206 * @qp: ilq's qp resource 1207 * @buf: puda buffer for rcv q 1208 * @wqe_idx: wqe index of completed rcvbuf 1209 */ 1210 static void 1211 irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, 1212 struct irdma_puda_buf *buf, u32 wqe_idx) 1213 { 1214 __le64 *wqe; 1215 u64 offset8, offset24; 1216 1217 /* Synch buffer for use by device */ 1218 dma_sync_single_for_device(hw_to_dev(qp->dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 1219 wqe = qp->qp_uk.rq_base[wqe_idx].elem; 1220 get_64bit_val(wqe, IRDMA_BYTE_24, &offset24); 1221 if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1222 get_64bit_val(wqe, IRDMA_BYTE_8, &offset8); 1223 if (offset24) 1224 offset8 &= ~FIELD_PREP(IRDMAQPSQ_VALID, 1); 1225 else 1226 offset8 |= FIELD_PREP(IRDMAQPSQ_VALID, 1); 1227 set_64bit_val(wqe, IRDMA_BYTE_8, offset8); 1228 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 1229 } 1230 if (offset24) 1231 offset24 = 0; 1232 else 1233 offset24 = FIELD_PREP(IRDMAQPSQ_VALID, 1); 1234 1235 set_64bit_val(wqe, IRDMA_BYTE_24, offset24); 1236 } 1237 1238 /** 1239 * irdma_ieq_get_fpdu_len - get length of fpdu with or without marker 1240 * @pfpdu: pointer to fpdu 1241 * @datap: pointer to data in the buffer 1242 * @rcv_seq: seqnum of the data buffer 1243 */ 1244 static u16 irdma_ieq_get_fpdu_len(struct irdma_pfpdu *pfpdu, u8 *datap, 1245 u32 rcv_seq){ 1246 u32 marker_seq, end_seq, blk_start; 1247 u8 marker_len = pfpdu->marker_len; 1248 u16 total_len = 0; 1249 u16 fpdu_len; 1250 1251 blk_start = (pfpdu->rcv_start_seq - rcv_seq) & (IRDMA_MRK_BLK_SZ - 1); 1252 if (!blk_start) { 1253 total_len = marker_len; 1254 marker_seq = rcv_seq + IRDMA_MRK_BLK_SZ; 1255 if (marker_len && *(u32 *)datap) 1256 return 0; 1257 } else { 1258 marker_seq = rcv_seq + blk_start; 1259 } 1260 1261 datap += total_len; 1262 fpdu_len = IRDMA_NTOHS(*(__be16 *) datap); 1263 fpdu_len += IRDMA_IEQ_MPA_FRAMING; 1264 fpdu_len = (fpdu_len + 3) & 0xfffc; 1265 1266 if (fpdu_len > pfpdu->max_fpdu_data) 1267 return 0; 1268 1269 total_len += fpdu_len; 1270 end_seq = rcv_seq + total_len; 1271 while ((int)(marker_seq - end_seq) < 0) { 1272 total_len += marker_len; 1273 end_seq += marker_len; 1274 marker_seq += IRDMA_MRK_BLK_SZ; 1275 } 1276 1277 return total_len; 1278 } 1279 1280 /** 1281 * irdma_ieq_copy_to_txbuf - copydata from rcv buf to tx buf 1282 * @buf: rcv buffer with partial 1283 * @txbuf: tx buffer for sending back 1284 * @buf_offset: rcv buffer offset to copy from 1285 * @txbuf_offset: at offset in tx buf to copy 1286 * @len: length of data to copy 1287 */ 1288 static void 1289 irdma_ieq_copy_to_txbuf(struct irdma_puda_buf *buf, 1290 struct irdma_puda_buf *txbuf, 1291 u16 buf_offset, u32 txbuf_offset, u32 len) 1292 { 1293 void *mem1 = (u8 *)buf->mem.va + buf_offset; 1294 void *mem2 = (u8 *)txbuf->mem.va + txbuf_offset; 1295 1296 irdma_memcpy(mem2, mem1, len); 1297 } 1298 1299 /** 1300 * irdma_ieq_setup_tx_buf - setup tx buffer for partial handling 1301 * @buf: reeive buffer with partial 1302 * @txbuf: buffer to prepare 1303 */ 1304 static void 1305 irdma_ieq_setup_tx_buf(struct irdma_puda_buf *buf, 1306 struct irdma_puda_buf *txbuf) 1307 { 1308 txbuf->tcphlen = buf->tcphlen; 1309 txbuf->ipv4 = buf->ipv4; 1310 1311 if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1312 txbuf->hdrlen = txbuf->tcphlen; 1313 irdma_ieq_copy_to_txbuf(buf, txbuf, IRDMA_TCP_OFFSET, 0, 1314 txbuf->hdrlen); 1315 } else { 1316 txbuf->maclen = buf->maclen; 1317 txbuf->hdrlen = buf->hdrlen; 1318 irdma_ieq_copy_to_txbuf(buf, txbuf, 0, 0, buf->hdrlen); 1319 } 1320 } 1321 1322 /** 1323 * irdma_ieq_check_first_buf - check if rcv buffer's seq is in range 1324 * @buf: receive exception buffer 1325 * @fps: first partial sequence number 1326 */ 1327 static void 1328 irdma_ieq_check_first_buf(struct irdma_puda_buf *buf, u32 fps) 1329 { 1330 u32 offset; 1331 1332 if (buf->seqnum < fps) { 1333 offset = fps - buf->seqnum; 1334 if (offset > buf->datalen) 1335 return; 1336 buf->data += offset; 1337 buf->datalen -= (u16)offset; 1338 buf->seqnum = fps; 1339 } 1340 } 1341 1342 /** 1343 * irdma_ieq_compl_pfpdu - write txbuf with full fpdu 1344 * @ieq: ieq resource 1345 * @rxlist: ieq's received buffer list 1346 * @pbufl: temporary list for buffers for fpddu 1347 * @txbuf: tx buffer for fpdu 1348 * @fpdu_len: total length of fpdu 1349 */ 1350 static void 1351 irdma_ieq_compl_pfpdu(struct irdma_puda_rsrc *ieq, 1352 struct list_head *rxlist, 1353 struct list_head *pbufl, 1354 struct irdma_puda_buf *txbuf, u16 fpdu_len) 1355 { 1356 struct irdma_puda_buf *buf; 1357 u32 nextseqnum; 1358 u16 txoffset, bufoffset; 1359 1360 buf = irdma_puda_get_listbuf(pbufl); 1361 if (!buf) 1362 return; 1363 1364 nextseqnum = buf->seqnum + fpdu_len; 1365 irdma_ieq_setup_tx_buf(buf, txbuf); 1366 if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1367 txoffset = txbuf->hdrlen; 1368 txbuf->totallen = txbuf->hdrlen + fpdu_len; 1369 txbuf->data = (u8 *)txbuf->mem.va + txoffset; 1370 } else { 1371 txoffset = buf->hdrlen; 1372 txbuf->totallen = buf->hdrlen + fpdu_len; 1373 txbuf->data = (u8 *)txbuf->mem.va + buf->hdrlen; 1374 } 1375 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); 1376 1377 do { 1378 if (buf->datalen >= fpdu_len) { 1379 /* copied full fpdu */ 1380 irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, 1381 fpdu_len); 1382 buf->datalen -= fpdu_len; 1383 buf->data += fpdu_len; 1384 buf->seqnum = nextseqnum; 1385 break; 1386 } 1387 /* copy partial fpdu */ 1388 irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, 1389 buf->datalen); 1390 txoffset += buf->datalen; 1391 fpdu_len -= buf->datalen; 1392 irdma_puda_ret_bufpool(ieq, buf); 1393 buf = irdma_puda_get_listbuf(pbufl); 1394 if (!buf) 1395 return; 1396 1397 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); 1398 } while (1); 1399 1400 /* last buffer on the list */ 1401 if (buf->datalen) 1402 list_add(&buf->list, rxlist); 1403 else 1404 irdma_puda_ret_bufpool(ieq, buf); 1405 } 1406 1407 /** 1408 * irdma_ieq_create_pbufl - create buffer list for single fpdu 1409 * @pfpdu: pointer to fpdu 1410 * @rxlist: resource list for receive ieq buffes 1411 * @pbufl: temp. list for buffers for fpddu 1412 * @buf: first receive buffer 1413 * @fpdu_len: total length of fpdu 1414 */ 1415 static int 1416 irdma_ieq_create_pbufl(struct irdma_pfpdu *pfpdu, 1417 struct list_head *rxlist, 1418 struct list_head *pbufl, 1419 struct irdma_puda_buf *buf, u16 fpdu_len) 1420 { 1421 int status = 0; 1422 struct irdma_puda_buf *nextbuf; 1423 u32 nextseqnum; 1424 u16 plen = fpdu_len - buf->datalen; 1425 bool done = false; 1426 1427 nextseqnum = buf->seqnum + buf->datalen; 1428 do { 1429 nextbuf = irdma_puda_get_listbuf(rxlist); 1430 if (!nextbuf) { 1431 status = -ENOBUFS; 1432 break; 1433 } 1434 list_add_tail(&nextbuf->list, pbufl); 1435 if (nextbuf->seqnum != nextseqnum) { 1436 pfpdu->bad_seq_num++; 1437 status = -ERANGE; 1438 break; 1439 } 1440 if (nextbuf->datalen >= plen) { 1441 done = true; 1442 } else { 1443 plen -= nextbuf->datalen; 1444 nextseqnum = nextbuf->seqnum + nextbuf->datalen; 1445 } 1446 1447 } while (!done); 1448 1449 return status; 1450 } 1451 1452 /** 1453 * irdma_ieq_handle_partial - process partial fpdu buffer 1454 * @ieq: ieq resource 1455 * @pfpdu: partial management per user qp 1456 * @buf: receive buffer 1457 * @fpdu_len: fpdu len in the buffer 1458 */ 1459 static int 1460 irdma_ieq_handle_partial(struct irdma_puda_rsrc *ieq, 1461 struct irdma_pfpdu *pfpdu, 1462 struct irdma_puda_buf *buf, u16 fpdu_len) 1463 { 1464 int status = 0; 1465 u8 *crcptr; 1466 u32 mpacrc; 1467 u32 seqnum = buf->seqnum; 1468 struct list_head pbufl; /* partial buffer list */ 1469 struct irdma_puda_buf *txbuf = NULL; 1470 struct list_head *rxlist = &pfpdu->rxlist; 1471 1472 ieq->partials_handled++; 1473 1474 INIT_LIST_HEAD(&pbufl); 1475 list_add(&buf->list, &pbufl); 1476 1477 status = irdma_ieq_create_pbufl(pfpdu, rxlist, &pbufl, buf, fpdu_len); 1478 if (status) 1479 goto error; 1480 1481 txbuf = irdma_puda_get_bufpool(ieq); 1482 if (!txbuf) { 1483 pfpdu->no_tx_bufs++; 1484 status = -ENOBUFS; 1485 goto error; 1486 } 1487 1488 irdma_ieq_compl_pfpdu(ieq, rxlist, &pbufl, txbuf, fpdu_len); 1489 irdma_ieq_update_tcpip_info(txbuf, fpdu_len, seqnum); 1490 1491 crcptr = txbuf->data + fpdu_len - 4; 1492 mpacrc = *(u32 *)crcptr; 1493 if (ieq->check_crc) { 1494 status = irdma_ieq_check_mpacrc(ieq->hash_desc, txbuf->data, 1495 (fpdu_len - 4), mpacrc); 1496 if (status) { 1497 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1498 "error bad crc\n"); 1499 pfpdu->mpa_crc_err = true; 1500 goto error; 1501 } 1502 } 1503 1504 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "IEQ TX BUFFER", 1505 txbuf->mem.va, txbuf->totallen); 1506 if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 1507 txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; 1508 txbuf->do_lpb = true; 1509 irdma_puda_send_buf(ieq, txbuf); 1510 pfpdu->rcv_nxt = seqnum + fpdu_len; 1511 return status; 1512 1513 error: 1514 while (!list_empty(&pbufl)) { 1515 buf = (struct irdma_puda_buf *)(&pbufl)->prev; 1516 list_move(&buf->list, rxlist); 1517 } 1518 if (txbuf) 1519 irdma_puda_ret_bufpool(ieq, txbuf); 1520 1521 return status; 1522 } 1523 1524 /** 1525 * irdma_ieq_process_buf - process buffer rcvd for ieq 1526 * @ieq: ieq resource 1527 * @pfpdu: partial management per user qp 1528 * @buf: receive buffer 1529 */ 1530 static int 1531 irdma_ieq_process_buf(struct irdma_puda_rsrc *ieq, 1532 struct irdma_pfpdu *pfpdu, 1533 struct irdma_puda_buf *buf) 1534 { 1535 u16 fpdu_len = 0; 1536 u16 datalen = buf->datalen; 1537 u8 *datap = buf->data; 1538 u8 *crcptr; 1539 u16 ioffset = 0; 1540 u32 mpacrc; 1541 u32 seqnum = buf->seqnum; 1542 u16 len = 0; 1543 u16 full = 0; 1544 bool partial = false; 1545 struct irdma_puda_buf *txbuf; 1546 struct list_head *rxlist = &pfpdu->rxlist; 1547 int ret = 0; 1548 1549 ioffset = (u16)(buf->data - (u8 *)buf->mem.va); 1550 while (datalen) { 1551 fpdu_len = irdma_ieq_get_fpdu_len(pfpdu, datap, buf->seqnum); 1552 if (!fpdu_len) { 1553 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1554 "error bad fpdu len\n"); 1555 list_add(&buf->list, rxlist); 1556 pfpdu->mpa_crc_err = true; 1557 return -EINVAL; 1558 } 1559 1560 if (datalen < fpdu_len) { 1561 partial = true; 1562 break; 1563 } 1564 crcptr = datap + fpdu_len - 4; 1565 mpacrc = *(u32 *)crcptr; 1566 if (ieq->check_crc) 1567 ret = irdma_ieq_check_mpacrc(ieq->hash_desc, datap, 1568 fpdu_len - 4, mpacrc); 1569 if (ret) { 1570 list_add(&buf->list, rxlist); 1571 irdma_debug(ieq->dev, IRDMA_DEBUG_ERR, 1572 "IRDMA_ERR_MPA_CRC\n"); 1573 pfpdu->mpa_crc_err = true; 1574 return ret; 1575 } 1576 full++; 1577 pfpdu->fpdu_processed++; 1578 ieq->fpdu_processed++; 1579 datap += fpdu_len; 1580 len += fpdu_len; 1581 datalen -= fpdu_len; 1582 } 1583 if (full) { 1584 /* copy full pdu's in the txbuf and send them out */ 1585 txbuf = irdma_puda_get_bufpool(ieq); 1586 if (!txbuf) { 1587 pfpdu->no_tx_bufs++; 1588 list_add(&buf->list, rxlist); 1589 return -ENOBUFS; 1590 } 1591 /* modify txbuf's buffer header */ 1592 irdma_ieq_setup_tx_buf(buf, txbuf); 1593 /* copy full fpdu's to new buffer */ 1594 if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1595 irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, 1596 txbuf->hdrlen, len); 1597 txbuf->totallen = txbuf->hdrlen + len; 1598 txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; 1599 } else { 1600 irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, 1601 buf->hdrlen, len); 1602 txbuf->totallen = buf->hdrlen + len; 1603 } 1604 irdma_ieq_update_tcpip_info(txbuf, len, buf->seqnum); 1605 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "IEQ TX BUFFER", 1606 txbuf->mem.va, txbuf->totallen); 1607 txbuf->do_lpb = true; 1608 irdma_puda_send_buf(ieq, txbuf); 1609 1610 if (!datalen) { 1611 pfpdu->rcv_nxt = buf->seqnum + len; 1612 irdma_puda_ret_bufpool(ieq, buf); 1613 return 0; 1614 } 1615 buf->data = datap; 1616 buf->seqnum = seqnum + len; 1617 buf->datalen = datalen; 1618 pfpdu->rcv_nxt = buf->seqnum; 1619 } 1620 if (partial) 1621 return irdma_ieq_handle_partial(ieq, pfpdu, buf, fpdu_len); 1622 1623 return 0; 1624 } 1625 1626 /** 1627 * irdma_ieq_process_fpdus - process fpdu's buffers on its list 1628 * @qp: qp for which partial fpdus 1629 * @ieq: ieq resource 1630 */ 1631 void 1632 irdma_ieq_process_fpdus(struct irdma_sc_qp *qp, 1633 struct irdma_puda_rsrc *ieq) 1634 { 1635 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1636 struct list_head *rxlist = &pfpdu->rxlist; 1637 struct irdma_puda_buf *buf; 1638 int status; 1639 1640 do { 1641 if (list_empty(rxlist)) 1642 break; 1643 buf = irdma_puda_get_listbuf(rxlist); 1644 if (!buf) { 1645 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1646 "error no buf\n"); 1647 break; 1648 } 1649 if (buf->seqnum != pfpdu->rcv_nxt) { 1650 /* This could be out of order or missing packet */ 1651 pfpdu->out_of_order++; 1652 list_add(&buf->list, rxlist); 1653 break; 1654 } 1655 /* keep processing buffers from the head of the list */ 1656 status = irdma_ieq_process_buf(ieq, pfpdu, buf); 1657 if (status && pfpdu->mpa_crc_err) { 1658 while (!list_empty(rxlist)) { 1659 buf = irdma_puda_get_listbuf(rxlist); 1660 irdma_puda_ret_bufpool(ieq, buf); 1661 pfpdu->crc_err++; 1662 ieq->crc_err++; 1663 } 1664 /* create CQP for AE */ 1665 irdma_ieq_mpa_crc_ae(ieq->dev, qp); 1666 } 1667 } while (!status); 1668 } 1669 1670 /** 1671 * irdma_ieq_create_ah - create an address handle for IEQ 1672 * @qp: qp pointer 1673 * @buf: buf received on IEQ used to create AH 1674 */ 1675 static int 1676 irdma_ieq_create_ah(struct irdma_sc_qp *qp, struct irdma_puda_buf *buf) 1677 { 1678 struct irdma_ah_info ah_info = {0}; 1679 1680 qp->pfpdu.ah_buf = buf; 1681 irdma_puda_ieq_get_ah_info(qp, &ah_info); 1682 return irdma_puda_create_ah(qp->vsi->dev, &ah_info, false, 1683 IRDMA_PUDA_RSRC_TYPE_IEQ, qp, 1684 &qp->pfpdu.ah); 1685 } 1686 1687 /** 1688 * irdma_ieq_handle_exception - handle qp's exception 1689 * @ieq: ieq resource 1690 * @qp: qp receiving excpetion 1691 * @buf: receive buffer 1692 */ 1693 static void 1694 irdma_ieq_handle_exception(struct irdma_puda_rsrc *ieq, 1695 struct irdma_sc_qp *qp, 1696 struct irdma_puda_buf *buf) 1697 { 1698 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1699 u32 *hw_host_ctx = (u32 *)qp->hw_host_ctx; 1700 u32 rcv_wnd = hw_host_ctx[23]; 1701 /* first partial seq # in q2 */ 1702 u32 fps = *(u32 *)(qp->q2_buf + Q2_FPSN_OFFSET); 1703 struct list_head *rxlist = &pfpdu->rxlist; 1704 struct list_head *plist; 1705 struct irdma_puda_buf *tmpbuf = NULL; 1706 unsigned long flags = 0; 1707 u8 hw_rev = qp->dev->hw_attrs.uk_attrs.hw_rev; 1708 1709 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "IEQ RX BUFFER", buf->mem.va, 1710 buf->totallen); 1711 1712 spin_lock_irqsave(&pfpdu->lock, flags); 1713 pfpdu->total_ieq_bufs++; 1714 if (pfpdu->mpa_crc_err) { 1715 pfpdu->crc_err++; 1716 goto error; 1717 } 1718 if (pfpdu->mode && fps != pfpdu->fps) { 1719 /* clean up qp as it is new partial sequence */ 1720 irdma_ieq_cleanup_qp(ieq, qp); 1721 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1722 "restarting new partial\n"); 1723 pfpdu->mode = false; 1724 } 1725 1726 if (!pfpdu->mode) { 1727 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "Q2 BUFFER", 1728 (u64 *)qp->q2_buf, 128); 1729 /* First_Partial_Sequence_Number check */ 1730 pfpdu->rcv_nxt = fps; 1731 pfpdu->fps = fps; 1732 pfpdu->mode = true; 1733 pfpdu->max_fpdu_data = (buf->ipv4) ? 1734 (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV4) : 1735 (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV6); 1736 pfpdu->pmode_count++; 1737 ieq->pmode_count++; 1738 INIT_LIST_HEAD(rxlist); 1739 irdma_ieq_check_first_buf(buf, fps); 1740 } 1741 1742 if (!(rcv_wnd >= (buf->seqnum - pfpdu->rcv_nxt))) { 1743 pfpdu->bad_seq_num++; 1744 ieq->bad_seq_num++; 1745 goto error; 1746 } 1747 1748 if (!list_empty(rxlist)) { 1749 tmpbuf = (struct irdma_puda_buf *)(rxlist)->next; 1750 while ((struct list_head *)tmpbuf != rxlist) { 1751 if (buf->seqnum == tmpbuf->seqnum) 1752 goto error; 1753 if ((int)(buf->seqnum - tmpbuf->seqnum) < 0) 1754 break; 1755 plist = &tmpbuf->list; 1756 tmpbuf = (struct irdma_puda_buf *)(plist)->next; 1757 } 1758 /* Insert buf before tmpbuf */ 1759 list_add_tail(&buf->list, &tmpbuf->list); 1760 } else { 1761 list_add_tail(&buf->list, rxlist); 1762 } 1763 pfpdu->nextseqnum = buf->seqnum + buf->datalen; 1764 pfpdu->lastrcv_buf = buf; 1765 if (hw_rev >= IRDMA_GEN_2 && !pfpdu->ah) { 1766 irdma_ieq_create_ah(qp, buf); 1767 if (!pfpdu->ah) 1768 goto error; 1769 goto exit; 1770 } 1771 if (hw_rev == IRDMA_GEN_1) 1772 irdma_ieq_process_fpdus(qp, ieq); 1773 else if (pfpdu->ah && pfpdu->ah->ah_info.ah_valid) 1774 irdma_ieq_process_fpdus(qp, ieq); 1775 exit: 1776 spin_unlock_irqrestore(&pfpdu->lock, flags); 1777 1778 return; 1779 1780 error: 1781 irdma_puda_ret_bufpool(ieq, buf); 1782 spin_unlock_irqrestore(&pfpdu->lock, flags); 1783 } 1784 1785 /** 1786 * irdma_ieq_receive - received exception buffer 1787 * @vsi: VSI of device 1788 * @buf: exception buffer received 1789 */ 1790 static void 1791 irdma_ieq_receive(struct irdma_sc_vsi *vsi, 1792 struct irdma_puda_buf *buf) 1793 { 1794 struct irdma_puda_rsrc *ieq = vsi->ieq; 1795 struct irdma_sc_qp *qp = NULL; 1796 u32 wqe_idx = ieq->compl_rxwqe_idx; 1797 1798 qp = irdma_ieq_get_qp(vsi->dev, buf); 1799 if (!qp) { 1800 ieq->stats_bad_qp_id++; 1801 irdma_puda_ret_bufpool(ieq, buf); 1802 } else { 1803 irdma_ieq_handle_exception(ieq, qp, buf); 1804 } 1805 /* 1806 * ieq->rx_wqe_idx is used by irdma_puda_replenish_rq() on which wqe_idx to start replenish rq 1807 */ 1808 if (!ieq->rxq_invalid_cnt) 1809 ieq->rx_wqe_idx = wqe_idx; 1810 ieq->rxq_invalid_cnt++; 1811 } 1812 1813 /** 1814 * irdma_ieq_tx_compl - put back after sending completed exception buffer 1815 * @vsi: sc VSI struct 1816 * @sqwrid: pointer to puda buffer 1817 */ 1818 static void 1819 irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid) 1820 { 1821 struct irdma_puda_rsrc *ieq = vsi->ieq; 1822 struct irdma_puda_buf *buf = sqwrid; 1823 1824 irdma_puda_ret_bufpool(ieq, buf); 1825 } 1826 1827 /** 1828 * irdma_ieq_cleanup_qp - qp is being destroyed 1829 * @ieq: ieq resource 1830 * @qp: all pending fpdu buffers 1831 */ 1832 void 1833 irdma_ieq_cleanup_qp(struct irdma_puda_rsrc *ieq, struct irdma_sc_qp *qp) 1834 { 1835 struct irdma_puda_buf *buf; 1836 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1837 struct list_head *rxlist = &pfpdu->rxlist; 1838 1839 if (qp->pfpdu.ah) { 1840 irdma_puda_free_ah(ieq->dev, qp->pfpdu.ah); 1841 qp->pfpdu.ah = NULL; 1842 qp->pfpdu.ah_buf = NULL; 1843 } 1844 1845 if (!pfpdu->mode) 1846 return; 1847 1848 while (!list_empty(rxlist)) { 1849 buf = irdma_puda_get_listbuf(rxlist); 1850 irdma_puda_ret_bufpool(ieq, buf); 1851 } 1852 } 1853