1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include "osdep.h" 36 #include "irdma_hmc.h" 37 #include "irdma_defs.h" 38 #include "irdma_type.h" 39 #include "irdma_protos.h" 40 #include "irdma_puda.h" 41 #include "irdma_ws.h" 42 43 static void 44 irdma_ieq_receive(struct irdma_sc_vsi *vsi, 45 struct irdma_puda_buf *buf); 46 static void irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid); 47 static void 48 irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, 49 struct irdma_puda_buf *buf, u32 wqe_idx); 50 /** 51 * irdma_puda_get_listbuf - get buffer from puda list 52 * @list: list to use for buffers (ILQ or IEQ) 53 */ 54 static struct irdma_puda_buf * 55 irdma_puda_get_listbuf(struct list_head *list) 56 { 57 struct irdma_puda_buf *buf = NULL; 58 59 if (!list_empty(list)) { 60 buf = (struct irdma_puda_buf *)(list)->next; 61 list_del((struct list_head *)&buf->list); 62 } 63 64 return buf; 65 } 66 67 /** 68 * irdma_puda_get_bufpool - return buffer from resource 69 * @rsrc: resource to use for buffer 70 */ 71 struct irdma_puda_buf * 72 irdma_puda_get_bufpool(struct irdma_puda_rsrc *rsrc) 73 { 74 struct irdma_puda_buf *buf = NULL; 75 struct list_head *list = &rsrc->bufpool; 76 unsigned long flags; 77 78 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 79 buf = irdma_puda_get_listbuf(list); 80 if (buf) { 81 rsrc->avail_buf_count--; 82 buf->vsi = rsrc->vsi; 83 } else { 84 rsrc->stats_buf_alloc_fail++; 85 } 86 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 87 88 return buf; 89 } 90 91 /** 92 * irdma_puda_ret_bufpool - return buffer to rsrc list 93 * @rsrc: resource to use for buffer 94 * @buf: buffer to return to resource 95 */ 96 void 97 irdma_puda_ret_bufpool(struct irdma_puda_rsrc *rsrc, 98 struct irdma_puda_buf *buf) 99 { 100 unsigned long flags; 101 102 buf->do_lpb = false; 103 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 104 list_add(&buf->list, &rsrc->bufpool); 105 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 106 rsrc->avail_buf_count++; 107 } 108 109 /** 110 * irdma_puda_post_recvbuf - set wqe for rcv buffer 111 * @rsrc: resource ptr 112 * @wqe_idx: wqe index to use 113 * @buf: puda buffer for rcv q 114 * @initial: flag if during init time 115 */ 116 static void 117 irdma_puda_post_recvbuf(struct irdma_puda_rsrc *rsrc, u32 wqe_idx, 118 struct irdma_puda_buf *buf, bool initial) 119 { 120 __le64 *wqe; 121 struct irdma_sc_qp *qp = &rsrc->qp; 122 u64 offset24 = 0; 123 124 /* Synch buffer for use by device */ 125 dma_sync_single_for_device(hw_to_dev(rsrc->dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 126 qp->qp_uk.rq_wrid_array[wqe_idx] = (uintptr_t)buf; 127 wqe = qp->qp_uk.rq_base[wqe_idx].elem; 128 if (!initial) 129 get_64bit_val(wqe, IRDMA_BYTE_24, &offset24); 130 131 offset24 = (offset24) ? 0 : FIELD_PREP(IRDMAQPSQ_VALID, 1); 132 133 set_64bit_val(wqe, IRDMA_BYTE_16, 0); 134 set_64bit_val(wqe, 0, buf->mem.pa); 135 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 136 set_64bit_val(wqe, IRDMA_BYTE_8, 137 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, buf->mem.size)); 138 } else { 139 set_64bit_val(wqe, IRDMA_BYTE_8, 140 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, buf->mem.size) | 141 offset24); 142 } 143 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 144 145 set_64bit_val(wqe, IRDMA_BYTE_24, offset24); 146 } 147 148 /** 149 * irdma_puda_replenish_rq - post rcv buffers 150 * @rsrc: resource to use for buffer 151 * @initial: flag if during init time 152 */ 153 static int 154 irdma_puda_replenish_rq(struct irdma_puda_rsrc *rsrc, bool initial) 155 { 156 u32 i; 157 u32 invalid_cnt = rsrc->rxq_invalid_cnt; 158 struct irdma_puda_buf *buf = NULL; 159 160 for (i = 0; i < invalid_cnt; i++) { 161 buf = irdma_puda_get_bufpool(rsrc); 162 if (!buf) 163 return -ENOBUFS; 164 irdma_puda_post_recvbuf(rsrc, rsrc->rx_wqe_idx, buf, initial); 165 rsrc->rx_wqe_idx = ((rsrc->rx_wqe_idx + 1) % rsrc->rq_size); 166 rsrc->rxq_invalid_cnt--; 167 } 168 169 return 0; 170 } 171 172 /** 173 * irdma_puda_alloc_buf - allocate mem for buffer 174 * @dev: iwarp device 175 * @len: length of buffer 176 */ 177 static struct irdma_puda_buf * 178 irdma_puda_alloc_buf(struct irdma_sc_dev *dev, 179 u32 len) 180 { 181 struct irdma_puda_buf *buf; 182 struct irdma_virt_mem buf_mem; 183 184 buf_mem.size = sizeof(struct irdma_puda_buf); 185 buf_mem.va = kzalloc(buf_mem.size, GFP_KERNEL); 186 if (!buf_mem.va) 187 return NULL; 188 189 buf = buf_mem.va; 190 buf->mem.size = len; 191 buf->mem.va = kzalloc(buf->mem.size, GFP_KERNEL); 192 if (!buf->mem.va) 193 goto free_virt; 194 buf->mem.pa = dma_map_single(hw_to_dev(dev->hw), buf->mem.va, buf->mem.size, DMA_BIDIRECTIONAL); 195 if (dma_mapping_error(hw_to_dev(dev->hw), buf->mem.pa)) { 196 kfree(buf->mem.va); 197 goto free_virt; 198 } 199 200 buf->buf_mem.va = buf_mem.va; 201 buf->buf_mem.size = buf_mem.size; 202 203 return buf; 204 205 free_virt: 206 kfree(buf_mem.va); 207 return NULL; 208 } 209 210 /** 211 * irdma_puda_dele_buf - delete buffer back to system 212 * @dev: iwarp device 213 * @buf: buffer to free 214 */ 215 static void 216 irdma_puda_dele_buf(struct irdma_sc_dev *dev, 217 struct irdma_puda_buf *buf) 218 { 219 if (!buf->virtdma) { 220 irdma_free_dma_mem(dev->hw, &buf->mem); 221 kfree(buf->buf_mem.va); 222 } 223 } 224 225 /** 226 * irdma_puda_get_next_send_wqe - return next wqe for processing 227 * @qp: puda qp for wqe 228 * @wqe_idx: wqe index for caller 229 */ 230 static __le64 * irdma_puda_get_next_send_wqe(struct irdma_qp_uk *qp, 231 u32 *wqe_idx){ 232 int ret_code = 0; 233 234 *wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); 235 if (!*wqe_idx) 236 qp->swqe_polarity = !qp->swqe_polarity; 237 IRDMA_RING_MOVE_HEAD(qp->sq_ring, ret_code); 238 if (ret_code) 239 return NULL; 240 241 return qp->sq_base[*wqe_idx].elem; 242 } 243 244 /** 245 * irdma_puda_poll_info - poll cq for completion 246 * @cq: cq for poll 247 * @info: info return for successful completion 248 */ 249 static int 250 irdma_puda_poll_info(struct irdma_sc_cq *cq, 251 struct irdma_puda_cmpl_info *info) 252 { 253 struct irdma_cq_uk *cq_uk = &cq->cq_uk; 254 u64 qword0, qword2, qword3, qword6; 255 __le64 *cqe; 256 __le64 *ext_cqe = NULL; 257 u64 qword7 = 0; 258 u64 comp_ctx; 259 bool valid_bit; 260 bool ext_valid = 0; 261 u32 major_err, minor_err; 262 u32 peek_head; 263 bool error; 264 u8 polarity; 265 266 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&cq->cq_uk); 267 get_64bit_val(cqe, IRDMA_BYTE_24, &qword3); 268 valid_bit = (bool)FIELD_GET(IRDMA_CQ_VALID, qword3); 269 if (valid_bit != cq_uk->polarity) 270 return -ENOENT; 271 272 if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 273 ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); 274 275 if (ext_valid) { 276 peek_head = (cq_uk->cq_ring.head + 1) % cq_uk->cq_ring.size; 277 ext_cqe = cq_uk->cq_base[peek_head].buf; 278 get_64bit_val(ext_cqe, IRDMA_BYTE_24, &qword7); 279 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); 280 if (!peek_head) 281 polarity ^= 1; 282 if (polarity != cq_uk->polarity) 283 return -ENOENT; 284 285 IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); 286 if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) 287 cq_uk->polarity = !cq_uk->polarity; 288 /* update cq tail in cq shadow memory also */ 289 IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); 290 } 291 292 irdma_debug_buf(cq->dev, IRDMA_DEBUG_PUDA, "PUDA CQE", cqe, 32); 293 if (ext_valid) 294 irdma_debug_buf(cq->dev, IRDMA_DEBUG_PUDA, "PUDA EXT-CQE", 295 ext_cqe, 32); 296 297 error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); 298 if (error) { 299 irdma_debug(cq->dev, IRDMA_DEBUG_PUDA, "receive error\n"); 300 major_err = (u32)(FIELD_GET(IRDMA_CQ_MAJERR, qword3)); 301 minor_err = (u32)(FIELD_GET(IRDMA_CQ_MINERR, qword3)); 302 info->compl_error = major_err << 16 | minor_err; 303 return -EIO; 304 } 305 306 get_64bit_val(cqe, IRDMA_BYTE_0, &qword0); 307 get_64bit_val(cqe, IRDMA_BYTE_16, &qword2); 308 309 info->q_type = (u8)FIELD_GET(IRDMA_CQ_SQ, qword3); 310 info->qp_id = (u32)FIELD_GET(IRDMACQ_QPID, qword2); 311 if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 312 info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); 313 314 get_64bit_val(cqe, IRDMA_BYTE_8, &comp_ctx); 315 info->qp = (struct irdma_qp_uk *)(irdma_uintptr) comp_ctx; 316 info->wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); 317 318 if (info->q_type == IRDMA_CQE_QTYPE_RQ) { 319 if (ext_valid) { 320 info->vlan_valid = (bool)FIELD_GET(IRDMA_CQ_UDVLANVALID, qword7); 321 if (info->vlan_valid) { 322 get_64bit_val(ext_cqe, IRDMA_BYTE_16, &qword6); 323 info->vlan = (u16)FIELD_GET(IRDMA_CQ_UDVLAN, qword6); 324 } 325 info->smac_valid = (bool)FIELD_GET(IRDMA_CQ_UDSMACVALID, qword7); 326 if (info->smac_valid) { 327 get_64bit_val(ext_cqe, IRDMA_BYTE_16, &qword6); 328 info->smac[0] = (u8)((qword6 >> 40) & 0xFF); 329 info->smac[1] = (u8)((qword6 >> 32) & 0xFF); 330 info->smac[2] = (u8)((qword6 >> 24) & 0xFF); 331 info->smac[3] = (u8)((qword6 >> 16) & 0xFF); 332 info->smac[4] = (u8)((qword6 >> 8) & 0xFF); 333 info->smac[5] = (u8)(qword6 & 0xFF); 334 } 335 } 336 337 if (cq->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 338 info->vlan_valid = (bool)FIELD_GET(IRDMA_VLAN_TAG_VALID, qword3); 339 info->l4proto = (u8)FIELD_GET(IRDMA_UDA_L4PROTO, qword2); 340 info->l3proto = (u8)FIELD_GET(IRDMA_UDA_L3PROTO, qword2); 341 } 342 343 info->payload_len = (u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); 344 } 345 346 return 0; 347 } 348 349 /** 350 * irdma_puda_poll_cmpl - processes completion for cq 351 * @dev: iwarp device 352 * @cq: cq getting interrupt 353 * @compl_err: return any completion err 354 */ 355 int 356 irdma_puda_poll_cmpl(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq, 357 u32 *compl_err) 358 { 359 struct irdma_qp_uk *qp; 360 struct irdma_cq_uk *cq_uk = &cq->cq_uk; 361 struct irdma_puda_cmpl_info info = {0}; 362 int ret = 0; 363 struct irdma_puda_buf *buf; 364 struct irdma_puda_rsrc *rsrc; 365 u8 cq_type = cq->cq_type; 366 unsigned long flags; 367 368 if (cq_type == IRDMA_CQ_TYPE_ILQ || cq_type == IRDMA_CQ_TYPE_IEQ) { 369 rsrc = (cq_type == IRDMA_CQ_TYPE_ILQ) ? cq->vsi->ilq : 370 cq->vsi->ieq; 371 } else { 372 irdma_debug(dev, IRDMA_DEBUG_PUDA, "qp_type error\n"); 373 return -EFAULT; 374 } 375 376 ret = irdma_puda_poll_info(cq, &info); 377 *compl_err = info.compl_error; 378 if (ret == -ENOENT) 379 return ret; 380 if (ret) 381 goto done; 382 383 qp = info.qp; 384 if (!qp || !rsrc) { 385 ret = -EFAULT; 386 goto done; 387 } 388 389 if (qp->qp_id != rsrc->qp_id) { 390 ret = -EFAULT; 391 goto done; 392 } 393 394 if (info.q_type == IRDMA_CQE_QTYPE_RQ) { 395 buf = (struct irdma_puda_buf *)(uintptr_t) 396 qp->rq_wrid_array[info.wqe_idx]; 397 398 /* reusing so synch the buffer for CPU use */ 399 dma_sync_single_for_cpu(hw_to_dev(dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 400 /* Get all the tcpip information in the buf header */ 401 ret = irdma_puda_get_tcpip_info(&info, buf); 402 if (ret) { 403 rsrc->stats_rcvd_pkt_err++; 404 if (cq_type == IRDMA_CQ_TYPE_ILQ) { 405 irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, 406 info.wqe_idx); 407 } else { 408 irdma_puda_ret_bufpool(rsrc, buf); 409 irdma_puda_replenish_rq(rsrc, false); 410 } 411 goto done; 412 } 413 414 rsrc->stats_pkt_rcvd++; 415 rsrc->compl_rxwqe_idx = info.wqe_idx; 416 irdma_debug(dev, IRDMA_DEBUG_PUDA, "RQ completion\n"); 417 rsrc->receive(rsrc->vsi, buf); 418 if (cq_type == IRDMA_CQ_TYPE_ILQ) 419 irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, info.wqe_idx); 420 else 421 irdma_puda_replenish_rq(rsrc, false); 422 423 } else { 424 irdma_debug(dev, IRDMA_DEBUG_PUDA, "SQ completion\n"); 425 buf = (struct irdma_puda_buf *)(uintptr_t) 426 qp->sq_wrtrk_array[info.wqe_idx].wrid; 427 428 /* reusing so synch the buffer for CPU use */ 429 dma_sync_single_for_cpu(hw_to_dev(dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 430 IRDMA_RING_SET_TAIL(qp->sq_ring, info.wqe_idx); 431 rsrc->xmit_complete(rsrc->vsi, buf); 432 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 433 rsrc->tx_wqe_avail_cnt++; 434 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 435 if (!list_empty(&rsrc->txpend)) 436 irdma_puda_send_buf(rsrc, NULL); 437 } 438 439 done: 440 IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); 441 if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) 442 cq_uk->polarity = !cq_uk->polarity; 443 /* update cq tail in cq shadow memory also */ 444 IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); 445 set_64bit_val(cq_uk->shadow_area, IRDMA_BYTE_0, 446 IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)); 447 448 return ret; 449 } 450 451 /** 452 * irdma_puda_send - complete send wqe for transmit 453 * @qp: puda qp for send 454 * @info: buffer information for transmit 455 */ 456 int 457 irdma_puda_send(struct irdma_sc_qp *qp, struct irdma_puda_send_info *info) 458 { 459 __le64 *wqe; 460 u32 iplen, l4len; 461 u64 hdr[2]; 462 u32 wqe_idx; 463 u8 iipt; 464 465 /* number of 32 bits DWORDS in header */ 466 l4len = info->tcplen >> 2; 467 if (info->ipv4) { 468 iipt = 3; 469 iplen = 5; 470 } else { 471 iipt = 1; 472 iplen = 10; 473 } 474 475 wqe = irdma_puda_get_next_send_wqe(&qp->qp_uk, &wqe_idx); 476 if (!wqe) 477 return -ENOSPC; 478 479 qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid = (uintptr_t)info->scratch; 480 /* Third line of WQE descriptor */ 481 /* maclen is in words */ 482 483 if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 484 hdr[0] = 0; /* Dest_QPN and Dest_QKey only for UD */ 485 hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | 486 FIELD_PREP(IRDMA_UDA_QPSQ_L4LEN, l4len) | 487 FIELD_PREP(IRDMAQPSQ_AHID, info->ah_id) | 488 FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | 489 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, 490 qp->qp_uk.swqe_polarity); 491 492 /* Forth line of WQE descriptor */ 493 494 set_64bit_val(wqe, IRDMA_BYTE_0, info->paddr); 495 set_64bit_val(wqe, IRDMA_BYTE_8, 496 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, info->len) | 497 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity)); 498 } else { 499 hdr[0] = FIELD_PREP(IRDMA_UDA_QPSQ_MACLEN, info->maclen >> 1) | 500 FIELD_PREP(IRDMA_UDA_QPSQ_IPLEN, iplen) | 501 FIELD_PREP(IRDMA_UDA_QPSQ_L4T, 1) | 502 FIELD_PREP(IRDMA_UDA_QPSQ_IIPT, iipt) | 503 FIELD_PREP(IRDMA_GEN1_UDA_QPSQ_L4LEN, l4len); 504 505 hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | 506 FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | 507 FIELD_PREP(IRDMA_UDA_QPSQ_DOLOOPBACK, info->do_lpb) | 508 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity); 509 510 /* Forth line of WQE descriptor */ 511 512 set_64bit_val(wqe, IRDMA_BYTE_0, info->paddr); 513 set_64bit_val(wqe, IRDMA_BYTE_8, 514 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, info->len)); 515 } 516 517 set_64bit_val(wqe, IRDMA_BYTE_16, hdr[0]); 518 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 519 520 set_64bit_val(wqe, IRDMA_BYTE_24, hdr[1]); 521 522 irdma_debug_buf(qp->dev, IRDMA_DEBUG_PUDA, "PUDA SEND WQE", wqe, 32); 523 irdma_uk_qp_post_wr(&qp->qp_uk); 524 return 0; 525 } 526 527 /** 528 * irdma_puda_send_buf - transmit puda buffer 529 * @rsrc: resource to use for buffer 530 * @buf: puda buffer to transmit 531 */ 532 void 533 irdma_puda_send_buf(struct irdma_puda_rsrc *rsrc, 534 struct irdma_puda_buf *buf) 535 { 536 struct irdma_puda_send_info info; 537 int ret = 0; 538 unsigned long flags; 539 540 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 541 /* 542 * if no wqe available or not from a completion and we have pending buffers, we must queue new buffer 543 */ 544 if (!rsrc->tx_wqe_avail_cnt || (buf && !list_empty(&rsrc->txpend))) { 545 list_add_tail(&buf->list, &rsrc->txpend); 546 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 547 rsrc->stats_sent_pkt_q++; 548 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 549 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 550 "adding to txpend\n"); 551 return; 552 } 553 rsrc->tx_wqe_avail_cnt--; 554 /* 555 * if we are coming from a completion and have pending buffers then Get one from pending list 556 */ 557 if (!buf) { 558 buf = irdma_puda_get_listbuf(&rsrc->txpend); 559 if (!buf) 560 goto done; 561 } 562 563 info.scratch = buf; 564 info.paddr = buf->mem.pa; 565 info.len = buf->totallen; 566 info.tcplen = buf->tcphlen; 567 info.ipv4 = buf->ipv4; 568 569 if (rsrc->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 570 info.ah_id = buf->ah_id; 571 } else { 572 info.maclen = buf->maclen; 573 info.do_lpb = buf->do_lpb; 574 } 575 576 /* Synch buffer for use by device */ 577 dma_sync_single_for_cpu(hw_to_dev(rsrc->dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 578 ret = irdma_puda_send(&rsrc->qp, &info); 579 if (ret) { 580 rsrc->tx_wqe_avail_cnt++; 581 rsrc->stats_sent_pkt_q++; 582 list_add(&buf->list, &rsrc->txpend); 583 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 584 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 585 "adding to puda_send\n"); 586 } else { 587 rsrc->stats_pkt_sent++; 588 } 589 done: 590 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 591 } 592 593 /** 594 * irdma_puda_qp_setctx - during init, set qp's context 595 * @rsrc: qp's resource 596 */ 597 static void 598 irdma_puda_qp_setctx(struct irdma_puda_rsrc *rsrc) 599 { 600 struct irdma_sc_qp *qp = &rsrc->qp; 601 __le64 *qp_ctx = qp->hw_host_ctx; 602 603 set_64bit_val(qp_ctx, IRDMA_BYTE_8, qp->sq_pa); 604 set_64bit_val(qp_ctx, IRDMA_BYTE_16, qp->rq_pa); 605 set_64bit_val(qp_ctx, IRDMA_BYTE_24, 606 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 607 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size)); 608 set_64bit_val(qp_ctx, IRDMA_BYTE_48, 609 FIELD_PREP(IRDMAQPC_SNDMSS, rsrc->buf_size)); 610 set_64bit_val(qp_ctx, IRDMA_BYTE_56, 0); 611 if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 612 set_64bit_val(qp_ctx, IRDMA_BYTE_64, 1); 613 set_64bit_val(qp_ctx, IRDMA_BYTE_136, 614 FIELD_PREP(IRDMAQPC_TXCQNUM, rsrc->cq_id) | 615 FIELD_PREP(IRDMAQPC_RXCQNUM, rsrc->cq_id)); 616 set_64bit_val(qp_ctx, IRDMA_BYTE_144, 617 FIELD_PREP(IRDMAQPC_STAT_INDEX, rsrc->stats_idx)); 618 set_64bit_val(qp_ctx, IRDMA_BYTE_160, 619 FIELD_PREP(IRDMAQPC_PRIVEN, 1) | 620 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, rsrc->stats_idx_valid)); 621 set_64bit_val(qp_ctx, IRDMA_BYTE_168, 622 FIELD_PREP(IRDMAQPC_QPCOMPCTX, (uintptr_t)qp)); 623 set_64bit_val(qp_ctx, IRDMA_BYTE_176, 624 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 625 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 626 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 627 628 irdma_debug_buf(rsrc->dev, IRDMA_DEBUG_PUDA, "PUDA QP CONTEXT", qp_ctx, 629 IRDMA_QP_CTX_SIZE); 630 } 631 632 /** 633 * irdma_puda_qp_wqe - setup wqe for qp create 634 * @dev: Device 635 * @qp: Resource qp 636 */ 637 static int 638 irdma_puda_qp_wqe(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp) 639 { 640 struct irdma_sc_cqp *cqp; 641 __le64 *wqe; 642 u64 hdr; 643 struct irdma_ccq_cqe_info compl_info; 644 int status = 0; 645 646 cqp = dev->cqp; 647 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); 648 if (!wqe) 649 return -ENOSPC; 650 651 set_64bit_val(wqe, IRDMA_BYTE_16, qp->hw_host_ctx_pa); 652 set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa); 653 654 hdr = qp->qp_uk.qp_id | 655 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | 656 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, IRDMA_QP_TYPE_UDA) | 657 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, 1) | 658 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, 2) | 659 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 660 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 661 662 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 663 664 irdma_debug_buf(cqp->dev, IRDMA_DEBUG_PUDA, "PUDA QP CREATE", wqe, 40); 665 irdma_sc_cqp_post_sq(cqp); 666 status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_QP, 667 &compl_info); 668 669 return status; 670 } 671 672 /** 673 * irdma_puda_qp_create - create qp for resource 674 * @rsrc: resource to use for buffer 675 */ 676 static int 677 irdma_puda_qp_create(struct irdma_puda_rsrc *rsrc) 678 { 679 struct irdma_sc_qp *qp = &rsrc->qp; 680 struct irdma_qp_uk *ukqp = &qp->qp_uk; 681 int ret = 0; 682 u32 sq_size, rq_size; 683 struct irdma_dma_mem *mem; 684 685 sq_size = rsrc->sq_size * IRDMA_QP_WQE_MIN_SIZE; 686 rq_size = rsrc->rq_size * IRDMA_QP_WQE_MIN_SIZE; 687 rsrc->qpmem.size = (sq_size + rq_size + (IRDMA_SHADOW_AREA_SIZE << 3) + 688 IRDMA_QP_CTX_SIZE); 689 rsrc->qpmem.va = irdma_allocate_dma_mem(rsrc->dev->hw, &rsrc->qpmem, 690 rsrc->qpmem.size, IRDMA_HW_PAGE_SIZE); 691 if (!rsrc->qpmem.va) 692 return -ENOMEM; 693 694 mem = &rsrc->qpmem; 695 memset(mem->va, 0, rsrc->qpmem.size); 696 qp->hw_sq_size = irdma_get_encoded_wqe_size(rsrc->sq_size, IRDMA_QUEUE_TYPE_SQ_RQ); 697 qp->hw_rq_size = irdma_get_encoded_wqe_size(rsrc->rq_size, IRDMA_QUEUE_TYPE_SQ_RQ); 698 qp->pd = &rsrc->sc_pd; 699 qp->qp_uk.qp_type = IRDMA_QP_TYPE_UDA; 700 qp->dev = rsrc->dev; 701 qp->qp_uk.back_qp = rsrc; 702 qp->sq_pa = mem->pa; 703 qp->rq_pa = qp->sq_pa + sq_size; 704 qp->vsi = rsrc->vsi; 705 ukqp->sq_base = mem->va; 706 ukqp->rq_base = &ukqp->sq_base[rsrc->sq_size]; 707 ukqp->shadow_area = ukqp->rq_base[rsrc->rq_size].elem; 708 ukqp->uk_attrs = &qp->dev->hw_attrs.uk_attrs; 709 qp->shadow_area_pa = qp->rq_pa + rq_size; 710 qp->hw_host_ctx = ukqp->shadow_area + IRDMA_SHADOW_AREA_SIZE; 711 qp->hw_host_ctx_pa = qp->shadow_area_pa + (IRDMA_SHADOW_AREA_SIZE << 3); 712 qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; 713 ukqp->qp_id = rsrc->qp_id; 714 ukqp->sq_wrtrk_array = rsrc->sq_wrtrk_array; 715 ukqp->rq_wrid_array = rsrc->rq_wrid_array; 716 ukqp->sq_size = rsrc->sq_size; 717 ukqp->rq_size = rsrc->rq_size; 718 719 IRDMA_RING_INIT(ukqp->sq_ring, ukqp->sq_size); 720 IRDMA_RING_INIT(ukqp->initial_ring, ukqp->sq_size); 721 IRDMA_RING_INIT(ukqp->rq_ring, ukqp->rq_size); 722 ukqp->wqe_alloc_db = qp->pd->dev->wqe_alloc_db; 723 724 ret = rsrc->dev->ws_add(qp->vsi, qp->user_pri); 725 if (ret) { 726 irdma_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem); 727 return ret; 728 } 729 730 irdma_qp_add_qos(qp); 731 irdma_puda_qp_setctx(rsrc); 732 733 if (rsrc->dev->ceq_valid) 734 ret = irdma_cqp_qp_create_cmd(rsrc->dev, qp); 735 else 736 ret = irdma_puda_qp_wqe(rsrc->dev, qp); 737 if (ret) { 738 irdma_qp_rem_qos(qp); 739 rsrc->dev->ws_remove(qp->vsi, qp->user_pri); 740 irdma_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem); 741 } 742 743 return ret; 744 } 745 746 /** 747 * irdma_puda_cq_wqe - setup wqe for CQ create 748 * @dev: Device 749 * @cq: resource for cq 750 */ 751 static int 752 irdma_puda_cq_wqe(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq) 753 { 754 __le64 *wqe; 755 struct irdma_sc_cqp *cqp; 756 u64 hdr; 757 struct irdma_ccq_cqe_info compl_info; 758 int status = 0; 759 760 cqp = dev->cqp; 761 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); 762 if (!wqe) 763 return -ENOSPC; 764 765 set_64bit_val(wqe, IRDMA_BYTE_0, cq->cq_uk.cq_size); 766 set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1)); 767 set_64bit_val(wqe, IRDMA_BYTE_16, 768 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold)); 769 set_64bit_val(wqe, IRDMA_BYTE_32, cq->cq_pa); 770 set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa); 771 set_64bit_val(wqe, IRDMA_BYTE_56, 772 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 773 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 774 775 hdr = cq->cq_uk.cq_id | 776 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | 777 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, 1) | 778 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, 1) | 779 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, 1) | 780 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 781 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 782 783 set_64bit_val(wqe, IRDMA_BYTE_24, hdr); 784 785 irdma_debug_buf(dev, IRDMA_DEBUG_PUDA, "PUDA CREATE CQ", wqe, 786 IRDMA_CQP_WQE_SIZE * 8); 787 irdma_sc_cqp_post_sq(dev->cqp); 788 status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_CQ, 789 &compl_info); 790 if (!status) { 791 struct irdma_sc_ceq *ceq = dev->ceq[0]; 792 793 if (ceq && ceq->reg_cq) 794 status = irdma_sc_add_cq_ctx(ceq, cq); 795 } 796 797 return status; 798 } 799 800 /** 801 * irdma_puda_cq_create - create cq for resource 802 * @rsrc: resource for which cq to create 803 */ 804 static int 805 irdma_puda_cq_create(struct irdma_puda_rsrc *rsrc) 806 { 807 struct irdma_sc_dev *dev = rsrc->dev; 808 struct irdma_sc_cq *cq = &rsrc->cq; 809 int ret = 0; 810 u32 cqsize; 811 struct irdma_dma_mem *mem; 812 struct irdma_cq_init_info info = {0}; 813 struct irdma_cq_uk_init_info *init_info = &info.cq_uk_init_info; 814 815 cq->vsi = rsrc->vsi; 816 cqsize = rsrc->cq_size * (sizeof(struct irdma_cqe)); 817 rsrc->cqmem.size = cqsize + sizeof(struct irdma_cq_shadow_area); 818 rsrc->cqmem.va = irdma_allocate_dma_mem(dev->hw, &rsrc->cqmem, 819 rsrc->cqmem.size, 820 IRDMA_CQ0_ALIGNMENT); 821 if (!rsrc->cqmem.va) 822 return -ENOMEM; 823 824 mem = &rsrc->cqmem; 825 info.dev = dev; 826 info.type = (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) ? 827 IRDMA_CQ_TYPE_ILQ : IRDMA_CQ_TYPE_IEQ; 828 info.shadow_read_threshold = rsrc->cq_size >> 2; 829 info.cq_base_pa = mem->pa; 830 info.shadow_area_pa = mem->pa + cqsize; 831 init_info->cq_base = mem->va; 832 init_info->shadow_area = (__le64 *) ((u8 *)mem->va + cqsize); 833 init_info->cq_size = rsrc->cq_size; 834 init_info->cq_id = rsrc->cq_id; 835 info.ceqe_mask = true; 836 info.ceq_id_valid = true; 837 info.vsi = rsrc->vsi; 838 839 ret = irdma_sc_cq_init(cq, &info); 840 if (ret) 841 goto error; 842 843 if (rsrc->dev->ceq_valid) 844 ret = irdma_cqp_cq_create_cmd(dev, cq); 845 else 846 ret = irdma_puda_cq_wqe(dev, cq); 847 error: 848 if (ret) 849 irdma_free_dma_mem(dev->hw, &rsrc->cqmem); 850 851 return ret; 852 } 853 854 /** 855 * irdma_puda_free_qp - free qp for resource 856 * @rsrc: resource for which qp to free 857 */ 858 static void 859 irdma_puda_free_qp(struct irdma_puda_rsrc *rsrc) 860 { 861 int ret; 862 struct irdma_ccq_cqe_info compl_info; 863 struct irdma_sc_dev *dev = rsrc->dev; 864 865 if (rsrc->dev->ceq_valid) { 866 irdma_cqp_qp_destroy_cmd(dev, &rsrc->qp); 867 rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); 868 return; 869 } 870 871 ret = irdma_sc_qp_destroy(&rsrc->qp, 0, false, true, true); 872 if (ret) 873 irdma_debug(dev, IRDMA_DEBUG_PUDA, 874 "error puda qp destroy wqe, status = %d\n", ret); 875 if (!ret) { 876 ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_QP, 877 &compl_info); 878 if (ret) 879 irdma_debug(dev, IRDMA_DEBUG_PUDA, 880 "error puda qp destroy failed, status = %d\n", 881 ret); 882 } 883 rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); 884 } 885 886 /** 887 * irdma_puda_free_cq - free cq for resource 888 * @rsrc: resource for which cq to free 889 */ 890 static void 891 irdma_puda_free_cq(struct irdma_puda_rsrc *rsrc) 892 { 893 int ret; 894 struct irdma_ccq_cqe_info compl_info; 895 struct irdma_sc_dev *dev = rsrc->dev; 896 897 if (rsrc->dev->ceq_valid) { 898 irdma_cqp_cq_destroy_cmd(dev, &rsrc->cq); 899 return; 900 } 901 902 ret = irdma_sc_cq_destroy(&rsrc->cq, 0, true); 903 if (ret) 904 irdma_debug(dev, IRDMA_DEBUG_PUDA, "error ieq cq destroy\n"); 905 if (!ret) { 906 ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_CQ, 907 &compl_info); 908 if (ret) 909 irdma_debug(dev, IRDMA_DEBUG_PUDA, 910 "error ieq qp destroy done\n"); 911 } 912 } 913 914 /** 915 * irdma_puda_dele_rsrc - delete all resources during close 916 * @vsi: VSI structure of device 917 * @type: type of resource to dele 918 * @reset: true if reset chip 919 */ 920 void 921 irdma_puda_dele_rsrc(struct irdma_sc_vsi *vsi, enum puda_rsrc_type type, 922 bool reset) 923 { 924 struct irdma_sc_dev *dev = vsi->dev; 925 struct irdma_puda_rsrc *rsrc; 926 struct irdma_puda_buf *buf = NULL; 927 struct irdma_puda_buf *nextbuf = NULL; 928 struct irdma_virt_mem *vmem; 929 struct irdma_sc_ceq *ceq; 930 931 ceq = vsi->dev->ceq[0]; 932 switch (type) { 933 case IRDMA_PUDA_RSRC_TYPE_ILQ: 934 rsrc = vsi->ilq; 935 vmem = &vsi->ilq_mem; 936 vsi->ilq = NULL; 937 if (ceq && ceq->reg_cq) 938 irdma_sc_remove_cq_ctx(ceq, &rsrc->cq); 939 break; 940 case IRDMA_PUDA_RSRC_TYPE_IEQ: 941 rsrc = vsi->ieq; 942 vmem = &vsi->ieq_mem; 943 vsi->ieq = NULL; 944 if (ceq && ceq->reg_cq) 945 irdma_sc_remove_cq_ctx(ceq, &rsrc->cq); 946 break; 947 default: 948 irdma_debug(dev, IRDMA_DEBUG_PUDA, 949 "error resource type = 0x%x\n", type); 950 return; 951 } 952 953 spin_lock_destroy(&rsrc->bufpool_lock); 954 switch (rsrc->cmpl) { 955 case PUDA_HASH_CRC_COMPLETE: 956 irdma_free_hash_desc(rsrc->hash_desc); 957 /* fallthrough */ 958 case PUDA_QP_CREATED: 959 irdma_qp_rem_qos(&rsrc->qp); 960 961 if (!reset) 962 irdma_puda_free_qp(rsrc); 963 964 irdma_free_dma_mem(dev->hw, &rsrc->qpmem); 965 /* fallthrough */ 966 case PUDA_CQ_CREATED: 967 if (!reset) 968 irdma_puda_free_cq(rsrc); 969 970 irdma_free_dma_mem(dev->hw, &rsrc->cqmem); 971 break; 972 default: 973 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 974 "error no resources\n"); 975 break; 976 } 977 /* Free all allocated puda buffers for both tx and rx */ 978 buf = rsrc->alloclist; 979 while (buf) { 980 nextbuf = buf->next; 981 irdma_puda_dele_buf(dev, buf); 982 buf = nextbuf; 983 rsrc->alloc_buf_count--; 984 } 985 986 kfree(vmem->va); 987 } 988 989 /** 990 * irdma_puda_allocbufs - allocate buffers for resource 991 * @rsrc: resource for buffer allocation 992 * @count: number of buffers to create 993 */ 994 static int 995 irdma_puda_allocbufs(struct irdma_puda_rsrc *rsrc, u32 count) 996 { 997 u32 i; 998 struct irdma_puda_buf *buf; 999 struct irdma_puda_buf *nextbuf; 1000 struct irdma_virt_mem buf_mem; 1001 struct irdma_dma_mem *dma_mem; 1002 bool virtdma = false; 1003 unsigned long flags; 1004 1005 buf_mem.size = count * sizeof(struct irdma_puda_buf); 1006 buf_mem.va = kzalloc(buf_mem.size, GFP_KERNEL); 1007 if (!buf_mem.va) { 1008 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 1009 "error virt_mem for buf\n"); 1010 rsrc->stats_buf_alloc_fail++; 1011 goto trysmall; 1012 } 1013 1014 /* 1015 * Allocate the large dma chunk and setup dma attributes into first puda buffer. This is required during free 1016 */ 1017 buf = (struct irdma_puda_buf *)buf_mem.va; 1018 buf->mem.va = irdma_allocate_dma_mem(rsrc->dev->hw, &buf->mem, 1019 rsrc->buf_size * count, 1); 1020 if (!buf->mem.va) { 1021 irdma_debug(rsrc->dev, IRDMA_DEBUG_PUDA, 1022 "error dma_mem for buf\n"); 1023 kfree(buf_mem.va); 1024 rsrc->stats_buf_alloc_fail++; 1025 goto trysmall; 1026 } 1027 1028 /* 1029 * dma_mem points to start of the large DMA chunk 1030 */ 1031 dma_mem = &buf->mem; 1032 1033 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 1034 for (i = 0; i < count; i++) { 1035 buf = ((struct irdma_puda_buf *)buf_mem.va) + i; 1036 1037 buf->mem.va = (char *)dma_mem->va + (i * rsrc->buf_size); 1038 buf->mem.pa = dma_mem->pa + (i * rsrc->buf_size); 1039 buf->mem.size = rsrc->buf_size; 1040 buf->virtdma = virtdma; 1041 virtdma = true; 1042 1043 buf->buf_mem.va = buf_mem.va; 1044 buf->buf_mem.size = buf_mem.size; 1045 1046 list_add(&buf->list, &rsrc->bufpool); 1047 rsrc->alloc_buf_count++; 1048 if (!rsrc->alloclist) { 1049 rsrc->alloclist = buf; 1050 } else { 1051 nextbuf = rsrc->alloclist; 1052 rsrc->alloclist = buf; 1053 buf->next = nextbuf; 1054 } 1055 } 1056 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 1057 1058 rsrc->avail_buf_count = rsrc->alloc_buf_count; 1059 return 0; 1060 trysmall: 1061 for (i = 0; i < count; i++) { 1062 buf = irdma_puda_alloc_buf(rsrc->dev, rsrc->buf_size); 1063 if (!buf) { 1064 rsrc->stats_buf_alloc_fail++; 1065 return -ENOMEM; 1066 } 1067 irdma_puda_ret_bufpool(rsrc, buf); 1068 rsrc->alloc_buf_count++; 1069 if (!rsrc->alloclist) { 1070 rsrc->alloclist = buf; 1071 } else { 1072 nextbuf = rsrc->alloclist; 1073 rsrc->alloclist = buf; 1074 buf->next = nextbuf; 1075 } 1076 } 1077 1078 rsrc->avail_buf_count = rsrc->alloc_buf_count; 1079 1080 return 0; 1081 } 1082 1083 /** 1084 * irdma_puda_create_rsrc - create resource (ilq or ieq) 1085 * @vsi: sc VSI struct 1086 * @info: resource information 1087 */ 1088 int 1089 irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi, 1090 struct irdma_puda_rsrc_info *info) 1091 { 1092 struct irdma_sc_dev *dev = vsi->dev; 1093 int ret = 0; 1094 struct irdma_puda_rsrc *rsrc; 1095 u32 pudasize; 1096 u32 sqwridsize, rqwridsize; 1097 struct irdma_virt_mem *vmem; 1098 1099 info->count = 1; 1100 pudasize = sizeof(struct irdma_puda_rsrc); 1101 sqwridsize = info->sq_size * sizeof(struct irdma_sq_uk_wr_trk_info); 1102 rqwridsize = info->rq_size * 8; 1103 switch (info->type) { 1104 case IRDMA_PUDA_RSRC_TYPE_ILQ: 1105 vmem = &vsi->ilq_mem; 1106 break; 1107 case IRDMA_PUDA_RSRC_TYPE_IEQ: 1108 vmem = &vsi->ieq_mem; 1109 break; 1110 default: 1111 return -EOPNOTSUPP; 1112 } 1113 vmem->size = pudasize + sqwridsize + rqwridsize; 1114 vmem->va = kzalloc(vmem->size, GFP_KERNEL); 1115 if (!vmem->va) 1116 return -ENOMEM; 1117 1118 rsrc = vmem->va; 1119 spin_lock_init(&rsrc->bufpool_lock); 1120 switch (info->type) { 1121 case IRDMA_PUDA_RSRC_TYPE_ILQ: 1122 vsi->ilq = vmem->va; 1123 vsi->ilq_count = info->count; 1124 rsrc->receive = info->receive; 1125 rsrc->xmit_complete = info->xmit_complete; 1126 break; 1127 case IRDMA_PUDA_RSRC_TYPE_IEQ: 1128 vsi->ieq_count = info->count; 1129 vsi->ieq = vmem->va; 1130 rsrc->receive = irdma_ieq_receive; 1131 rsrc->xmit_complete = irdma_ieq_tx_compl; 1132 break; 1133 default: 1134 return -EOPNOTSUPP; 1135 } 1136 1137 rsrc->type = info->type; 1138 rsrc->sq_wrtrk_array = (struct irdma_sq_uk_wr_trk_info *) 1139 ((u8 *)vmem->va + pudasize); 1140 rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize); 1141 /* Initialize all ieq lists */ 1142 INIT_LIST_HEAD(&rsrc->bufpool); 1143 INIT_LIST_HEAD(&rsrc->txpend); 1144 1145 rsrc->tx_wqe_avail_cnt = info->sq_size - 1; 1146 irdma_sc_pd_init(dev, &rsrc->sc_pd, info->pd_id, info->abi_ver); 1147 rsrc->qp_id = info->qp_id; 1148 rsrc->cq_id = info->cq_id; 1149 rsrc->sq_size = info->sq_size; 1150 rsrc->rq_size = info->rq_size; 1151 rsrc->cq_size = info->rq_size + info->sq_size; 1152 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1153 if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) 1154 rsrc->cq_size += info->rq_size; 1155 } 1156 rsrc->buf_size = info->buf_size; 1157 rsrc->dev = dev; 1158 rsrc->vsi = vsi; 1159 rsrc->stats_idx = info->stats_idx; 1160 rsrc->stats_idx_valid = info->stats_idx_valid; 1161 1162 ret = irdma_puda_cq_create(rsrc); 1163 if (!ret) { 1164 rsrc->cmpl = PUDA_CQ_CREATED; 1165 ret = irdma_puda_qp_create(rsrc); 1166 } 1167 if (ret) { 1168 irdma_debug(dev, IRDMA_DEBUG_PUDA, 1169 "error qp_create type=%d, status=%d\n", rsrc->type, 1170 ret); 1171 goto error; 1172 } 1173 rsrc->cmpl = PUDA_QP_CREATED; 1174 1175 ret = irdma_puda_allocbufs(rsrc, info->tx_buf_cnt + info->rq_size); 1176 if (ret) { 1177 irdma_debug(dev, IRDMA_DEBUG_PUDA, "error alloc_buf\n"); 1178 goto error; 1179 } 1180 1181 rsrc->rxq_invalid_cnt = info->rq_size; 1182 ret = irdma_puda_replenish_rq(rsrc, true); 1183 if (ret) 1184 goto error; 1185 1186 if (info->type == IRDMA_PUDA_RSRC_TYPE_IEQ) { 1187 if (!irdma_init_hash_desc(&rsrc->hash_desc)) { 1188 rsrc->check_crc = true; 1189 rsrc->cmpl = PUDA_HASH_CRC_COMPLETE; 1190 ret = 0; 1191 } 1192 } 1193 1194 irdma_sc_ccq_arm(&rsrc->cq); 1195 return ret; 1196 1197 error: 1198 irdma_puda_dele_rsrc(vsi, info->type, false); 1199 1200 return ret; 1201 } 1202 1203 /** 1204 * irdma_ilq_putback_rcvbuf - ilq buffer to put back on rq 1205 * @qp: ilq's qp resource 1206 * @buf: puda buffer for rcv q 1207 * @wqe_idx: wqe index of completed rcvbuf 1208 */ 1209 static void 1210 irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, 1211 struct irdma_puda_buf *buf, u32 wqe_idx) 1212 { 1213 __le64 *wqe; 1214 u64 offset8, offset24; 1215 1216 /* Synch buffer for use by device */ 1217 dma_sync_single_for_device(hw_to_dev(qp->dev->hw), buf->mem.pa, buf->mem.size, DMA_BIDIRECTIONAL); 1218 wqe = qp->qp_uk.rq_base[wqe_idx].elem; 1219 get_64bit_val(wqe, IRDMA_BYTE_24, &offset24); 1220 if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1221 get_64bit_val(wqe, IRDMA_BYTE_8, &offset8); 1222 if (offset24) 1223 offset8 &= ~FIELD_PREP(IRDMAQPSQ_VALID, 1); 1224 else 1225 offset8 |= FIELD_PREP(IRDMAQPSQ_VALID, 1); 1226 set_64bit_val(wqe, IRDMA_BYTE_8, offset8); 1227 irdma_wmb(); /* make sure WQE is written before valid bit is set */ 1228 } 1229 if (offset24) 1230 offset24 = 0; 1231 else 1232 offset24 = FIELD_PREP(IRDMAQPSQ_VALID, 1); 1233 1234 set_64bit_val(wqe, IRDMA_BYTE_24, offset24); 1235 } 1236 1237 /** 1238 * irdma_ieq_get_fpdu_len - get length of fpdu with or without marker 1239 * @pfpdu: pointer to fpdu 1240 * @datap: pointer to data in the buffer 1241 * @rcv_seq: seqnum of the data buffer 1242 */ 1243 static u16 irdma_ieq_get_fpdu_len(struct irdma_pfpdu *pfpdu, u8 *datap, 1244 u32 rcv_seq){ 1245 u32 marker_seq, end_seq, blk_start; 1246 u8 marker_len = pfpdu->marker_len; 1247 u16 total_len = 0; 1248 u16 fpdu_len; 1249 1250 blk_start = (pfpdu->rcv_start_seq - rcv_seq) & (IRDMA_MRK_BLK_SZ - 1); 1251 if (!blk_start) { 1252 total_len = marker_len; 1253 marker_seq = rcv_seq + IRDMA_MRK_BLK_SZ; 1254 if (marker_len && *(u32 *)datap) 1255 return 0; 1256 } else { 1257 marker_seq = rcv_seq + blk_start; 1258 } 1259 1260 datap += total_len; 1261 fpdu_len = IRDMA_NTOHS(*(__be16 *) datap); 1262 fpdu_len += IRDMA_IEQ_MPA_FRAMING; 1263 fpdu_len = (fpdu_len + 3) & 0xfffc; 1264 1265 if (fpdu_len > pfpdu->max_fpdu_data) 1266 return 0; 1267 1268 total_len += fpdu_len; 1269 end_seq = rcv_seq + total_len; 1270 while ((int)(marker_seq - end_seq) < 0) { 1271 total_len += marker_len; 1272 end_seq += marker_len; 1273 marker_seq += IRDMA_MRK_BLK_SZ; 1274 } 1275 1276 return total_len; 1277 } 1278 1279 /** 1280 * irdma_ieq_copy_to_txbuf - copydata from rcv buf to tx buf 1281 * @buf: rcv buffer with partial 1282 * @txbuf: tx buffer for sending back 1283 * @buf_offset: rcv buffer offset to copy from 1284 * @txbuf_offset: at offset in tx buf to copy 1285 * @len: length of data to copy 1286 */ 1287 static void 1288 irdma_ieq_copy_to_txbuf(struct irdma_puda_buf *buf, 1289 struct irdma_puda_buf *txbuf, 1290 u16 buf_offset, u32 txbuf_offset, u32 len) 1291 { 1292 void *mem1 = (u8 *)buf->mem.va + buf_offset; 1293 void *mem2 = (u8 *)txbuf->mem.va + txbuf_offset; 1294 1295 irdma_memcpy(mem2, mem1, len); 1296 } 1297 1298 /** 1299 * irdma_ieq_setup_tx_buf - setup tx buffer for partial handling 1300 * @buf: reeive buffer with partial 1301 * @txbuf: buffer to prepare 1302 */ 1303 static void 1304 irdma_ieq_setup_tx_buf(struct irdma_puda_buf *buf, 1305 struct irdma_puda_buf *txbuf) 1306 { 1307 txbuf->tcphlen = buf->tcphlen; 1308 txbuf->ipv4 = buf->ipv4; 1309 1310 if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1311 txbuf->hdrlen = txbuf->tcphlen; 1312 irdma_ieq_copy_to_txbuf(buf, txbuf, IRDMA_TCP_OFFSET, 0, 1313 txbuf->hdrlen); 1314 } else { 1315 txbuf->maclen = buf->maclen; 1316 txbuf->hdrlen = buf->hdrlen; 1317 irdma_ieq_copy_to_txbuf(buf, txbuf, 0, 0, buf->hdrlen); 1318 } 1319 } 1320 1321 /** 1322 * irdma_ieq_check_first_buf - check if rcv buffer's seq is in range 1323 * @buf: receive exception buffer 1324 * @fps: first partial sequence number 1325 */ 1326 static void 1327 irdma_ieq_check_first_buf(struct irdma_puda_buf *buf, u32 fps) 1328 { 1329 u32 offset; 1330 1331 if (buf->seqnum < fps) { 1332 offset = fps - buf->seqnum; 1333 if (offset > buf->datalen) 1334 return; 1335 buf->data += offset; 1336 buf->datalen -= (u16)offset; 1337 buf->seqnum = fps; 1338 } 1339 } 1340 1341 /** 1342 * irdma_ieq_compl_pfpdu - write txbuf with full fpdu 1343 * @ieq: ieq resource 1344 * @rxlist: ieq's received buffer list 1345 * @pbufl: temporary list for buffers for fpddu 1346 * @txbuf: tx buffer for fpdu 1347 * @fpdu_len: total length of fpdu 1348 */ 1349 static void 1350 irdma_ieq_compl_pfpdu(struct irdma_puda_rsrc *ieq, 1351 struct list_head *rxlist, 1352 struct list_head *pbufl, 1353 struct irdma_puda_buf *txbuf, u16 fpdu_len) 1354 { 1355 struct irdma_puda_buf *buf; 1356 u32 nextseqnum; 1357 u16 txoffset, bufoffset; 1358 1359 buf = irdma_puda_get_listbuf(pbufl); 1360 if (!buf) 1361 return; 1362 1363 nextseqnum = buf->seqnum + fpdu_len; 1364 irdma_ieq_setup_tx_buf(buf, txbuf); 1365 if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1366 txoffset = txbuf->hdrlen; 1367 txbuf->totallen = txbuf->hdrlen + fpdu_len; 1368 txbuf->data = (u8 *)txbuf->mem.va + txoffset; 1369 } else { 1370 txoffset = buf->hdrlen; 1371 txbuf->totallen = buf->hdrlen + fpdu_len; 1372 txbuf->data = (u8 *)txbuf->mem.va + buf->hdrlen; 1373 } 1374 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); 1375 1376 do { 1377 if (buf->datalen >= fpdu_len) { 1378 /* copied full fpdu */ 1379 irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, 1380 fpdu_len); 1381 buf->datalen -= fpdu_len; 1382 buf->data += fpdu_len; 1383 buf->seqnum = nextseqnum; 1384 break; 1385 } 1386 /* copy partial fpdu */ 1387 irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, 1388 buf->datalen); 1389 txoffset += buf->datalen; 1390 fpdu_len -= buf->datalen; 1391 irdma_puda_ret_bufpool(ieq, buf); 1392 buf = irdma_puda_get_listbuf(pbufl); 1393 if (!buf) 1394 return; 1395 1396 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); 1397 } while (1); 1398 1399 /* last buffer on the list */ 1400 if (buf->datalen) 1401 list_add(&buf->list, rxlist); 1402 else 1403 irdma_puda_ret_bufpool(ieq, buf); 1404 } 1405 1406 /** 1407 * irdma_ieq_create_pbufl - create buffer list for single fpdu 1408 * @pfpdu: pointer to fpdu 1409 * @rxlist: resource list for receive ieq buffes 1410 * @pbufl: temp. list for buffers for fpddu 1411 * @buf: first receive buffer 1412 * @fpdu_len: total length of fpdu 1413 */ 1414 static int 1415 irdma_ieq_create_pbufl(struct irdma_pfpdu *pfpdu, 1416 struct list_head *rxlist, 1417 struct list_head *pbufl, 1418 struct irdma_puda_buf *buf, u16 fpdu_len) 1419 { 1420 int status = 0; 1421 struct irdma_puda_buf *nextbuf; 1422 u32 nextseqnum; 1423 u16 plen = fpdu_len - buf->datalen; 1424 bool done = false; 1425 1426 nextseqnum = buf->seqnum + buf->datalen; 1427 do { 1428 nextbuf = irdma_puda_get_listbuf(rxlist); 1429 if (!nextbuf) { 1430 status = -ENOBUFS; 1431 break; 1432 } 1433 list_add_tail(&nextbuf->list, pbufl); 1434 if (nextbuf->seqnum != nextseqnum) { 1435 pfpdu->bad_seq_num++; 1436 status = -ERANGE; 1437 break; 1438 } 1439 if (nextbuf->datalen >= plen) { 1440 done = true; 1441 } else { 1442 plen -= nextbuf->datalen; 1443 nextseqnum = nextbuf->seqnum + nextbuf->datalen; 1444 } 1445 1446 } while (!done); 1447 1448 return status; 1449 } 1450 1451 /** 1452 * irdma_ieq_handle_partial - process partial fpdu buffer 1453 * @ieq: ieq resource 1454 * @pfpdu: partial management per user qp 1455 * @buf: receive buffer 1456 * @fpdu_len: fpdu len in the buffer 1457 */ 1458 static int 1459 irdma_ieq_handle_partial(struct irdma_puda_rsrc *ieq, 1460 struct irdma_pfpdu *pfpdu, 1461 struct irdma_puda_buf *buf, u16 fpdu_len) 1462 { 1463 int status = 0; 1464 u8 *crcptr; 1465 u32 mpacrc; 1466 u32 seqnum = buf->seqnum; 1467 struct list_head pbufl; /* partial buffer list */ 1468 struct irdma_puda_buf *txbuf = NULL; 1469 struct list_head *rxlist = &pfpdu->rxlist; 1470 1471 ieq->partials_handled++; 1472 1473 INIT_LIST_HEAD(&pbufl); 1474 list_add(&buf->list, &pbufl); 1475 1476 status = irdma_ieq_create_pbufl(pfpdu, rxlist, &pbufl, buf, fpdu_len); 1477 if (status) 1478 goto error; 1479 1480 txbuf = irdma_puda_get_bufpool(ieq); 1481 if (!txbuf) { 1482 pfpdu->no_tx_bufs++; 1483 status = -ENOBUFS; 1484 goto error; 1485 } 1486 1487 irdma_ieq_compl_pfpdu(ieq, rxlist, &pbufl, txbuf, fpdu_len); 1488 irdma_ieq_update_tcpip_info(txbuf, fpdu_len, seqnum); 1489 1490 crcptr = txbuf->data + fpdu_len - 4; 1491 mpacrc = *(u32 *)crcptr; 1492 if (ieq->check_crc) { 1493 status = irdma_ieq_check_mpacrc(ieq->hash_desc, txbuf->data, 1494 (fpdu_len - 4), mpacrc); 1495 if (status) { 1496 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1497 "error bad crc\n"); 1498 pfpdu->mpa_crc_err = true; 1499 goto error; 1500 } 1501 } 1502 1503 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "IEQ TX BUFFER", 1504 txbuf->mem.va, txbuf->totallen); 1505 if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 1506 txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; 1507 txbuf->do_lpb = true; 1508 irdma_puda_send_buf(ieq, txbuf); 1509 pfpdu->rcv_nxt = seqnum + fpdu_len; 1510 return status; 1511 1512 error: 1513 while (!list_empty(&pbufl)) { 1514 buf = (struct irdma_puda_buf *)(&pbufl)->prev; 1515 list_move(&buf->list, rxlist); 1516 } 1517 if (txbuf) 1518 irdma_puda_ret_bufpool(ieq, txbuf); 1519 1520 return status; 1521 } 1522 1523 /** 1524 * irdma_ieq_process_buf - process buffer rcvd for ieq 1525 * @ieq: ieq resource 1526 * @pfpdu: partial management per user qp 1527 * @buf: receive buffer 1528 */ 1529 static int 1530 irdma_ieq_process_buf(struct irdma_puda_rsrc *ieq, 1531 struct irdma_pfpdu *pfpdu, 1532 struct irdma_puda_buf *buf) 1533 { 1534 u16 fpdu_len = 0; 1535 u16 datalen = buf->datalen; 1536 u8 *datap = buf->data; 1537 u8 *crcptr; 1538 u16 ioffset = 0; 1539 u32 mpacrc; 1540 u32 seqnum = buf->seqnum; 1541 u16 len = 0; 1542 u16 full = 0; 1543 bool partial = false; 1544 struct irdma_puda_buf *txbuf; 1545 struct list_head *rxlist = &pfpdu->rxlist; 1546 int ret = 0; 1547 1548 ioffset = (u16)(buf->data - (u8 *)buf->mem.va); 1549 while (datalen) { 1550 fpdu_len = irdma_ieq_get_fpdu_len(pfpdu, datap, buf->seqnum); 1551 if (!fpdu_len) { 1552 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1553 "error bad fpdu len\n"); 1554 list_add(&buf->list, rxlist); 1555 pfpdu->mpa_crc_err = true; 1556 return -EINVAL; 1557 } 1558 1559 if (datalen < fpdu_len) { 1560 partial = true; 1561 break; 1562 } 1563 crcptr = datap + fpdu_len - 4; 1564 mpacrc = *(u32 *)crcptr; 1565 if (ieq->check_crc) 1566 ret = irdma_ieq_check_mpacrc(ieq->hash_desc, datap, 1567 fpdu_len - 4, mpacrc); 1568 if (ret) { 1569 list_add(&buf->list, rxlist); 1570 irdma_debug(ieq->dev, IRDMA_DEBUG_ERR, 1571 "IRDMA_ERR_MPA_CRC\n"); 1572 pfpdu->mpa_crc_err = true; 1573 return ret; 1574 } 1575 full++; 1576 pfpdu->fpdu_processed++; 1577 ieq->fpdu_processed++; 1578 datap += fpdu_len; 1579 len += fpdu_len; 1580 datalen -= fpdu_len; 1581 } 1582 if (full) { 1583 /* copy full pdu's in the txbuf and send them out */ 1584 txbuf = irdma_puda_get_bufpool(ieq); 1585 if (!txbuf) { 1586 pfpdu->no_tx_bufs++; 1587 list_add(&buf->list, rxlist); 1588 return -ENOBUFS; 1589 } 1590 /* modify txbuf's buffer header */ 1591 irdma_ieq_setup_tx_buf(buf, txbuf); 1592 /* copy full fpdu's to new buffer */ 1593 if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { 1594 irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, 1595 txbuf->hdrlen, len); 1596 txbuf->totallen = txbuf->hdrlen + len; 1597 txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; 1598 } else { 1599 irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, 1600 buf->hdrlen, len); 1601 txbuf->totallen = buf->hdrlen + len; 1602 } 1603 irdma_ieq_update_tcpip_info(txbuf, len, buf->seqnum); 1604 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "IEQ TX BUFFER", 1605 txbuf->mem.va, txbuf->totallen); 1606 txbuf->do_lpb = true; 1607 irdma_puda_send_buf(ieq, txbuf); 1608 1609 if (!datalen) { 1610 pfpdu->rcv_nxt = buf->seqnum + len; 1611 irdma_puda_ret_bufpool(ieq, buf); 1612 return 0; 1613 } 1614 buf->data = datap; 1615 buf->seqnum = seqnum + len; 1616 buf->datalen = datalen; 1617 pfpdu->rcv_nxt = buf->seqnum; 1618 } 1619 if (partial) 1620 return irdma_ieq_handle_partial(ieq, pfpdu, buf, fpdu_len); 1621 1622 return 0; 1623 } 1624 1625 /** 1626 * irdma_ieq_process_fpdus - process fpdu's buffers on its list 1627 * @qp: qp for which partial fpdus 1628 * @ieq: ieq resource 1629 */ 1630 void 1631 irdma_ieq_process_fpdus(struct irdma_sc_qp *qp, 1632 struct irdma_puda_rsrc *ieq) 1633 { 1634 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1635 struct list_head *rxlist = &pfpdu->rxlist; 1636 struct irdma_puda_buf *buf; 1637 int status; 1638 1639 do { 1640 if (list_empty(rxlist)) 1641 break; 1642 buf = irdma_puda_get_listbuf(rxlist); 1643 if (!buf) { 1644 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1645 "error no buf\n"); 1646 break; 1647 } 1648 if (buf->seqnum != pfpdu->rcv_nxt) { 1649 /* This could be out of order or missing packet */ 1650 pfpdu->out_of_order++; 1651 list_add(&buf->list, rxlist); 1652 break; 1653 } 1654 /* keep processing buffers from the head of the list */ 1655 status = irdma_ieq_process_buf(ieq, pfpdu, buf); 1656 if (status && pfpdu->mpa_crc_err) { 1657 while (!list_empty(rxlist)) { 1658 buf = irdma_puda_get_listbuf(rxlist); 1659 irdma_puda_ret_bufpool(ieq, buf); 1660 pfpdu->crc_err++; 1661 ieq->crc_err++; 1662 } 1663 /* create CQP for AE */ 1664 irdma_ieq_mpa_crc_ae(ieq->dev, qp); 1665 } 1666 } while (!status); 1667 } 1668 1669 /** 1670 * irdma_ieq_create_ah - create an address handle for IEQ 1671 * @qp: qp pointer 1672 * @buf: buf received on IEQ used to create AH 1673 */ 1674 static int 1675 irdma_ieq_create_ah(struct irdma_sc_qp *qp, struct irdma_puda_buf *buf) 1676 { 1677 struct irdma_ah_info ah_info = {0}; 1678 1679 qp->pfpdu.ah_buf = buf; 1680 irdma_puda_ieq_get_ah_info(qp, &ah_info); 1681 return irdma_puda_create_ah(qp->vsi->dev, &ah_info, false, 1682 IRDMA_PUDA_RSRC_TYPE_IEQ, qp, 1683 &qp->pfpdu.ah); 1684 } 1685 1686 /** 1687 * irdma_ieq_handle_exception - handle qp's exception 1688 * @ieq: ieq resource 1689 * @qp: qp receiving excpetion 1690 * @buf: receive buffer 1691 */ 1692 static void 1693 irdma_ieq_handle_exception(struct irdma_puda_rsrc *ieq, 1694 struct irdma_sc_qp *qp, 1695 struct irdma_puda_buf *buf) 1696 { 1697 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1698 u32 *hw_host_ctx = (u32 *)qp->hw_host_ctx; 1699 u32 rcv_wnd = hw_host_ctx[23]; 1700 /* first partial seq # in q2 */ 1701 u32 fps = *(u32 *)(qp->q2_buf + Q2_FPSN_OFFSET); 1702 struct list_head *rxlist = &pfpdu->rxlist; 1703 struct list_head *plist; 1704 struct irdma_puda_buf *tmpbuf = NULL; 1705 unsigned long flags = 0; 1706 u8 hw_rev = qp->dev->hw_attrs.uk_attrs.hw_rev; 1707 1708 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "IEQ RX BUFFER", buf->mem.va, 1709 buf->totallen); 1710 1711 spin_lock_irqsave(&pfpdu->lock, flags); 1712 pfpdu->total_ieq_bufs++; 1713 if (pfpdu->mpa_crc_err) { 1714 pfpdu->crc_err++; 1715 goto error; 1716 } 1717 if (pfpdu->mode && fps != pfpdu->fps) { 1718 /* clean up qp as it is new partial sequence */ 1719 irdma_ieq_cleanup_qp(ieq, qp); 1720 irdma_debug(ieq->dev, IRDMA_DEBUG_IEQ, 1721 "restarting new partial\n"); 1722 pfpdu->mode = false; 1723 } 1724 1725 if (!pfpdu->mode) { 1726 irdma_debug_buf(ieq->dev, IRDMA_DEBUG_IEQ, "Q2 BUFFER", 1727 (u64 *)qp->q2_buf, 128); 1728 /* First_Partial_Sequence_Number check */ 1729 pfpdu->rcv_nxt = fps; 1730 pfpdu->fps = fps; 1731 pfpdu->mode = true; 1732 pfpdu->max_fpdu_data = (buf->ipv4) ? 1733 (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV4) : 1734 (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV6); 1735 pfpdu->pmode_count++; 1736 ieq->pmode_count++; 1737 INIT_LIST_HEAD(rxlist); 1738 irdma_ieq_check_first_buf(buf, fps); 1739 } 1740 1741 if (!(rcv_wnd >= (buf->seqnum - pfpdu->rcv_nxt))) { 1742 pfpdu->bad_seq_num++; 1743 ieq->bad_seq_num++; 1744 goto error; 1745 } 1746 1747 if (!list_empty(rxlist)) { 1748 tmpbuf = (struct irdma_puda_buf *)(rxlist)->next; 1749 while ((struct list_head *)tmpbuf != rxlist) { 1750 if (buf->seqnum == tmpbuf->seqnum) 1751 goto error; 1752 if ((int)(buf->seqnum - tmpbuf->seqnum) < 0) 1753 break; 1754 plist = &tmpbuf->list; 1755 tmpbuf = (struct irdma_puda_buf *)(plist)->next; 1756 } 1757 /* Insert buf before tmpbuf */ 1758 list_add_tail(&buf->list, &tmpbuf->list); 1759 } else { 1760 list_add_tail(&buf->list, rxlist); 1761 } 1762 pfpdu->nextseqnum = buf->seqnum + buf->datalen; 1763 pfpdu->lastrcv_buf = buf; 1764 if (hw_rev >= IRDMA_GEN_2 && !pfpdu->ah) { 1765 irdma_ieq_create_ah(qp, buf); 1766 if (!pfpdu->ah) 1767 goto error; 1768 goto exit; 1769 } 1770 if (hw_rev == IRDMA_GEN_1) 1771 irdma_ieq_process_fpdus(qp, ieq); 1772 else if (pfpdu->ah && pfpdu->ah->ah_info.ah_valid) 1773 irdma_ieq_process_fpdus(qp, ieq); 1774 exit: 1775 spin_unlock_irqrestore(&pfpdu->lock, flags); 1776 1777 return; 1778 1779 error: 1780 irdma_puda_ret_bufpool(ieq, buf); 1781 spin_unlock_irqrestore(&pfpdu->lock, flags); 1782 } 1783 1784 /** 1785 * irdma_ieq_receive - received exception buffer 1786 * @vsi: VSI of device 1787 * @buf: exception buffer received 1788 */ 1789 static void 1790 irdma_ieq_receive(struct irdma_sc_vsi *vsi, 1791 struct irdma_puda_buf *buf) 1792 { 1793 struct irdma_puda_rsrc *ieq = vsi->ieq; 1794 struct irdma_sc_qp *qp = NULL; 1795 u32 wqe_idx = ieq->compl_rxwqe_idx; 1796 1797 qp = irdma_ieq_get_qp(vsi->dev, buf); 1798 if (!qp) { 1799 ieq->stats_bad_qp_id++; 1800 irdma_puda_ret_bufpool(ieq, buf); 1801 } else { 1802 irdma_ieq_handle_exception(ieq, qp, buf); 1803 } 1804 /* 1805 * ieq->rx_wqe_idx is used by irdma_puda_replenish_rq() on which wqe_idx to start replenish rq 1806 */ 1807 if (!ieq->rxq_invalid_cnt) 1808 ieq->rx_wqe_idx = wqe_idx; 1809 ieq->rxq_invalid_cnt++; 1810 } 1811 1812 /** 1813 * irdma_ieq_tx_compl - put back after sending completed exception buffer 1814 * @vsi: sc VSI struct 1815 * @sqwrid: pointer to puda buffer 1816 */ 1817 static void 1818 irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid) 1819 { 1820 struct irdma_puda_rsrc *ieq = vsi->ieq; 1821 struct irdma_puda_buf *buf = sqwrid; 1822 1823 irdma_puda_ret_bufpool(ieq, buf); 1824 } 1825 1826 /** 1827 * irdma_ieq_cleanup_qp - qp is being destroyed 1828 * @ieq: ieq resource 1829 * @qp: all pending fpdu buffers 1830 */ 1831 void 1832 irdma_ieq_cleanup_qp(struct irdma_puda_rsrc *ieq, struct irdma_sc_qp *qp) 1833 { 1834 struct irdma_puda_buf *buf; 1835 struct irdma_pfpdu *pfpdu = &qp->pfpdu; 1836 struct list_head *rxlist = &pfpdu->rxlist; 1837 1838 if (qp->pfpdu.ah) { 1839 irdma_puda_free_ah(ieq->dev, qp->pfpdu.ah); 1840 qp->pfpdu.ah = NULL; 1841 qp->pfpdu.ah_buf = NULL; 1842 } 1843 1844 if (!pfpdu->mode) 1845 return; 1846 1847 while (!list_empty(rxlist)) { 1848 buf = irdma_puda_get_listbuf(rxlist); 1849 irdma_puda_ret_bufpool(ieq, buf); 1850 } 1851 } 1852