1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include "irdma_main.h" 36 37 static struct irdma_rsrc_limits rsrc_limits_table[] = { 38 [0] = { 39 .qplimit = SZ_128, 40 }, 41 [1] = { 42 .qplimit = SZ_1K, 43 }, 44 [2] = { 45 .qplimit = SZ_2K, 46 }, 47 [3] = { 48 .qplimit = SZ_4K, 49 }, 50 [4] = { 51 .qplimit = SZ_16K, 52 }, 53 [5] = { 54 .qplimit = SZ_64K, 55 }, 56 [6] = { 57 .qplimit = SZ_128K, 58 }, 59 [7] = { 60 .qplimit = SZ_256K, 61 }, 62 }; 63 64 /* types of hmc objects */ 65 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = { 66 IRDMA_HMC_IW_QP, 67 IRDMA_HMC_IW_CQ, 68 IRDMA_HMC_IW_HTE, 69 IRDMA_HMC_IW_ARP, 70 IRDMA_HMC_IW_APBVT_ENTRY, 71 IRDMA_HMC_IW_MR, 72 IRDMA_HMC_IW_XF, 73 IRDMA_HMC_IW_XFFL, 74 IRDMA_HMC_IW_Q1, 75 IRDMA_HMC_IW_Q1FL, 76 IRDMA_HMC_IW_PBLE, 77 IRDMA_HMC_IW_TIMER, 78 IRDMA_HMC_IW_FSIMC, 79 IRDMA_HMC_IW_FSIAV, 80 IRDMA_HMC_IW_RRF, 81 IRDMA_HMC_IW_RRFFL, 82 IRDMA_HMC_IW_HDR, 83 IRDMA_HMC_IW_MD, 84 IRDMA_HMC_IW_OOISC, 85 IRDMA_HMC_IW_OOISCFFL, 86 }; 87 88 /** 89 * irdma_iwarp_ce_handler - handle iwarp completions 90 * @iwcq: iwarp cq receiving event 91 */ 92 static void 93 irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq) 94 { 95 struct irdma_cq *cq = iwcq->back_cq; 96 97 if (!cq->user_mode) 98 atomic_set(&cq->armed, 0); 99 if (cq->ibcq.comp_handler) 100 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 101 } 102 103 /** 104 * irdma_puda_ce_handler - handle puda completion events 105 * @rf: RDMA PCI function 106 * @cq: puda completion q for event 107 */ 108 static void 109 irdma_puda_ce_handler(struct irdma_pci_f *rf, 110 struct irdma_sc_cq *cq) 111 { 112 struct irdma_sc_dev *dev = &rf->sc_dev; 113 u32 compl_error; 114 int status; 115 116 do { 117 status = irdma_puda_poll_cmpl(dev, cq, &compl_error); 118 if (status == -ENOENT) 119 break; 120 if (status) { 121 irdma_debug(dev, IRDMA_DEBUG_ERR, "puda status = %d\n", status); 122 break; 123 } 124 if (compl_error) { 125 irdma_debug(dev, IRDMA_DEBUG_ERR, 126 "puda compl_err =0x%x\n", 127 compl_error); 128 break; 129 } 130 } while (1); 131 132 irdma_sc_ccq_arm(cq); 133 } 134 135 /** 136 * irdma_process_ceq - handle ceq for completions 137 * @rf: RDMA PCI function 138 * @ceq: ceq having cq for completion 139 */ 140 static void 141 irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq) 142 { 143 struct irdma_sc_dev *dev = &rf->sc_dev; 144 struct irdma_sc_ceq *sc_ceq; 145 struct irdma_sc_cq *cq; 146 unsigned long flags; 147 148 sc_ceq = &ceq->sc_ceq; 149 do { 150 spin_lock_irqsave(&ceq->ce_lock, flags); 151 cq = irdma_sc_process_ceq(dev, sc_ceq); 152 if (!cq) { 153 spin_unlock_irqrestore(&ceq->ce_lock, flags); 154 break; 155 } 156 157 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP) 158 irdma_iwarp_ce_handler(cq); 159 160 spin_unlock_irqrestore(&ceq->ce_lock, flags); 161 162 if (cq->cq_type == IRDMA_CQ_TYPE_CQP) 163 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work); 164 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ || 165 cq->cq_type == IRDMA_CQ_TYPE_IEQ) 166 irdma_puda_ce_handler(rf, cq); 167 } while (1); 168 } 169 170 static void 171 irdma_set_flush_fields(struct irdma_sc_qp *qp, 172 struct irdma_aeqe_info *info) 173 { 174 struct qp_err_code qp_err; 175 176 qp->sq_flush_code = info->sq; 177 qp->rq_flush_code = info->rq; 178 qp_err = irdma_ae_to_qp_err_code(info->ae_id); 179 180 qp->flush_code = qp_err.flush_code; 181 qp->event_type = qp_err.event_type; 182 } 183 184 /** 185 * irdma_complete_cqp_request - perform post-completion cleanup 186 * @cqp: device CQP 187 * @cqp_request: CQP request 188 * 189 * Mark CQP request as done, wake up waiting thread or invoke 190 * callback function and release/free CQP request. 191 */ 192 static void 193 irdma_complete_cqp_request(struct irdma_cqp *cqp, 194 struct irdma_cqp_request *cqp_request) 195 { 196 if (cqp_request->waiting) { 197 cqp_request->request_done = true; 198 wake_up(&cqp_request->waitq); 199 } else if (cqp_request->callback_fcn) { 200 cqp_request->callback_fcn(cqp_request); 201 } 202 irdma_put_cqp_request(cqp, cqp_request); 203 } 204 205 /** 206 * irdma_process_aeq - handle aeq events 207 * @rf: RDMA PCI function 208 */ 209 static void 210 irdma_process_aeq(struct irdma_pci_f *rf) 211 { 212 struct irdma_sc_dev *dev = &rf->sc_dev; 213 struct irdma_aeq *aeq = &rf->aeq; 214 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq; 215 struct irdma_aeqe_info aeinfo; 216 struct irdma_aeqe_info *info = &aeinfo; 217 int ret; 218 struct irdma_qp *iwqp = NULL; 219 struct irdma_cq *iwcq = NULL; 220 struct irdma_sc_qp *qp = NULL; 221 struct irdma_device *iwdev = rf->iwdev; 222 struct irdma_qp_host_ctx_info *ctx_info = NULL; 223 unsigned long flags; 224 225 u32 aeqcnt = 0; 226 227 if (!sc_aeq->size) 228 return; 229 230 do { 231 memset(info, 0, sizeof(*info)); 232 ret = irdma_sc_get_next_aeqe(sc_aeq, info); 233 if (ret) 234 break; 235 236 aeqcnt++; 237 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_AEQ, 238 "ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n", 239 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state, 240 info->iwarp_state, info->ae_src); 241 242 if (info->qp) { 243 spin_lock_irqsave(&rf->qptable_lock, flags); 244 iwqp = rf->qp_table[info->qp_cq_id]; 245 if (!iwqp) { 246 spin_unlock_irqrestore(&rf->qptable_lock, 247 flags); 248 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) { 249 struct irdma_device *iwdev = rf->iwdev; 250 251 if (!iwdev->vsi.tc_change_pending) 252 continue; 253 254 atomic_dec(&iwdev->vsi.qp_suspend_reqs); 255 wake_up(&iwdev->suspend_wq); 256 continue; 257 } 258 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_AEQ, 259 "qp_id %d is already freed\n", 260 info->qp_cq_id); 261 continue; 262 } 263 irdma_qp_add_ref(&iwqp->ibqp); 264 spin_unlock_irqrestore(&rf->qptable_lock, flags); 265 qp = &iwqp->sc_qp; 266 spin_lock_irqsave(&iwqp->lock, flags); 267 iwqp->hw_tcp_state = info->tcp_state; 268 iwqp->hw_iwarp_state = info->iwarp_state; 269 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE) 270 iwqp->last_aeq = info->ae_id; 271 spin_unlock_irqrestore(&iwqp->lock, flags); 272 ctx_info = &iwqp->ctx_info; 273 } else { 274 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR) 275 continue; 276 } 277 278 switch (info->ae_id) { 279 struct irdma_cm_node *cm_node; 280 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 281 cm_node = iwqp->cm_node; 282 if (cm_node->accept_pend) { 283 atomic_dec(&cm_node->listener->pend_accepts_cnt); 284 cm_node->accept_pend = 0; 285 } 286 iwqp->rts_ae_rcvd = 1; 287 wake_up_interruptible(&iwqp->waitq); 288 break; 289 case IRDMA_AE_LLP_FIN_RECEIVED: 290 if (qp->term_flags) 291 break; 292 if (atomic_inc_return(&iwqp->close_timer_started) == 1) { 293 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT; 294 if (iwqp->ibqp_state == IB_QPS_RTS) { 295 irdma_next_iw_state(iwqp, 296 IRDMA_QP_STATE_CLOSING, 297 0, 0, 0); 298 irdma_cm_disconn(iwqp); 299 } 300 irdma_schedule_cm_timer(iwqp->cm_node, 301 (struct irdma_puda_buf *)iwqp, 302 IRDMA_TIMER_TYPE_CLOSE, 303 1, 0); 304 } 305 break; 306 case IRDMA_AE_LLP_CLOSE_COMPLETE: 307 if (qp->term_flags) 308 irdma_terminate_done(qp, 0); 309 else 310 irdma_cm_disconn(iwqp); 311 break; 312 case IRDMA_AE_BAD_CLOSE: 313 case IRDMA_AE_RESET_SENT: 314 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 315 0); 316 irdma_cm_disconn(iwqp); 317 break; 318 case IRDMA_AE_LLP_CONNECTION_RESET: 319 if (atomic_read(&iwqp->close_timer_started)) 320 break; 321 irdma_cm_disconn(iwqp); 322 break; 323 case IRDMA_AE_QP_SUSPEND_COMPLETE: 324 if (iwqp->iwdev->vsi.tc_change_pending) { 325 atomic_dec(&iwqp->sc_qp.vsi->qp_suspend_reqs); 326 wake_up(&iwqp->iwdev->suspend_wq); 327 } 328 break; 329 case IRDMA_AE_TERMINATE_SENT: 330 irdma_terminate_send_fin(qp); 331 break; 332 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 333 irdma_terminate_received(qp, info); 334 break; 335 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 336 case IRDMA_AE_CQ_OPERATION_ERROR: 337 irdma_dev_err(&iwdev->ibdev, 338 "Processing CQ[0x%x] op error, AE 0x%04X\n", 339 info->qp_cq_id, info->ae_id); 340 spin_lock_irqsave(&rf->cqtable_lock, flags); 341 iwcq = rf->cq_table[info->qp_cq_id]; 342 if (!iwcq) { 343 spin_unlock_irqrestore(&rf->cqtable_lock, 344 flags); 345 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_AEQ, 346 "cq_id %d is already freed\n", 347 info->qp_cq_id); 348 continue; 349 } 350 irdma_cq_add_ref(&iwcq->ibcq); 351 spin_unlock_irqrestore(&rf->cqtable_lock, flags); 352 if (iwcq->ibcq.event_handler) { 353 struct ib_event ibevent; 354 355 ibevent.device = iwcq->ibcq.device; 356 ibevent.event = IB_EVENT_CQ_ERR; 357 ibevent.element.cq = &iwcq->ibcq; 358 iwcq->ibcq.event_handler(&ibevent, 359 iwcq->ibcq.cq_context); 360 } 361 irdma_cq_rem_ref(&iwcq->ibcq); 362 break; 363 case IRDMA_AE_RESET_NOT_SENT: 364 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 365 break; 366 case IRDMA_AE_RESOURCE_EXHAUSTION: 367 irdma_dev_err(&iwdev->ibdev, 368 "Resource exhaustion reason: q1 = %d xmit or rreq = %d\n", 369 info->ae_src == IRDMA_AE_SOURCE_RSRC_EXHT_Q1, 370 info->ae_src == IRDMA_AE_SOURCE_RSRC_EXHT_XT_RR); 371 break; 372 case IRDMA_AE_PRIV_OPERATION_DENIED: 373 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 374 case IRDMA_AE_STAG_ZERO_INVALID: 375 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 376 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 377 case IRDMA_AE_DDP_UBE_INVALID_MO: 378 case IRDMA_AE_DDP_UBE_INVALID_QN: 379 case IRDMA_AE_DDP_NO_L_BIT: 380 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 381 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 382 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 383 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 384 case IRDMA_AE_INVALID_ARP_ENTRY: 385 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 386 case IRDMA_AE_STALE_ARP_ENTRY: 387 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 388 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 389 case IRDMA_AE_LLP_SYN_RECEIVED: 390 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 391 case IRDMA_AE_LCE_QP_CATASTROPHIC: 392 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC: 393 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 394 default: 395 irdma_dev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d ae_source=%d\n", 396 info->ae_id, info->qp, info->qp_cq_id, info->ae_src); 397 if (rdma_protocol_roce(&iwqp->iwdev->ibdev, 1)) { 398 ctx_info->roce_info->err_rq_idx_valid = info->err_rq_idx_valid; 399 if (info->rq) { 400 ctx_info->roce_info->err_rq_idx = info->wqe_idx; 401 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, 402 ctx_info); 403 } 404 irdma_set_flush_fields(qp, info); 405 irdma_cm_disconn(iwqp); 406 break; 407 } 408 ctx_info->iwarp_info->err_rq_idx_valid = info->err_rq_idx_valid; 409 if (info->rq) { 410 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx; 411 ctx_info->tcp_info_valid = false; 412 ctx_info->iwarp_info_valid = true; 413 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, 414 ctx_info); 415 } 416 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS && 417 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) { 418 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0); 419 irdma_cm_disconn(iwqp); 420 } else { 421 irdma_terminate_connection(qp, info); 422 } 423 break; 424 } 425 if (info->qp) 426 irdma_qp_rem_ref(&iwqp->ibqp); 427 } while (1); 428 429 if (aeqcnt) 430 irdma_sc_repost_aeq_entries(dev, aeqcnt); 431 } 432 433 /** 434 * irdma_ena_intr - set up device interrupts 435 * @dev: hardware control device structure 436 * @msix_id: id of the interrupt to be enabled 437 */ 438 static void 439 irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id) 440 { 441 dev->irq_ops->irdma_en_irq(dev, msix_id); 442 } 443 444 /** 445 * irdma_dpc - tasklet for aeq and ceq 0 446 * @t: tasklet_struct ptr 447 */ 448 static void 449 irdma_dpc(unsigned long t) 450 { 451 struct irdma_pci_f *rf = from_tasklet(rf, (struct tasklet_struct *)t, 452 dpc_tasklet); 453 454 if (rf->msix_shared) 455 irdma_process_ceq(rf, rf->ceqlist); 456 irdma_process_aeq(rf); 457 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx); 458 } 459 460 /** 461 * irdma_ceq_dpc - dpc handler for CEQ 462 * @t: tasklet_struct ptr 463 */ 464 static void 465 irdma_ceq_dpc(unsigned long t) 466 { 467 struct irdma_ceq *iwceq = from_tasklet(iwceq, (struct tasklet_struct *)t, 468 dpc_tasklet); 469 struct irdma_pci_f *rf = iwceq->rf; 470 471 irdma_process_ceq(rf, iwceq); 472 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx); 473 } 474 475 /** 476 * irdma_save_msix_info - copy msix vector information to iwarp device 477 * @rf: RDMA PCI function 478 * 479 * Allocate iwdev msix table and copy the msix info to the table 480 * Return 0 if successful, otherwise return error 481 */ 482 static int 483 irdma_save_msix_info(struct irdma_pci_f *rf) 484 { 485 struct irdma_qvlist_info *iw_qvlist; 486 struct irdma_qv_info *iw_qvinfo; 487 u32 ceq_idx; 488 u32 i; 489 u32 size; 490 491 if (!rf->msix_count) { 492 irdma_dev_err(to_ibdev(&rf->sc_dev), "No MSI-X vectors reserved for RDMA.\n"); 493 return -EINVAL; 494 } 495 496 size = sizeof(struct irdma_msix_vector) * rf->msix_count; 497 size += sizeof(struct irdma_qvlist_info); 498 size += sizeof(struct irdma_qv_info) * rf->msix_count - 1; 499 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL); 500 if (!rf->iw_msixtbl) 501 return -ENOMEM; 502 503 rf->iw_qvlist = (struct irdma_qvlist_info *) 504 (&rf->iw_msixtbl[rf->msix_count]); 505 iw_qvlist = rf->iw_qvlist; 506 iw_qvinfo = iw_qvlist->qv_info; 507 iw_qvlist->num_vectors = rf->msix_count; 508 if (rf->msix_count <= num_online_cpus()) 509 rf->msix_shared = true; 510 else if (rf->msix_count > num_online_cpus() + 1) 511 rf->msix_count = num_online_cpus() + 1; 512 513 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) { 514 rf->iw_msixtbl[i].idx = rf->msix_info.entry + i; 515 rf->iw_msixtbl[i].cpu_affinity = ceq_idx; 516 if (!i) { 517 iw_qvinfo->aeq_idx = 0; 518 if (rf->msix_shared) 519 iw_qvinfo->ceq_idx = ceq_idx++; 520 else 521 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; 522 } else { 523 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; 524 iw_qvinfo->ceq_idx = ceq_idx++; 525 } 526 iw_qvinfo->itr_idx = IRDMA_IDX_NOITR; 527 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx; 528 } 529 530 return 0; 531 } 532 533 /** 534 * irdma_irq_handler - interrupt handler for aeq and ceq0 535 * @data: RDMA PCI function 536 */ 537 static void 538 irdma_irq_handler(void *data) 539 { 540 struct irdma_pci_f *rf = data; 541 542 tasklet_schedule(&rf->dpc_tasklet); 543 } 544 545 /** 546 * irdma_ceq_handler - interrupt handler for ceq 547 * @data: ceq pointer 548 */ 549 static void 550 irdma_ceq_handler(void *data) 551 { 552 struct irdma_ceq *iwceq = data; 553 554 tasklet_schedule(&iwceq->dpc_tasklet); 555 } 556 557 /** 558 * irdma_free_irq - free device interrupts in FreeBSD manner 559 * @rf: RDMA PCI function 560 * @msix_vec: msix vector to disable irq 561 * 562 * The function is called when destroying irq. It tearsdown 563 * the interrupt and release resources. 564 */ 565 static void 566 irdma_free_irq(struct irdma_pci_f *rf, struct irdma_msix_vector *msix_vec) 567 { 568 if (msix_vec->tag) { 569 bus_teardown_intr(rf->dev_ctx.dev, msix_vec->res, 570 msix_vec->tag); 571 msix_vec->tag = NULL; 572 } 573 if (msix_vec->res) { 574 bus_release_resource(rf->dev_ctx.dev, SYS_RES_IRQ, 575 msix_vec->idx + 1, 576 msix_vec->res); 577 msix_vec->res = NULL; 578 } 579 } 580 581 /** 582 * irdma_destroy_irq - destroy device interrupts 583 * @rf: RDMA PCI function 584 * @msix_vec: msix vector to disable irq 585 * @dev_id: parameter to pass to free_irq (used during irq setup) 586 * 587 * The function is called when destroying aeq/ceq 588 */ 589 static void 590 irdma_destroy_irq(struct irdma_pci_f *rf, 591 struct irdma_msix_vector *msix_vec, void *dev_id) 592 { 593 struct irdma_sc_dev *dev = &rf->sc_dev; 594 595 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx); 596 irdma_free_irq(rf, msix_vec); 597 } 598 599 /** 600 * irdma_destroy_cqp - destroy control qp 601 * @rf: RDMA PCI function 602 * @free_hwcqp: 1 if hw cqp should be freed 603 * 604 * Issue destroy cqp request and 605 * free the resources associated with the cqp 606 */ 607 static void 608 irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp) 609 { 610 struct irdma_sc_dev *dev = &rf->sc_dev; 611 struct irdma_cqp *cqp = &rf->cqp; 612 int status = 0; 613 614 if (rf->cqp_cmpl_wq) 615 destroy_workqueue(rf->cqp_cmpl_wq); 616 status = irdma_sc_cqp_destroy(dev->cqp, free_hwcqp); 617 if (status) 618 irdma_debug(dev, IRDMA_DEBUG_ERR, "Destroy CQP failed %d\n", status); 619 620 irdma_cleanup_pending_cqp_op(rf); 621 irdma_free_dma_mem(dev->hw, &cqp->sq); 622 kfree(cqp->scratch_array); 623 cqp->scratch_array = NULL; 624 kfree(cqp->cqp_requests); 625 cqp->cqp_requests = NULL; 626 } 627 628 static void 629 irdma_destroy_virt_aeq(struct irdma_pci_f *rf) 630 { 631 struct irdma_aeq *aeq = &rf->aeq; 632 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 633 dma_addr_t *pg_arr = (dma_addr_t *) aeq->palloc.level1.addr; 634 635 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt); 636 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 637 vfree(aeq->mem.va); 638 } 639 640 /** 641 * irdma_destroy_aeq - destroy aeq 642 * @rf: RDMA PCI function 643 * 644 * Issue a destroy aeq request and 645 * free the resources associated with the aeq 646 * The function is called during driver unload 647 */ 648 static void 649 irdma_destroy_aeq(struct irdma_pci_f *rf) 650 { 651 struct irdma_sc_dev *dev = &rf->sc_dev; 652 struct irdma_aeq *aeq = &rf->aeq; 653 int status = -EBUSY; 654 655 if (!rf->msix_shared) { 656 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false); 657 irdma_destroy_irq(rf, rf->iw_msixtbl, rf); 658 } 659 if (rf->reset) 660 goto exit; 661 662 aeq->sc_aeq.size = 0; 663 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY); 664 if (status) 665 irdma_debug(dev, IRDMA_DEBUG_ERR, "Destroy AEQ failed %d\n", status); 666 667 exit: 668 if (aeq->virtual_map) 669 irdma_destroy_virt_aeq(rf); 670 else 671 irdma_free_dma_mem(dev->hw, &aeq->mem); 672 } 673 674 /** 675 * irdma_destroy_ceq - destroy ceq 676 * @rf: RDMA PCI function 677 * @iwceq: ceq to be destroyed 678 * 679 * Issue a destroy ceq request and 680 * free the resources associated with the ceq 681 */ 682 static void 683 irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq) 684 { 685 struct irdma_sc_dev *dev = &rf->sc_dev; 686 int status; 687 688 if (rf->reset) 689 goto exit; 690 691 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1); 692 if (status) { 693 irdma_debug(dev, IRDMA_DEBUG_ERR, "CEQ destroy command failed %d\n", status); 694 goto exit; 695 } 696 697 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq); 698 if (status) 699 irdma_debug(dev, IRDMA_DEBUG_ERR, 700 "CEQ destroy completion failed %d\n", 701 status); 702 exit: 703 spin_lock_destroy(&iwceq->ce_lock); 704 spin_lock_destroy(&iwceq->sc_ceq.req_cq_lock); 705 kfree(iwceq->sc_ceq.reg_cq); 706 irdma_free_dma_mem(dev->hw, &iwceq->mem); 707 } 708 709 /** 710 * irdma_del_ceq_0 - destroy ceq 0 711 * @rf: RDMA PCI function 712 * 713 * Disable the ceq 0 interrupt and destroy the ceq 0 714 */ 715 static void 716 irdma_del_ceq_0(struct irdma_pci_f *rf) 717 { 718 struct irdma_ceq *iwceq = rf->ceqlist; 719 struct irdma_msix_vector *msix_vec; 720 721 if (rf->msix_shared) { 722 msix_vec = &rf->iw_msixtbl[0]; 723 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, 724 msix_vec->ceq_id, 725 msix_vec->idx, false); 726 irdma_destroy_irq(rf, msix_vec, rf); 727 } else { 728 msix_vec = &rf->iw_msixtbl[1]; 729 irdma_destroy_irq(rf, msix_vec, iwceq); 730 } 731 732 irdma_destroy_ceq(rf, iwceq); 733 rf->sc_dev.ceq_valid = false; 734 rf->ceqs_count = 0; 735 } 736 737 /** 738 * irdma_del_ceqs - destroy all ceq's except CEQ 0 739 * @rf: RDMA PCI function 740 * 741 * Go through all of the device ceq's, except 0, and for each 742 * ceq disable the ceq interrupt and destroy the ceq 743 */ 744 static void 745 irdma_del_ceqs(struct irdma_pci_f *rf) 746 { 747 struct irdma_ceq *iwceq = &rf->ceqlist[1]; 748 struct irdma_msix_vector *msix_vec; 749 u32 i = 0; 750 751 if (rf->msix_shared) 752 msix_vec = &rf->iw_msixtbl[1]; 753 else 754 msix_vec = &rf->iw_msixtbl[2]; 755 756 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) { 757 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id, 758 msix_vec->idx, false); 759 irdma_destroy_irq(rf, msix_vec, iwceq); 760 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 761 IRDMA_OP_CEQ_DESTROY); 762 spin_lock_destroy(&iwceq->ce_lock); 763 spin_lock_destroy(&iwceq->sc_ceq.req_cq_lock); 764 kfree(iwceq->sc_ceq.reg_cq); 765 irdma_free_dma_mem(rf->sc_dev.hw, &iwceq->mem); 766 } 767 rf->ceqs_count = 1; 768 } 769 770 /** 771 * irdma_destroy_ccq - destroy control cq 772 * @rf: RDMA PCI function 773 * 774 * Issue destroy ccq request and 775 * free the resources associated with the ccq 776 */ 777 static void 778 irdma_destroy_ccq(struct irdma_pci_f *rf) 779 { 780 struct irdma_sc_dev *dev = &rf->sc_dev; 781 struct irdma_ccq *ccq = &rf->ccq; 782 int status = 0; 783 784 if (!rf->reset) 785 status = irdma_sc_ccq_destroy(dev->ccq, 0, true); 786 if (status) 787 irdma_debug(dev, IRDMA_DEBUG_ERR, "CCQ destroy failed %d\n", status); 788 irdma_free_dma_mem(dev->hw, &ccq->mem_cq); 789 } 790 791 /** 792 * irdma_close_hmc_objects_type - delete hmc objects of a given type 793 * @dev: iwarp device 794 * @obj_type: the hmc object type to be deleted 795 * @hmc_info: host memory info struct 796 * @privileged: permission to close HMC objects 797 * @reset: true if called before reset 798 */ 799 static void 800 irdma_close_hmc_objects_type(struct irdma_sc_dev *dev, 801 enum irdma_hmc_rsrc_type obj_type, 802 struct irdma_hmc_info *hmc_info, 803 bool privileged, bool reset) 804 { 805 struct irdma_hmc_del_obj_info info = {0}; 806 807 info.hmc_info = hmc_info; 808 info.rsrc_type = obj_type; 809 info.count = hmc_info->hmc_obj[obj_type].cnt; 810 info.privileged = privileged; 811 if (irdma_sc_del_hmc_obj(dev, &info, reset)) 812 irdma_debug(dev, IRDMA_DEBUG_ERR, 813 "del HMC obj of type %d failed\n", 814 obj_type); 815 } 816 817 /** 818 * irdma_del_hmc_objects - remove all device hmc objects 819 * @dev: iwarp device 820 * @hmc_info: hmc_info to free 821 * @privileged: permission to delete HMC objects 822 * @reset: true if called before reset 823 * @vers: hardware version 824 */ 825 void 826 irdma_del_hmc_objects(struct irdma_sc_dev *dev, 827 struct irdma_hmc_info *hmc_info, bool privileged, 828 bool reset, enum irdma_vers vers) 829 { 830 unsigned int i; 831 832 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 833 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 834 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 835 hmc_info, privileged, reset); 836 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 837 break; 838 } 839 } 840 841 /** 842 * irdma_create_hmc_obj_type - create hmc object of a given type 843 * @dev: hardware control device structure 844 * @info: information for the hmc object to create 845 */ 846 static int 847 irdma_create_hmc_obj_type(struct irdma_sc_dev *dev, 848 struct irdma_hmc_create_obj_info *info) 849 { 850 return irdma_sc_create_hmc_obj(dev, info); 851 } 852 853 /** 854 * irdma_create_hmc_objs - create all hmc objects for the device 855 * @rf: RDMA PCI function 856 * @privileged: permission to create HMC objects 857 * @vers: HW version 858 * 859 * Create the device hmc objects and allocate hmc pages 860 * Return 0 if successful, otherwise clean up and return error 861 */ 862 static int 863 irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, 864 enum irdma_vers vers) 865 { 866 struct irdma_sc_dev *dev = &rf->sc_dev; 867 struct irdma_hmc_create_obj_info info = {0}; 868 int i, status = 0; 869 870 info.hmc_info = dev->hmc_info; 871 info.privileged = privileged; 872 info.entry_type = rf->sd_type; 873 874 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 875 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE) 876 continue; 877 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) { 878 info.rsrc_type = iw_hmc_obj_types[i]; 879 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt; 880 info.add_sd_cnt = 0; 881 status = irdma_create_hmc_obj_type(dev, &info); 882 if (status) { 883 irdma_debug(dev, IRDMA_DEBUG_ERR, 884 "create obj type %d status = %d\n", 885 iw_hmc_obj_types[i], status); 886 break; 887 } 888 } 889 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 890 break; 891 } 892 893 if (!status) 894 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id, 895 true, true); 896 897 while (i) { 898 i--; 899 /* destroy the hmc objects of a given type */ 900 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 901 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 902 dev->hmc_info, privileged, 903 false); 904 } 905 906 return status; 907 } 908 909 /** 910 * irdma_obj_aligned_mem - get aligned memory from device allocated memory 911 * @rf: RDMA PCI function 912 * @memptr: points to the memory addresses 913 * @size: size of memory needed 914 * @mask: mask for the aligned memory 915 * 916 * Get aligned memory of the requested size and 917 * update the memptr to point to the new aligned memory 918 * Return 0 if successful, otherwise return no memory error 919 */ 920 static int 921 irdma_obj_aligned_mem(struct irdma_pci_f *rf, 922 struct irdma_dma_mem *memptr, u32 size, 923 u32 mask) 924 { 925 unsigned long va, newva; 926 unsigned long extra; 927 928 va = (unsigned long)rf->obj_next.va; 929 newva = va; 930 if (mask) 931 newva = ALIGN(va, (unsigned long)mask + 1ULL); 932 extra = newva - va; 933 memptr->va = (u8 *)va + extra; 934 memptr->pa = rf->obj_next.pa + extra; 935 memptr->size = size; 936 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size)) 937 return -ENOMEM; 938 939 rf->obj_next.va = (u8 *)memptr->va + size; 940 rf->obj_next.pa = memptr->pa + size; 941 942 return 0; 943 } 944 945 /** 946 * irdma_create_cqp - create control qp 947 * @rf: RDMA PCI function 948 * 949 * Return 0, if the cqp and all the resources associated with it 950 * are successfully created, otherwise return error 951 */ 952 static int 953 irdma_create_cqp(struct irdma_pci_f *rf) 954 { 955 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048; 956 struct irdma_dma_mem mem; 957 struct irdma_sc_dev *dev = &rf->sc_dev; 958 struct irdma_cqp_init_info cqp_init_info = {0}; 959 struct irdma_cqp *cqp = &rf->cqp; 960 u16 maj_err, min_err; 961 int i, status; 962 963 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL); 964 memset(cqp->cqp_requests, 0, sqsize * sizeof(*cqp->cqp_requests)); 965 if (!cqp->cqp_requests) 966 return -ENOMEM; 967 968 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL); 969 memset(cqp->scratch_array, 0, sqsize * sizeof(*cqp->scratch_array)); 970 if (!cqp->scratch_array) { 971 status = -ENOMEM; 972 goto err_scratch; 973 } 974 975 dev->cqp = &cqp->sc_cqp; 976 dev->cqp->dev = dev; 977 cqp->sq.size = sizeof(struct irdma_cqp_sq_wqe) * sqsize; 978 cqp->sq.va = irdma_allocate_dma_mem(dev->hw, &cqp->sq, cqp->sq.size, 979 IRDMA_CQP_ALIGNMENT); 980 if (!cqp->sq.va) { 981 status = -ENOMEM; 982 goto err_sq; 983 } 984 985 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx), 986 IRDMA_HOST_CTX_ALIGNMENT_M); 987 if (status) 988 goto err_ctx; 989 990 dev->cqp->host_ctx_pa = mem.pa; 991 dev->cqp->host_ctx = mem.va; 992 /* populate the cqp init info */ 993 cqp_init_info.dev = dev; 994 cqp_init_info.sq_size = sqsize; 995 cqp_init_info.sq = cqp->sq.va; 996 cqp_init_info.sq_pa = cqp->sq.pa; 997 cqp_init_info.host_ctx_pa = mem.pa; 998 cqp_init_info.host_ctx = mem.va; 999 cqp_init_info.hmc_profile = rf->rsrc_profile; 1000 cqp_init_info.scratch_array = cqp->scratch_array; 1001 cqp_init_info.protocol_used = rf->protocol_used; 1002 cqp_init_info.en_rem_endpoint_trk = rf->en_rem_endpoint_trk; 1003 memcpy(&cqp_init_info.dcqcn_params, &rf->dcqcn_params, 1004 sizeof(cqp_init_info.dcqcn_params)); 1005 1006 switch (rf->rdma_ver) { 1007 case IRDMA_GEN_1: 1008 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1; 1009 break; 1010 case IRDMA_GEN_2: 1011 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2; 1012 break; 1013 } 1014 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info); 1015 if (status) { 1016 irdma_debug(dev, IRDMA_DEBUG_ERR, "cqp init status %d\n", status); 1017 goto err_ctx; 1018 } 1019 1020 spin_lock_init(&cqp->req_lock); 1021 spin_lock_init(&cqp->compl_lock); 1022 1023 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err); 1024 if (status) { 1025 irdma_debug(dev, IRDMA_DEBUG_ERR, 1026 "cqp create failed - status %d maj_err %d min_err %d\n", 1027 status, maj_err, min_err); 1028 goto err_create; 1029 } 1030 1031 INIT_LIST_HEAD(&cqp->cqp_avail_reqs); 1032 INIT_LIST_HEAD(&cqp->cqp_pending_reqs); 1033 1034 /* init the waitqueue of the cqp_requests and add them to the list */ 1035 for (i = 0; i < sqsize; i++) { 1036 init_waitqueue_head(&cqp->cqp_requests[i].waitq); 1037 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs); 1038 } 1039 init_waitqueue_head(&cqp->remove_wq); 1040 return 0; 1041 1042 err_create: 1043 err_ctx: 1044 irdma_free_dma_mem(dev->hw, &cqp->sq); 1045 err_sq: 1046 kfree(cqp->scratch_array); 1047 cqp->scratch_array = NULL; 1048 err_scratch: 1049 kfree(cqp->cqp_requests); 1050 cqp->cqp_requests = NULL; 1051 1052 return status; 1053 } 1054 1055 /** 1056 * irdma_create_ccq - create control cq 1057 * @rf: RDMA PCI function 1058 * 1059 * Return 0, if the ccq and the resources associated with it 1060 * are successfully created, otherwise return error 1061 */ 1062 static int 1063 irdma_create_ccq(struct irdma_pci_f *rf) 1064 { 1065 struct irdma_sc_dev *dev = &rf->sc_dev; 1066 struct irdma_ccq_init_info info = {0}; 1067 struct irdma_ccq *ccq = &rf->ccq; 1068 int status; 1069 1070 dev->ccq = &ccq->sc_cq; 1071 dev->ccq->dev = dev; 1072 info.dev = dev; 1073 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area); 1074 ccq->mem_cq.size = sizeof(struct irdma_cqe) * IW_CCQ_SIZE; 1075 ccq->mem_cq.va = irdma_allocate_dma_mem(dev->hw, &ccq->mem_cq, 1076 ccq->mem_cq.size, 1077 IRDMA_CQ0_ALIGNMENT); 1078 if (!ccq->mem_cq.va) 1079 return -ENOMEM; 1080 1081 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area, 1082 ccq->shadow_area.size, 1083 IRDMA_SHADOWAREA_M); 1084 if (status) 1085 goto exit; 1086 1087 ccq->sc_cq.back_cq = ccq; 1088 /* populate the ccq init info */ 1089 info.cq_base = ccq->mem_cq.va; 1090 info.cq_pa = ccq->mem_cq.pa; 1091 info.num_elem = IW_CCQ_SIZE; 1092 info.shadow_area = ccq->shadow_area.va; 1093 info.shadow_area_pa = ccq->shadow_area.pa; 1094 info.ceqe_mask = false; 1095 info.ceq_id_valid = true; 1096 info.shadow_read_threshold = 16; 1097 info.vsi = &rf->default_vsi; 1098 status = irdma_sc_ccq_init(dev->ccq, &info); 1099 if (!status) 1100 status = irdma_sc_ccq_create(dev->ccq, 0, true, true); 1101 exit: 1102 if (status) 1103 irdma_free_dma_mem(dev->hw, &ccq->mem_cq); 1104 1105 return status; 1106 } 1107 1108 /** 1109 * irdma_alloc_set_mac - set up a mac address table entry 1110 * @iwdev: irdma device 1111 * 1112 * Allocate a mac ip entry and add it to the hw table Return 0 1113 * if successful, otherwise return error 1114 */ 1115 static int 1116 irdma_alloc_set_mac(struct irdma_device *iwdev) 1117 { 1118 int status; 1119 1120 status = irdma_alloc_local_mac_entry(iwdev->rf, 1121 &iwdev->mac_ip_table_idx); 1122 if (!status) { 1123 status = irdma_add_local_mac_entry(iwdev->rf, 1124 (const u8 *)if_getlladdr(iwdev->netdev), 1125 (u8)iwdev->mac_ip_table_idx); 1126 if (status) 1127 irdma_del_local_mac_entry(iwdev->rf, 1128 (u8)iwdev->mac_ip_table_idx); 1129 } 1130 return status; 1131 } 1132 1133 /** 1134 * irdma_irq_request - set up the msix interrupt vector 1135 * @rf: RDMA PCI function 1136 * @msix_vec: interrupt vector information 1137 * @handler: function pointer to associate with interrupt 1138 * @argument: argument passed to the handler 1139 * 1140 * Allocate interrupt resources and setup interrupt 1141 * Return 0 if successful, otherwise return error 1142 * Note that after this function bus_describe_intr shall 1143 * be called. 1144 */ 1145 static int 1146 irdma_irq_request(struct irdma_pci_f *rf, 1147 struct irdma_msix_vector *msix_vec, 1148 driver_intr_t handler, void *argument) 1149 { 1150 device_t dev = rf->dev_ctx.dev; 1151 int rid = msix_vec->idx + 1; 1152 int err, status; 1153 1154 msix_vec->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 1155 if (!msix_vec->res) { 1156 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1157 "Unable to allocate bus resource int[%d]\n", 1158 rid); 1159 return -EINVAL; 1160 } 1161 err = bus_setup_intr(dev, msix_vec->res, INTR_TYPE_NET | INTR_MPSAFE, 1162 NULL, handler, argument, &msix_vec->tag); 1163 if (err) { 1164 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1165 "Unable to register handler with %x status\n", 1166 err); 1167 status = -EINVAL; 1168 goto fail_intr; 1169 } 1170 return 0; 1171 1172 fail_intr: 1173 bus_release_resource(dev, SYS_RES_IRQ, rid, msix_vec->res); 1174 msix_vec->res = NULL; 1175 1176 return status; 1177 } 1178 1179 /** 1180 * irdma_cfg_ceq_vector - set up the msix interrupt vector for 1181 * ceq 1182 * @rf: RDMA PCI function 1183 * @iwceq: ceq associated with the vector 1184 * @ceq_id: the id number of the iwceq 1185 * @msix_vec: interrupt vector information 1186 * 1187 * Allocate interrupt resources and enable irq handling 1188 * Return 0 if successful, otherwise return error 1189 */ 1190 static int 1191 irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1192 u32 ceq_id, struct irdma_msix_vector *msix_vec) 1193 { 1194 int status; 1195 1196 if (rf->msix_shared && !ceq_id) { 1197 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1198 "irdma-%s-AEQCEQ-0", dev_name(&rf->pcidev->dev)); 1199 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1200 status = irdma_irq_request(rf, msix_vec, irdma_irq_handler, rf); 1201 if (status) 1202 return status; 1203 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "%s", msix_vec->name); 1204 } else { 1205 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1206 "irdma-%s-CEQ-%d", 1207 dev_name(&rf->pcidev->dev), ceq_id); 1208 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc); 1209 1210 status = irdma_irq_request(rf, msix_vec, irdma_ceq_handler, iwceq); 1211 if (status) 1212 return status; 1213 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "%s", msix_vec->name); 1214 } 1215 msix_vec->ceq_id = ceq_id; 1216 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true); 1217 1218 return 0; 1219 } 1220 1221 /** 1222 * irdma_cfg_aeq_vector - set up the msix vector for aeq 1223 * @rf: RDMA PCI function 1224 * 1225 * Allocate interrupt resources and enable irq handling 1226 * Return 0 if successful, otherwise return error 1227 */ 1228 static int 1229 irdma_cfg_aeq_vector(struct irdma_pci_f *rf) 1230 { 1231 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl; 1232 u32 ret = 0; 1233 1234 if (!rf->msix_shared) { 1235 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1236 "irdma-%s-AEQ", dev_name(&rf->pcidev->dev)); 1237 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1238 ret = irdma_irq_request(rf, msix_vec, irdma_irq_handler, rf); 1239 if (ret) 1240 return ret; 1241 bus_describe_intr(rf->dev_ctx.dev, msix_vec->res, msix_vec->tag, "%s", msix_vec->name); 1242 } 1243 if (ret) { 1244 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, "aeq irq config fail\n"); 1245 return -EINVAL; 1246 } 1247 1248 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true); 1249 1250 return 0; 1251 } 1252 1253 /** 1254 * irdma_create_ceq - create completion event queue 1255 * @rf: RDMA PCI function 1256 * @iwceq: pointer to the ceq resources to be created 1257 * @ceq_id: the id number of the iwceq 1258 * @vsi: SC vsi struct 1259 * 1260 * Return 0, if the ceq and the resources associated with it 1261 * are successfully created, otherwise return error 1262 */ 1263 static int 1264 irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1265 u32 ceq_id, struct irdma_sc_vsi *vsi) 1266 { 1267 int status; 1268 struct irdma_ceq_init_info info = {0}; 1269 struct irdma_sc_dev *dev = &rf->sc_dev; 1270 u64 scratch; 1271 u32 ceq_size; 1272 1273 info.ceq_id = ceq_id; 1274 iwceq->rf = rf; 1275 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 1276 dev->hw_attrs.max_hw_ceq_size); 1277 iwceq->mem.size = sizeof(struct irdma_ceqe) * ceq_size; 1278 iwceq->mem.va = irdma_allocate_dma_mem(dev->hw, &iwceq->mem, 1279 iwceq->mem.size, 1280 IRDMA_CEQ_ALIGNMENT); 1281 if (!iwceq->mem.va) 1282 return -ENOMEM; 1283 1284 info.ceq_id = ceq_id; 1285 info.ceqe_base = iwceq->mem.va; 1286 info.ceqe_pa = iwceq->mem.pa; 1287 info.elem_cnt = ceq_size; 1288 info.reg_cq = kzalloc(sizeof(struct irdma_sc_cq *) * info.elem_cnt, GFP_KERNEL); 1289 1290 iwceq->sc_ceq.ceq_id = ceq_id; 1291 info.dev = dev; 1292 info.vsi = vsi; 1293 scratch = (uintptr_t)&rf->cqp.sc_cqp; 1294 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info); 1295 if (!status) { 1296 if (dev->ceq_valid) 1297 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 1298 IRDMA_OP_CEQ_CREATE); 1299 else 1300 status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch); 1301 } 1302 1303 if (status) { 1304 kfree(info.reg_cq); 1305 irdma_free_dma_mem(dev->hw, &iwceq->mem); 1306 } 1307 1308 return status; 1309 } 1310 1311 /** 1312 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource 1313 * @rf: RDMA PCI function 1314 * 1315 * Allocate a list for all device completion event queues 1316 * Create the ceq 0 and configure it's msix interrupt vector 1317 * Return 0, if successfully set up, otherwise return error 1318 */ 1319 static int 1320 irdma_setup_ceq_0(struct irdma_pci_f *rf) 1321 { 1322 struct irdma_ceq *iwceq; 1323 struct irdma_msix_vector *msix_vec; 1324 u32 i; 1325 int status = 0; 1326 u32 num_ceqs; 1327 1328 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1329 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL); 1330 memset(rf->ceqlist, 0, num_ceqs * sizeof(*rf->ceqlist)); 1331 if (!rf->ceqlist) { 1332 status = -ENOMEM; 1333 goto exit; 1334 } 1335 1336 iwceq = &rf->ceqlist[0]; 1337 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi); 1338 if (status) { 1339 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1340 "create ceq status = %d\n", 1341 status); 1342 goto exit; 1343 } 1344 1345 spin_lock_init(&iwceq->ce_lock); 1346 i = rf->msix_shared ? 0 : 1; 1347 msix_vec = &rf->iw_msixtbl[i]; 1348 iwceq->irq = msix_vec->irq; 1349 iwceq->msix_idx = msix_vec->idx; 1350 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec); 1351 if (status) { 1352 irdma_destroy_ceq(rf, iwceq); 1353 goto exit; 1354 } 1355 1356 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1357 rf->ceqs_count++; 1358 1359 exit: 1360 if (status && !rf->ceqs_count) { 1361 kfree(rf->ceqlist); 1362 rf->ceqlist = NULL; 1363 return status; 1364 } 1365 rf->sc_dev.ceq_valid = true; 1366 1367 return 0; 1368 } 1369 1370 /** 1371 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources 1372 * @rf: RDMA PCI function 1373 * @vsi: VSI structure for this CEQ 1374 * 1375 * Allocate a list for all device completion event queues 1376 * Create the ceq's and configure their msix interrupt vectors 1377 * Return 0, if ceqs are successfully set up, otherwise return error 1378 */ 1379 static int 1380 irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi) 1381 { 1382 u32 i; 1383 u32 ceq_id; 1384 struct irdma_ceq *iwceq; 1385 struct irdma_msix_vector *msix_vec; 1386 int status; 1387 u32 num_ceqs; 1388 1389 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1390 i = (rf->msix_shared) ? 1 : 2; 1391 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) { 1392 iwceq = &rf->ceqlist[ceq_id]; 1393 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi); 1394 if (status) { 1395 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_ERR, 1396 "create ceq status = %d\n", 1397 status); 1398 goto del_ceqs; 1399 } 1400 spin_lock_init(&iwceq->ce_lock); 1401 msix_vec = &rf->iw_msixtbl[i]; 1402 iwceq->irq = msix_vec->irq; 1403 iwceq->msix_idx = msix_vec->idx; 1404 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec); 1405 if (status) { 1406 irdma_destroy_ceq(rf, iwceq); 1407 goto del_ceqs; 1408 } 1409 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1410 rf->ceqs_count++; 1411 } 1412 1413 return 0; 1414 1415 del_ceqs: 1416 irdma_del_ceqs(rf); 1417 1418 return status; 1419 } 1420 1421 static int 1422 irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size) 1423 { 1424 struct irdma_aeq *aeq = &rf->aeq; 1425 dma_addr_t *pg_arr; 1426 u32 pg_cnt; 1427 int status; 1428 1429 if (rf->rdma_ver < IRDMA_GEN_2) 1430 return -EOPNOTSUPP; 1431 1432 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size; 1433 aeq->mem.va = vzalloc(aeq->mem.size); 1434 1435 if (!aeq->mem.va) 1436 return -ENOMEM; 1437 1438 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 1439 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true); 1440 if (status) { 1441 vfree(aeq->mem.va); 1442 return status; 1443 } 1444 1445 pg_arr = (dma_addr_t *) aeq->palloc.level1.addr; 1446 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt); 1447 if (status) { 1448 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 1449 vfree(aeq->mem.va); 1450 return status; 1451 } 1452 1453 return 0; 1454 } 1455 1456 /** 1457 * irdma_create_aeq - create async event queue 1458 * @rf: RDMA PCI function 1459 * 1460 * Return 0, if the aeq and the resources associated with it 1461 * are successfully created, otherwise return error 1462 */ 1463 static int 1464 irdma_create_aeq(struct irdma_pci_f *rf) 1465 { 1466 struct irdma_aeq_init_info info = {0}; 1467 struct irdma_sc_dev *dev = &rf->sc_dev; 1468 struct irdma_aeq *aeq = &rf->aeq; 1469 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info; 1470 u32 aeq_size; 1471 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1; 1472 int status; 1473 1474 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt + 1475 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1476 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size); 1477 1478 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * aeq_size; 1479 aeq->mem.va = irdma_allocate_dma_mem(dev->hw, &aeq->mem, aeq->mem.size, 1480 IRDMA_AEQ_ALIGNMENT); 1481 if (aeq->mem.va) 1482 goto skip_virt_aeq; 1483 1484 /* physically mapped aeq failed. setup virtual aeq */ 1485 status = irdma_create_virt_aeq(rf, aeq_size); 1486 if (status) 1487 return status; 1488 1489 info.virtual_map = true; 1490 aeq->virtual_map = info.virtual_map; 1491 info.pbl_chunk_size = 1; 1492 info.first_pm_pbl_idx = aeq->palloc.level1.idx; 1493 1494 skip_virt_aeq: 1495 info.aeqe_base = aeq->mem.va; 1496 info.aeq_elem_pa = aeq->mem.pa; 1497 info.elem_cnt = aeq_size; 1498 info.dev = dev; 1499 info.msix_idx = rf->iw_msixtbl->idx; 1500 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info); 1501 if (status) 1502 goto err; 1503 1504 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE); 1505 if (status) 1506 goto err; 1507 1508 return 0; 1509 1510 err: 1511 if (aeq->virtual_map) 1512 irdma_destroy_virt_aeq(rf); 1513 else 1514 irdma_free_dma_mem(dev->hw, &aeq->mem); 1515 1516 return status; 1517 } 1518 1519 /** 1520 * irdma_setup_aeq - set up the device aeq 1521 * @rf: RDMA PCI function 1522 * 1523 * Create the aeq and configure its msix interrupt vector 1524 * Return 0 if successful, otherwise return error 1525 */ 1526 static int 1527 irdma_setup_aeq(struct irdma_pci_f *rf) 1528 { 1529 struct irdma_sc_dev *dev = &rf->sc_dev; 1530 int status; 1531 1532 status = irdma_create_aeq(rf); 1533 if (status) 1534 return status; 1535 1536 status = irdma_cfg_aeq_vector(rf); 1537 if (status) { 1538 irdma_destroy_aeq(rf); 1539 return status; 1540 } 1541 1542 if (!rf->msix_shared) 1543 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx); 1544 1545 return 0; 1546 } 1547 1548 /** 1549 * irdma_initialize_ilq - create iwarp local queue for cm 1550 * @iwdev: irdma device 1551 * 1552 * Return 0 if successful, otherwise return error 1553 */ 1554 static int 1555 irdma_initialize_ilq(struct irdma_device *iwdev) 1556 { 1557 struct irdma_puda_rsrc_info info = {0}; 1558 int status; 1559 1560 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ; 1561 info.cq_id = 1; 1562 info.qp_id = 1; 1563 info.count = 1; 1564 info.pd_id = 1; 1565 info.abi_ver = IRDMA_ABI_VER; 1566 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1567 info.rq_size = info.sq_size; 1568 info.buf_size = 1024; 1569 info.tx_buf_cnt = 2 * info.sq_size; 1570 info.receive = irdma_receive_ilq; 1571 info.xmit_complete = irdma_free_sqbuf; 1572 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1573 if (status) 1574 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_ERR, "ilq create fail\n"); 1575 1576 return status; 1577 } 1578 1579 /** 1580 * irdma_initialize_ieq - create iwarp exception queue 1581 * @iwdev: irdma device 1582 * 1583 * Return 0 if successful, otherwise return error 1584 */ 1585 static int 1586 irdma_initialize_ieq(struct irdma_device *iwdev) 1587 { 1588 struct irdma_puda_rsrc_info info = {0}; 1589 int status; 1590 1591 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ; 1592 info.cq_id = 2; 1593 info.qp_id = iwdev->vsi.exception_lan_q; 1594 info.count = 1; 1595 info.pd_id = 2; 1596 info.abi_ver = IRDMA_ABI_VER; 1597 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1598 info.rq_size = info.sq_size; 1599 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD; 1600 info.tx_buf_cnt = 4096; 1601 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1602 if (status) 1603 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_ERR, "ieq create fail\n"); 1604 1605 return status; 1606 } 1607 1608 /** 1609 * irdma_reinitialize_ieq - destroy and re-create ieq 1610 * @vsi: VSI structure 1611 */ 1612 void 1613 irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi) 1614 { 1615 struct irdma_device *iwdev = vsi->back_vsi; 1616 struct irdma_pci_f *rf = iwdev->rf; 1617 1618 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false); 1619 if (irdma_initialize_ieq(iwdev)) { 1620 iwdev->rf->reset = true; 1621 rf->gen_ops.request_reset(rf); 1622 } 1623 } 1624 1625 /** 1626 * irdma_hmc_setup - create hmc objects for the device 1627 * @rf: RDMA PCI function 1628 * 1629 * Set up the device private memory space for the number and size of 1630 * the hmc objects and create the objects 1631 * Return 0 if successful, otherwise return error 1632 */ 1633 static int 1634 irdma_hmc_setup(struct irdma_pci_f *rf) 1635 { 1636 int status; 1637 struct irdma_sc_dev *dev = &rf->sc_dev; 1638 u32 qpcnt; 1639 1640 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit; 1641 1642 rf->sd_type = IRDMA_SD_TYPE_DIRECT; 1643 status = irdma_cfg_fpm_val(dev, qpcnt); 1644 if (status) 1645 return status; 1646 1647 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver); 1648 1649 return status; 1650 } 1651 1652 /** 1653 * irdma_del_init_mem - deallocate memory resources 1654 * @rf: RDMA PCI function 1655 */ 1656 static void 1657 irdma_del_init_mem(struct irdma_pci_f *rf) 1658 { 1659 struct irdma_sc_dev *dev = &rf->sc_dev; 1660 1661 kfree(dev->hmc_info->sd_table.sd_entry); 1662 dev->hmc_info->sd_table.sd_entry = NULL; 1663 vfree(rf->mem_rsrc); 1664 rf->mem_rsrc = NULL; 1665 irdma_free_dma_mem(&rf->hw, &rf->obj_mem); 1666 if (rf->rdma_ver != IRDMA_GEN_1) { 1667 kfree(rf->allocated_ws_nodes); 1668 rf->allocated_ws_nodes = NULL; 1669 } 1670 mutex_destroy(&dev->ws_mutex); 1671 kfree(rf->ceqlist); 1672 rf->ceqlist = NULL; 1673 kfree(rf->iw_msixtbl); 1674 rf->iw_msixtbl = NULL; 1675 kfree(rf->hmc_info_mem); 1676 rf->hmc_info_mem = NULL; 1677 } 1678 /** 1679 * irdma_initialize_dev - initialize device 1680 * @rf: RDMA PCI function 1681 * 1682 * Allocate memory for the hmc objects and initialize iwdev 1683 * Return 0 if successful, otherwise clean up the resources 1684 * and return error 1685 */ 1686 static int 1687 irdma_initialize_dev(struct irdma_pci_f *rf) 1688 { 1689 int status; 1690 struct irdma_sc_dev *dev = &rf->sc_dev; 1691 struct irdma_device_init_info info = {0}; 1692 struct irdma_dma_mem mem; 1693 u32 size; 1694 1695 size = sizeof(struct irdma_hmc_pble_rsrc) + 1696 sizeof(struct irdma_hmc_info) + 1697 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX); 1698 1699 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL); 1700 if (!rf->hmc_info_mem) 1701 return -ENOMEM; 1702 1703 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem; 1704 dev->hmc_info = &rf->hw.hmc; 1705 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *) 1706 (rf->pble_rsrc + 1); 1707 1708 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE, 1709 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); 1710 if (status) 1711 goto error; 1712 1713 info.fpm_query_buf_pa = mem.pa; 1714 info.fpm_query_buf = mem.va; 1715 1716 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE, 1717 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M); 1718 if (status) 1719 goto error; 1720 1721 info.fpm_commit_buf_pa = mem.pa; 1722 info.fpm_commit_buf = mem.va; 1723 1724 info.bar0 = rf->hw.hw_addr; 1725 info.hmc_fn_id = rf->peer_info->pf_id; 1726 /* 1727 * the debug_mask is already assigned at this point through sysctl and so the value shouldn't be overwritten 1728 */ 1729 info.debug_mask = rf->sc_dev.debug_mask; 1730 info.hw = &rf->hw; 1731 status = irdma_sc_dev_init(&rf->sc_dev, &info); 1732 if (status) 1733 goto error; 1734 1735 return status; 1736 error: 1737 kfree(rf->hmc_info_mem); 1738 rf->hmc_info_mem = NULL; 1739 1740 return status; 1741 } 1742 1743 /** 1744 * irdma_rt_deinit_hw - clean up the irdma device resources 1745 * @iwdev: irdma device 1746 * 1747 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the 1748 * device queues and free the pble and the hmc objects 1749 */ 1750 void 1751 irdma_rt_deinit_hw(struct irdma_device *iwdev) 1752 { 1753 struct irdma_sc_qp qp = {{0}}; 1754 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_INIT, "state = %d\n", iwdev->init_state); 1755 1756 switch (iwdev->init_state) { 1757 case IP_ADDR_REGISTERED: 1758 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1759 irdma_del_local_mac_entry(iwdev->rf, 1760 (u8)iwdev->mac_ip_table_idx); 1761 /* fallthrough */ 1762 case AEQ_CREATED: 1763 case PBLE_CHUNK_MEM: 1764 case CEQS_CREATED: 1765 case REM_ENDPOINT_TRK_CREATED: 1766 if (iwdev->rf->en_rem_endpoint_trk) { 1767 qp.dev = &iwdev->rf->sc_dev; 1768 qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID; 1769 qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP; 1770 irdma_cqp_qp_destroy_cmd(qp.dev, &qp); 1771 } 1772 /* fallthrough */ 1773 case IEQ_CREATED: 1774 if (!iwdev->roce_mode) 1775 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, 1776 iwdev->rf->reset); 1777 /* fallthrough */ 1778 case ILQ_CREATED: 1779 if (!iwdev->roce_mode) 1780 irdma_puda_dele_rsrc(&iwdev->vsi, 1781 IRDMA_PUDA_RSRC_TYPE_ILQ, 1782 iwdev->rf->reset); 1783 break; 1784 default: 1785 irdma_dev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state); 1786 break; 1787 } 1788 1789 irdma_cleanup_cm_core(&iwdev->cm_core); 1790 if (iwdev->vsi.pestat) { 1791 irdma_vsi_stats_free(&iwdev->vsi); 1792 kfree(iwdev->vsi.pestat); 1793 } 1794 if (iwdev->cleanup_wq) 1795 destroy_workqueue(iwdev->cleanup_wq); 1796 } 1797 1798 static int 1799 irdma_setup_init_state(struct irdma_pci_f *rf) 1800 { 1801 int status; 1802 1803 status = irdma_save_msix_info(rf); 1804 if (status) 1805 return status; 1806 1807 rf->obj_mem.size = 8192; 1808 rf->obj_mem.va = irdma_allocate_dma_mem(&rf->hw, &rf->obj_mem, 1809 rf->obj_mem.size, 1810 IRDMA_HW_PAGE_SIZE); 1811 if (!rf->obj_mem.va) { 1812 status = -ENOMEM; 1813 goto clean_msixtbl; 1814 } 1815 1816 rf->obj_next = rf->obj_mem; 1817 status = irdma_initialize_dev(rf); 1818 if (status) 1819 goto clean_obj_mem; 1820 1821 return 0; 1822 1823 clean_obj_mem: 1824 irdma_free_dma_mem(&rf->hw, &rf->obj_mem); 1825 clean_msixtbl: 1826 kfree(rf->iw_msixtbl); 1827 rf->iw_msixtbl = NULL; 1828 return status; 1829 } 1830 1831 /** 1832 * irdma_get_used_rsrc - determine resources used internally 1833 * @iwdev: irdma device 1834 * 1835 * Called at the end of open to get all internal allocations 1836 */ 1837 static void 1838 irdma_get_used_rsrc(struct irdma_device *iwdev) 1839 { 1840 iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds, 1841 iwdev->rf->max_pd); 1842 iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps, 1843 iwdev->rf->max_qp); 1844 iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs, 1845 iwdev->rf->max_cq); 1846 iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs, 1847 iwdev->rf->max_mr); 1848 } 1849 1850 void 1851 irdma_ctrl_deinit_hw(struct irdma_pci_f *rf) 1852 { 1853 enum init_completion_state state = rf->init_state; 1854 1855 rf->init_state = INVALID_STATE; 1856 if (rf->rsrc_created) { 1857 irdma_destroy_aeq(rf); 1858 irdma_destroy_pble_prm(rf->pble_rsrc); 1859 irdma_del_ceqs(rf); 1860 rf->rsrc_created = false; 1861 } 1862 1863 switch (state) { 1864 case CEQ0_CREATED: 1865 irdma_del_ceq_0(rf); 1866 /* fallthrough */ 1867 case CCQ_CREATED: 1868 irdma_destroy_ccq(rf); 1869 /* fallthrough */ 1870 case HW_RSRC_INITIALIZED: 1871 case HMC_OBJS_CREATED: 1872 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true, 1873 rf->reset, rf->rdma_ver); 1874 /* fallthrough */ 1875 case CQP_CREATED: 1876 irdma_destroy_cqp(rf, !rf->reset); 1877 /* fallthrough */ 1878 case INITIAL_STATE: 1879 irdma_del_init_mem(rf); 1880 break; 1881 case INVALID_STATE: 1882 default: 1883 irdma_dev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state); 1884 break; 1885 } 1886 } 1887 1888 /** 1889 * irdma_rt_init_hw - Initializes runtime portion of HW 1890 * @iwdev: irdma device 1891 * @l2params: qos, tc, mtu info from netdev driver 1892 * 1893 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma 1894 * device resource objects. 1895 */ 1896 int 1897 irdma_rt_init_hw(struct irdma_device *iwdev, 1898 struct irdma_l2params *l2params) 1899 { 1900 struct irdma_pci_f *rf = iwdev->rf; 1901 struct irdma_sc_dev *dev = &rf->sc_dev; 1902 struct irdma_sc_qp qp = {{0}}; 1903 struct irdma_vsi_init_info vsi_info = {0}; 1904 struct irdma_vsi_stats_info stats_info = {0}; 1905 int status; 1906 1907 vsi_info.dev = dev; 1908 vsi_info.back_vsi = iwdev; 1909 vsi_info.params = l2params; 1910 vsi_info.pf_data_vsi_num = iwdev->vsi_num; 1911 vsi_info.register_qset = rf->gen_ops.register_qset; 1912 vsi_info.unregister_qset = rf->gen_ops.unregister_qset; 1913 vsi_info.exception_lan_q = 2; 1914 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info); 1915 1916 status = irdma_setup_cm_core(iwdev, rf->rdma_ver); 1917 if (status) 1918 return status; 1919 1920 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL); 1921 if (!stats_info.pestat) { 1922 irdma_cleanup_cm_core(&iwdev->cm_core); 1923 return -ENOMEM; 1924 } 1925 stats_info.fcn_id = dev->hmc_fn_id; 1926 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info); 1927 if (status) { 1928 irdma_cleanup_cm_core(&iwdev->cm_core); 1929 kfree(stats_info.pestat); 1930 return status; 1931 } 1932 1933 do { 1934 if (!iwdev->roce_mode) { 1935 status = irdma_initialize_ilq(iwdev); 1936 if (status) 1937 break; 1938 iwdev->init_state = ILQ_CREATED; 1939 status = irdma_initialize_ieq(iwdev); 1940 if (status) 1941 break; 1942 iwdev->init_state = IEQ_CREATED; 1943 } 1944 if (iwdev->rf->en_rem_endpoint_trk) { 1945 qp.dev = dev; 1946 qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID; 1947 qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP; 1948 status = irdma_cqp_qp_create_cmd(dev, &qp); 1949 if (status) 1950 break; 1951 iwdev->init_state = REM_ENDPOINT_TRK_CREATED; 1952 } 1953 if (!rf->rsrc_created) { 1954 status = irdma_setup_ceqs(rf, &iwdev->vsi); 1955 if (status) 1956 break; 1957 1958 iwdev->init_state = CEQS_CREATED; 1959 1960 status = irdma_hmc_init_pble(&rf->sc_dev, 1961 rf->pble_rsrc); 1962 if (status) { 1963 irdma_del_ceqs(rf); 1964 break; 1965 } 1966 1967 iwdev->init_state = PBLE_CHUNK_MEM; 1968 1969 status = irdma_setup_aeq(rf); 1970 if (status) { 1971 irdma_destroy_pble_prm(rf->pble_rsrc); 1972 irdma_del_ceqs(rf); 1973 break; 1974 } 1975 iwdev->init_state = AEQ_CREATED; 1976 rf->rsrc_created = true; 1977 } 1978 1979 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1980 irdma_alloc_set_mac(iwdev); 1981 irdma_add_ip(iwdev); 1982 iwdev->init_state = IP_ADDR_REGISTERED; 1983 1984 /* 1985 * handles asynch cleanup tasks - disconnect CM , free qp, free cq bufs 1986 */ 1987 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq", 1988 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 1989 if (!iwdev->cleanup_wq) 1990 return -ENOMEM; 1991 irdma_get_used_rsrc(iwdev); 1992 init_waitqueue_head(&iwdev->suspend_wq); 1993 1994 return 0; 1995 } while (0); 1996 1997 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n", 1998 status, iwdev->init_state); 1999 irdma_rt_deinit_hw(iwdev); 2000 2001 return status; 2002 } 2003 2004 /** 2005 * irdma_ctrl_init_hw - Initializes control portion of HW 2006 * @rf: RDMA PCI function 2007 * 2008 * Create admin queues, HMC obejcts and RF resource objects 2009 */ 2010 int 2011 irdma_ctrl_init_hw(struct irdma_pci_f *rf) 2012 { 2013 struct irdma_sc_dev *dev = &rf->sc_dev; 2014 int status; 2015 do { 2016 status = irdma_setup_init_state(rf); 2017 if (status) 2018 break; 2019 rf->init_state = INITIAL_STATE; 2020 2021 status = irdma_create_cqp(rf); 2022 if (status) 2023 break; 2024 rf->init_state = CQP_CREATED; 2025 2026 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT; 2027 if (rf->rdma_ver != IRDMA_GEN_1) { 2028 status = irdma_get_rdma_features(dev); 2029 if (status) 2030 break; 2031 } 2032 2033 status = irdma_hmc_setup(rf); 2034 if (status) 2035 break; 2036 rf->init_state = HMC_OBJS_CREATED; 2037 2038 status = irdma_initialize_hw_rsrc(rf); 2039 if (status) 2040 break; 2041 rf->init_state = HW_RSRC_INITIALIZED; 2042 2043 status = irdma_create_ccq(rf); 2044 if (status) 2045 break; 2046 rf->init_state = CCQ_CREATED; 2047 2048 status = irdma_setup_ceq_0(rf); 2049 if (status) 2050 break; 2051 rf->init_state = CEQ0_CREATED; 2052 /* Handles processing of CQP completions */ 2053 rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq", 2054 WQ_HIGHPRI | WQ_UNBOUND); 2055 if (!rf->cqp_cmpl_wq) { 2056 status = -ENOMEM; 2057 break; 2058 } 2059 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker); 2060 irdma_sc_ccq_arm(dev->ccq); 2061 return 0; 2062 } while (0); 2063 2064 pr_err("IRDMA hardware initialization FAILED init_state=%d status=%d\n", 2065 rf->init_state, status); 2066 irdma_ctrl_deinit_hw(rf); 2067 return status; 2068 } 2069 2070 /** 2071 * irdma_set_hw_rsrc - set hw memory resources. 2072 * @rf: RDMA PCI function 2073 */ 2074 static void 2075 irdma_set_hw_rsrc(struct irdma_pci_f *rf) 2076 { 2077 rf->allocated_qps = (void *)(rf->mem_rsrc + 2078 (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); 2079 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)]; 2080 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)]; 2081 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)]; 2082 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)]; 2083 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)]; 2084 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)]; 2085 2086 rf->qp_table = (struct irdma_qp **) 2087 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]); 2088 rf->cq_table = (struct irdma_cq **)(&rf->qp_table[rf->max_qp]); 2089 2090 spin_lock_init(&rf->rsrc_lock); 2091 spin_lock_init(&rf->arp_lock); 2092 spin_lock_init(&rf->qptable_lock); 2093 spin_lock_init(&rf->cqtable_lock); 2094 spin_lock_init(&rf->qh_list_lock); 2095 } 2096 2097 /** 2098 * irdma_calc_mem_rsrc_size - calculate memory resources size. 2099 * @rf: RDMA PCI function 2100 */ 2101 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf){ 2102 u32 rsrc_size; 2103 2104 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size; 2105 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp); 2106 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr); 2107 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq); 2108 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd); 2109 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size); 2110 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah); 2111 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg); 2112 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp; 2113 rsrc_size += sizeof(struct irdma_cq **) * rf->max_cq; 2114 2115 return rsrc_size; 2116 } 2117 2118 /** 2119 * irdma_initialize_hw_rsrc - initialize hw resource tracking array 2120 * @rf: RDMA PCI function 2121 */ 2122 u32 2123 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 2124 { 2125 u32 rsrc_size; 2126 u32 mrdrvbits; 2127 u32 ret; 2128 2129 if (rf->rdma_ver != IRDMA_GEN_1) { 2130 rf->allocated_ws_nodes = 2131 kcalloc(BITS_TO_LONGS(IRDMA_MAX_WS_NODES), 2132 sizeof(unsigned long), GFP_KERNEL); 2133 if (!rf->allocated_ws_nodes) 2134 return -ENOMEM; 2135 2136 set_bit(0, rf->allocated_ws_nodes); 2137 rf->max_ws_node_id = IRDMA_MAX_WS_NODES; 2138 } 2139 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size; 2140 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt; 2141 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 2142 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 2143 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds; 2144 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt; 2145 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt; 2146 rf->max_mcg = rf->max_qp; 2147 2148 rsrc_size = irdma_calc_mem_rsrc_size(rf); 2149 rf->mem_rsrc = vzalloc(rsrc_size); 2150 if (!rf->mem_rsrc) { 2151 ret = -ENOMEM; 2152 goto mem_rsrc_vmalloc_fail; 2153 } 2154 2155 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; 2156 2157 irdma_set_hw_rsrc(rf); 2158 2159 set_bit(0, rf->allocated_mrs); 2160 set_bit(0, rf->allocated_qps); 2161 set_bit(0, rf->allocated_cqs); 2162 set_bit(0, rf->allocated_pds); 2163 set_bit(0, rf->allocated_arps); 2164 set_bit(0, rf->allocated_ahs); 2165 set_bit(0, rf->allocated_mcgs); 2166 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */ 2167 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */ 2168 set_bit(IRDMA_REM_ENDPOINT_TRK_QPID, rf->allocated_qps); /* qp 3 Remote Endpt trk */ 2169 set_bit(1, rf->allocated_cqs); 2170 set_bit(1, rf->allocated_pds); 2171 set_bit(2, rf->allocated_cqs); 2172 set_bit(2, rf->allocated_pds); 2173 2174 INIT_LIST_HEAD(&rf->mc_qht_list.list); 2175 /* stag index mask has a minimum of 14 bits */ 2176 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14); 2177 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits)); 2178 2179 return 0; 2180 2181 mem_rsrc_vmalloc_fail: 2182 kfree(rf->allocated_ws_nodes); 2183 rf->allocated_ws_nodes = NULL; 2184 2185 return ret; 2186 } 2187 2188 /** 2189 * irdma_cqp_ce_handler - handle cqp completions 2190 * @rf: RDMA PCI function 2191 * @cq: cq for cqp completions 2192 */ 2193 void 2194 irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) 2195 { 2196 struct irdma_cqp_request *cqp_request; 2197 struct irdma_sc_dev *dev = &rf->sc_dev; 2198 u32 cqe_count = 0; 2199 struct irdma_ccq_cqe_info info; 2200 unsigned long flags; 2201 int ret; 2202 2203 do { 2204 memset(&info, 0, sizeof(info)); 2205 spin_lock_irqsave(&rf->cqp.compl_lock, flags); 2206 ret = irdma_sc_ccq_get_cqe_info(cq, &info); 2207 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags); 2208 if (ret) 2209 break; 2210 2211 cqp_request = (struct irdma_cqp_request *) 2212 (uintptr_t)info.scratch; 2213 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd, 2214 info.maj_err_code, 2215 info.min_err_code)) 2216 irdma_dev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n", 2217 info.op_code, info.maj_err_code, info.min_err_code); 2218 if (cqp_request) { 2219 cqp_request->compl_info.maj_err_code = info.maj_err_code; 2220 cqp_request->compl_info.min_err_code = info.min_err_code; 2221 cqp_request->compl_info.op_ret_val = info.op_ret_val; 2222 cqp_request->compl_info.error = info.error; 2223 irdma_complete_cqp_request(&rf->cqp, cqp_request); 2224 } 2225 2226 cqe_count++; 2227 } while (1); 2228 2229 if (cqe_count) { 2230 irdma_process_bh(dev); 2231 irdma_sc_ccq_arm(dev->ccq); 2232 } 2233 } 2234 2235 /** 2236 * cqp_compl_worker - Handle cqp completions 2237 * @work: Pointer to work structure 2238 */ 2239 void 2240 cqp_compl_worker(struct work_struct *work) 2241 { 2242 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f, 2243 cqp_cmpl_work); 2244 struct irdma_sc_cq *cq = &rf->ccq.sc_cq; 2245 2246 irdma_cqp_ce_handler(rf, cq); 2247 } 2248 2249 /** 2250 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port 2251 * @cm_core: cm's core 2252 * @port: port to identify apbvt entry 2253 */ 2254 static struct irdma_apbvt_entry * 2255 irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core, 2256 u16 port) 2257 { 2258 struct irdma_apbvt_entry *entry; 2259 2260 HASH_FOR_EACH_POSSIBLE(cm_core->apbvt_hash_tbl, entry, hlist, port) { 2261 if (entry->port == port) { 2262 entry->use_cnt++; 2263 return entry; 2264 } 2265 } 2266 2267 return NULL; 2268 } 2269 2270 /** 2271 * irdma_next_iw_state - modify qp state 2272 * @iwqp: iwarp qp to modify 2273 * @state: next state for qp 2274 * @del_hash: del hash 2275 * @term: term message 2276 * @termlen: length of term message 2277 */ 2278 void 2279 irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 2280 u8 termlen) 2281 { 2282 struct irdma_modify_qp_info info = {0}; 2283 2284 info.next_iwarp_state = state; 2285 info.remove_hash_idx = del_hash; 2286 info.cq_num_valid = true; 2287 info.arp_cache_idx_valid = true; 2288 info.dont_send_term = true; 2289 info.dont_send_fin = true; 2290 info.termlen = termlen; 2291 2292 if (term & IRDMAQP_TERM_SEND_TERM_ONLY) 2293 info.dont_send_term = false; 2294 if (term & IRDMAQP_TERM_SEND_FIN_ONLY) 2295 info.dont_send_fin = false; 2296 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR) 2297 info.reset_tcp_conn = true; 2298 iwqp->hw_iwarp_state = state; 2299 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0); 2300 iwqp->iwarp_state = info.next_iwarp_state; 2301 } 2302 2303 /** 2304 * irdma_del_local_mac_entry - remove a mac entry from the hw 2305 * table 2306 * @rf: RDMA PCI function 2307 * @idx: the index of the mac ip address to delete 2308 */ 2309 void 2310 irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx) 2311 { 2312 struct irdma_cqp *iwcqp = &rf->cqp; 2313 struct irdma_cqp_request *cqp_request; 2314 struct cqp_cmds_info *cqp_info; 2315 2316 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2317 if (!cqp_request) 2318 return; 2319 2320 cqp_info = &cqp_request->info; 2321 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY; 2322 cqp_info->post_sq = 1; 2323 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp; 2324 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request; 2325 cqp_info->in.u.del_local_mac_entry.entry_idx = idx; 2326 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0; 2327 2328 irdma_handle_cqp_op(rf, cqp_request); 2329 irdma_put_cqp_request(iwcqp, cqp_request); 2330 } 2331 2332 /** 2333 * irdma_add_local_mac_entry - add a mac ip address entry to the 2334 * hw table 2335 * @rf: RDMA PCI function 2336 * @mac_addr: pointer to mac address 2337 * @idx: the index of the mac ip address to add 2338 */ 2339 int 2340 irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx) 2341 { 2342 struct irdma_local_mac_entry_info *info; 2343 struct irdma_cqp *iwcqp = &rf->cqp; 2344 struct irdma_cqp_request *cqp_request; 2345 struct cqp_cmds_info *cqp_info; 2346 int status; 2347 2348 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2349 if (!cqp_request) 2350 return -ENOMEM; 2351 2352 cqp_info = &cqp_request->info; 2353 cqp_info->post_sq = 1; 2354 info = &cqp_info->in.u.add_local_mac_entry.info; 2355 ether_addr_copy(info->mac_addr, mac_addr); 2356 info->entry_idx = idx; 2357 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2358 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY; 2359 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp; 2360 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2361 2362 status = irdma_handle_cqp_op(rf, cqp_request); 2363 irdma_put_cqp_request(iwcqp, cqp_request); 2364 2365 return status; 2366 } 2367 2368 /** 2369 * irdma_alloc_local_mac_entry - allocate a mac entry 2370 * @rf: RDMA PCI function 2371 * @mac_tbl_idx: the index of the new mac address 2372 * 2373 * Allocate a mac address entry and update the mac_tbl_idx 2374 * to hold the index of the newly created mac address 2375 * Return 0 if successful, otherwise return error 2376 */ 2377 int 2378 irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx) 2379 { 2380 struct irdma_cqp *iwcqp = &rf->cqp; 2381 struct irdma_cqp_request *cqp_request; 2382 struct cqp_cmds_info *cqp_info; 2383 int status = 0; 2384 2385 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2386 if (!cqp_request) 2387 return -ENOMEM; 2388 2389 cqp_info = &cqp_request->info; 2390 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY; 2391 cqp_info->post_sq = 1; 2392 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp; 2393 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request; 2394 status = irdma_handle_cqp_op(rf, cqp_request); 2395 if (!status) 2396 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val; 2397 2398 irdma_put_cqp_request(iwcqp, cqp_request); 2399 2400 return status; 2401 } 2402 2403 /** 2404 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt 2405 * @iwdev: irdma device 2406 * @accel_local_port: port for apbvt 2407 * @add_port: add ordelete port 2408 */ 2409 static int 2410 irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, 2411 u16 accel_local_port, bool add_port) 2412 { 2413 struct irdma_apbvt_info *info; 2414 struct irdma_cqp_request *cqp_request; 2415 struct cqp_cmds_info *cqp_info; 2416 int status; 2417 2418 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port); 2419 if (!cqp_request) 2420 return -ENOMEM; 2421 2422 cqp_info = &cqp_request->info; 2423 info = &cqp_info->in.u.manage_apbvt_entry.info; 2424 memset(info, 0, sizeof(*info)); 2425 info->add = add_port; 2426 info->port = accel_local_port; 2427 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY; 2428 cqp_info->post_sq = 1; 2429 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2430 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request; 2431 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_DEV, "%s: port=0x%04x\n", 2432 (!add_port) ? "DELETE" : "ADD", accel_local_port); 2433 2434 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2435 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2436 2437 return status; 2438 } 2439 2440 /** 2441 * irdma_add_apbvt - add tcp port to HW apbvt table 2442 * @iwdev: irdma device 2443 * @port: port for apbvt 2444 */ 2445 struct irdma_apbvt_entry * 2446 irdma_add_apbvt(struct irdma_device *iwdev, u16 port) 2447 { 2448 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2449 struct irdma_apbvt_entry *entry; 2450 unsigned long flags; 2451 2452 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2453 entry = irdma_lookup_apbvt_entry(cm_core, port); 2454 if (entry) { 2455 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2456 return entry; 2457 } 2458 2459 entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 2460 if (!entry) { 2461 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2462 return NULL; 2463 } 2464 2465 entry->port = port; 2466 entry->use_cnt = 1; 2467 HASH_ADD(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port); 2468 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2469 2470 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) { 2471 kfree(entry); 2472 return NULL; 2473 } 2474 2475 return entry; 2476 } 2477 2478 /** 2479 * irdma_del_apbvt - delete tcp port from HW apbvt table 2480 * @iwdev: irdma device 2481 * @entry: apbvt entry object 2482 */ 2483 void 2484 irdma_del_apbvt(struct irdma_device *iwdev, 2485 struct irdma_apbvt_entry *entry) 2486 { 2487 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2488 unsigned long flags; 2489 2490 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2491 if (--entry->use_cnt) { 2492 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2493 return; 2494 } 2495 2496 HASH_DEL(cm_core->apbvt_hash_tbl, &entry->hlist); 2497 /* 2498 * apbvt_lock is held across CQP delete APBVT OP (non-waiting) to protect against race where add APBVT CQP can 2499 * race ahead of the delete APBVT for same port. 2500 */ 2501 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false); 2502 kfree(entry); 2503 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2504 } 2505 2506 /** 2507 * irdma_manage_arp_cache - manage hw arp cache 2508 * @rf: RDMA PCI function 2509 * @mac_addr: mac address ptr 2510 * @ip_addr: ip addr for arp cache 2511 * @action: add, delete or modify 2512 */ 2513 void 2514 irdma_manage_arp_cache(struct irdma_pci_f *rf, const unsigned char *mac_addr, 2515 u32 *ip_addr, u32 action) 2516 { 2517 struct irdma_add_arp_cache_entry_info *info; 2518 struct irdma_cqp_request *cqp_request; 2519 struct cqp_cmds_info *cqp_info; 2520 int arp_index; 2521 2522 arp_index = irdma_arp_table(rf, ip_addr, mac_addr, action); 2523 if (arp_index == -1) 2524 return; 2525 2526 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); 2527 if (!cqp_request) 2528 return; 2529 2530 cqp_info = &cqp_request->info; 2531 if (action == IRDMA_ARP_ADD) { 2532 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY; 2533 info = &cqp_info->in.u.add_arp_cache_entry.info; 2534 memset(info, 0, sizeof(*info)); 2535 info->arp_index = (u16)arp_index; 2536 info->permanent = true; 2537 ether_addr_copy(info->mac_addr, mac_addr); 2538 cqp_info->in.u.add_arp_cache_entry.scratch = 2539 (uintptr_t)cqp_request; 2540 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2541 } else { 2542 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY; 2543 cqp_info->in.u.del_arp_cache_entry.scratch = 2544 (uintptr_t)cqp_request; 2545 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2546 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index; 2547 } 2548 2549 cqp_info->post_sq = 1; 2550 irdma_handle_cqp_op(rf, cqp_request); 2551 irdma_put_cqp_request(&rf->cqp, cqp_request); 2552 } 2553 2554 /** 2555 * irdma_send_syn_cqp_callback - do syn/ack after qhash 2556 * @cqp_request: qhash cqp completion 2557 */ 2558 static void 2559 irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request) 2560 { 2561 struct irdma_cm_node *cm_node = cqp_request->param; 2562 2563 irdma_send_syn(cm_node, 1); 2564 irdma_rem_ref_cm_node(cm_node); 2565 } 2566 2567 /** 2568 * irdma_manage_qhash - add or modify qhash 2569 * @iwdev: irdma device 2570 * @cminfo: cm info for qhash 2571 * @etype: type (syn or quad) 2572 * @mtype: type of qhash 2573 * @cmnode: cmnode associated with connection 2574 * @wait: wait for completion 2575 */ 2576 int 2577 irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 2578 enum irdma_quad_entry_type etype, 2579 enum irdma_quad_hash_manage_type mtype, void *cmnode, 2580 bool wait) 2581 { 2582 struct irdma_qhash_table_info *info; 2583 struct irdma_cqp *iwcqp = &iwdev->rf->cqp; 2584 struct irdma_cqp_request *cqp_request; 2585 struct cqp_cmds_info *cqp_info; 2586 struct irdma_cm_node *cm_node = cmnode; 2587 int status; 2588 2589 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); 2590 if (!cqp_request) 2591 return -ENOMEM; 2592 2593 cqp_info = &cqp_request->info; 2594 info = &cqp_info->in.u.manage_qhash_table_entry.info; 2595 memset(info, 0, sizeof(*info)); 2596 info->vsi = &iwdev->vsi; 2597 info->manage = mtype; 2598 info->entry_type = etype; 2599 if (cminfo->vlan_id < VLAN_N_VID) { 2600 info->vlan_valid = true; 2601 info->vlan_id = cminfo->vlan_id; 2602 } else { 2603 info->vlan_valid = false; 2604 } 2605 info->ipv4_valid = cminfo->ipv4; 2606 info->user_pri = cminfo->user_pri; 2607 ether_addr_copy(info->mac_addr, if_getlladdr(iwdev->netdev)); 2608 info->qp_num = cminfo->qh_qpid; 2609 info->dest_port = cminfo->loc_port; 2610 info->dest_ip[0] = cminfo->loc_addr[0]; 2611 info->dest_ip[1] = cminfo->loc_addr[1]; 2612 info->dest_ip[2] = cminfo->loc_addr[2]; 2613 info->dest_ip[3] = cminfo->loc_addr[3]; 2614 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED || 2615 etype == IRDMA_QHASH_TYPE_UDP_UNICAST || 2616 etype == IRDMA_QHASH_TYPE_UDP_MCAST || 2617 etype == IRDMA_QHASH_TYPE_ROCE_MCAST || 2618 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) { 2619 info->src_port = cminfo->rem_port; 2620 info->src_ip[0] = cminfo->rem_addr[0]; 2621 info->src_ip[1] = cminfo->rem_addr[1]; 2622 info->src_ip[2] = cminfo->rem_addr[2]; 2623 info->src_ip[3] = cminfo->rem_addr[3]; 2624 } 2625 if (cmnode) { 2626 cqp_request->callback_fcn = irdma_send_syn_cqp_callback; 2627 cqp_request->param = cmnode; 2628 if (!wait) 2629 atomic_inc(&cm_node->refcnt); 2630 } 2631 if (info->ipv4_valid) 2632 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_CM, 2633 "%s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n", 2634 (!mtype) ? "DELETE" : "ADD", 2635 __builtin_return_address(0), info->dest_port, 2636 info->src_port, info->dest_ip, info->src_ip, 2637 info->mac_addr, cminfo->vlan_id, 2638 cmnode ? cmnode : NULL); 2639 else 2640 irdma_debug(&iwdev->rf->sc_dev, IRDMA_DEBUG_CM, 2641 "%s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n", 2642 (!mtype) ? "DELETE" : "ADD", 2643 __builtin_return_address(0), info->dest_port, 2644 info->src_port, info->dest_ip, info->src_ip, 2645 info->mac_addr, cminfo->vlan_id, 2646 cmnode ? cmnode : NULL); 2647 2648 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2649 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request; 2650 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY; 2651 cqp_info->post_sq = 1; 2652 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2653 if (status && cm_node && !wait) 2654 irdma_rem_ref_cm_node(cm_node); 2655 2656 irdma_put_cqp_request(iwcqp, cqp_request); 2657 2658 return status; 2659 } 2660 2661 /** 2662 * irdma_hw_flush_wqes - flush qp's wqe 2663 * @rf: RDMA PCI function 2664 * @qp: hardware control qp 2665 * @info: info for flush 2666 * @wait: flag wait for completion 2667 */ 2668 int 2669 irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2670 struct irdma_qp_flush_info *info, bool wait) 2671 { 2672 int status; 2673 struct irdma_qp_flush_info *hw_info; 2674 struct irdma_cqp_request *cqp_request; 2675 struct cqp_cmds_info *cqp_info; 2676 struct irdma_qp *iwqp = qp->qp_uk.back_qp; 2677 2678 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2679 if (!cqp_request) 2680 return -ENOMEM; 2681 2682 cqp_info = &cqp_request->info; 2683 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info; 2684 memcpy(hw_info, info, sizeof(*hw_info)); 2685 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2686 cqp_info->post_sq = 1; 2687 cqp_info->in.u.qp_flush_wqes.qp = qp; 2688 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; 2689 status = irdma_handle_cqp_op(rf, cqp_request); 2690 if (status) { 2691 qp->qp_uk.sq_flush_complete = true; 2692 qp->qp_uk.rq_flush_complete = true; 2693 irdma_put_cqp_request(&rf->cqp, cqp_request); 2694 return status; 2695 } 2696 2697 if (!wait || cqp_request->compl_info.maj_err_code) 2698 goto put_cqp; 2699 2700 if (info->rq) { 2701 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2702 cqp_request->compl_info.min_err_code == 0) { 2703 /* RQ WQE flush was requested but did not happen */ 2704 qp->qp_uk.rq_flush_complete = true; 2705 } 2706 } 2707 if (info->sq) { 2708 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2709 cqp_request->compl_info.min_err_code == 0) { 2710 /* SQ WQE flush was requested but did not happen */ 2711 qp->qp_uk.sq_flush_complete = true; 2712 } 2713 } 2714 2715 irdma_debug(&rf->sc_dev, IRDMA_DEBUG_VERBS, 2716 "qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n", 2717 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state, 2718 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state, 2719 cqp_request->compl_info.maj_err_code, cqp_request->compl_info.min_err_code); 2720 put_cqp: 2721 irdma_put_cqp_request(&rf->cqp, cqp_request); 2722 2723 return status; 2724 } 2725 2726 /** 2727 * irdma_gen_ae - generate AE 2728 * @rf: RDMA PCI function 2729 * @qp: qp associated with AE 2730 * @info: info for ae 2731 * @wait: wait for completion 2732 */ 2733 void 2734 irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2735 struct irdma_gen_ae_info *info, bool wait) 2736 { 2737 struct irdma_gen_ae_info *ae_info; 2738 struct irdma_cqp_request *cqp_request; 2739 struct cqp_cmds_info *cqp_info; 2740 2741 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2742 if (!cqp_request) 2743 return; 2744 2745 cqp_info = &cqp_request->info; 2746 ae_info = &cqp_request->info.in.u.gen_ae.info; 2747 memcpy(ae_info, info, sizeof(*ae_info)); 2748 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE; 2749 cqp_info->post_sq = 1; 2750 cqp_info->in.u.gen_ae.qp = qp; 2751 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request; 2752 2753 irdma_handle_cqp_op(rf, cqp_request); 2754 irdma_put_cqp_request(&rf->cqp, cqp_request); 2755 } 2756 2757 void 2758 irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) 2759 { 2760 struct irdma_qp_flush_info info = {0}; 2761 struct irdma_pci_f *rf = iwqp->iwdev->rf; 2762 u8 flush_code = iwqp->sc_qp.flush_code; 2763 2764 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) 2765 return; 2766 2767 /* Set flush info fields */ 2768 info.sq = flush_mask & IRDMA_FLUSH_SQ; 2769 info.rq = flush_mask & IRDMA_FLUSH_RQ; 2770 2771 /* Generate userflush errors in CQE */ 2772 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2773 info.sq_minor_code = FLUSH_GENERAL_ERR; 2774 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2775 info.rq_minor_code = FLUSH_GENERAL_ERR; 2776 info.userflushcode = true; 2777 2778 if (flush_mask & IRDMA_REFLUSH) { 2779 if (info.sq) 2780 iwqp->sc_qp.flush_sq = false; 2781 if (info.rq) 2782 iwqp->sc_qp.flush_rq = false; 2783 } else { 2784 if (flush_code) { 2785 if (info.sq && iwqp->sc_qp.sq_flush_code) 2786 info.sq_minor_code = flush_code; 2787 if (info.rq && iwqp->sc_qp.rq_flush_code) 2788 info.rq_minor_code = flush_code; 2789 } 2790 if (irdma_upload_context && irdma_upload_qp_context(iwqp, 0, 1)) 2791 irdma_dev_warn(&iwqp->iwdev->ibdev, "failed to upload QP context\n"); 2792 if (!iwqp->user_mode) 2793 irdma_sched_qp_flush_work(iwqp); 2794 } 2795 2796 /* Issue flush */ 2797 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info, 2798 flush_mask & IRDMA_FLUSH_WAIT); 2799 iwqp->flush_issued = true; 2800 } 2801