xref: /freebsd/sys/dev/irdma/irdma_defs.h (revision db33c6f3ae9d1231087710068ee4ea5398aacca7)
1 /*-
2  * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
3  *
4  * Copyright (c) 2015 - 2023 Intel Corporation
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenFabrics.org BSD license below:
11  *
12  *   Redistribution and use in source and binary forms, with or
13  *   without modification, are permitted provided that the following
14  *   conditions are met:
15  *
16  *    - Redistributions of source code must retain the above
17  *	copyright notice, this list of conditions and the following
18  *	disclaimer.
19  *
20  *    - Redistributions in binary form must reproduce the above
21  *	copyright notice, this list of conditions and the following
22  *	disclaimer in the documentation and/or other materials
23  *	provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 
35 #ifndef IRDMA_DEFS_H
36 #define IRDMA_DEFS_H
37 
38 #define IRDMA_FIRST_USER_QP_ID	3
39 
40 #define ECN_CODE_PT_MASK 3
41 #define ECN_CODE_PT_VAL	2
42 
43 #define IRDMA_PUSH_OFFSET		(8 * 1024 * 1024)
44 #define IRDMA_PF_FIRST_PUSH_PAGE_INDEX	16
45 #define IRDMA_PF_BAR_RSVD		(60 * 1024)
46 
47 #define IRDMA_PE_DB_SIZE_4M	1
48 #define IRDMA_PE_DB_SIZE_8M	2
49 
50 #define IRDMA_IRD_HW_SIZE_4	0
51 #define IRDMA_IRD_HW_SIZE_16	1
52 #define IRDMA_IRD_HW_SIZE_64	2
53 #define IRDMA_IRD_HW_SIZE_128	3
54 #define IRDMA_IRD_HW_SIZE_256	4
55 
56 #define IRDMA_QP_STATE_INVALID		0
57 #define IRDMA_QP_STATE_IDLE		1
58 #define IRDMA_QP_STATE_RTS		2
59 #define IRDMA_QP_STATE_CLOSING		3
60 #define IRDMA_QP_STATE_SQD		3
61 #define IRDMA_QP_STATE_RTR		4
62 #define IRDMA_QP_STATE_TERMINATE	5
63 #define IRDMA_QP_STATE_ERROR		6
64 
65 #define IRDMA_MAX_USER_PRIORITY		8
66 #define IRDMA_DSCP_NUM_VAL		64
67 #define IRDMA_MAX_TRAFFIC_CLASS		8
68 #define IRDMA_MAX_STATS_COUNT		128
69 #define IRDMA_FIRST_NON_PF_STAT		4
70 
71 #define IRDMA_MIN_MTU_IPV4	576
72 #define IRDMA_MIN_MTU_IPV6	1280
73 #define IRDMA_MTU_TO_MSS_IPV4	40
74 #define IRDMA_MTU_TO_MSS_IPV6	60
75 #define IRDMA_DEFAULT_MTU	1500
76 
77 #define Q2_FPSN_OFFSET		64
78 #define TERM_DDP_LEN_TAGGED	14
79 #define TERM_DDP_LEN_UNTAGGED	18
80 #define TERM_RDMA_LEN		28
81 #define RDMA_OPCODE_M		0x0f
82 #define RDMA_READ_REQ_OPCODE	1
83 #define Q2_BAD_FRAME_OFFSET	72
84 #define CQE_MAJOR_DRV		0x8000
85 
86 #define IRDMA_TERM_SENT		1
87 #define IRDMA_TERM_RCVD		2
88 #define IRDMA_TERM_DONE		4
89 #define IRDMA_MAC_HLEN		14
90 #define IRDMA_BYTE_0		0
91 #define IRDMA_BYTE_8		8
92 #define IRDMA_BYTE_16		16
93 #define IRDMA_BYTE_24		24
94 #define IRDMA_BYTE_32		32
95 #define IRDMA_BYTE_40		40
96 #define IRDMA_BYTE_48		48
97 #define IRDMA_BYTE_56		56
98 #define IRDMA_BYTE_64		64
99 #define IRDMA_BYTE_72		72
100 #define IRDMA_BYTE_80		80
101 #define IRDMA_BYTE_88		88
102 #define IRDMA_BYTE_96		96
103 #define IRDMA_BYTE_104		104
104 #define IRDMA_BYTE_112		112
105 #define IRDMA_BYTE_120		120
106 #define IRDMA_BYTE_128		128
107 #define IRDMA_BYTE_136		136
108 #define IRDMA_BYTE_144		144
109 #define IRDMA_BYTE_152		152
110 #define IRDMA_BYTE_160		160
111 #define IRDMA_BYTE_168		168
112 #define IRDMA_BYTE_176		176
113 #define IRDMA_BYTE_184		184
114 #define IRDMA_BYTE_192		192
115 #define IRDMA_BYTE_200		200
116 #define IRDMA_BYTE_208		208
117 #define IRDMA_BYTE_216		216
118 
119 #define IRDMA_CQP_WAIT_POLL_REGS	1
120 #define IRDMA_CQP_WAIT_POLL_CQ		2
121 #define IRDMA_CQP_WAIT_EVENT		3
122 
123 #define IRDMA_AE_SOURCE_RSVD		0x0
124 #define IRDMA_AE_SOURCE_RQ		0x1
125 #define IRDMA_AE_SOURCE_RQ_0011		0x3
126 
127 #define IRDMA_AE_SOURCE_CQ		0x2
128 #define IRDMA_AE_SOURCE_CQ_0110		0x6
129 #define IRDMA_AE_SOURCE_CQ_1010		0xa
130 #define IRDMA_AE_SOURCE_CQ_1110		0xe
131 
132 #define IRDMA_AE_SOURCE_SQ		0x5
133 #define IRDMA_AE_SOURCE_SQ_0111		0x7
134 
135 #define IRDMA_AE_SOURCE_IN_WR		0x9
136 #define IRDMA_AE_SOURCE_IN_RR		0xb
137 #define IRDMA_AE_SOURCE_OUT_RR		0xd
138 #define IRDMA_AE_SOURCE_OUT_RR_1111	0xf
139 
140 #define IRDMA_AE_SOURCE_RSRC_EXHT_Q1	0x1
141 #define IRDMA_AE_SOURCE_RSRC_EXHT_XT_RR	0x5
142 
143 #define IRDMA_TCP_STATE_NON_EXISTENT	0
144 #define IRDMA_TCP_STATE_CLOSED		1
145 #define IRDMA_TCP_STATE_LISTEN		2
146 #define IRDMA_STATE_SYN_SEND		3
147 #define IRDMA_TCP_STATE_SYN_RECEIVED	4
148 #define IRDMA_TCP_STATE_ESTABLISHED	5
149 #define IRDMA_TCP_STATE_CLOSE_WAIT	6
150 #define IRDMA_TCP_STATE_FIN_WAIT_1	7
151 #define IRDMA_TCP_STATE_CLOSING		8
152 #define IRDMA_TCP_STATE_LAST_ACK	9
153 #define IRDMA_TCP_STATE_FIN_WAIT_2	10
154 #define IRDMA_TCP_STATE_TIME_WAIT	11
155 #define IRDMA_TCP_STATE_RESERVED_1	12
156 #define IRDMA_TCP_STATE_RESERVED_2	13
157 #define IRDMA_TCP_STATE_RESERVED_3	14
158 #define IRDMA_TCP_STATE_RESERVED_4	15
159 
160 #define IRDMA_CQP_SW_SQSIZE_4		4
161 #define IRDMA_CQP_SW_SQSIZE_2048	2048
162 
163 #define IRDMA_CQ_TYPE_IWARP	1
164 #define IRDMA_CQ_TYPE_ILQ	2
165 #define IRDMA_CQ_TYPE_IEQ	3
166 #define IRDMA_CQ_TYPE_CQP	4
167 
168 #define IRDMA_DONE_COUNT	1000
169 #define IRDMA_SLEEP_COUNT	10
170 
171 #define IRDMA_UPDATE_SD_BUFF_SIZE	128
172 #define IRDMA_FEATURE_BUF_SIZE		(8 * IRDMA_MAX_FEATURES)
173 
174 #define IRDMA_MAX_QUANTA_PER_WR	8
175 
176 #define IRDMA_QP_SW_MAX_WQ_QUANTA	32768
177 #define IRDMA_QP_SW_MAX_SQ_QUANTA	32768
178 #define IRDMA_QP_SW_MAX_RQ_QUANTA	32768
179 
180 #define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \
181 	((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
182 
183 #define IRDMAQP_TERM_SEND_TERM_AND_FIN		0
184 #define IRDMAQP_TERM_SEND_TERM_ONLY		1
185 #define IRDMAQP_TERM_SEND_FIN_ONLY		2
186 #define IRDMAQP_TERM_DONOT_SEND_TERM_OR_FIN	3
187 
188 #define IRDMA_QP_TYPE_IWARP	1
189 #define IRDMA_QP_TYPE_UDA	2
190 #define IRDMA_QP_TYPE_ROCE_RC	3
191 #define IRDMA_QP_TYPE_ROCE_UD	4
192 
193 #define IRDMA_HW_PAGE_SIZE	4096
194 #define IRDMA_HW_PAGE_SHIFT	12
195 #define IRDMA_CQE_QTYPE_RQ	0
196 #define IRDMA_CQE_QTYPE_SQ	1
197 
198 #define IRDMA_QP_SW_MIN_WQSIZE	8 /* in WRs*/
199 #define IRDMA_QP_WQE_MIN_SIZE	32
200 #define IRDMA_QP_WQE_MAX_SIZE	256
201 #define IRDMA_QP_WQE_MIN_QUANTA 1
202 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2
203 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3
204 
205 #define IRDMA_SQ_RSVD	258
206 #define IRDMA_RQ_RSVD	1
207 
208 #define IRDMA_FEATURE_RTS_AE			BIT_ULL(0)
209 #define IRDMA_FEATURE_CQ_RESIZE			BIT_ULL(1)
210 #define IRDMA_FEATURE_RELAX_RQ_ORDER		BIT_ULL(2)
211 #define IRDMA_FEATURE_64_BYTE_CQE		BIT_ULL(5)
212 
213 #define IRDMAQP_OP_RDMA_WRITE			0x00
214 #define IRDMAQP_OP_RDMA_READ			0x01
215 #define IRDMAQP_OP_RDMA_SEND			0x03
216 #define IRDMAQP_OP_RDMA_SEND_INV		0x04
217 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT		0x05
218 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV	0x06
219 #define IRDMAQP_OP_BIND_MW			0x08
220 #define IRDMAQP_OP_FAST_REGISTER		0x09
221 #define IRDMAQP_OP_LOCAL_INVALIDATE		0x0a
222 #define IRDMAQP_OP_RDMA_READ_LOC_INV		0x0b
223 #define IRDMAQP_OP_NOP				0x0c
224 #define IRDMAQP_OP_RDMA_WRITE_SOL		0x0d
225 #define IRDMAQP_OP_GEN_RTS_AE			0x30
226 
227 enum irdma_cqp_op_type {
228 	IRDMA_OP_CEQ_DESTROY			= 1,
229 	IRDMA_OP_AEQ_DESTROY			= 2,
230 	IRDMA_OP_DELETE_ARP_CACHE_ENTRY		= 3,
231 	IRDMA_OP_MANAGE_APBVT_ENTRY		= 4,
232 	IRDMA_OP_CEQ_CREATE			= 5,
233 	IRDMA_OP_AEQ_CREATE			= 6,
234 	IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY	= 7,
235 	IRDMA_OP_QP_MODIFY			= 8,
236 	IRDMA_OP_QP_UPLOAD_CONTEXT		= 9,
237 	IRDMA_OP_CQ_CREATE			= 10,
238 	IRDMA_OP_CQ_DESTROY			= 11,
239 	IRDMA_OP_QP_CREATE			= 12,
240 	IRDMA_OP_QP_DESTROY			= 13,
241 	IRDMA_OP_ALLOC_STAG			= 14,
242 	IRDMA_OP_MR_REG_NON_SHARED		= 15,
243 	IRDMA_OP_DEALLOC_STAG			= 16,
244 	IRDMA_OP_MW_ALLOC			= 17,
245 	IRDMA_OP_QP_FLUSH_WQES			= 18,
246 	IRDMA_OP_ADD_ARP_CACHE_ENTRY		= 19,
247 	IRDMA_OP_MANAGE_PUSH_PAGE		= 20,
248 	IRDMA_OP_UPDATE_PE_SDS			= 21,
249 	IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE	= 22,
250 	IRDMA_OP_SUSPEND			= 23,
251 	IRDMA_OP_RESUME				= 24,
252 	IRDMA_OP_QUERY_FPM_VAL			= 26,
253 	IRDMA_OP_COMMIT_FPM_VAL			= 27,
254 	IRDMA_OP_AH_CREATE			= 28,
255 	IRDMA_OP_AH_MODIFY			= 29,
256 	IRDMA_OP_AH_DESTROY			= 30,
257 	IRDMA_OP_MC_CREATE			= 31,
258 	IRDMA_OP_MC_DESTROY			= 32,
259 	IRDMA_OP_MC_MODIFY			= 33,
260 	IRDMA_OP_STATS_ALLOCATE			= 34,
261 	IRDMA_OP_STATS_FREE			= 35,
262 	IRDMA_OP_STATS_GATHER			= 36,
263 	IRDMA_OP_WS_ADD_NODE			= 37,
264 	IRDMA_OP_WS_MODIFY_NODE			= 38,
265 	IRDMA_OP_WS_DELETE_NODE			= 39,
266 	IRDMA_OP_WS_FAILOVER_START		= 40,
267 	IRDMA_OP_WS_FAILOVER_COMPLETE		= 41,
268 	IRDMA_OP_SET_UP_MAP			= 42,
269 	IRDMA_OP_GEN_AE				= 43,
270 	IRDMA_OP_QUERY_RDMA_FEATURES		= 44,
271 	IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY		= 45,
272 	IRDMA_OP_ADD_LOCAL_MAC_ENTRY		= 46,
273 	IRDMA_OP_DELETE_LOCAL_MAC_ENTRY		= 47,
274 	IRDMA_OP_CQ_MODIFY			= 48,
275 
276 	/* Must be last entry */
277 	IRDMA_MAX_CQP_OPS			= 49,
278 };
279 
280 /* CQP SQ WQES */
281 #define IRDMA_CQP_OP_CREATE_QP				0x00
282 #define IRDMA_CQP_OP_MODIFY_QP				0x01
283 #define IRDMA_CQP_OP_DESTROY_QP				0x02
284 #define IRDMA_CQP_OP_CREATE_CQ				0x03
285 #define IRDMA_CQP_OP_MODIFY_CQ				0x04
286 #define IRDMA_CQP_OP_DESTROY_CQ				0x05
287 #define IRDMA_CQP_OP_ALLOC_STAG				0x09
288 #define IRDMA_CQP_OP_REG_MR				0x0a
289 #define IRDMA_CQP_OP_QUERY_STAG				0x0b
290 #define IRDMA_CQP_OP_REG_SMR				0x0c
291 #define IRDMA_CQP_OP_DEALLOC_STAG			0x0d
292 #define IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE		0x0e
293 #define IRDMA_CQP_OP_MANAGE_ARP				0x0f
294 #define IRDMA_CQP_OP_MANAGE_PUSH_PAGES			0x11
295 #define IRDMA_CQP_OP_QUERY_RDMA_FEATURES		0x12
296 #define IRDMA_CQP_OP_UPLOAD_CONTEXT			0x13
297 #define IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY	0x14
298 #define IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE		0x15
299 #define IRDMA_CQP_OP_CREATE_CEQ				0x16
300 #define IRDMA_CQP_OP_DESTROY_CEQ			0x18
301 #define IRDMA_CQP_OP_CREATE_AEQ				0x19
302 #define IRDMA_CQP_OP_DESTROY_AEQ			0x1b
303 #define IRDMA_CQP_OP_CREATE_ADDR_HANDLE			0x1c
304 #define IRDMA_CQP_OP_MODIFY_ADDR_HANDLE			0x1d
305 #define IRDMA_CQP_OP_DESTROY_ADDR_HANDLE		0x1e
306 #define IRDMA_CQP_OP_UPDATE_PE_SDS			0x1f
307 #define IRDMA_CQP_OP_QUERY_FPM_VAL			0x20
308 #define IRDMA_CQP_OP_COMMIT_FPM_VAL			0x21
309 #define IRDMA_CQP_OP_FLUSH_WQES				0x22
310 /* IRDMA_CQP_OP_GEN_AE is the same value as IRDMA_CQP_OP_FLUSH_WQES */
311 #define IRDMA_CQP_OP_GEN_AE				0x22
312 #define IRDMA_CQP_OP_MANAGE_APBVT			0x23
313 #define IRDMA_CQP_OP_NOP				0x24
314 #define IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY	0x25
315 #define IRDMA_CQP_OP_CREATE_MCAST_GRP			0x26
316 #define IRDMA_CQP_OP_MODIFY_MCAST_GRP			0x27
317 #define IRDMA_CQP_OP_DESTROY_MCAST_GRP			0x28
318 #define IRDMA_CQP_OP_SUSPEND_QP				0x29
319 #define IRDMA_CQP_OP_RESUME_QP				0x2a
320 #define IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED		0x2b
321 #define IRDMA_CQP_OP_WORK_SCHED_NODE			0x2c
322 #define IRDMA_CQP_OP_MANAGE_STATS			0x2d
323 #define IRDMA_CQP_OP_GATHER_STATS			0x2e
324 #define IRDMA_CQP_OP_UP_MAP				0x2f
325 
326 #ifndef LS_64_1
327 #define LS_64_1(val, bits)	((u64)(uintptr_t)(val) << (bits))
328 #define RS_64_1(val, bits)	((u64)(uintptr_t)(val) >> (bits))
329 #define LS_32_1(val, bits)	((u32)((val) << (bits)))
330 #define RS_32_1(val, bits)	((u32)((val) >> (bits)))
331 #endif
332 #ifndef GENMASK_ULL
333 #define GENMASK_ULL(high, low)	((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (low))
334 #endif /* GENMASK_ULL */
335 #ifndef GENMASK
336 #define GENMASK(high, low)	((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low))
337 #endif /* GENMASK */
338 #ifndef FIELD_PREP
339 #define FIELD_PREP(mask, val)	(((u64)(val) << mask##_S) & (mask))
340 #define FIELD_GET(mask, val)	(((val) & mask) >> mask##_S)
341 #endif /* FIELD_PREP */
342 
343 #define FLD_LS_64(dev, val, field)	\
344 	(((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
345 #define FLD_RS_64(dev, val, field)	\
346 	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
347 #define FLD_LS_32(dev, val, field)	\
348 	(((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
349 #define FLD_RS_32(dev, val, field)	\
350 	((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
351 
352 #define IRDMA_MAX_STATS_16	0xffffULL
353 #define IRDMA_MAX_STATS_24	0xffffffULL
354 #define IRDMA_MAX_STATS_32	0xffffffffULL
355 #define IRDMA_MAX_STATS_48	0xffffffffffffULL
356 #define IRDMA_MAX_STATS_56	0xffffffffffffffULL
357 #define IRDMA_MAX_STATS_64	0xffffffffffffffffULL
358 
359 #define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF
360 #define IRDMA_CQPSQ_QHASH_VLANID_S 32
361 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
362 #define IRDMA_CQPSQ_QHASH_QPN_S 32
363 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
364 #define IRDMA_CQPSQ_QHASH_QS_HANDLE_S 0
365 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
366 #define IRDMA_CQPSQ_QHASH_SRC_PORT_S 16
367 #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
368 #define IRDMA_CQPSQ_QHASH_DEST_PORT_S 0
369 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
370 #define IRDMA_CQPSQ_QHASH_ADDR0_S 32
371 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
372 #define IRDMA_CQPSQ_QHASH_ADDR1_S 0
373 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
374 #define IRDMA_CQPSQ_QHASH_ADDR2_S 32
375 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
376 #define IRDMA_CQPSQ_QHASH_ADDR3_S 0
377 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
378 #define IRDMA_CQPSQ_QHASH_WQEVALID_S 63
379 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
380 #define IRDMA_CQPSQ_QHASH_OPCODE_S 32
381 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
382 #define IRDMA_CQPSQ_QHASH_MANAGE_S 61
383 #define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)
384 #define IRDMA_CQPSQ_QHASH_IPV4VALID_S 60
385 #define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
386 #define IRDMA_CQPSQ_QHASH_VLANVALID_S 59
387 #define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)
388 #define IRDMA_CQPSQ_QHASH_ENTRYTYPE_S 42
389 #define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)
390 #define IRDMA_CQPSQ_STATS_WQEVALID_S 63
391 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
392 #define IRDMA_CQPSQ_STATS_ALLOC_INST_S 62
393 #define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)
394 #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX_S 60
395 #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)
396 #define IRDMA_CQPSQ_STATS_USE_INST_S 61
397 #define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)
398 #define IRDMA_CQPSQ_STATS_OP_S 32
399 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
400 #define IRDMA_CQPSQ_STATS_INST_INDEX_S 0
401 #define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)
402 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX_S 0
403 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(15, 0)
404 #define IRDMA_CQPSQ_WS_WQEVALID_S 63
405 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
406 #define IRDMA_CQPSQ_WS_NODEOP_S 52
407 #define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(55, 52)
408 
409 #define IRDMA_CQPSQ_WS_ENABLENODE_S 62
410 #define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)
411 #define IRDMA_CQPSQ_WS_NODETYPE_S 61
412 #define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)
413 #define IRDMA_CQPSQ_WS_PRIOTYPE_S 59
414 #define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59)
415 #define IRDMA_CQPSQ_WS_TC_S 56
416 #define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56)
417 #define IRDMA_CQPSQ_WS_VMVFTYPE_S 54
418 #define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54)
419 #define IRDMA_CQPSQ_WS_VMVFNUM_S 42
420 #define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42)
421 #define IRDMA_CQPSQ_WS_OP_S 32
422 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
423 #define IRDMA_CQPSQ_WS_PARENTID_S 16
424 #define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(25, 16)
425 #define IRDMA_CQPSQ_WS_NODEID_S 0
426 #define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0)
427 #define IRDMA_CQPSQ_WS_VSI_S 48
428 #define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48)
429 #define IRDMA_CQPSQ_WS_WEIGHT_S 32
430 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
431 
432 #define IRDMA_CQPSQ_UP_WQEVALID_S 63
433 #define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
434 #define IRDMA_CQPSQ_UP_USEVLAN_S 62
435 #define IRDMA_CQPSQ_UP_USEVLAN BIT_ULL(62)
436 #define IRDMA_CQPSQ_UP_USEOVERRIDE_S 61
437 #define IRDMA_CQPSQ_UP_USEOVERRIDE BIT_ULL(61)
438 #define IRDMA_CQPSQ_UP_OP_S 32
439 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
440 #define IRDMA_CQPSQ_UP_HMCFCNIDX_S 0
441 #define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0)
442 #define IRDMA_CQPSQ_UP_CNPOVERRIDE_S 32
443 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
444 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID_S 63
445 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
446 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN_S 0
447 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)
448 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP_S 32
449 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
450 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED_S 32
451 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
452 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION_S 16
453 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16)
454 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION_S 0
455 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)
456 #define IRDMA_CQPHC_SQSIZE_S 8
457 #define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8)
458 #define IRDMA_CQPHC_DISABLE_PFPDUS_S 1
459 #define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1)
460 #define IRDMA_CQPHC_ROCEV2_RTO_POLICY_S 2
461 #define IRDMA_CQPHC_ROCEV2_RTO_POLICY BIT_ULL(2)
462 #define IRDMA_CQPHC_PROTOCOL_USED_S 3
463 #define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3)
464 #define IRDMA_CQPHC_MIN_RATE_S 48
465 #define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)
466 #define IRDMA_CQPHC_MIN_DEC_FACTOR_S 56
467 #define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56)
468 #define IRDMA_CQPHC_DCQCN_T_S 0
469 #define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)
470 #define IRDMA_CQPHC_HAI_FACTOR_S 32
471 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
472 #define IRDMA_CQPHC_RAI_FACTOR_S 48
473 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
474 #define IRDMA_CQPHC_DCQCN_B_S 0
475 #define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)
476 #define IRDMA_CQPHC_DCQCN_F_S 25
477 #define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25)
478 #define IRDMA_CQPHC_CC_CFG_VALID_S 31
479 #define IRDMA_CQPHC_CC_CFG_VALID BIT_ULL(31)
480 #define IRDMA_CQPHC_RREDUCE_MPERIOD_S 32
481 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
482 #define IRDMA_CQPHC_HW_MINVER_S 0
483 #define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)
484 
485 #define IRDMA_CQPHC_HW_MAJVER_GEN_1 0
486 #define IRDMA_CQPHC_HW_MAJVER_GEN_2 1
487 #define IRDMA_CQPHC_HW_MAJVER_GEN_3 2
488 #define IRDMA_CQPHC_HW_MAJVER_S 16
489 #define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16)
490 #define IRDMA_CQPHC_CEQPERVF_S 32
491 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
492 
493 #define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK_S 3
494 #define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK BIT_ULL(3)
495 
496 #define IRDMA_CQPHC_ENABLED_VFS_S 32
497 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
498 
499 #define IRDMA_CQPHC_HMC_PROFILE_S 0
500 #define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)
501 #define IRDMA_CQPHC_SVER_S 24
502 #define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24)
503 #define IRDMA_CQPHC_SQBASE_S 9
504 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
505 
506 #define IRDMA_CQPHC_QPCTX_S 0
507 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
508 #define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0
509 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
510 #define IRDMA_CQ_DBSA_CQEIDX_S 0
511 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
512 #define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0
513 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
514 #define IRDMA_CQ_DBSA_ARM_NEXT_S 14
515 #define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14)
516 #define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15
517 #define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15)
518 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16
519 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)
520 
521 /* CQP and iWARP Completion Queue */
522 #define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S
523 #define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX
524 
525 #define IRDMA_CCQ_OPRETVAL_S 0
526 #define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)
527 
528 #define IRDMA_CQ_MINERR_S 0
529 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
530 #define IRDMA_CQ_MAJERR_S 16
531 #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)
532 #define IRDMA_CQ_WQEIDX_S 32
533 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
534 #define IRDMA_CQ_EXTCQE_S 50
535 #define IRDMA_CQ_EXTCQE BIT_ULL(50)
536 #define IRDMA_OOO_CMPL_S 54
537 #define IRDMA_OOO_CMPL BIT_ULL(54)
538 #define IRDMA_CQ_ERROR_S 55
539 #define IRDMA_CQ_ERROR BIT_ULL(55)
540 #define IRDMA_CQ_SQ_S 62
541 #define IRDMA_CQ_SQ BIT_ULL(62)
542 
543 #define IRDMA_CQ_VALID_S 63
544 #define IRDMA_CQ_VALID BIT_ULL(63)
545 #define IRDMA_CQ_IMMVALID BIT_ULL(62)
546 #define IRDMA_CQ_UDSMACVALID_S 61
547 #define IRDMA_CQ_UDSMACVALID BIT_ULL(61)
548 #define IRDMA_CQ_UDVLANVALID_S 60
549 #define IRDMA_CQ_UDVLANVALID BIT_ULL(60)
550 #define IRDMA_CQ_UDSMAC_S 0
551 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
552 #define IRDMA_CQ_UDVLAN_S 48
553 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
554 
555 #define IRDMA_CQ_IMMDATA_S 0
556 #define IRDMA_CQ_IMMVALID_S 62
557 #define IRDMA_CQ_IMMDATA GENMASK_ULL(125, 62)
558 #define IRDMA_CQ_IMMDATALOW32_S 0
559 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
560 #define IRDMA_CQ_IMMDATAUP32_S 32
561 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
562 #define IRDMACQ_PAYLDLEN_S 0
563 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
564 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS_S 32
565 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32)
566 #define IRDMACQ_INVSTAG_S 0
567 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
568 #define IRDMACQ_QPID_S 32
569 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
570 
571 #define IRDMACQ_UDSRCQPN_S 0
572 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
573 #define IRDMACQ_PSHDROP_S 51
574 #define IRDMACQ_PSHDROP BIT_ULL(51)
575 #define IRDMACQ_STAG_S 53
576 #define IRDMACQ_STAG BIT_ULL(53)
577 #define IRDMACQ_IPV4_S 53
578 #define IRDMACQ_IPV4 BIT_ULL(53)
579 #define IRDMACQ_SOEVENT_S 54
580 #define IRDMACQ_SOEVENT BIT_ULL(54)
581 #define IRDMACQ_OP_S 56
582 #define IRDMACQ_OP GENMASK_ULL(61, 56)
583 
584 #define IRDMA_CEQE_CQCTX_S 0
585 #define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)
586 #define IRDMA_CEQE_VALID_S 63
587 #define IRDMA_CEQE_VALID BIT_ULL(63)
588 
589 /* AEQE format */
590 #define IRDMA_AEQE_COMPCTX_S IRDMA_CQPHC_QPCTX_S
591 #define IRDMA_AEQE_COMPCTX IRDMA_CQPHC_QPCTX
592 #define IRDMA_AEQE_QPCQID_LOW_S 0
593 #define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)
594 #define IRDMA_AEQE_QPCQID_HI_S 46
595 #define IRDMA_AEQE_QPCQID_HI BIT_ULL(46)
596 #define IRDMA_AEQE_WQDESCIDX_S 18
597 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
598 #define IRDMA_AEQE_OVERFLOW_S 33
599 #define IRDMA_AEQE_OVERFLOW BIT_ULL(33)
600 #define IRDMA_AEQE_AECODE_S 34
601 #define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34)
602 #define IRDMA_AEQE_AESRC_S 50
603 #define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50)
604 #define IRDMA_AEQE_IWSTATE_S 54
605 #define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54)
606 #define IRDMA_AEQE_TCPSTATE_S 57
607 #define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57)
608 #define IRDMA_AEQE_Q2DATA_S 61
609 #define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61)
610 #define IRDMA_AEQE_VALID_S 63
611 #define IRDMA_AEQE_VALID BIT_ULL(63)
612 
613 #define IRDMA_UDA_QPSQ_NEXT_HDR_S 16
614 #define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16)
615 #define IRDMA_UDA_QPSQ_OPCODE_S 32
616 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
617 #define IRDMA_UDA_QPSQ_L4LEN_S 42
618 #define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42)
619 #define IRDMA_GEN1_UDA_QPSQ_L4LEN_S 24
620 #define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24)
621 #define IRDMA_UDA_QPSQ_AHIDX_S 0
622 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
623 #define IRDMA_UDA_QPSQ_VALID_S 63
624 #define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
625 #define IRDMA_UDA_QPSQ_SIGCOMPL_S 62
626 #define IRDMA_UDA_QPSQ_SIGCOMPL BIT_ULL(62)
627 #define IRDMA_UDA_QPSQ_MACLEN_S 56
628 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
629 #define IRDMA_UDA_QPSQ_IPLEN_S 48
630 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
631 #define IRDMA_UDA_QPSQ_L4T_S 30
632 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
633 #define IRDMA_UDA_QPSQ_IIPT_S 28
634 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
635 #define IRDMA_UDA_PAYLOADLEN_S 0
636 #define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)
637 #define IRDMA_UDA_HDRLEN_S 16
638 #define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16)
639 #define IRDMA_VLAN_TAG_VALID_S 50
640 #define IRDMA_VLAN_TAG_VALID BIT_ULL(50)
641 #define IRDMA_UDA_L3PROTO_S 0
642 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
643 #define IRDMA_UDA_L4PROTO_S 16
644 #define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16)
645 #define IRDMA_UDA_QPSQ_DOLOOPBACK_S 44
646 #define IRDMA_UDA_QPSQ_DOLOOPBACK BIT_ULL(44)
647 #define IRDMA_CQPSQ_BUFSIZE_S 0
648 #define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)
649 #define IRDMA_CQPSQ_OPCODE_S 32
650 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
651 #define IRDMA_CQPSQ_WQEVALID_S 63
652 #define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
653 #define IRDMA_CQPSQ_TPHVAL_S 0
654 #define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)
655 
656 #define IRDMA_CQPSQ_VSIIDX_S 8
657 #define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(17, 8)
658 #define IRDMA_CQPSQ_TPHEN_S 60
659 #define IRDMA_CQPSQ_TPHEN BIT_ULL(60)
660 
661 #define IRDMA_CQPSQ_PBUFADDR_S IRDMA_CQPHC_QPCTX_S
662 #define IRDMA_CQPSQ_PBUFADDR IRDMA_CQPHC_QPCTX
663 
664 /* Create/Modify/Destroy QP */
665 
666 #define IRDMA_CQPSQ_QP_NEWMSS_S 32
667 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
668 #define IRDMA_CQPSQ_QP_TERMLEN_S 48
669 #define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)
670 
671 #define IRDMA_CQPSQ_QP_QPCTX_S IRDMA_CQPHC_QPCTX_S
672 #define IRDMA_CQPSQ_QP_QPCTX IRDMA_CQPHC_QPCTX
673 
674 #define IRDMA_CQPSQ_QP_QPID_S 0
675 #define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL)
676 
677 #define IRDMA_CQPSQ_QP_OP_S 32
678 #define IRDMA_CQPSQ_QP_OP_M IRDMACQ_OP_M
679 #define IRDMA_CQPSQ_QP_ORDVALID_S 42
680 #define IRDMA_CQPSQ_QP_ORDVALID BIT_ULL(42)
681 #define IRDMA_CQPSQ_QP_TOECTXVALID_S 43
682 #define IRDMA_CQPSQ_QP_TOECTXVALID BIT_ULL(43)
683 #define IRDMA_CQPSQ_QP_CACHEDVARVALID_S 44
684 #define IRDMA_CQPSQ_QP_CACHEDVARVALID BIT_ULL(44)
685 #define IRDMA_CQPSQ_QP_VQ_S 45
686 #define IRDMA_CQPSQ_QP_VQ BIT_ULL(45)
687 #define IRDMA_CQPSQ_QP_FORCELOOPBACK_S 46
688 #define IRDMA_CQPSQ_QP_FORCELOOPBACK BIT_ULL(46)
689 #define IRDMA_CQPSQ_QP_CQNUMVALID_S 47
690 #define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47)
691 #define IRDMA_CQPSQ_QP_QPTYPE_S 48
692 #define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)
693 #define IRDMA_CQPSQ_QP_MACVALID_S 51
694 #define IRDMA_CQPSQ_QP_MACVALID BIT_ULL(51)
695 #define IRDMA_CQPSQ_QP_MSSCHANGE_S 52
696 #define IRDMA_CQPSQ_QP_MSSCHANGE BIT_ULL(52)
697 #define IRDMA_CQPSQ_QP_IGNOREMWBOUND_S 54
698 #define IRDMA_CQPSQ_QP_IGNOREMWBOUND BIT_ULL(54)
699 #define IRDMA_CQPSQ_QP_REMOVEHASHENTRY_S 55
700 #define IRDMA_CQPSQ_QP_REMOVEHASHENTRY BIT_ULL(55)
701 #define IRDMA_CQPSQ_QP_TERMACT_S 56
702 #define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56)
703 #define IRDMA_CQPSQ_QP_RESETCON_S 58
704 #define IRDMA_CQPSQ_QP_RESETCON BIT_ULL(58)
705 #define IRDMA_CQPSQ_QP_ARPTABIDXVALID_S 59
706 #define IRDMA_CQPSQ_QP_ARPTABIDXVALID BIT_ULL(59)
707 #define IRDMA_CQPSQ_QP_NEXTIWSTATE_S 60
708 #define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60)
709 
710 #define IRDMA_CQPSQ_QP_DBSHADOWADDR_S IRDMA_CQPHC_QPCTX_S
711 #define IRDMA_CQPSQ_QP_DBSHADOWADDR IRDMA_CQPHC_QPCTX
712 
713 #define IRDMA_CQPSQ_CQ_CQSIZE_S 0
714 #define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)
715 #define IRDMA_CQPSQ_CQ_CQCTX_S 0
716 #define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)
717 #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD_S 0
718 #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0)
719 
720 #define IRDMA_CQPSQ_CQ_OP_S 32
721 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
722 #define IRDMA_CQPSQ_CQ_CQRESIZE_S 43
723 #define IRDMA_CQPSQ_CQ_CQRESIZE BIT_ULL(43)
724 #define IRDMA_CQPSQ_CQ_LPBLSIZE_S 44
725 #define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44)
726 #define IRDMA_CQPSQ_CQ_CHKOVERFLOW_S 46
727 #define IRDMA_CQPSQ_CQ_CHKOVERFLOW BIT_ULL(46)
728 #define IRDMA_CQPSQ_CQ_VIRTMAP_S 47
729 #define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47)
730 #define IRDMA_CQPSQ_CQ_ENCEQEMASK_S 48
731 #define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48)
732 #define IRDMA_CQPSQ_CQ_CEQIDVALID_S 49
733 #define IRDMA_CQPSQ_CQ_CEQIDVALID BIT_ULL(49)
734 #define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT_S 61
735 #define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT BIT_ULL(61)
736 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX_S 0
737 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
738 
739 /* Allocate/Register/Register Shared/Deallocate Stag */
740 #define IRDMA_CQPSQ_STAG_VA_FBO_S IRDMA_CQPHC_QPCTX_S
741 #define IRDMA_CQPSQ_STAG_VA_FBO IRDMA_CQPHC_QPCTX
742 #define IRDMA_CQPSQ_STAG_STAGLEN_S 0
743 #define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)
744 #define IRDMA_CQPSQ_STAG_KEY_S 0
745 #define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)
746 #define IRDMA_CQPSQ_STAG_IDX_S 8
747 #define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8)
748 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX_S 32
749 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
750 #define IRDMA_CQPSQ_STAG_MR_S 43
751 #define IRDMA_CQPSQ_STAG_MR BIT_ULL(43)
752 #define IRDMA_CQPSQ_STAG_MWTYPE_S 42
753 #define IRDMA_CQPSQ_STAG_MWTYPE BIT_ULL(42)
754 #define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY_S 58
755 #define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY BIT_ULL(58)
756 
757 #define IRDMA_CQPSQ_STAG_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S
758 #define IRDMA_CQPSQ_STAG_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M
759 #define IRDMA_CQPSQ_STAG_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE
760 #define IRDMA_CQPSQ_STAG_HPAGESIZE_S 46
761 #define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)
762 #define IRDMA_CQPSQ_STAG_ARIGHTS_S 48
763 #define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)
764 #define IRDMA_CQPSQ_STAG_REMACCENABLED_S 53
765 #define IRDMA_CQPSQ_STAG_REMACCENABLED BIT_ULL(53)
766 #define IRDMA_CQPSQ_STAG_VABASEDTO_S 59
767 #define IRDMA_CQPSQ_STAG_VABASEDTO BIT_ULL(59)
768 #define IRDMA_CQPSQ_STAG_USEHMCFNIDX_S 60
769 #define IRDMA_CQPSQ_STAG_USEHMCFNIDX BIT_ULL(60)
770 #define IRDMA_CQPSQ_STAG_USEPFRID_S 61
771 #define IRDMA_CQPSQ_STAG_USEPFRID BIT_ULL(61)
772 
773 #define IRDMA_CQPSQ_STAG_PBA_S IRDMA_CQPHC_QPCTX_S
774 #define IRDMA_CQPSQ_STAG_PBA IRDMA_CQPHC_QPCTX
775 #define IRDMA_CQPSQ_STAG_HMCFNIDX_S 0
776 #define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0)
777 
778 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX_S 0
779 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
780 
781 #define IRDMA_CQPSQ_QUERYSTAG_IDX_S IRDMA_CQPSQ_STAG_IDX_S
782 #define IRDMA_CQPSQ_QUERYSTAG_IDX IRDMA_CQPSQ_STAG_IDX
783 #define IRDMA_CQPSQ_MLM_TABLEIDX_S 0
784 #define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)
785 #define IRDMA_CQPSQ_MLM_FREEENTRY_S 62
786 #define IRDMA_CQPSQ_MLM_FREEENTRY BIT_ULL(62)
787 #define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT_S 61
788 #define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT BIT_ULL(61)
789 #define IRDMA_CQPSQ_MLM_MAC0_S 0
790 #define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)
791 #define IRDMA_CQPSQ_MLM_MAC1_S 8
792 #define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8)
793 #define IRDMA_CQPSQ_MLM_MAC2_S 16
794 #define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16)
795 #define IRDMA_CQPSQ_MLM_MAC3_S 24
796 #define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24)
797 #define IRDMA_CQPSQ_MLM_MAC4_S 32
798 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
799 #define IRDMA_CQPSQ_MLM_MAC5_S 40
800 #define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)
801 #define IRDMA_CQPSQ_MAT_REACHMAX_S 0
802 #define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)
803 #define IRDMA_CQPSQ_MAT_MACADDR_S 0
804 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
805 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX_S 0
806 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)
807 #define IRDMA_CQPSQ_MAT_ENTRYVALID_S 42
808 #define IRDMA_CQPSQ_MAT_ENTRYVALID BIT_ULL(42)
809 #define IRDMA_CQPSQ_MAT_PERMANENT_S 43
810 #define IRDMA_CQPSQ_MAT_PERMANENT BIT_ULL(43)
811 #define IRDMA_CQPSQ_MAT_QUERY_S 44
812 #define IRDMA_CQPSQ_MAT_QUERY BIT_ULL(44)
813 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT_S 0
814 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)
815 #define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX_S 16
816 #define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16)
817 #define IRDMA_CQPSQ_MVPBP_SD_INX_S 32
818 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
819 #define IRDMA_CQPSQ_MVPBP_INV_PD_ENT_S 62
820 #define IRDMA_CQPSQ_MVPBP_INV_PD_ENT BIT_ULL(62)
821 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA_S 3
822 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
823 
824 /* Manage Push Page - MPP */
825 #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff
826 #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff
827 
828 #define IRDMA_CQPSQ_MPP_QS_HANDLE_S 0
829 #define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0)
830 #define IRDMA_CQPSQ_MPP_PPIDX_S 0
831 #define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0)
832 #define IRDMA_CQPSQ_MPP_PPTYPE_S 60
833 #define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60)
834 
835 #define IRDMA_CQPSQ_MPP_FREE_PAGE_S 62
836 #define IRDMA_CQPSQ_MPP_FREE_PAGE BIT_ULL(62)
837 
838 /* Upload Context - UCTX */
839 #define IRDMA_CQPSQ_UCTX_QPCTXADDR_S IRDMA_CQPHC_QPCTX_S
840 #define IRDMA_CQPSQ_UCTX_QPCTXADDR IRDMA_CQPHC_QPCTX
841 #define IRDMA_CQPSQ_UCTX_QPID_S 0
842 #define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)
843 #define IRDMA_CQPSQ_UCTX_QPTYPE_S 48
844 #define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)
845 
846 #define IRDMA_CQPSQ_UCTX_RAWFORMAT_S 61
847 #define IRDMA_CQPSQ_UCTX_RAWFORMAT BIT_ULL(61)
848 #define IRDMA_CQPSQ_UCTX_FREEZEQP_S 62
849 #define IRDMA_CQPSQ_UCTX_FREEZEQP BIT_ULL(62)
850 #define IRDMA_CQPSQ_MHMC_VFIDX_S 0
851 #define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)
852 #define IRDMA_CQPSQ_MHMC_FREEPMFN_S 62
853 #define IRDMA_CQPSQ_MHMC_FREEPMFN BIT_ULL(62)
854 
855 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE_S 0
856 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)
857 #define IRDMA_CQPSQ_SHMCRP_VFNUM_S 32
858 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
859 #define IRDMA_CQPSQ_CEQ_CEQSIZE_S 0
860 #define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)
861 #define IRDMA_CQPSQ_CEQ_CEQID_S 0
862 #define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)
863 
864 #define IRDMA_CQPSQ_CEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S
865 #define IRDMA_CQPSQ_CEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M
866 #define IRDMA_CQPSQ_CEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE
867 #define IRDMA_CQPSQ_CEQ_VMAP_S 47
868 #define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47)
869 #define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE_S 46
870 #define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE BIT_ULL(46)
871 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX_S 0
872 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
873 #define IRDMA_CQPSQ_AEQ_AEQECNT_S 0
874 #define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)
875 
876 #define IRDMA_CQPSQ_AEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S
877 #define IRDMA_CQPSQ_AEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M
878 #define IRDMA_CQPSQ_AEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE
879 #define IRDMA_CQPSQ_AEQ_VMAP_S 47
880 #define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47)
881 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX_S 0
882 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
883 
884 #define IRDMA_COMMIT_FPM_QPCNT_S 0
885 #define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0)
886 
887 #define IRDMA_COMMIT_FPM_BASE_S 32
888 #define IRDMA_CQPSQ_CFPM_HMCFNID_S 0
889 #define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0)
890 
891 #define IRDMA_CQPSQ_FWQE_AECODE_S 0
892 #define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)
893 #define IRDMA_CQPSQ_FWQE_AESOURCE_S 16
894 #define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16)
895 #define IRDMA_CQPSQ_FWQE_RQMNERR_S 0
896 #define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)
897 #define IRDMA_CQPSQ_FWQE_RQMJERR_S 16
898 #define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16)
899 #define IRDMA_CQPSQ_FWQE_SQMNERR_S 32
900 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
901 #define IRDMA_CQPSQ_FWQE_SQMJERR_S 48
902 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
903 #define IRDMA_CQPSQ_FWQE_QPID_S 0
904 #define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)
905 #define IRDMA_CQPSQ_FWQE_GENERATE_AE_S 59
906 #define IRDMA_CQPSQ_FWQE_GENERATE_AE BIT_ULL(59)
907 #define IRDMA_CQPSQ_FWQE_USERFLCODE_S 60
908 #define IRDMA_CQPSQ_FWQE_USERFLCODE BIT_ULL(60)
909 #define IRDMA_CQPSQ_FWQE_FLUSHSQ_S 61
910 #define IRDMA_CQPSQ_FWQE_FLUSHSQ BIT_ULL(61)
911 #define IRDMA_CQPSQ_FWQE_FLUSHRQ_S 62
912 #define IRDMA_CQPSQ_FWQE_FLUSHRQ BIT_ULL(62)
913 #define IRDMA_CQPSQ_MAPT_PORT_S 0
914 #define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)
915 #define IRDMA_CQPSQ_MAPT_ADDPORT_S 62
916 #define IRDMA_CQPSQ_MAPT_ADDPORT BIT_ULL(62)
917 #define IRDMA_CQPSQ_UPESD_SDCMD_S 0
918 #define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)
919 #define IRDMA_CQPSQ_UPESD_SDDATALOW_S 0
920 #define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)
921 #define IRDMA_CQPSQ_UPESD_SDDATAHI_S 32
922 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
923 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID_S 63
924 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
925 
926 #define IRDMA_CQPSQ_UPESD_BM_PF 0
927 #define IRDMA_CQPSQ_UPESD_BM_CP_LM 1
928 #define IRDMA_CQPSQ_UPESD_BM_AXF 2
929 #define IRDMA_CQPSQ_UPESD_BM_LM 4
930 #define IRDMA_CQPSQ_UPESD_BM_S 32
931 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
932 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT_S 0
933 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)
934 #define IRDMA_CQPSQ_UPESD_SKIP_ENTRY_S 7
935 #define IRDMA_CQPSQ_UPESD_SKIP_ENTRY BIT_ULL(7)
936 
937 /* Suspend QP */
938 #define IRDMA_CQPSQ_SUSPENDQP_QPID_S 0
939 #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)
940 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE_S 0
941 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)
942 
943 #define IRDMA_CQPSQ_RESUMEQP_QPID_S IRDMA_CQPSQ_SUSPENDQP_QPID_S
944 #define IRDMA_CQPSQ_RESUMEQP_QPID_M IRDMA_CQPSQ_SUSPENDQP_QPID_M
945 #define IRDMA_CQPSQ_RESUMEQP_QPID IRDMA_CQPSQ_SUSPENDQP_QPID
946 
947 #define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001
948 #define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005
949 
950 #define IRDMA_CQPSQ_MAJ_NO_ERROR 0x0000
951 #define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000
952 #define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001
953 #define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF
954 #define IRDMAQPC_DDP_VER_S 0
955 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
956 #define IRDMAQPC_IBRDENABLE_S 2
957 #define IRDMAQPC_IBRDENABLE BIT_ULL(2)
958 #define IRDMAQPC_IPV4_S 3
959 #define IRDMAQPC_IPV4 BIT_ULL(3)
960 #define IRDMAQPC_NONAGLE_S 4
961 #define IRDMAQPC_NONAGLE BIT_ULL(4)
962 #define IRDMAQPC_INSERTVLANTAG_S 5
963 #define IRDMAQPC_INSERTVLANTAG BIT_ULL(5)
964 #define IRDMAQPC_ISQP1_S 6
965 #define IRDMAQPC_ISQP1 BIT_ULL(6)
966 #define IRDMAQPC_TIMESTAMP_S 7
967 #define IRDMAQPC_TIMESTAMP BIT_ULL(7)
968 #define IRDMAQPC_RQWQESIZE_S 8
969 #define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8)
970 #define IRDMAQPC_INSERTL2TAG2_S 11
971 #define IRDMAQPC_INSERTL2TAG2 BIT_ULL(11)
972 #define IRDMAQPC_LIMIT_S 12
973 #define IRDMAQPC_LIMIT GENMASK_ULL(13, 12)
974 
975 #define IRDMAQPC_ECN_EN_S 14
976 #define IRDMAQPC_ECN_EN BIT_ULL(14)
977 #define IRDMAQPC_DROPOOOSEG_S 15
978 #define IRDMAQPC_DROPOOOSEG BIT_ULL(15)
979 #define IRDMAQPC_DUPACK_THRESH_S 16
980 #define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16)
981 #define IRDMAQPC_ERR_RQ_IDX_VALID_S 19
982 #define IRDMAQPC_ERR_RQ_IDX_VALID BIT_ULL(19)
983 #define IRDMAQPC_DIS_VLAN_CHECKS_S 19
984 #define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19)
985 #define IRDMAQPC_DC_TCP_EN_S 25
986 #define IRDMAQPC_DC_TCP_EN BIT_ULL(25)
987 #define IRDMAQPC_RCVTPHEN_S 28
988 #define IRDMAQPC_RCVTPHEN BIT_ULL(28)
989 #define IRDMAQPC_XMITTPHEN_S 29
990 #define IRDMAQPC_XMITTPHEN BIT_ULL(29)
991 #define IRDMAQPC_RQTPHEN_S 30
992 #define IRDMAQPC_RQTPHEN BIT_ULL(30)
993 #define IRDMAQPC_SQTPHEN_S 31
994 #define IRDMAQPC_SQTPHEN BIT_ULL(31)
995 #define IRDMAQPC_PPIDX_S 32
996 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
997 #define IRDMAQPC_PMENA_S 47
998 #define IRDMAQPC_PMENA BIT_ULL(47)
999 #define IRDMAQPC_RDMAP_VER_S 62
1000 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
1001 #define IRDMAQPC_ROCE_TVER_S 60
1002 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
1003 
1004 #define IRDMAQPC_SQADDR_S IRDMA_CQPHC_QPCTX_S
1005 #define IRDMAQPC_SQADDR IRDMA_CQPHC_QPCTX
1006 
1007 #define IRDMAQPC_RQADDR_S IRDMA_CQPHC_QPCTX_S
1008 #define IRDMAQPC_RQADDR IRDMA_CQPHC_QPCTX
1009 #define IRDMAQPC_TTL_S 0
1010 #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
1011 #define IRDMAQPC_RQSIZE_S 8
1012 #define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8)
1013 #define IRDMAQPC_SQSIZE_S 12
1014 #define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12)
1015 #define IRDMAQPC_GEN1_SRCMACADDRIDX_S 16
1016 #define IRDMAQPC_GEN1_SRCMACADDRIDX GENMASK(21, 16)
1017 #define IRDMAQPC_AVOIDSTRETCHACK_S 23
1018 #define IRDMAQPC_AVOIDSTRETCHACK BIT_ULL(23)
1019 #define IRDMAQPC_TOS_S 24
1020 #define IRDMAQPC_TOS GENMASK_ULL(31, 24)
1021 #define IRDMAQPC_SRCPORTNUM_S 32
1022 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
1023 #define IRDMAQPC_DESTPORTNUM_S 48
1024 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
1025 #define IRDMAQPC_DESTIPADDR0_S 32
1026 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
1027 #define IRDMAQPC_DESTIPADDR1_S 0
1028 #define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)
1029 #define IRDMAQPC_DESTIPADDR2_S 32
1030 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
1031 #define IRDMAQPC_DESTIPADDR3_S 0
1032 #define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)
1033 #define IRDMAQPC_SNDMSS_S 16
1034 #define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16)
1035 #define IRDMAQPC_SYN_RST_HANDLING_S 30
1036 #define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30)
1037 #define IRDMAQPC_VLANTAG_S 32
1038 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
1039 #define IRDMAQPC_ARPIDX_S 48
1040 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
1041 #define IRDMAQPC_FLOWLABEL_S 0
1042 #define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)
1043 #define IRDMAQPC_WSCALE_S 20
1044 #define IRDMAQPC_WSCALE BIT_ULL(20)
1045 #define IRDMAQPC_KEEPALIVE_S 21
1046 #define IRDMAQPC_KEEPALIVE BIT_ULL(21)
1047 #define IRDMAQPC_IGNORE_TCP_OPT_S 22
1048 #define IRDMAQPC_IGNORE_TCP_OPT BIT_ULL(22)
1049 #define IRDMAQPC_IGNORE_TCP_UNS_OPT_S 23
1050 #define IRDMAQPC_IGNORE_TCP_UNS_OPT BIT_ULL(23)
1051 #define IRDMAQPC_TCPSTATE_S 28
1052 #define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28)
1053 #define IRDMAQPC_RCVSCALE_S 32
1054 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
1055 #define IRDMAQPC_SNDSCALE_S 40
1056 #define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40)
1057 #define IRDMAQPC_PDIDX_S 48
1058 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
1059 #define IRDMAQPC_PDIDXHI_S 20
1060 #define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20)
1061 #define IRDMAQPC_PKEY_S 32
1062 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
1063 #define IRDMAQPC_ACKCREDITS_S 20
1064 #define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20)
1065 #define IRDMAQPC_QKEY_S 32
1066 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
1067 #define IRDMAQPC_DESTQP_S 0
1068 #define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)
1069 #define IRDMAQPC_KALIVE_TIMER_MAX_PROBES_S 16
1070 #define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16)
1071 #define IRDMAQPC_KEEPALIVE_INTERVAL_S 24
1072 #define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24)
1073 #define IRDMAQPC_TIMESTAMP_RECENT_S 0
1074 #define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)
1075 #define IRDMAQPC_TIMESTAMP_AGE_S 32
1076 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
1077 #define IRDMAQPC_SNDNXT_S 0
1078 #define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)
1079 #define IRDMAQPC_ISN_S 32
1080 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
1081 #define IRDMAQPC_PSNNXT_S 0
1082 #define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)
1083 #define IRDMAQPC_LSN_S 32
1084 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
1085 #define IRDMAQPC_SNDWND_S 32
1086 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
1087 #define IRDMAQPC_RCVNXT_S 0
1088 #define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)
1089 #define IRDMAQPC_EPSN_S 0
1090 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
1091 #define IRDMAQPC_RCVWND_S 32
1092 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
1093 #define IRDMAQPC_SNDMAX_S 0
1094 #define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)
1095 #define IRDMAQPC_SNDUNA_S 32
1096 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
1097 #define IRDMAQPC_PSNMAX_S 0
1098 #define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)
1099 #define IRDMAQPC_PSNUNA_S 32
1100 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
1101 #define IRDMAQPC_SRTT_S 0
1102 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
1103 #define IRDMAQPC_RTTVAR_S 32
1104 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
1105 #define IRDMAQPC_SSTHRESH_S 0
1106 #define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)
1107 #define IRDMAQPC_CWND_S 32
1108 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
1109 #define IRDMAQPC_CWNDROCE_S 32
1110 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
1111 #define IRDMAQPC_SNDWL1_S 0
1112 #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
1113 #define IRDMAQPC_SNDWL2_S 32
1114 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
1115 #define IRDMAQPC_ERR_RQ_IDX_S 32
1116 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32)
1117 #define IRDMAQPC_RTOMIN_S 57
1118 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
1119 #define IRDMAQPC_MAXSNDWND_S 0
1120 #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
1121 #define IRDMAQPC_REXMIT_THRESH_S 48
1122 #define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)
1123 #define IRDMAQPC_RNRNAK_THRESH_S 54
1124 #define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54)
1125 #define IRDMAQPC_TXCQNUM_S 0
1126 #define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0)
1127 #define IRDMAQPC_RXCQNUM_S 32
1128 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
1129 #define IRDMAQPC_STAT_INDEX_S 0
1130 #define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)
1131 #define IRDMAQPC_Q2ADDR_S 8
1132 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
1133 #define IRDMAQPC_LASTBYTESENT_S 0
1134 #define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)
1135 #define IRDMAQPC_MACADDRESS_S 16
1136 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
1137 #define IRDMAQPC_ORDSIZE_S 0
1138 #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
1139 
1140 #define IRDMAQPC_IRDSIZE_S 16
1141 #define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16)
1142 
1143 #define IRDMAQPC_UDPRIVCQENABLE_S 19
1144 #define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19)
1145 #define IRDMAQPC_WRRDRSPOK_S 20
1146 #define IRDMAQPC_WRRDRSPOK BIT_ULL(20)
1147 #define IRDMAQPC_RDOK_S 21
1148 #define IRDMAQPC_RDOK BIT_ULL(21)
1149 #define IRDMAQPC_SNDMARKERS_S 22
1150 #define IRDMAQPC_SNDMARKERS BIT_ULL(22)
1151 #define IRDMAQPC_DCQCNENABLE_S 22
1152 #define IRDMAQPC_DCQCNENABLE BIT_ULL(22)
1153 #define IRDMAQPC_FW_CC_ENABLE_S 28
1154 #define IRDMAQPC_FW_CC_ENABLE BIT_ULL(28)
1155 #define IRDMAQPC_RCVNOICRC_S 31
1156 #define IRDMAQPC_RCVNOICRC BIT_ULL(31)
1157 #define IRDMAQPC_BINDEN_S 23
1158 #define IRDMAQPC_BINDEN BIT_ULL(23)
1159 #define IRDMAQPC_FASTREGEN_S 24
1160 #define IRDMAQPC_FASTREGEN BIT_ULL(24)
1161 #define IRDMAQPC_PRIVEN_S 25
1162 #define IRDMAQPC_PRIVEN BIT_ULL(25)
1163 #define IRDMAQPC_TIMELYENABLE_S 27
1164 #define IRDMAQPC_TIMELYENABLE BIT_ULL(27)
1165 #define IRDMAQPC_THIGH_S 52
1166 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
1167 #define IRDMAQPC_TLOW_S 32
1168 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
1169 #define IRDMAQPC_REMENDPOINTIDX_S 0
1170 #define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)
1171 #define IRDMAQPC_USESTATSINSTANCE_S 26
1172 #define IRDMAQPC_USESTATSINSTANCE BIT_ULL(26)
1173 #define IRDMAQPC_IWARPMODE_S 28
1174 #define IRDMAQPC_IWARPMODE BIT_ULL(28)
1175 #define IRDMAQPC_RCVMARKERS_S 29
1176 #define IRDMAQPC_RCVMARKERS BIT_ULL(29)
1177 #define IRDMAQPC_ALIGNHDRS_S 30
1178 #define IRDMAQPC_ALIGNHDRS BIT_ULL(30)
1179 #define IRDMAQPC_RCVNOMPACRC_S 31
1180 #define IRDMAQPC_RCVNOMPACRC BIT_ULL(31)
1181 #define IRDMAQPC_RCVMARKOFFSET_S 32
1182 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
1183 #define IRDMAQPC_SNDMARKOFFSET_S 48
1184 #define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)
1185 
1186 #define IRDMAQPC_QPCOMPCTX_S IRDMA_CQPHC_QPCTX_S
1187 #define IRDMAQPC_QPCOMPCTX IRDMA_CQPHC_QPCTX
1188 #define IRDMAQPC_SQTPHVAL_S 0
1189 #define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)
1190 #define IRDMAQPC_RQTPHVAL_S 8
1191 #define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8)
1192 #define IRDMAQPC_QSHANDLE_S 16
1193 #define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16)
1194 #define IRDMAQPC_EXCEPTION_LAN_QUEUE_S 32
1195 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
1196 #define IRDMAQPC_LOCAL_IPADDR3_S 0
1197 #define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)
1198 #define IRDMAQPC_LOCAL_IPADDR2_S 32
1199 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
1200 #define IRDMAQPC_LOCAL_IPADDR1_S 0
1201 #define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)
1202 #define IRDMAQPC_LOCAL_IPADDR0_S 32
1203 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
1204 #define IRDMA_FW_VER_MINOR_S 0
1205 #define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)
1206 #define IRDMA_FW_VER_MAJOR_S 16
1207 #define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16)
1208 #define IRDMA_FEATURE_INFO_S 0
1209 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
1210 #define IRDMA_FEATURE_CNT_S 32
1211 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
1212 #define IRDMA_FEATURE_TYPE_S 48
1213 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
1214 #define IRDMA_RSVD_S 41
1215 #define IRDMA_RSVD GENMASK_ULL(55, 41)
1216 
1217 #define IRDMAQPSQ_OPCODE_S 32
1218 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
1219 #define IRDMAQPSQ_COPY_HOST_PBL_S 43
1220 #define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43)
1221 #define IRDMAQPSQ_ADDFRAGCNT_S 38
1222 #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
1223 #define IRDMAQPSQ_PUSHWQE_S 56
1224 #define IRDMAQPSQ_PUSHWQE BIT_ULL(56)
1225 #define IRDMAQPSQ_STREAMMODE_S 58
1226 #define IRDMAQPSQ_STREAMMODE BIT_ULL(58)
1227 #define IRDMAQPSQ_WAITFORRCVPDU_S 59
1228 #define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59)
1229 #define IRDMAQPSQ_READFENCE_S 60
1230 #define IRDMAQPSQ_READFENCE BIT_ULL(60)
1231 #define IRDMAQPSQ_LOCALFENCE_S 61
1232 #define IRDMAQPSQ_LOCALFENCE BIT_ULL(61)
1233 #define IRDMAQPSQ_UDPHEADER_S 61
1234 #define IRDMAQPSQ_UDPHEADER BIT_ULL(61)
1235 #define IRDMAQPSQ_L4LEN_S 42
1236 #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)
1237 #define IRDMAQPSQ_SIGCOMPL_S 62
1238 #define IRDMAQPSQ_SIGCOMPL BIT_ULL(62)
1239 #define IRDMAQPSQ_VALID_S 63
1240 #define IRDMAQPSQ_VALID BIT_ULL(63)
1241 
1242 #define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S
1243 #define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX
1244 #define IRDMAQPSQ_FRAG_VALID_S 63
1245 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
1246 #define IRDMAQPSQ_FRAG_LEN_S 32
1247 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
1248 #define IRDMAQPSQ_FRAG_STAG_S 0
1249 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
1250 #define IRDMAQPSQ_GEN1_FRAG_LEN_S 0
1251 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
1252 #define IRDMAQPSQ_GEN1_FRAG_STAG_S 32
1253 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
1254 #define IRDMAQPSQ_REMSTAGINV_S 0
1255 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
1256 #define IRDMAQPSQ_DESTQKEY_S 0
1257 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
1258 #define IRDMAQPSQ_DESTQPN_S 32
1259 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
1260 #define IRDMAQPSQ_AHID_S 0
1261 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
1262 #define IRDMAQPSQ_INLINEDATAFLAG_S 57
1263 #define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57)
1264 
1265 #define IRDMA_INLINE_VALID_S 7
1266 #define IRDMAQPSQ_INLINEDATALEN_S 48
1267 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
1268 #define IRDMAQPSQ_IMMDATAFLAG_S 47
1269 #define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)
1270 #define IRDMAQPSQ_REPORTRTT_S 46
1271 #define IRDMAQPSQ_REPORTRTT BIT_ULL(46)
1272 
1273 #define IRDMAQPSQ_IMMDATA_S 0
1274 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
1275 #define IRDMAQPSQ_REMSTAG_S 0
1276 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
1277 
1278 #define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S
1279 #define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX
1280 
1281 #define IRDMAQPSQ_STAGRIGHTS_S 48
1282 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
1283 #define IRDMAQPSQ_VABASEDTO_S 53
1284 #define IRDMAQPSQ_VABASEDTO BIT_ULL(53)
1285 #define IRDMAQPSQ_MEMWINDOWTYPE_S 54
1286 #define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54)
1287 
1288 #define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S
1289 #define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX
1290 #define IRDMAQPSQ_PARENTMRSTAG_S 32
1291 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
1292 #define IRDMAQPSQ_MWSTAG_S 0
1293 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
1294 
1295 #define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S
1296 #define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX
1297 
1298 #define IRDMAQPSQ_LOCSTAG_S 0
1299 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
1300 
1301 #define IRDMAQPSQ_STAGKEY_S 0
1302 #define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)
1303 #define IRDMAQPSQ_STAGINDEX_S 8
1304 #define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8)
1305 #define IRDMAQPSQ_COPYHOSTPBLS_S 43
1306 #define IRDMAQPSQ_COPYHOSTPBLS BIT_ULL(43)
1307 #define IRDMAQPSQ_LPBLSIZE_S 44
1308 #define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44)
1309 #define IRDMAQPSQ_HPAGESIZE_S 46
1310 #define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)
1311 #define IRDMAQPSQ_STAGLEN_S 0
1312 #define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)
1313 #define IRDMAQPSQ_FIRSTPMPBLIDXLO_S 48
1314 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
1315 #define IRDMAQPSQ_FIRSTPMPBLIDXHI_S 0
1316 #define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)
1317 #define IRDMAQPSQ_PBLADDR_S 12
1318 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
1319 
1320 /* iwarp QP RQ WQE common fields */
1321 #define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S
1322 #define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT
1323 
1324 #define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S
1325 #define IRDMAQPRQ_VALID IRDMAQPSQ_VALID
1326 
1327 #define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S
1328 #define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX
1329 
1330 #define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S
1331 #define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN
1332 
1333 #define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S
1334 #define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG
1335 
1336 #define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S
1337 #define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO
1338 
1339 #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26)
1340 #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27)
1341 #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28)
1342 
1343 #define IRDMA_QUERY_FPM_MAX_QPS_S 0
1344 #define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0)
1345 #define IRDMA_QUERY_FPM_MAX_CQS_S 0
1346 #define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0)
1347 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX_S 0
1348 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)
1349 #define IRDMA_QUERY_FPM_MAX_PE_SDS_S 32
1350 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
1351 
1352 #define IRDMA_QUERY_FPM_MAX_CEQS_S 0
1353 #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)
1354 #define IRDMA_QUERY_FPM_XFBLOCKSIZE_S 32
1355 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
1356 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE_S 32
1357 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
1358 #define IRDMA_QUERY_FPM_HTMULTIPLIER_S 16
1359 #define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16)
1360 #define IRDMA_QUERY_FPM_TIMERBUCKET_S 32
1361 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
1362 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE_S 32
1363 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
1364 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE_S 32
1365 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
1366 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE_S 32
1367 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
1368 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID_S 0
1369 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(15, 0)
1370 
1371 #define IRDMA_GET_CURRENT_AEQ_ELEM(_aeq) \
1372 	( \
1373 		(_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
1374 	)
1375 
1376 #define IRDMA_GET_CURRENT_CEQ_ELEM(_ceq) \
1377 	( \
1378 		(_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
1379 	)
1380 
1381 #define IRDMA_GET_CEQ_ELEM_AT_POS(_ceq, _pos) \
1382 	( \
1383 		(_ceq)->ceqe_base[_pos].buf  \
1384 	)
1385 
1386 #define IRDMA_RING_GET_NEXT_TAIL(_ring, _idx) \
1387 	( \
1388 		((_ring).tail + (_idx)) % (_ring).size \
1389 	)
1390 
1391 #define IRDMA_GET_RING_OFFSET(_ring, _i) \
1392 	( \
1393 		((_ring).head + (_i)) % (_ring).size \
1394 	)
1395 
1396 #define IRDMA_GET_CQ_ELEM_AT_OFFSET(_cq, _i, _cqe) \
1397 	{ \
1398 		__u32 offset; \
1399 		offset = IRDMA_GET_RING_OFFSET((_cq)->cq_ring, _i); \
1400 		(_cqe) = (_cq)->cq_base[offset].buf; \
1401 	}
1402 #define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \
1403 	( \
1404 		(_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf  \
1405 	)
1406 #define IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(_cq) \
1407 	( \
1408 		((struct irdma_extended_cqe *) \
1409 		((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
1410 	)
1411 
1412 #define IRDMA_RING_INIT(_ring, _size) \
1413 	{ \
1414 		(_ring).head = 0; \
1415 		(_ring).tail = 0; \
1416 		(_ring).size = (_size); \
1417 	}
1418 #define IRDMA_RING_SIZE(_ring) ((_ring).size)
1419 #define IRDMA_RING_CURRENT_HEAD(_ring) ((_ring).head)
1420 #define IRDMA_RING_CURRENT_TAIL(_ring) ((_ring).tail)
1421 
1422 #define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \
1423 	{ \
1424 		u32 size; \
1425 		size = (_ring).size;  \
1426 		if (!IRDMA_RING_FULL_ERR(_ring)) { \
1427 			(_ring).head = ((_ring).head + 1) % size; \
1428 			(_retcode) = 0; \
1429 		} else { \
1430 			(_retcode) = -ENOSPC; \
1431 		} \
1432 	}
1433 #define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
1434 	{ \
1435 		u32 size; \
1436 		size = (_ring).size; \
1437 		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \
1438 			(_ring).head = ((_ring).head + (_count)) % size; \
1439 			(_retcode) = 0; \
1440 		} else { \
1441 			(_retcode) = -ENOSPC; \
1442 		} \
1443 	}
1444 #define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \
1445 	{ \
1446 		u32 size; \
1447 		size = (_ring).size;  \
1448 		if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \
1449 			(_ring).head = ((_ring).head + 1) % size; \
1450 			(_retcode) = 0; \
1451 		} else { \
1452 			(_retcode) = -ENOSPC; \
1453 		} \
1454 	}
1455 #define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
1456 	{ \
1457 		u32 size; \
1458 		size = (_ring).size; \
1459 		if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1460 			(_ring).head = ((_ring).head + (_count)) % size; \
1461 			(_retcode) = 0; \
1462 		} else { \
1463 			(_retcode) = -ENOSPC; \
1464 		} \
1465 	}
1466 #define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \
1467 	(_ring).head = ((_ring).head + (_count)) % (_ring).size
1468 
1469 #define IRDMA_RING_MOVE_TAIL(_ring) \
1470 	(_ring).tail = ((_ring).tail + 1) % (_ring).size
1471 
1472 #define IRDMA_RING_MOVE_HEAD_NOCHECK(_ring) \
1473 	(_ring).head = ((_ring).head + 1) % (_ring).size
1474 
1475 #define IRDMA_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \
1476 	(_ring).tail = ((_ring).tail + (_count)) % (_ring).size
1477 
1478 #define IRDMA_RING_SET_TAIL(_ring, _pos) \
1479 	(_ring).tail = (_pos) % (_ring).size
1480 
1481 #define IRDMA_RING_FULL_ERR(_ring) \
1482 	( \
1483 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1))  \
1484 	)
1485 
1486 #define IRDMA_ERR_RING_FULL2(_ring) \
1487 	( \
1488 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2))  \
1489 	)
1490 
1491 #define IRDMA_ERR_RING_FULL3(_ring) \
1492 	( \
1493 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3))  \
1494 	)
1495 
1496 #define IRDMA_SQ_RING_FULL_ERR(_ring) \
1497 	( \
1498 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257))  \
1499 	)
1500 
1501 #define IRDMA_ERR_SQ_RING_FULL2(_ring) \
1502 	( \
1503 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258))  \
1504 	)
1505 #define IRDMA_ERR_SQ_RING_FULL3(_ring) \
1506 	( \
1507 		(IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259))  \
1508 	)
1509 #define IRDMA_RING_MORE_WORK(_ring) \
1510 	( \
1511 		(IRDMA_RING_USED_QUANTA(_ring) != 0) \
1512 	)
1513 
1514 #define IRDMA_RING_USED_QUANTA(_ring) \
1515 	( \
1516 		(((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1517 	)
1518 
1519 #define IRDMA_RING_FREE_QUANTA(_ring) \
1520 	( \
1521 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1522 	)
1523 
1524 #define IRDMA_SQ_RING_FREE_QUANTA(_ring) \
1525 	( \
1526 		((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1527 	)
1528 
1529 #define IRDMA_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \
1530 	{ \
1531 		index = IRDMA_RING_CURRENT_HEAD(_ring); \
1532 		IRDMA_RING_MOVE_HEAD(_ring, _retcode); \
1533 	}
1534 
1535 enum irdma_protocol_used {
1536 	IRDMA_ANY_PROTOCOL = 0,
1537 	IRDMA_IWARP_PROTOCOL_ONLY = 1,
1538 	IRDMA_ROCE_PROTOCOL_ONLY = 2,
1539 };
1540 
1541 enum irdma_qp_wqe_size {
1542 	IRDMA_WQE_SIZE_32  = 32,
1543 	IRDMA_WQE_SIZE_64  = 64,
1544 	IRDMA_WQE_SIZE_96  = 96,
1545 	IRDMA_WQE_SIZE_128 = 128,
1546 	IRDMA_WQE_SIZE_256 = 256,
1547 };
1548 
1549 enum irdma_ws_op_type {
1550 	IRDMA_WS_OP_TYPE_NODE = 0,
1551 	IRDMA_WS_OP_TYPE_LEAF_NODE_GROUP,
1552 };
1553 
1554 enum irdma_ws_rate_limit_flags {
1555 	IRDMA_WS_RATE_LIMIT_FLAGS_VALID = 0x1,
1556 	IRDMA_WS_NO_RDMA_RATE_LIMIT = 0x2,
1557 	IRDMA_WS_LEAF_NODE_IS_PART_GROUP = 0x4,
1558 	IRDMA_WS_TREE_RATE_LIMITING = 0x8,
1559 	IRDMA_WS_PACING_CONTROL = 0x10,
1560 };
1561 
1562 enum irdma_ws_node_op {
1563 	IRDMA_ADD_NODE = 0,
1564 	IRDMA_MODIFY_NODE,
1565 	IRDMA_DEL_NODE,
1566 };
1567 
1568 enum {	IRDMA_Q_ALIGNMENT_M		 = (128 - 1),
1569 	IRDMA_AEQ_ALIGNMENT_M		 = (256 - 1),
1570 	IRDMA_Q2_ALIGNMENT_M		 = (256 - 1),
1571 	IRDMA_CEQ_ALIGNMENT_M		 = (256 - 1),
1572 	IRDMA_CQ0_ALIGNMENT_M		 = (256 - 1),
1573 	IRDMA_HOST_CTX_ALIGNMENT_M	 = (4 - 1),
1574 	IRDMA_SHADOWAREA_M		 = (128 - 1),
1575 	IRDMA_FPM_QUERY_BUF_ALIGNMENT_M	 = (4 - 1),
1576 	IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1577 };
1578 
1579 enum irdma_alignment {
1580 	IRDMA_CQP_ALIGNMENT	    = 0x200,
1581 	IRDMA_AEQ_ALIGNMENT	    = 0x100,
1582 	IRDMA_CEQ_ALIGNMENT	    = 0x100,
1583 	IRDMA_CQ0_ALIGNMENT	    = 0x100,
1584 	IRDMA_SD_BUF_ALIGNMENT      = 0x80,
1585 	IRDMA_FEATURE_BUF_ALIGNMENT = 0x10,
1586 };
1587 
1588 /**
1589  * set_64bit_val - set 64 bit value to hw wqe
1590  * @wqe_words: wqe addr to write
1591  * @byte_index: index in wqe
1592  * @val: value to write
1593  **/
1594 static inline void set_64bit_val(__le64 *wqe_words, u32 byte_index, u64 val)
1595 {
1596 	wqe_words[byte_index >> 3] = cpu_to_le64(val);
1597 }
1598 
1599 /**
1600  * set_32bit_val - set 32 bit value to hw wqe
1601  * @wqe_words: wqe addr to write
1602  * @byte_index: index in wqe
1603  * @val: value to write
1604  **/
1605 static inline void set_32bit_val(__le32 *wqe_words, u32 byte_index, u32 val)
1606 {
1607 	wqe_words[byte_index >> 2] = cpu_to_le32(val);
1608 }
1609 
1610 /**
1611  * get_64bit_val - read 64 bit value from wqe
1612  * @wqe_words: wqe addr
1613  * @byte_index: index to read from
1614  * @val: read value
1615  **/
1616 static inline void get_64bit_val(__le64 *wqe_words, u32 byte_index, u64 *val)
1617 {
1618 	*val = le64_to_cpu(wqe_words[byte_index >> 3]);
1619 }
1620 
1621 /**
1622  * get_32bit_val - read 32 bit value from wqe
1623  * @wqe_words: wqe addr
1624  * @byte_index: index to reaad from
1625  * @val: return 32 bit value
1626  **/
1627 static inline void get_32bit_val(__le32 *wqe_words, u32 byte_index, u32 *val)
1628 {
1629 	*val = le32_to_cpu(wqe_words[byte_index >> 2]);
1630 }
1631 #endif /* IRDMA_DEFS_H */
1632