1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2015 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #ifndef IRDMA_DEFS_H 37 #define IRDMA_DEFS_H 38 39 #define IRDMA_FIRST_USER_QP_ID 3 40 41 #define ECN_CODE_PT_MASK 3 42 #define ECN_CODE_PT_VAL 2 43 44 #define IRDMA_PUSH_OFFSET (8 * 1024 * 1024) 45 #define IRDMA_PF_FIRST_PUSH_PAGE_INDEX 16 46 #define IRDMA_PF_BAR_RSVD (60 * 1024) 47 48 #define IRDMA_PE_DB_SIZE_4M 1 49 #define IRDMA_PE_DB_SIZE_8M 2 50 51 #define IRDMA_IRD_HW_SIZE_4 0 52 #define IRDMA_IRD_HW_SIZE_16 1 53 #define IRDMA_IRD_HW_SIZE_64 2 54 #define IRDMA_IRD_HW_SIZE_128 3 55 #define IRDMA_IRD_HW_SIZE_256 4 56 57 #define IRDMA_QP_STATE_INVALID 0 58 #define IRDMA_QP_STATE_IDLE 1 59 #define IRDMA_QP_STATE_RTS 2 60 #define IRDMA_QP_STATE_CLOSING 3 61 #define IRDMA_QP_STATE_SQD 3 62 #define IRDMA_QP_STATE_RTR 4 63 #define IRDMA_QP_STATE_TERMINATE 5 64 #define IRDMA_QP_STATE_ERROR 6 65 66 #define IRDMA_MAX_USER_PRIORITY 8 67 #define IRDMA_DSCP_NUM_VAL 64 68 #define IRDMA_MAX_TRAFFIC_CLASS 8 69 #define IRDMA_MAX_STATS_COUNT 128 70 #define IRDMA_FIRST_NON_PF_STAT 4 71 72 #define IRDMA_MIN_MTU_IPV4 576 73 #define IRDMA_MIN_MTU_IPV6 1280 74 #define IRDMA_MTU_TO_MSS_IPV4 40 75 #define IRDMA_MTU_TO_MSS_IPV6 60 76 #define IRDMA_DEFAULT_MTU 1500 77 78 #define Q2_FPSN_OFFSET 64 79 #define TERM_DDP_LEN_TAGGED 14 80 #define TERM_DDP_LEN_UNTAGGED 18 81 #define TERM_RDMA_LEN 28 82 #define RDMA_OPCODE_M 0x0f 83 #define RDMA_READ_REQ_OPCODE 1 84 #define Q2_BAD_FRAME_OFFSET 72 85 #define CQE_MAJOR_DRV 0x8000 86 87 #define IRDMA_TERM_SENT 1 88 #define IRDMA_TERM_RCVD 2 89 #define IRDMA_TERM_DONE 4 90 #define IRDMA_MAC_HLEN 14 91 #define IRDMA_BYTE_0 0 92 #define IRDMA_BYTE_8 8 93 #define IRDMA_BYTE_16 16 94 #define IRDMA_BYTE_24 24 95 #define IRDMA_BYTE_32 32 96 #define IRDMA_BYTE_40 40 97 #define IRDMA_BYTE_48 48 98 #define IRDMA_BYTE_56 56 99 #define IRDMA_BYTE_64 64 100 #define IRDMA_BYTE_72 72 101 #define IRDMA_BYTE_80 80 102 #define IRDMA_BYTE_88 88 103 #define IRDMA_BYTE_96 96 104 #define IRDMA_BYTE_104 104 105 #define IRDMA_BYTE_112 112 106 #define IRDMA_BYTE_120 120 107 #define IRDMA_BYTE_128 128 108 #define IRDMA_BYTE_136 136 109 #define IRDMA_BYTE_144 144 110 #define IRDMA_BYTE_152 152 111 #define IRDMA_BYTE_160 160 112 #define IRDMA_BYTE_168 168 113 #define IRDMA_BYTE_176 176 114 #define IRDMA_BYTE_184 184 115 #define IRDMA_BYTE_192 192 116 #define IRDMA_BYTE_200 200 117 #define IRDMA_BYTE_208 208 118 #define IRDMA_BYTE_216 216 119 120 #define IRDMA_CQP_WAIT_POLL_REGS 1 121 #define IRDMA_CQP_WAIT_POLL_CQ 2 122 #define IRDMA_CQP_WAIT_EVENT 3 123 124 #define IRDMA_AE_SOURCE_RSVD 0x0 125 #define IRDMA_AE_SOURCE_RQ 0x1 126 #define IRDMA_AE_SOURCE_RQ_0011 0x3 127 128 #define IRDMA_AE_SOURCE_CQ 0x2 129 #define IRDMA_AE_SOURCE_CQ_0110 0x6 130 #define IRDMA_AE_SOURCE_CQ_1010 0xa 131 #define IRDMA_AE_SOURCE_CQ_1110 0xe 132 133 #define IRDMA_AE_SOURCE_SQ 0x5 134 #define IRDMA_AE_SOURCE_SQ_0111 0x7 135 136 #define IRDMA_AE_SOURCE_IN_WR 0x9 137 #define IRDMA_AE_SOURCE_IN_RR 0xb 138 #define IRDMA_AE_SOURCE_OUT_RR 0xd 139 #define IRDMA_AE_SOURCE_OUT_RR_1111 0xf 140 141 #define IRDMA_TCP_STATE_NON_EXISTENT 0 142 #define IRDMA_TCP_STATE_CLOSED 1 143 #define IRDMA_TCP_STATE_LISTEN 2 144 #define IRDMA_STATE_SYN_SEND 3 145 #define IRDMA_TCP_STATE_SYN_RECEIVED 4 146 #define IRDMA_TCP_STATE_ESTABLISHED 5 147 #define IRDMA_TCP_STATE_CLOSE_WAIT 6 148 #define IRDMA_TCP_STATE_FIN_WAIT_1 7 149 #define IRDMA_TCP_STATE_CLOSING 8 150 #define IRDMA_TCP_STATE_LAST_ACK 9 151 #define IRDMA_TCP_STATE_FIN_WAIT_2 10 152 #define IRDMA_TCP_STATE_TIME_WAIT 11 153 #define IRDMA_TCP_STATE_RESERVED_1 12 154 #define IRDMA_TCP_STATE_RESERVED_2 13 155 #define IRDMA_TCP_STATE_RESERVED_3 14 156 #define IRDMA_TCP_STATE_RESERVED_4 15 157 158 #define IRDMA_CQP_SW_SQSIZE_4 4 159 #define IRDMA_CQP_SW_SQSIZE_2048 2048 160 161 #define IRDMA_CQ_TYPE_IWARP 1 162 #define IRDMA_CQ_TYPE_ILQ 2 163 #define IRDMA_CQ_TYPE_IEQ 3 164 #define IRDMA_CQ_TYPE_CQP 4 165 166 #define IRDMA_DONE_COUNT 1000 167 #define IRDMA_SLEEP_COUNT 10 168 169 #define IRDMA_UPDATE_SD_BUFF_SIZE 128 170 #define IRDMA_FEATURE_BUF_SIZE (8 * IRDMA_MAX_FEATURES) 171 172 #define IRDMA_MAX_QUANTA_PER_WR 8 173 174 #define IRDMA_QP_SW_MAX_WQ_QUANTA 32768 175 #define IRDMA_QP_SW_MAX_SQ_QUANTA 32768 176 #define IRDMA_QP_SW_MAX_RQ_QUANTA 32768 177 178 #define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \ 179 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr)) 180 181 #define IRDMAQP_TERM_SEND_TERM_AND_FIN 0 182 #define IRDMAQP_TERM_SEND_TERM_ONLY 1 183 #define IRDMAQP_TERM_SEND_FIN_ONLY 2 184 #define IRDMAQP_TERM_DONOT_SEND_TERM_OR_FIN 3 185 186 #define IRDMA_QP_TYPE_IWARP 1 187 #define IRDMA_QP_TYPE_UDA 2 188 #define IRDMA_QP_TYPE_ROCE_RC 3 189 #define IRDMA_QP_TYPE_ROCE_UD 4 190 191 #define IRDMA_HW_PAGE_SIZE 4096 192 #define IRDMA_HW_PAGE_SHIFT 12 193 #define IRDMA_CQE_QTYPE_RQ 0 194 #define IRDMA_CQE_QTYPE_SQ 1 195 196 #define IRDMA_QP_WQE_MIN_SIZE 32 197 #define IRDMA_QP_WQE_MAX_SIZE 256 198 #define IRDMA_QP_WQE_MIN_QUANTA 1 199 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2 200 #define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3 201 202 #define IRDMA_SQ_RSVD 258 203 #define IRDMA_RQ_RSVD 1 204 205 #define IRDMA_FEATURE_RTS_AE BIT_ULL(0) 206 #define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1) 207 #define IRDMA_FEATURE_RELAX_RQ_ORDER BIT_ULL(2) 208 #define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5) 209 210 #define IRDMAQP_OP_RDMA_WRITE 0x00 211 #define IRDMAQP_OP_RDMA_READ 0x01 212 #define IRDMAQP_OP_RDMA_SEND 0x03 213 #define IRDMAQP_OP_RDMA_SEND_INV 0x04 214 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT 0x05 215 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV 0x06 216 #define IRDMAQP_OP_BIND_MW 0x08 217 #define IRDMAQP_OP_FAST_REGISTER 0x09 218 #define IRDMAQP_OP_LOCAL_INVALIDATE 0x0a 219 #define IRDMAQP_OP_RDMA_READ_LOC_INV 0x0b 220 #define IRDMAQP_OP_NOP 0x0c 221 #define IRDMAQP_OP_RDMA_WRITE_SOL 0x0d 222 #define IRDMAQP_OP_GEN_RTS_AE 0x30 223 224 enum irdma_cqp_op_type { 225 IRDMA_OP_CEQ_DESTROY = 1, 226 IRDMA_OP_AEQ_DESTROY = 2, 227 IRDMA_OP_DELETE_ARP_CACHE_ENTRY = 3, 228 IRDMA_OP_MANAGE_APBVT_ENTRY = 4, 229 IRDMA_OP_CEQ_CREATE = 5, 230 IRDMA_OP_AEQ_CREATE = 6, 231 IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY = 7, 232 IRDMA_OP_QP_MODIFY = 8, 233 IRDMA_OP_QP_UPLOAD_CONTEXT = 9, 234 IRDMA_OP_CQ_CREATE = 10, 235 IRDMA_OP_CQ_DESTROY = 11, 236 IRDMA_OP_QP_CREATE = 12, 237 IRDMA_OP_QP_DESTROY = 13, 238 IRDMA_OP_ALLOC_STAG = 14, 239 IRDMA_OP_MR_REG_NON_SHARED = 15, 240 IRDMA_OP_DEALLOC_STAG = 16, 241 IRDMA_OP_MW_ALLOC = 17, 242 IRDMA_OP_QP_FLUSH_WQES = 18, 243 IRDMA_OP_ADD_ARP_CACHE_ENTRY = 19, 244 IRDMA_OP_MANAGE_PUSH_PAGE = 20, 245 IRDMA_OP_UPDATE_PE_SDS = 21, 246 IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE = 22, 247 IRDMA_OP_SUSPEND = 23, 248 IRDMA_OP_RESUME = 24, 249 IRDMA_OP_MANAGE_VF_PBLE_BP = 25, 250 IRDMA_OP_QUERY_FPM_VAL = 26, 251 IRDMA_OP_COMMIT_FPM_VAL = 27, 252 IRDMA_OP_REQ_CMDS = 28, 253 IRDMA_OP_CMPL_CMDS = 29, 254 IRDMA_OP_AH_CREATE = 30, 255 IRDMA_OP_AH_MODIFY = 31, 256 IRDMA_OP_AH_DESTROY = 32, 257 IRDMA_OP_MC_CREATE = 33, 258 IRDMA_OP_MC_DESTROY = 34, 259 IRDMA_OP_MC_MODIFY = 35, 260 IRDMA_OP_STATS_ALLOCATE = 36, 261 IRDMA_OP_STATS_FREE = 37, 262 IRDMA_OP_STATS_GATHER = 38, 263 IRDMA_OP_WS_ADD_NODE = 39, 264 IRDMA_OP_WS_MODIFY_NODE = 40, 265 IRDMA_OP_WS_DELETE_NODE = 41, 266 IRDMA_OP_WS_FAILOVER_START = 42, 267 IRDMA_OP_WS_FAILOVER_COMPLETE = 43, 268 IRDMA_OP_SET_UP_MAP = 44, 269 IRDMA_OP_GEN_AE = 45, 270 IRDMA_OP_QUERY_RDMA_FEATURES = 46, 271 IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY = 47, 272 IRDMA_OP_ADD_LOCAL_MAC_ENTRY = 48, 273 IRDMA_OP_DELETE_LOCAL_MAC_ENTRY = 49, 274 IRDMA_OP_CQ_MODIFY = 50, 275 276 /* Must be last entry */ 277 IRDMA_MAX_CQP_OPS = 51, 278 }; 279 280 /* CQP SQ WQES */ 281 #define IRDMA_CQP_OP_CREATE_QP 0 282 #define IRDMA_CQP_OP_MODIFY_QP 0x1 283 #define IRDMA_CQP_OP_DESTROY_QP 0x02 284 #define IRDMA_CQP_OP_CREATE_CQ 0x03 285 #define IRDMA_CQP_OP_MODIFY_CQ 0x04 286 #define IRDMA_CQP_OP_DESTROY_CQ 0x05 287 #define IRDMA_CQP_OP_ALLOC_STAG 0x09 288 #define IRDMA_CQP_OP_REG_MR 0x0a 289 #define IRDMA_CQP_OP_QUERY_STAG 0x0b 290 #define IRDMA_CQP_OP_REG_SMR 0x0c 291 #define IRDMA_CQP_OP_DEALLOC_STAG 0x0d 292 #define IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE 0x0e 293 #define IRDMA_CQP_OP_MANAGE_ARP 0x0f 294 #define IRDMA_CQP_OP_MANAGE_VF_PBLE_BP 0x10 295 #define IRDMA_CQP_OP_MANAGE_PUSH_PAGES 0x11 296 #define IRDMA_CQP_OP_QUERY_RDMA_FEATURES 0x12 297 #define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13 298 #define IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY 0x14 299 #define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13 300 #define IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15 301 #define IRDMA_CQP_OP_CREATE_CEQ 0x16 302 #define IRDMA_CQP_OP_DESTROY_CEQ 0x18 303 #define IRDMA_CQP_OP_CREATE_AEQ 0x19 304 #define IRDMA_CQP_OP_DESTROY_AEQ 0x1b 305 #define IRDMA_CQP_OP_CREATE_ADDR_HANDLE 0x1c 306 #define IRDMA_CQP_OP_MODIFY_ADDR_HANDLE 0x1d 307 #define IRDMA_CQP_OP_DESTROY_ADDR_HANDLE 0x1e 308 #define IRDMA_CQP_OP_UPDATE_PE_SDS 0x1f 309 #define IRDMA_CQP_OP_QUERY_FPM_VAL 0x20 310 #define IRDMA_CQP_OP_COMMIT_FPM_VAL 0x21 311 #define IRDMA_CQP_OP_FLUSH_WQES 0x22 312 /* IRDMA_CQP_OP_GEN_AE is the same value as IRDMA_CQP_OP_FLUSH_WQES */ 313 #define IRDMA_CQP_OP_GEN_AE 0x22 314 #define IRDMA_CQP_OP_MANAGE_APBVT 0x23 315 #define IRDMA_CQP_OP_NOP 0x24 316 #define IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25 317 #define IRDMA_CQP_OP_CREATE_MCAST_GRP 0x26 318 #define IRDMA_CQP_OP_MODIFY_MCAST_GRP 0x27 319 #define IRDMA_CQP_OP_DESTROY_MCAST_GRP 0x28 320 #define IRDMA_CQP_OP_SUSPEND_QP 0x29 321 #define IRDMA_CQP_OP_RESUME_QP 0x2a 322 #define IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b 323 #define IRDMA_CQP_OP_WORK_SCHED_NODE 0x2c 324 #define IRDMA_CQP_OP_MANAGE_STATS 0x2d 325 #define IRDMA_CQP_OP_GATHER_STATS 0x2e 326 #define IRDMA_CQP_OP_UP_MAP 0x2f 327 328 #ifndef LS_64_1 329 #define LS_64_1(val, bits) ((u64)(uintptr_t)(val) << (bits)) 330 #define RS_64_1(val, bits) ((u64)(uintptr_t)(val) >> (bits)) 331 #define LS_32_1(val, bits) ((u32)((val) << (bits))) 332 #define RS_32_1(val, bits) ((u32)((val) >> (bits))) 333 #endif 334 #ifndef GENMASK_ULL 335 #define GENMASK_ULL(high, low) ((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (low)) 336 #endif /* GENMASK_ULL */ 337 #ifndef GENMASK 338 #define GENMASK(high, low) ((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low)) 339 #endif /* GENMASK */ 340 #ifndef FIELD_PREP 341 #define FIELD_PREP(mask, val) (((u64)(val) << mask##_S) & (mask)) 342 #define FIELD_GET(mask, val) (((val) & mask) >> mask##_S) 343 #endif /* FIELD_PREP */ 344 345 #define FLD_LS_64(dev, val, field) \ 346 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M]) 347 #define FLD_RS_64(dev, val, field) \ 348 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S]) 349 #define FLD_LS_32(dev, val, field) \ 350 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M]) 351 #define FLD_RS_32(dev, val, field) \ 352 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S]) 353 354 #define IRDMA_MAX_STATS_16 0xffffULL 355 #define IRDMA_MAX_STATS_24 0xffffffULL 356 #define IRDMA_MAX_STATS_32 0xffffffffULL 357 #define IRDMA_MAX_STATS_48 0xffffffffffffULL 358 #define IRDMA_MAX_STATS_56 0xffffffffffffffULL 359 #define IRDMA_MAX_STATS_64 0xffffffffffffffffULL 360 361 #define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF 362 #define IRDMA_CQPSQ_QHASH_VLANID_S 32 363 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32) 364 #define IRDMA_CQPSQ_QHASH_QPN_S 32 365 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32) 366 #define IRDMA_CQPSQ_QHASH_QS_HANDLE_S 0 367 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0) 368 #define IRDMA_CQPSQ_QHASH_SRC_PORT_S 16 369 #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16) 370 #define IRDMA_CQPSQ_QHASH_DEST_PORT_S 0 371 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0) 372 #define IRDMA_CQPSQ_QHASH_ADDR0_S 32 373 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32) 374 #define IRDMA_CQPSQ_QHASH_ADDR1_S 0 375 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0) 376 #define IRDMA_CQPSQ_QHASH_ADDR2_S 32 377 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32) 378 #define IRDMA_CQPSQ_QHASH_ADDR3_S 0 379 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0) 380 #define IRDMA_CQPSQ_QHASH_WQEVALID_S 63 381 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63) 382 #define IRDMA_CQPSQ_QHASH_OPCODE_S 32 383 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32) 384 #define IRDMA_CQPSQ_QHASH_MANAGE_S 61 385 #define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61) 386 #define IRDMA_CQPSQ_QHASH_IPV4VALID_S 60 387 #define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60) 388 #define IRDMA_CQPSQ_QHASH_VLANVALID_S 59 389 #define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59) 390 #define IRDMA_CQPSQ_QHASH_ENTRYTYPE_S 42 391 #define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42) 392 #define IRDMA_CQPSQ_STATS_WQEVALID_S 63 393 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63) 394 #define IRDMA_CQPSQ_STATS_ALLOC_INST_S 62 395 #define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62) 396 #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX_S 60 397 #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60) 398 #define IRDMA_CQPSQ_STATS_USE_INST_S 61 399 #define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61) 400 #define IRDMA_CQPSQ_STATS_OP_S 32 401 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32) 402 #define IRDMA_CQPSQ_STATS_INST_INDEX_S 0 403 #define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0) 404 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX_S 0 405 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(15, 0) 406 #define IRDMA_CQPSQ_WS_WQEVALID_S 63 407 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63) 408 #define IRDMA_CQPSQ_WS_NODEOP_S 52 409 #define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(55, 52) 410 411 #define IRDMA_CQPSQ_WS_ENABLENODE_S 62 412 #define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62) 413 #define IRDMA_CQPSQ_WS_NODETYPE_S 61 414 #define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61) 415 #define IRDMA_CQPSQ_WS_PRIOTYPE_S 59 416 #define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59) 417 #define IRDMA_CQPSQ_WS_TC_S 56 418 #define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56) 419 #define IRDMA_CQPSQ_WS_VMVFTYPE_S 54 420 #define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54) 421 #define IRDMA_CQPSQ_WS_VMVFNUM_S 42 422 #define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42) 423 #define IRDMA_CQPSQ_WS_OP_S 32 424 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32) 425 #define IRDMA_CQPSQ_WS_PARENTID_S 16 426 #define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(25, 16) 427 #define IRDMA_CQPSQ_WS_NODEID_S 0 428 #define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0) 429 #define IRDMA_CQPSQ_WS_VSI_S 48 430 #define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48) 431 #define IRDMA_CQPSQ_WS_WEIGHT_S 32 432 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32) 433 434 #define IRDMA_CQPSQ_UP_WQEVALID_S 63 435 #define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63) 436 #define IRDMA_CQPSQ_UP_USEVLAN_S 62 437 #define IRDMA_CQPSQ_UP_USEVLAN BIT_ULL(62) 438 #define IRDMA_CQPSQ_UP_USEOVERRIDE_S 61 439 #define IRDMA_CQPSQ_UP_USEOVERRIDE BIT_ULL(61) 440 #define IRDMA_CQPSQ_UP_OP_S 32 441 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32) 442 #define IRDMA_CQPSQ_UP_HMCFCNIDX_S 0 443 #define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0) 444 #define IRDMA_CQPSQ_UP_CNPOVERRIDE_S 32 445 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32) 446 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID_S 63 447 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63) 448 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN_S 0 449 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0) 450 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP_S 32 451 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32) 452 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED_S 32 453 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32) 454 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION_S 16 455 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16) 456 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION_S 0 457 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0) 458 #define IRDMA_CQPHC_SQSIZE_S 8 459 #define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8) 460 #define IRDMA_CQPHC_DISABLE_PFPDUS_S 1 461 #define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1) 462 #define IRDMA_CQPHC_ROCEV2_RTO_POLICY_S 2 463 #define IRDMA_CQPHC_ROCEV2_RTO_POLICY BIT_ULL(2) 464 #define IRDMA_CQPHC_PROTOCOL_USED_S 3 465 #define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3) 466 #define IRDMA_CQPHC_MIN_RATE_S 48 467 #define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48) 468 #define IRDMA_CQPHC_MIN_DEC_FACTOR_S 56 469 #define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56) 470 #define IRDMA_CQPHC_DCQCN_T_S 0 471 #define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0) 472 #define IRDMA_CQPHC_HAI_FACTOR_S 32 473 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32) 474 #define IRDMA_CQPHC_RAI_FACTOR_S 48 475 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48) 476 #define IRDMA_CQPHC_DCQCN_B_S 0 477 #define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0) 478 #define IRDMA_CQPHC_DCQCN_F_S 25 479 #define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25) 480 #define IRDMA_CQPHC_CC_CFG_VALID_S 31 481 #define IRDMA_CQPHC_CC_CFG_VALID BIT_ULL(31) 482 #define IRDMA_CQPHC_RREDUCE_MPERIOD_S 32 483 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32) 484 #define IRDMA_CQPHC_HW_MINVER_S 0 485 #define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0) 486 487 #define IRDMA_CQPHC_HW_MAJVER_GEN_1 0 488 #define IRDMA_CQPHC_HW_MAJVER_GEN_2 1 489 #define IRDMA_CQPHC_HW_MAJVER_GEN_3 2 490 #define IRDMA_CQPHC_HW_MAJVER_S 16 491 #define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16) 492 #define IRDMA_CQPHC_CEQPERVF_S 32 493 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32) 494 495 #define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK_S 3 496 #define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK BIT_ULL(3) 497 498 #define IRDMA_CQPHC_ENABLED_VFS_S 32 499 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32) 500 501 #define IRDMA_CQPHC_HMC_PROFILE_S 0 502 #define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0) 503 #define IRDMA_CQPHC_SVER_S 24 504 #define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24) 505 #define IRDMA_CQPHC_SQBASE_S 9 506 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9) 507 508 #define IRDMA_CQPHC_QPCTX_S 0 509 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0) 510 #define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0 511 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0) 512 #define IRDMA_CQ_DBSA_CQEIDX_S 0 513 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0) 514 #define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0 515 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0) 516 #define IRDMA_CQ_DBSA_ARM_NEXT_S 14 517 #define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14) 518 #define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15 519 #define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15) 520 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16 521 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16) 522 523 /* CQP and iWARP Completion Queue */ 524 #define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S 525 #define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX 526 527 #define IRDMA_CCQ_OPRETVAL_S 0 528 #define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0) 529 530 #define IRDMA_CQ_MINERR_S 0 531 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0) 532 #define IRDMA_CQ_MAJERR_S 16 533 #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16) 534 #define IRDMA_CQ_WQEIDX_S 32 535 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32) 536 #define IRDMA_CQ_EXTCQE_S 50 537 #define IRDMA_CQ_EXTCQE BIT_ULL(50) 538 #define IRDMA_OOO_CMPL_S 54 539 #define IRDMA_OOO_CMPL BIT_ULL(54) 540 #define IRDMA_CQ_ERROR_S 55 541 #define IRDMA_CQ_ERROR BIT_ULL(55) 542 #define IRDMA_CQ_SQ_S 62 543 #define IRDMA_CQ_SQ BIT_ULL(62) 544 545 #define IRDMA_CQ_VALID_S 63 546 #define IRDMA_CQ_VALID BIT_ULL(63) 547 #define IRDMA_CQ_IMMVALID BIT_ULL(62) 548 #define IRDMA_CQ_UDSMACVALID_S 61 549 #define IRDMA_CQ_UDSMACVALID BIT_ULL(61) 550 #define IRDMA_CQ_UDVLANVALID_S 60 551 #define IRDMA_CQ_UDVLANVALID BIT_ULL(60) 552 #define IRDMA_CQ_UDSMAC_S 0 553 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0) 554 #define IRDMA_CQ_UDVLAN_S 48 555 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48) 556 557 #define IRDMA_CQ_IMMDATA_S 0 558 #define IRDMA_CQ_IMMVALID_S 62 559 #define IRDMA_CQ_IMMDATA GENMASK_ULL(125, 62) 560 #define IRDMA_CQ_IMMDATALOW32_S 0 561 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0) 562 #define IRDMA_CQ_IMMDATAUP32_S 32 563 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32) 564 #define IRDMACQ_PAYLDLEN_S 0 565 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0) 566 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS_S 32 567 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32) 568 #define IRDMACQ_INVSTAG_S 0 569 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0) 570 #define IRDMACQ_QPID_S 32 571 #define IRDMACQ_QPID GENMASK_ULL(55, 32) 572 573 #define IRDMACQ_UDSRCQPN_S 0 574 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0) 575 #define IRDMACQ_PSHDROP_S 51 576 #define IRDMACQ_PSHDROP BIT_ULL(51) 577 #define IRDMACQ_STAG_S 53 578 #define IRDMACQ_STAG BIT_ULL(53) 579 #define IRDMACQ_IPV4_S 53 580 #define IRDMACQ_IPV4 BIT_ULL(53) 581 #define IRDMACQ_SOEVENT_S 54 582 #define IRDMACQ_SOEVENT BIT_ULL(54) 583 #define IRDMACQ_OP_S 56 584 #define IRDMACQ_OP GENMASK_ULL(61, 56) 585 586 #define IRDMA_CEQE_CQCTX_S 0 587 #define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0) 588 #define IRDMA_CEQE_VALID_S 63 589 #define IRDMA_CEQE_VALID BIT_ULL(63) 590 591 /* AEQE format */ 592 #define IRDMA_AEQE_COMPCTX_S IRDMA_CQPHC_QPCTX_S 593 #define IRDMA_AEQE_COMPCTX IRDMA_CQPHC_QPCTX 594 #define IRDMA_AEQE_QPCQID_LOW_S 0 595 #define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0) 596 #define IRDMA_AEQE_QPCQID_HI_S 46 597 #define IRDMA_AEQE_QPCQID_HI BIT_ULL(46) 598 #define IRDMA_AEQE_WQDESCIDX_S 18 599 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18) 600 #define IRDMA_AEQE_OVERFLOW_S 33 601 #define IRDMA_AEQE_OVERFLOW BIT_ULL(33) 602 #define IRDMA_AEQE_AECODE_S 34 603 #define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34) 604 #define IRDMA_AEQE_AESRC_S 50 605 #define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50) 606 #define IRDMA_AEQE_IWSTATE_S 54 607 #define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54) 608 #define IRDMA_AEQE_TCPSTATE_S 57 609 #define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57) 610 #define IRDMA_AEQE_Q2DATA_S 61 611 #define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61) 612 #define IRDMA_AEQE_VALID_S 63 613 #define IRDMA_AEQE_VALID BIT_ULL(63) 614 615 #define IRDMA_UDA_QPSQ_NEXT_HDR_S 16 616 #define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16) 617 #define IRDMA_UDA_QPSQ_OPCODE_S 32 618 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32) 619 #define IRDMA_UDA_QPSQ_L4LEN_S 42 620 #define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42) 621 #define IRDMA_GEN1_UDA_QPSQ_L4LEN_S 24 622 #define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24) 623 #define IRDMA_UDA_QPSQ_AHIDX_S 0 624 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0) 625 #define IRDMA_UDA_QPSQ_VALID_S 63 626 #define IRDMA_UDA_QPSQ_VALID BIT_ULL(63) 627 #define IRDMA_UDA_QPSQ_SIGCOMPL_S 62 628 #define IRDMA_UDA_QPSQ_SIGCOMPL BIT_ULL(62) 629 #define IRDMA_UDA_QPSQ_MACLEN_S 56 630 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56) 631 #define IRDMA_UDA_QPSQ_IPLEN_S 48 632 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48) 633 #define IRDMA_UDA_QPSQ_L4T_S 30 634 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30) 635 #define IRDMA_UDA_QPSQ_IIPT_S 28 636 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28) 637 #define IRDMA_UDA_PAYLOADLEN_S 0 638 #define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0) 639 #define IRDMA_UDA_HDRLEN_S 16 640 #define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16) 641 #define IRDMA_VLAN_TAG_VALID_S 50 642 #define IRDMA_VLAN_TAG_VALID BIT_ULL(50) 643 #define IRDMA_UDA_L3PROTO_S 0 644 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0) 645 #define IRDMA_UDA_L4PROTO_S 16 646 #define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16) 647 #define IRDMA_UDA_QPSQ_DOLOOPBACK_S 44 648 #define IRDMA_UDA_QPSQ_DOLOOPBACK BIT_ULL(44) 649 #define IRDMA_CQPSQ_BUFSIZE_S 0 650 #define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0) 651 #define IRDMA_CQPSQ_OPCODE_S 32 652 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32) 653 #define IRDMA_CQPSQ_WQEVALID_S 63 654 #define IRDMA_CQPSQ_WQEVALID BIT_ULL(63) 655 #define IRDMA_CQPSQ_TPHVAL_S 0 656 #define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0) 657 658 #define IRDMA_CQPSQ_VSIIDX_S 8 659 #define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(17, 8) 660 #define IRDMA_CQPSQ_TPHEN_S 60 661 #define IRDMA_CQPSQ_TPHEN BIT_ULL(60) 662 663 #define IRDMA_CQPSQ_PBUFADDR_S IRDMA_CQPHC_QPCTX_S 664 #define IRDMA_CQPSQ_PBUFADDR IRDMA_CQPHC_QPCTX 665 666 /* Create/Modify/Destroy QP */ 667 668 #define IRDMA_CQPSQ_QP_NEWMSS_S 32 669 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32) 670 #define IRDMA_CQPSQ_QP_TERMLEN_S 48 671 #define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48) 672 673 #define IRDMA_CQPSQ_QP_QPCTX_S IRDMA_CQPHC_QPCTX_S 674 #define IRDMA_CQPSQ_QP_QPCTX IRDMA_CQPHC_QPCTX 675 676 #define IRDMA_CQPSQ_QP_QPID_S 0 677 #define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL) 678 679 #define IRDMA_CQPSQ_QP_OP_S 32 680 #define IRDMA_CQPSQ_QP_OP_M IRDMACQ_OP_M 681 #define IRDMA_CQPSQ_QP_ORDVALID_S 42 682 #define IRDMA_CQPSQ_QP_ORDVALID BIT_ULL(42) 683 #define IRDMA_CQPSQ_QP_TOECTXVALID_S 43 684 #define IRDMA_CQPSQ_QP_TOECTXVALID BIT_ULL(43) 685 #define IRDMA_CQPSQ_QP_CACHEDVARVALID_S 44 686 #define IRDMA_CQPSQ_QP_CACHEDVARVALID BIT_ULL(44) 687 #define IRDMA_CQPSQ_QP_VQ_S 45 688 #define IRDMA_CQPSQ_QP_VQ BIT_ULL(45) 689 #define IRDMA_CQPSQ_QP_FORCELOOPBACK_S 46 690 #define IRDMA_CQPSQ_QP_FORCELOOPBACK BIT_ULL(46) 691 #define IRDMA_CQPSQ_QP_CQNUMVALID_S 47 692 #define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47) 693 #define IRDMA_CQPSQ_QP_QPTYPE_S 48 694 #define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48) 695 #define IRDMA_CQPSQ_QP_MACVALID_S 51 696 #define IRDMA_CQPSQ_QP_MACVALID BIT_ULL(51) 697 #define IRDMA_CQPSQ_QP_MSSCHANGE_S 52 698 #define IRDMA_CQPSQ_QP_MSSCHANGE BIT_ULL(52) 699 700 #define IRDMA_CQPSQ_QP_IGNOREMWBOUND_S 54 701 #define IRDMA_CQPSQ_QP_IGNOREMWBOUND BIT_ULL(54) 702 #define IRDMA_CQPSQ_QP_REMOVEHASHENTRY_S 55 703 #define IRDMA_CQPSQ_QP_REMOVEHASHENTRY BIT_ULL(55) 704 #define IRDMA_CQPSQ_QP_TERMACT_S 56 705 #define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56) 706 #define IRDMA_CQPSQ_QP_RESETCON_S 58 707 #define IRDMA_CQPSQ_QP_RESETCON BIT_ULL(58) 708 #define IRDMA_CQPSQ_QP_ARPTABIDXVALID_S 59 709 #define IRDMA_CQPSQ_QP_ARPTABIDXVALID BIT_ULL(59) 710 #define IRDMA_CQPSQ_QP_NEXTIWSTATE_S 60 711 #define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60) 712 713 #define IRDMA_CQPSQ_QP_DBSHADOWADDR_S IRDMA_CQPHC_QPCTX_S 714 #define IRDMA_CQPSQ_QP_DBSHADOWADDR IRDMA_CQPHC_QPCTX 715 716 #define IRDMA_CQPSQ_CQ_CQSIZE_S 0 717 #define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0) 718 #define IRDMA_CQPSQ_CQ_CQCTX_S 0 719 #define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0) 720 #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD_S 0 721 #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0) 722 723 #define IRDMA_CQPSQ_CQ_OP_S 32 724 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32) 725 #define IRDMA_CQPSQ_CQ_CQRESIZE_S 43 726 #define IRDMA_CQPSQ_CQ_CQRESIZE BIT_ULL(43) 727 #define IRDMA_CQPSQ_CQ_LPBLSIZE_S 44 728 #define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44) 729 #define IRDMA_CQPSQ_CQ_CHKOVERFLOW_S 46 730 #define IRDMA_CQPSQ_CQ_CHKOVERFLOW BIT_ULL(46) 731 #define IRDMA_CQPSQ_CQ_VIRTMAP_S 47 732 #define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47) 733 #define IRDMA_CQPSQ_CQ_ENCEQEMASK_S 48 734 #define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48) 735 #define IRDMA_CQPSQ_CQ_CEQIDVALID_S 49 736 #define IRDMA_CQPSQ_CQ_CEQIDVALID BIT_ULL(49) 737 #define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT_S 61 738 #define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT BIT_ULL(61) 739 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX_S 0 740 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0) 741 742 /* Allocate/Register/Register Shared/Deallocate Stag */ 743 #define IRDMA_CQPSQ_STAG_VA_FBO_S IRDMA_CQPHC_QPCTX_S 744 #define IRDMA_CQPSQ_STAG_VA_FBO IRDMA_CQPHC_QPCTX 745 #define IRDMA_CQPSQ_STAG_STAGLEN_S 0 746 #define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0) 747 #define IRDMA_CQPSQ_STAG_KEY_S 0 748 #define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0) 749 #define IRDMA_CQPSQ_STAG_IDX_S 8 750 #define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8) 751 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX_S 32 752 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32) 753 #define IRDMA_CQPSQ_STAG_MR_S 43 754 #define IRDMA_CQPSQ_STAG_MR BIT_ULL(43) 755 #define IRDMA_CQPSQ_STAG_MWTYPE_S 42 756 #define IRDMA_CQPSQ_STAG_MWTYPE BIT_ULL(42) 757 #define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY_S 58 758 #define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY BIT_ULL(58) 759 760 #define IRDMA_CQPSQ_STAG_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S 761 #define IRDMA_CQPSQ_STAG_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M 762 #define IRDMA_CQPSQ_STAG_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE 763 #define IRDMA_CQPSQ_STAG_HPAGESIZE_S 46 764 #define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46) 765 #define IRDMA_CQPSQ_STAG_ARIGHTS_S 48 766 #define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48) 767 #define IRDMA_CQPSQ_STAG_REMACCENABLED_S 53 768 #define IRDMA_CQPSQ_STAG_REMACCENABLED BIT_ULL(53) 769 #define IRDMA_CQPSQ_STAG_VABASEDTO_S 59 770 #define IRDMA_CQPSQ_STAG_VABASEDTO BIT_ULL(59) 771 #define IRDMA_CQPSQ_STAG_USEHMCFNIDX_S 60 772 #define IRDMA_CQPSQ_STAG_USEHMCFNIDX BIT_ULL(60) 773 #define IRDMA_CQPSQ_STAG_USEPFRID_S 61 774 #define IRDMA_CQPSQ_STAG_USEPFRID BIT_ULL(61) 775 776 #define IRDMA_CQPSQ_STAG_PBA_S IRDMA_CQPHC_QPCTX_S 777 #define IRDMA_CQPSQ_STAG_PBA IRDMA_CQPHC_QPCTX 778 #define IRDMA_CQPSQ_STAG_HMCFNIDX_S 0 779 #define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0) 780 781 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX_S 0 782 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0) 783 784 #define IRDMA_CQPSQ_QUERYSTAG_IDX_S IRDMA_CQPSQ_STAG_IDX_S 785 #define IRDMA_CQPSQ_QUERYSTAG_IDX IRDMA_CQPSQ_STAG_IDX 786 #define IRDMA_CQPSQ_MLM_TABLEIDX_S 0 787 #define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0) 788 #define IRDMA_CQPSQ_MLM_FREEENTRY_S 62 789 #define IRDMA_CQPSQ_MLM_FREEENTRY BIT_ULL(62) 790 #define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT_S 61 791 #define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT BIT_ULL(61) 792 #define IRDMA_CQPSQ_MLM_MAC0_S 0 793 #define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0) 794 #define IRDMA_CQPSQ_MLM_MAC1_S 8 795 #define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8) 796 #define IRDMA_CQPSQ_MLM_MAC2_S 16 797 #define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16) 798 #define IRDMA_CQPSQ_MLM_MAC3_S 24 799 #define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24) 800 #define IRDMA_CQPSQ_MLM_MAC4_S 32 801 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32) 802 #define IRDMA_CQPSQ_MLM_MAC5_S 40 803 #define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40) 804 #define IRDMA_CQPSQ_MAT_REACHMAX_S 0 805 #define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0) 806 #define IRDMA_CQPSQ_MAT_MACADDR_S 0 807 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0) 808 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX_S 0 809 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0) 810 #define IRDMA_CQPSQ_MAT_ENTRYVALID_S 42 811 #define IRDMA_CQPSQ_MAT_ENTRYVALID BIT_ULL(42) 812 #define IRDMA_CQPSQ_MAT_PERMANENT_S 43 813 #define IRDMA_CQPSQ_MAT_PERMANENT BIT_ULL(43) 814 #define IRDMA_CQPSQ_MAT_QUERY_S 44 815 #define IRDMA_CQPSQ_MAT_QUERY BIT_ULL(44) 816 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT_S 0 817 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0) 818 #define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX_S 16 819 #define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16) 820 #define IRDMA_CQPSQ_MVPBP_SD_INX_S 32 821 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32) 822 #define IRDMA_CQPSQ_MVPBP_INV_PD_ENT_S 62 823 #define IRDMA_CQPSQ_MVPBP_INV_PD_ENT BIT_ULL(62) 824 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA_S 3 825 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3) 826 827 /* Manage Push Page - MPP */ 828 #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff 829 #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff 830 831 #define IRDMA_CQPSQ_MPP_QS_HANDLE_S 0 832 #define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0) 833 #define IRDMA_CQPSQ_MPP_PPIDX_S 0 834 #define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0) 835 #define IRDMA_CQPSQ_MPP_PPTYPE_S 60 836 #define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60) 837 838 #define IRDMA_CQPSQ_MPP_FREE_PAGE_S 62 839 #define IRDMA_CQPSQ_MPP_FREE_PAGE BIT_ULL(62) 840 841 /* Upload Context - UCTX */ 842 #define IRDMA_CQPSQ_UCTX_QPCTXADDR_S IRDMA_CQPHC_QPCTX_S 843 #define IRDMA_CQPSQ_UCTX_QPCTXADDR IRDMA_CQPHC_QPCTX 844 #define IRDMA_CQPSQ_UCTX_QPID_S 0 845 #define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0) 846 #define IRDMA_CQPSQ_UCTX_QPTYPE_S 48 847 #define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48) 848 849 #define IRDMA_CQPSQ_UCTX_RAWFORMAT_S 61 850 #define IRDMA_CQPSQ_UCTX_RAWFORMAT BIT_ULL(61) 851 #define IRDMA_CQPSQ_UCTX_FREEZEQP_S 62 852 #define IRDMA_CQPSQ_UCTX_FREEZEQP BIT_ULL(62) 853 854 #define IRDMA_CQPSQ_MHMC_VFIDX_S 0 855 #define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0) 856 #define IRDMA_CQPSQ_MHMC_FREEPMFN_S 62 857 #define IRDMA_CQPSQ_MHMC_FREEPMFN BIT_ULL(62) 858 859 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE_S 0 860 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0) 861 #define IRDMA_CQPSQ_SHMCRP_VFNUM_S 32 862 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32) 863 #define IRDMA_CQPSQ_CEQ_CEQSIZE_S 0 864 #define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0) 865 #define IRDMA_CQPSQ_CEQ_CEQID_S 0 866 #define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0) 867 868 #define IRDMA_CQPSQ_CEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S 869 #define IRDMA_CQPSQ_CEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M 870 #define IRDMA_CQPSQ_CEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE 871 #define IRDMA_CQPSQ_CEQ_VMAP_S 47 872 #define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47) 873 #define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE_S 46 874 #define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE BIT_ULL(46) 875 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX_S 0 876 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0) 877 #define IRDMA_CQPSQ_AEQ_AEQECNT_S 0 878 #define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0) 879 880 #define IRDMA_CQPSQ_AEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S 881 #define IRDMA_CQPSQ_AEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M 882 #define IRDMA_CQPSQ_AEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE 883 #define IRDMA_CQPSQ_AEQ_VMAP_S 47 884 #define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47) 885 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX_S 0 886 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0) 887 888 #define IRDMA_COMMIT_FPM_QPCNT_S 0 889 #define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0) 890 891 #define IRDMA_COMMIT_FPM_BASE_S 32 892 #define IRDMA_CQPSQ_CFPM_HMCFNID_S 0 893 #define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0) 894 895 #define IRDMA_CQPSQ_FWQE_AECODE_S 0 896 #define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0) 897 #define IRDMA_CQPSQ_FWQE_AESOURCE_S 16 898 #define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16) 899 #define IRDMA_CQPSQ_FWQE_RQMNERR_S 0 900 #define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0) 901 #define IRDMA_CQPSQ_FWQE_RQMJERR_S 16 902 #define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16) 903 #define IRDMA_CQPSQ_FWQE_SQMNERR_S 32 904 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32) 905 #define IRDMA_CQPSQ_FWQE_SQMJERR_S 48 906 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48) 907 #define IRDMA_CQPSQ_FWQE_QPID_S 0 908 #define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0) 909 #define IRDMA_CQPSQ_FWQE_GENERATE_AE_S 59 910 #define IRDMA_CQPSQ_FWQE_GENERATE_AE BIT_ULL(59) 911 #define IRDMA_CQPSQ_FWQE_USERFLCODE_S 60 912 #define IRDMA_CQPSQ_FWQE_USERFLCODE BIT_ULL(60) 913 #define IRDMA_CQPSQ_FWQE_FLUSHSQ_S 61 914 #define IRDMA_CQPSQ_FWQE_FLUSHSQ BIT_ULL(61) 915 #define IRDMA_CQPSQ_FWQE_FLUSHRQ_S 62 916 #define IRDMA_CQPSQ_FWQE_FLUSHRQ BIT_ULL(62) 917 #define IRDMA_CQPSQ_MAPT_PORT_S 0 918 #define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0) 919 #define IRDMA_CQPSQ_MAPT_ADDPORT_S 62 920 #define IRDMA_CQPSQ_MAPT_ADDPORT BIT_ULL(62) 921 #define IRDMA_CQPSQ_UPESD_SDCMD_S 0 922 #define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0) 923 #define IRDMA_CQPSQ_UPESD_SDDATALOW_S 0 924 #define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0) 925 #define IRDMA_CQPSQ_UPESD_SDDATAHI_S 32 926 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32) 927 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID_S 63 928 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63) 929 930 #define IRDMA_CQPSQ_UPESD_BM_PF 0 931 #define IRDMA_CQPSQ_UPESD_BM_CP_LM 1 932 #define IRDMA_CQPSQ_UPESD_BM_AXF 2 933 #define IRDMA_CQPSQ_UPESD_BM_LM 4 934 #define IRDMA_CQPSQ_UPESD_BM_S 32 935 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32) 936 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT_S 0 937 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0) 938 #define IRDMA_CQPSQ_UPESD_SKIP_ENTRY_S 7 939 #define IRDMA_CQPSQ_UPESD_SKIP_ENTRY BIT_ULL(7) 940 941 /* Suspend QP */ 942 #define IRDMA_CQPSQ_SUSPENDQP_QPID_S 0 943 #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0) 944 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE_S 0 945 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0) 946 947 #define IRDMA_CQPSQ_RESUMEQP_QPID_S IRDMA_CQPSQ_SUSPENDQP_QPID_S 948 #define IRDMA_CQPSQ_RESUMEQP_QPID_M IRDMA_CQPSQ_SUSPENDQP_QPID_M 949 #define IRDMA_CQPSQ_RESUMEQP_QPID IRDMA_CQPSQ_SUSPENDQP_QPID 950 951 #define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001 952 #define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005 953 954 #define IRDMA_CQPSQ_MAJ_NO_ERROR 0x0000 955 #define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000 956 #define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001 957 #define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF 958 #define IRDMAQPC_DDP_VER_S 0 959 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0) 960 #define IRDMAQPC_IBRDENABLE_S 2 961 #define IRDMAQPC_IBRDENABLE BIT_ULL(2) 962 #define IRDMAQPC_IPV4_S 3 963 #define IRDMAQPC_IPV4 BIT_ULL(3) 964 #define IRDMAQPC_NONAGLE_S 4 965 #define IRDMAQPC_NONAGLE BIT_ULL(4) 966 #define IRDMAQPC_INSERTVLANTAG_S 5 967 #define IRDMAQPC_INSERTVLANTAG BIT_ULL(5) 968 #define IRDMAQPC_ISQP1_S 6 969 #define IRDMAQPC_ISQP1 BIT_ULL(6) 970 #define IRDMAQPC_TIMESTAMP_S 7 971 #define IRDMAQPC_TIMESTAMP BIT_ULL(7) 972 #define IRDMAQPC_RQWQESIZE_S 8 973 #define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8) 974 #define IRDMAQPC_INSERTL2TAG2_S 11 975 #define IRDMAQPC_INSERTL2TAG2 BIT_ULL(11) 976 #define IRDMAQPC_LIMIT_S 12 977 #define IRDMAQPC_LIMIT GENMASK_ULL(13, 12) 978 979 #define IRDMAQPC_ECN_EN_S 14 980 #define IRDMAQPC_ECN_EN BIT_ULL(14) 981 #define IRDMAQPC_DROPOOOSEG_S 15 982 #define IRDMAQPC_DROPOOOSEG BIT_ULL(15) 983 #define IRDMAQPC_DUPACK_THRESH_S 16 984 #define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16) 985 #define IRDMAQPC_ERR_RQ_IDX_VALID_S 19 986 #define IRDMAQPC_ERR_RQ_IDX_VALID BIT_ULL(19) 987 #define IRDMAQPC_DIS_VLAN_CHECKS_S 19 988 #define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19) 989 #define IRDMAQPC_DC_TCP_EN_S 25 990 #define IRDMAQPC_DC_TCP_EN BIT_ULL(25) 991 #define IRDMAQPC_RCVTPHEN_S 28 992 #define IRDMAQPC_RCVTPHEN BIT_ULL(28) 993 #define IRDMAQPC_XMITTPHEN_S 29 994 #define IRDMAQPC_XMITTPHEN BIT_ULL(29) 995 #define IRDMAQPC_RQTPHEN_S 30 996 #define IRDMAQPC_RQTPHEN BIT_ULL(30) 997 #define IRDMAQPC_SQTPHEN_S 31 998 #define IRDMAQPC_SQTPHEN BIT_ULL(31) 999 #define IRDMAQPC_PPIDX_S 32 1000 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32) 1001 #define IRDMAQPC_PMENA_S 47 1002 #define IRDMAQPC_PMENA BIT_ULL(47) 1003 #define IRDMAQPC_RDMAP_VER_S 62 1004 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62) 1005 #define IRDMAQPC_ROCE_TVER_S 60 1006 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60) 1007 1008 #define IRDMAQPC_SQADDR_S IRDMA_CQPHC_QPCTX_S 1009 #define IRDMAQPC_SQADDR IRDMA_CQPHC_QPCTX 1010 1011 #define IRDMAQPC_RQADDR_S IRDMA_CQPHC_QPCTX_S 1012 #define IRDMAQPC_RQADDR IRDMA_CQPHC_QPCTX 1013 #define IRDMAQPC_TTL_S 0 1014 #define IRDMAQPC_TTL GENMASK_ULL(7, 0) 1015 #define IRDMAQPC_RQSIZE_S 8 1016 #define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8) 1017 #define IRDMAQPC_SQSIZE_S 12 1018 #define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12) 1019 #define IRDMAQPC_GEN1_SRCMACADDRIDX_S 16 1020 #define IRDMAQPC_GEN1_SRCMACADDRIDX GENMASK(21, 16) 1021 #define IRDMAQPC_AVOIDSTRETCHACK_S 23 1022 #define IRDMAQPC_AVOIDSTRETCHACK BIT_ULL(23) 1023 #define IRDMAQPC_TOS_S 24 1024 #define IRDMAQPC_TOS GENMASK_ULL(31, 24) 1025 #define IRDMAQPC_SRCPORTNUM_S 32 1026 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32) 1027 #define IRDMAQPC_DESTPORTNUM_S 48 1028 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48) 1029 #define IRDMAQPC_DESTIPADDR0_S 32 1030 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32) 1031 #define IRDMAQPC_DESTIPADDR1_S 0 1032 #define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0) 1033 #define IRDMAQPC_DESTIPADDR2_S 32 1034 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32) 1035 #define IRDMAQPC_DESTIPADDR3_S 0 1036 #define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0) 1037 #define IRDMAQPC_SNDMSS_S 16 1038 #define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16) 1039 #define IRDMAQPC_SYN_RST_HANDLING_S 30 1040 #define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30) 1041 #define IRDMAQPC_VLANTAG_S 32 1042 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32) 1043 #define IRDMAQPC_ARPIDX_S 48 1044 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48) 1045 #define IRDMAQPC_FLOWLABEL_S 0 1046 #define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0) 1047 #define IRDMAQPC_WSCALE_S 20 1048 #define IRDMAQPC_WSCALE BIT_ULL(20) 1049 #define IRDMAQPC_KEEPALIVE_S 21 1050 #define IRDMAQPC_KEEPALIVE BIT_ULL(21) 1051 #define IRDMAQPC_IGNORE_TCP_OPT_S 22 1052 #define IRDMAQPC_IGNORE_TCP_OPT BIT_ULL(22) 1053 #define IRDMAQPC_IGNORE_TCP_UNS_OPT_S 23 1054 #define IRDMAQPC_IGNORE_TCP_UNS_OPT BIT_ULL(23) 1055 #define IRDMAQPC_TCPSTATE_S 28 1056 #define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28) 1057 #define IRDMAQPC_RCVSCALE_S 32 1058 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32) 1059 #define IRDMAQPC_SNDSCALE_S 40 1060 #define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40) 1061 #define IRDMAQPC_PDIDX_S 48 1062 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48) 1063 #define IRDMAQPC_PDIDXHI_S 20 1064 #define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20) 1065 #define IRDMAQPC_PKEY_S 32 1066 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32) 1067 #define IRDMAQPC_ACKCREDITS_S 20 1068 #define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20) 1069 #define IRDMAQPC_QKEY_S 32 1070 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32) 1071 #define IRDMAQPC_DESTQP_S 0 1072 #define IRDMAQPC_DESTQP GENMASK_ULL(23, 0) 1073 #define IRDMAQPC_KALIVE_TIMER_MAX_PROBES_S 16 1074 #define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16) 1075 #define IRDMAQPC_KEEPALIVE_INTERVAL_S 24 1076 #define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24) 1077 #define IRDMAQPC_TIMESTAMP_RECENT_S 0 1078 #define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0) 1079 #define IRDMAQPC_TIMESTAMP_AGE_S 32 1080 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32) 1081 #define IRDMAQPC_SNDNXT_S 0 1082 #define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0) 1083 #define IRDMAQPC_ISN_S 32 1084 #define IRDMAQPC_ISN GENMASK_ULL(55, 32) 1085 #define IRDMAQPC_PSNNXT_S 0 1086 #define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0) 1087 #define IRDMAQPC_LSN_S 32 1088 #define IRDMAQPC_LSN GENMASK_ULL(55, 32) 1089 #define IRDMAQPC_SNDWND_S 32 1090 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32) 1091 #define IRDMAQPC_RCVNXT_S 0 1092 #define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0) 1093 #define IRDMAQPC_EPSN_S 0 1094 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0) 1095 #define IRDMAQPC_RCVWND_S 32 1096 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32) 1097 #define IRDMAQPC_SNDMAX_S 0 1098 #define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0) 1099 #define IRDMAQPC_SNDUNA_S 32 1100 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32) 1101 #define IRDMAQPC_PSNMAX_S 0 1102 #define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0) 1103 #define IRDMAQPC_PSNUNA_S 32 1104 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32) 1105 #define IRDMAQPC_SRTT_S 0 1106 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0) 1107 #define IRDMAQPC_RTTVAR_S 32 1108 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32) 1109 #define IRDMAQPC_SSTHRESH_S 0 1110 #define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0) 1111 #define IRDMAQPC_CWND_S 32 1112 #define IRDMAQPC_CWND GENMASK_ULL(63, 32) 1113 #define IRDMAQPC_CWNDROCE_S 32 1114 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32) 1115 #define IRDMAQPC_SNDWL1_S 0 1116 #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0) 1117 #define IRDMAQPC_SNDWL2_S 32 1118 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32) 1119 #define IRDMAQPC_ERR_RQ_IDX_S 32 1120 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32) 1121 #define IRDMAQPC_RTOMIN_S 57 1122 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57) 1123 #define IRDMAQPC_MAXSNDWND_S 0 1124 #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0) 1125 #define IRDMAQPC_REXMIT_THRESH_S 48 1126 #define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48) 1127 #define IRDMAQPC_RNRNAK_THRESH_S 54 1128 #define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54) 1129 #define IRDMAQPC_TXCQNUM_S 0 1130 #define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0) 1131 #define IRDMAQPC_RXCQNUM_S 32 1132 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32) 1133 #define IRDMAQPC_STAT_INDEX_S 0 1134 #define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0) 1135 #define IRDMAQPC_Q2ADDR_S 8 1136 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8) 1137 #define IRDMAQPC_LASTBYTESENT_S 0 1138 #define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0) 1139 #define IRDMAQPC_MACADDRESS_S 16 1140 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16) 1141 #define IRDMAQPC_ORDSIZE_S 0 1142 #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0) 1143 1144 #define IRDMAQPC_IRDSIZE_S 16 1145 #define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16) 1146 1147 #define IRDMAQPC_UDPRIVCQENABLE_S 19 1148 #define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19) 1149 #define IRDMAQPC_WRRDRSPOK_S 20 1150 #define IRDMAQPC_WRRDRSPOK BIT_ULL(20) 1151 #define IRDMAQPC_RDOK_S 21 1152 #define IRDMAQPC_RDOK BIT_ULL(21) 1153 #define IRDMAQPC_SNDMARKERS_S 22 1154 #define IRDMAQPC_SNDMARKERS BIT_ULL(22) 1155 #define IRDMAQPC_DCQCNENABLE_S 22 1156 #define IRDMAQPC_DCQCNENABLE BIT_ULL(22) 1157 #define IRDMAQPC_FW_CC_ENABLE_S 28 1158 #define IRDMAQPC_FW_CC_ENABLE BIT_ULL(28) 1159 #define IRDMAQPC_RCVNOICRC_S 31 1160 #define IRDMAQPC_RCVNOICRC BIT_ULL(31) 1161 #define IRDMAQPC_BINDEN_S 23 1162 #define IRDMAQPC_BINDEN BIT_ULL(23) 1163 #define IRDMAQPC_FASTREGEN_S 24 1164 #define IRDMAQPC_FASTREGEN BIT_ULL(24) 1165 #define IRDMAQPC_PRIVEN_S 25 1166 #define IRDMAQPC_PRIVEN BIT_ULL(25) 1167 #define IRDMAQPC_TIMELYENABLE_S 27 1168 #define IRDMAQPC_TIMELYENABLE BIT_ULL(27) 1169 #define IRDMAQPC_THIGH_S 52 1170 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52) 1171 #define IRDMAQPC_TLOW_S 32 1172 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32) 1173 #define IRDMAQPC_REMENDPOINTIDX_S 0 1174 #define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0) 1175 #define IRDMAQPC_USESTATSINSTANCE_S 26 1176 #define IRDMAQPC_USESTATSINSTANCE BIT_ULL(26) 1177 #define IRDMAQPC_IWARPMODE_S 28 1178 #define IRDMAQPC_IWARPMODE BIT_ULL(28) 1179 #define IRDMAQPC_RCVMARKERS_S 29 1180 #define IRDMAQPC_RCVMARKERS BIT_ULL(29) 1181 #define IRDMAQPC_ALIGNHDRS_S 30 1182 #define IRDMAQPC_ALIGNHDRS BIT_ULL(30) 1183 #define IRDMAQPC_RCVNOMPACRC_S 31 1184 #define IRDMAQPC_RCVNOMPACRC BIT_ULL(31) 1185 #define IRDMAQPC_RCVMARKOFFSET_S 32 1186 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32) 1187 #define IRDMAQPC_SNDMARKOFFSET_S 48 1188 #define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48) 1189 1190 #define IRDMAQPC_QPCOMPCTX_S IRDMA_CQPHC_QPCTX_S 1191 #define IRDMAQPC_QPCOMPCTX IRDMA_CQPHC_QPCTX 1192 #define IRDMAQPC_SQTPHVAL_S 0 1193 #define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0) 1194 #define IRDMAQPC_RQTPHVAL_S 8 1195 #define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8) 1196 #define IRDMAQPC_QSHANDLE_S 16 1197 #define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16) 1198 #define IRDMAQPC_EXCEPTION_LAN_QUEUE_S 32 1199 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32) 1200 #define IRDMAQPC_LOCAL_IPADDR3_S 0 1201 #define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0) 1202 #define IRDMAQPC_LOCAL_IPADDR2_S 32 1203 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32) 1204 #define IRDMAQPC_LOCAL_IPADDR1_S 0 1205 #define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0) 1206 #define IRDMAQPC_LOCAL_IPADDR0_S 32 1207 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32) 1208 #define IRDMA_FW_VER_MINOR_S 0 1209 #define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0) 1210 #define IRDMA_FW_VER_MAJOR_S 16 1211 #define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16) 1212 #define IRDMA_FEATURE_INFO_S 0 1213 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0) 1214 #define IRDMA_FEATURE_CNT_S 32 1215 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32) 1216 #define IRDMA_FEATURE_TYPE_S 48 1217 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48) 1218 #define IRDMA_RSVD_S 41 1219 #define IRDMA_RSVD GENMASK_ULL(55, 41) 1220 1221 #define IRDMAQPSQ_OPCODE_S 32 1222 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32) 1223 #define IRDMAQPSQ_COPY_HOST_PBL_S 43 1224 #define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43) 1225 #define IRDMAQPSQ_ADDFRAGCNT_S 38 1226 #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38) 1227 #define IRDMAQPSQ_PUSHWQE_S 56 1228 #define IRDMAQPSQ_PUSHWQE BIT_ULL(56) 1229 #define IRDMAQPSQ_STREAMMODE_S 58 1230 #define IRDMAQPSQ_STREAMMODE BIT_ULL(58) 1231 #define IRDMAQPSQ_WAITFORRCVPDU_S 59 1232 #define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59) 1233 #define IRDMAQPSQ_READFENCE_S 60 1234 #define IRDMAQPSQ_READFENCE BIT_ULL(60) 1235 #define IRDMAQPSQ_LOCALFENCE_S 61 1236 #define IRDMAQPSQ_LOCALFENCE BIT_ULL(61) 1237 #define IRDMAQPSQ_UDPHEADER_S 61 1238 #define IRDMAQPSQ_UDPHEADER BIT_ULL(61) 1239 #define IRDMAQPSQ_L4LEN_S 42 1240 #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42) 1241 #define IRDMAQPSQ_SIGCOMPL_S 62 1242 #define IRDMAQPSQ_SIGCOMPL BIT_ULL(62) 1243 #define IRDMAQPSQ_VALID_S 63 1244 #define IRDMAQPSQ_VALID BIT_ULL(63) 1245 1246 #define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S 1247 #define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX 1248 #define IRDMAQPSQ_FRAG_VALID_S 63 1249 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63) 1250 #define IRDMAQPSQ_FRAG_LEN_S 32 1251 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32) 1252 #define IRDMAQPSQ_FRAG_STAG_S 0 1253 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0) 1254 #define IRDMAQPSQ_GEN1_FRAG_LEN_S 0 1255 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0) 1256 #define IRDMAQPSQ_GEN1_FRAG_STAG_S 32 1257 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32) 1258 #define IRDMAQPSQ_REMSTAGINV_S 0 1259 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0) 1260 #define IRDMAQPSQ_DESTQKEY_S 0 1261 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0) 1262 #define IRDMAQPSQ_DESTQPN_S 32 1263 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32) 1264 #define IRDMAQPSQ_AHID_S 0 1265 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0) 1266 #define IRDMAQPSQ_INLINEDATAFLAG_S 57 1267 #define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57) 1268 1269 #define IRDMA_INLINE_VALID_S 7 1270 #define IRDMAQPSQ_INLINEDATALEN_S 48 1271 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48) 1272 #define IRDMAQPSQ_IMMDATAFLAG_S 47 1273 #define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47) 1274 #define IRDMAQPSQ_REPORTRTT_S 46 1275 #define IRDMAQPSQ_REPORTRTT BIT_ULL(46) 1276 1277 #define IRDMAQPSQ_IMMDATA_S 0 1278 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0) 1279 #define IRDMAQPSQ_REMSTAG_S 0 1280 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0) 1281 1282 #define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S 1283 #define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX 1284 1285 #define IRDMAQPSQ_STAGRIGHTS_S 48 1286 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48) 1287 #define IRDMAQPSQ_VABASEDTO_S 53 1288 #define IRDMAQPSQ_VABASEDTO BIT_ULL(53) 1289 #define IRDMAQPSQ_MEMWINDOWTYPE_S 54 1290 #define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54) 1291 1292 #define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S 1293 #define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX 1294 #define IRDMAQPSQ_PARENTMRSTAG_S 32 1295 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32) 1296 #define IRDMAQPSQ_MWSTAG_S 0 1297 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0) 1298 1299 #define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S 1300 #define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX 1301 1302 #define IRDMAQPSQ_LOCSTAG_S 0 1303 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0) 1304 1305 #define IRDMAQPSQ_STAGKEY_S 0 1306 #define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0) 1307 #define IRDMAQPSQ_STAGINDEX_S 8 1308 #define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8) 1309 #define IRDMAQPSQ_COPYHOSTPBLS_S 43 1310 #define IRDMAQPSQ_COPYHOSTPBLS BIT_ULL(43) 1311 #define IRDMAQPSQ_LPBLSIZE_S 44 1312 #define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44) 1313 #define IRDMAQPSQ_HPAGESIZE_S 46 1314 #define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46) 1315 #define IRDMAQPSQ_STAGLEN_S 0 1316 #define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0) 1317 #define IRDMAQPSQ_FIRSTPMPBLIDXLO_S 48 1318 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48) 1319 #define IRDMAQPSQ_FIRSTPMPBLIDXHI_S 0 1320 #define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0) 1321 #define IRDMAQPSQ_PBLADDR_S 12 1322 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12) 1323 1324 /* iwarp QP RQ WQE common fields */ 1325 #define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S 1326 #define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT 1327 1328 #define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S 1329 #define IRDMAQPRQ_VALID IRDMAQPSQ_VALID 1330 1331 #define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S 1332 #define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX 1333 1334 #define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S 1335 #define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN 1336 1337 #define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S 1338 #define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG 1339 1340 #define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S 1341 #define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO 1342 1343 #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26) 1344 #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27) 1345 #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28) 1346 1347 #define IRDMA_QUERY_FPM_MAX_QPS_S 0 1348 #define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0) 1349 #define IRDMA_QUERY_FPM_MAX_CQS_S 0 1350 #define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0) 1351 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX_S 0 1352 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0) 1353 #define IRDMA_QUERY_FPM_MAX_PE_SDS_S 32 1354 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32) 1355 1356 #define IRDMA_QUERY_FPM_MAX_CEQS_S 0 1357 #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0) 1358 #define IRDMA_QUERY_FPM_XFBLOCKSIZE_S 32 1359 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32) 1360 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE_S 32 1361 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32) 1362 #define IRDMA_QUERY_FPM_HTMULTIPLIER_S 16 1363 #define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16) 1364 #define IRDMA_QUERY_FPM_TIMERBUCKET_S 32 1365 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32) 1366 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE_S 32 1367 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32) 1368 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE_S 32 1369 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32) 1370 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE_S 32 1371 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32) 1372 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID_S 0 1373 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(15, 0) 1374 1375 #define IRDMA_GET_CURRENT_AEQ_ELEM(_aeq) \ 1376 ( \ 1377 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \ 1378 ) 1379 1380 #define IRDMA_GET_CURRENT_CEQ_ELEM(_ceq) \ 1381 ( \ 1382 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \ 1383 ) 1384 1385 #define IRDMA_GET_CEQ_ELEM_AT_POS(_ceq, _pos) \ 1386 ( \ 1387 (_ceq)->ceqe_base[_pos].buf \ 1388 ) 1389 1390 #define IRDMA_RING_GET_NEXT_TAIL(_ring, _idx) \ 1391 ( \ 1392 ((_ring).tail + (_idx)) % (_ring).size \ 1393 ) 1394 1395 #define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \ 1396 ( \ 1397 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \ 1398 ) 1399 #define IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(_cq) \ 1400 ( \ 1401 ((struct irdma_extended_cqe *) \ 1402 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \ 1403 ) 1404 1405 #define IRDMA_RING_INIT(_ring, _size) \ 1406 { \ 1407 (_ring).head = 0; \ 1408 (_ring).tail = 0; \ 1409 (_ring).size = (_size); \ 1410 } 1411 #define IRDMA_RING_SIZE(_ring) ((_ring).size) 1412 #define IRDMA_RING_CURRENT_HEAD(_ring) ((_ring).head) 1413 #define IRDMA_RING_CURRENT_TAIL(_ring) ((_ring).tail) 1414 1415 #define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \ 1416 { \ 1417 register u32 size; \ 1418 size = (_ring).size; \ 1419 if (!IRDMA_RING_FULL_ERR(_ring)) { \ 1420 (_ring).head = ((_ring).head + 1) % size; \ 1421 (_retcode) = 0; \ 1422 } else { \ 1423 (_retcode) = -ENOSPC; \ 1424 } \ 1425 } 1426 #define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ 1427 { \ 1428 register u32 size; \ 1429 size = (_ring).size; \ 1430 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \ 1431 (_ring).head = ((_ring).head + (_count)) % size; \ 1432 (_retcode) = 0; \ 1433 } else { \ 1434 (_retcode) = -ENOSPC; \ 1435 } \ 1436 } 1437 #define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \ 1438 { \ 1439 register u32 size; \ 1440 size = (_ring).size; \ 1441 if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \ 1442 (_ring).head = ((_ring).head + 1) % size; \ 1443 (_retcode) = 0; \ 1444 } else { \ 1445 (_retcode) = -ENOSPC; \ 1446 } \ 1447 } 1448 #define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ 1449 { \ 1450 register u32 size; \ 1451 size = (_ring).size; \ 1452 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \ 1453 (_ring).head = ((_ring).head + (_count)) % size; \ 1454 (_retcode) = 0; \ 1455 } else { \ 1456 (_retcode) = -ENOSPC; \ 1457 } \ 1458 } 1459 #define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \ 1460 (_ring).head = ((_ring).head + (_count)) % (_ring).size 1461 1462 #define IRDMA_RING_MOVE_TAIL(_ring) \ 1463 (_ring).tail = ((_ring).tail + 1) % (_ring).size 1464 1465 #define IRDMA_RING_MOVE_HEAD_NOCHECK(_ring) \ 1466 (_ring).head = ((_ring).head + 1) % (_ring).size 1467 1468 #define IRDMA_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \ 1469 (_ring).tail = ((_ring).tail + (_count)) % (_ring).size 1470 1471 #define IRDMA_RING_SET_TAIL(_ring, _pos) \ 1472 (_ring).tail = (_pos) % (_ring).size 1473 1474 #define IRDMA_RING_FULL_ERR(_ring) \ 1475 ( \ 1476 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \ 1477 ) 1478 1479 #define IRDMA_ERR_RING_FULL2(_ring) \ 1480 ( \ 1481 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \ 1482 ) 1483 1484 #define IRDMA_ERR_RING_FULL3(_ring) \ 1485 ( \ 1486 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \ 1487 ) 1488 1489 #define IRDMA_SQ_RING_FULL_ERR(_ring) \ 1490 ( \ 1491 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \ 1492 ) 1493 1494 #define IRDMA_ERR_SQ_RING_FULL2(_ring) \ 1495 ( \ 1496 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \ 1497 ) 1498 #define IRDMA_ERR_SQ_RING_FULL3(_ring) \ 1499 ( \ 1500 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \ 1501 ) 1502 #define IRDMA_RING_MORE_WORK(_ring) \ 1503 ( \ 1504 (IRDMA_RING_USED_QUANTA(_ring) != 0) \ 1505 ) 1506 1507 #define IRDMA_RING_USED_QUANTA(_ring) \ 1508 ( \ 1509 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \ 1510 ) 1511 1512 #define IRDMA_RING_FREE_QUANTA(_ring) \ 1513 ( \ 1514 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \ 1515 ) 1516 1517 #define IRDMA_SQ_RING_FREE_QUANTA(_ring) \ 1518 ( \ 1519 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \ 1520 ) 1521 1522 #define IRDMA_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \ 1523 { \ 1524 index = IRDMA_RING_CURRENT_HEAD(_ring); \ 1525 IRDMA_RING_MOVE_HEAD(_ring, _retcode); \ 1526 } 1527 1528 enum irdma_protocol_used { 1529 IRDMA_ANY_PROTOCOL = 0, 1530 IRDMA_IWARP_PROTOCOL_ONLY = 1, 1531 IRDMA_ROCE_PROTOCOL_ONLY = 2, 1532 }; 1533 1534 enum irdma_qp_wqe_size { 1535 IRDMA_WQE_SIZE_32 = 32, 1536 IRDMA_WQE_SIZE_64 = 64, 1537 IRDMA_WQE_SIZE_96 = 96, 1538 IRDMA_WQE_SIZE_128 = 128, 1539 IRDMA_WQE_SIZE_256 = 256, 1540 }; 1541 1542 enum irdma_ws_node_op { 1543 IRDMA_ADD_NODE = 0, 1544 IRDMA_MODIFY_NODE, 1545 IRDMA_DEL_NODE, 1546 }; 1547 1548 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1), 1549 IRDMA_AEQ_ALIGNMENT_M = (256 - 1), 1550 IRDMA_Q2_ALIGNMENT_M = (256 - 1), 1551 IRDMA_CEQ_ALIGNMENT_M = (256 - 1), 1552 IRDMA_CQ0_ALIGNMENT_M = (256 - 1), 1553 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1), 1554 IRDMA_SHADOWAREA_M = (128 - 1), 1555 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1), 1556 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1), 1557 }; 1558 1559 enum irdma_alignment { 1560 IRDMA_CQP_ALIGNMENT = 0x200, 1561 IRDMA_AEQ_ALIGNMENT = 0x100, 1562 IRDMA_CEQ_ALIGNMENT = 0x100, 1563 IRDMA_CQ0_ALIGNMENT = 0x100, 1564 IRDMA_SD_BUF_ALIGNMENT = 0x80, 1565 IRDMA_FEATURE_BUF_ALIGNMENT = 0x10, 1566 }; 1567 1568 enum icrdma_protocol_used { 1569 ICRDMA_ANY_PROTOCOL = 0, 1570 ICRDMA_IWARP_PROTOCOL_ONLY = 1, 1571 ICRDMA_ROCE_PROTOCOL_ONLY = 2, 1572 }; 1573 1574 /** 1575 * set_64bit_val - set 64 bit value to hw wqe 1576 * @wqe_words: wqe addr to write 1577 * @byte_index: index in wqe 1578 * @val: value to write 1579 **/ 1580 static inline void set_64bit_val(__le64 *wqe_words, u32 byte_index, u64 val) 1581 { 1582 wqe_words[byte_index >> 3] = cpu_to_le64(val); 1583 } 1584 1585 /** 1586 * set_32bit_val - set 32 bit value to hw wqe 1587 * @wqe_words: wqe addr to write 1588 * @byte_index: index in wqe 1589 * @val: value to write 1590 **/ 1591 static inline void set_32bit_val(__le32 *wqe_words, u32 byte_index, u32 val) 1592 { 1593 wqe_words[byte_index >> 2] = cpu_to_le32(val); 1594 } 1595 1596 /** 1597 * get_64bit_val - read 64 bit value from wqe 1598 * @wqe_words: wqe addr 1599 * @byte_index: index to read from 1600 * @val: read value 1601 **/ 1602 static inline void get_64bit_val(__le64 *wqe_words, u32 byte_index, u64 *val) 1603 { 1604 *val = le64_to_cpu(wqe_words[byte_index >> 3]); 1605 } 1606 1607 /** 1608 * get_32bit_val - read 32 bit value from wqe 1609 * @wqe_words: wqe addr 1610 * @byte_index: index to reaad from 1611 * @val: return 32 bit value 1612 **/ 1613 static inline void get_32bit_val(__le32 *wqe_words, u32 byte_index, u32 *val) 1614 { 1615 *val = le32_to_cpu(wqe_words[byte_index >> 2]); 1616 } 1617 #endif /* IRDMA_DEFS_H */ 1618