1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2017 - 2021 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 /*$FreeBSD$*/ 35 36 #ifndef IRDMA_H 37 #define IRDMA_H 38 39 #define RDMA_BIT2(type, a) ((u##type) 1UL << a) 40 #define RDMA_MASK3(type, mask, shift) ((u##type) mask << shift) 41 #define MAKEMASK(m, s) ((m) << (s)) 42 #define IRDMA_WQEALLOC_WQE_DESC_INDEX_S 20 43 #define IRDMA_WQEALLOC_WQE_DESC_INDEX_M (0xfff << IRDMA_WQEALLOC_WQE_DESC_INDEX_S) 44 45 #define IRDMA_CQPTAIL_WQTAIL_S 0 46 #define IRDMA_CQPTAIL_WQTAIL_M (0x7ff << IRDMA_CQPTAIL_WQTAIL_S) 47 48 #define IRDMA_CQPTAIL_CQP_OP_ERR_S 31 49 #define IRDMA_CQPTAIL_CQP_OP_ERR_M (0x1 << IRDMA_CQPTAIL_CQP_OP_ERR_S) 50 51 #define IRDMA_CQPERRCODES_CQP_MINOR_CODE_S 0 52 #define IRDMA_CQPERRCODES_CQP_MINOR_CODE_M (0xffff << IRDMA_CQPERRCODES_CQP_MINOR_CODE_S) 53 #define IRDMA_CQPERRCODES_CQP_MAJOR_CODE_S 16 54 #define IRDMA_CQPERRCODES_CQP_MAJOR_CODE_M (0xffff << IRDMA_CQPERRCODES_CQP_MAJOR_CODE_S) 55 56 #define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE_S 4 57 #define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE_M (0x3 << IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE_S) 58 59 #define IRDMA_GLINT_RATE_INTERVAL_S 0 60 #define IRDMA_GLINT_RATE_INTERVAL_M (0x3c << IRDMA_GLINT_RATE_INTERVAL_S) 61 62 #define IRDMA_GLINT_RATE_INTRL_ENA_S 6 63 #define IRDMA_GLINT_RATE_INTRL_ENA_M BIT(6) 64 65 #define IRDMA_GLINT_DYN_CTL_INTENA_S 0 66 #define IRDMA_GLINT_DYN_CTL_INTENA_M (0x1 << IRDMA_GLINT_DYN_CTL_INTENA_S) 67 68 #define IRDMA_GLINT_DYN_CTL_CLEARPBA_S 1 69 #define IRDMA_GLINT_DYN_CTL_CLEARPBA_M (0x1 << IRDMA_GLINT_DYN_CTL_CLEARPBA_S) 70 71 #define IRDMA_GLINT_DYN_CTL_ITR_INDX_S 3 72 #define IRDMA_GLINT_DYN_CTL_ITR_INDX_M (0x3 << IRDMA_GLINT_DYN_CTL_ITR_INDX_S) 73 74 #define IRDMA_GLINT_DYN_CTL_INTERVAL_S 5 75 #define IRDMA_GLINT_DYN_CTL_INTERVAL_M (0xfff << IRDMA_GLINT_DYN_CTL_INTERVAL_S) 76 77 #define IRDMA_GLINT_CEQCTL_ITR_INDX_S 11 78 #define IRDMA_GLINT_CEQCTL_ITR_INDX_M (0x3 << IRDMA_GLINT_CEQCTL_ITR_INDX_S) 79 80 #define IRDMA_GLINT_CEQCTL_CAUSE_ENA_S 30 81 #define IRDMA_GLINT_CEQCTL_CAUSE_ENA_M (0x1 << IRDMA_GLINT_CEQCTL_CAUSE_ENA_S) 82 83 #define IRDMA_GLINT_CEQCTL_MSIX_INDX_S 0 84 #define IRDMA_GLINT_CEQCTL_MSIX_INDX_M (0x7ff << IRDMA_GLINT_CEQCTL_MSIX_INDX_S) 85 86 #define IRDMA_PFINT_AEQCTL_MSIX_INDX_S 0 87 #define IRDMA_PFINT_AEQCTL_MSIX_INDX_M (0x7ff << IRDMA_PFINT_AEQCTL_MSIX_INDX_S) 88 89 #define IRDMA_PFINT_AEQCTL_ITR_INDX_S 11 90 #define IRDMA_PFINT_AEQCTL_ITR_INDX_M (0x3 << IRDMA_PFINT_AEQCTL_ITR_INDX_S) 91 92 #define IRDMA_PFINT_AEQCTL_CAUSE_ENA_S 30 93 #define IRDMA_PFINT_AEQCTL_CAUSE_ENA_M (0x1 << IRDMA_PFINT_AEQCTL_CAUSE_ENA_S) 94 95 #define IRDMA_PFHMC_PDINV_PMSDIDX_S 0 96 #define IRDMA_PFHMC_PDINV_PMSDIDX_M (0xfff << IRDMA_PFHMC_PDINV_PMSDIDX_S) 97 98 #define IRDMA_PFHMC_PDINV_PMSDPARTSEL_S 15 99 #define IRDMA_PFHMC_PDINV_PMSDPARTSEL_M (0x1 << IRDMA_PFHMC_PDINV_PMSDPARTSEL_S) 100 101 #define IRDMA_PFHMC_PDINV_PMPDIDX_S 16 102 #define IRDMA_PFHMC_PDINV_PMPDIDX_M (0x1ff << IRDMA_PFHMC_PDINV_PMPDIDX_S) 103 104 #define IRDMA_PFHMC_SDDATALOW_PMSDVALID_S 0 105 #define IRDMA_PFHMC_SDDATALOW_PMSDVALID_M (0x1 << IRDMA_PFHMC_SDDATALOW_PMSDVALID_S) 106 #define IRDMA_PFHMC_SDDATALOW_PMSDTYPE_S 1 107 #define IRDMA_PFHMC_SDDATALOW_PMSDTYPE_M (0x1 << IRDMA_PFHMC_SDDATALOW_PMSDTYPE_S) 108 #define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT_S 2 109 #define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT_M (0x3ff << IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT_S) 110 #define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW_S 12 111 #define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW_M (0xfffff << IRDMA_PFHMC_SDDATALOW_PMSDDATALOW_S) 112 113 #define IRDMA_PFHMC_SDCMD_PMSDWR_S 31 114 #define IRDMA_PFHMC_SDCMD_PMSDWR_M (0x1 << IRDMA_PFHMC_SDCMD_PMSDWR_S) 115 116 #define IRDMA_INVALID_CQ_IDX 0xffffffff 117 118 enum irdma_registers { 119 IRDMA_CQPTAIL, 120 IRDMA_CQPDB, 121 IRDMA_CCQPSTATUS, 122 IRDMA_CCQPHIGH, 123 IRDMA_CCQPLOW, 124 IRDMA_CQARM, 125 IRDMA_CQACK, 126 IRDMA_AEQALLOC, 127 IRDMA_CQPERRCODES, 128 IRDMA_WQEALLOC, 129 IRDMA_GLINT_DYN_CTL, 130 IRDMA_DB_ADDR_OFFSET, 131 IRDMA_GLPCI_LBARCTRL, 132 IRDMA_GLPE_CPUSTATUS0, 133 IRDMA_GLPE_CPUSTATUS1, 134 IRDMA_GLPE_CPUSTATUS2, 135 IRDMA_PFINT_AEQCTL, 136 IRDMA_GLINT_CEQCTL, 137 IRDMA_VSIQF_PE_CTL1, 138 IRDMA_PFHMC_PDINV, 139 IRDMA_GLHMC_VFPDINV, 140 IRDMA_GLPE_CRITERR, 141 IRDMA_GLINT_RATE, 142 IRDMA_MAX_REGS, /* Must be last entry */ 143 }; 144 145 enum irdma_shifts { 146 IRDMA_CCQPSTATUS_CCQP_DONE_S, 147 IRDMA_CCQPSTATUS_CCQP_ERR_S, 148 IRDMA_CQPSQ_STAG_PDID_S, 149 IRDMA_CQPSQ_CQ_CEQID_S, 150 IRDMA_CQPSQ_CQ_CQID_S, 151 IRDMA_COMMIT_FPM_CQCNT_S, 152 IRDMA_MAX_SHIFTS, 153 }; 154 155 enum irdma_masks { 156 IRDMA_CCQPSTATUS_CCQP_DONE_M, 157 IRDMA_CCQPSTATUS_CCQP_ERR_M, 158 IRDMA_CQPSQ_STAG_PDID_M, 159 IRDMA_CQPSQ_CQ_CEQID_M, 160 IRDMA_CQPSQ_CQ_CQID_M, 161 IRDMA_COMMIT_FPM_CQCNT_M, 162 IRDMA_MAX_MASKS, /* Must be last entry */ 163 }; 164 165 #define IRDMA_MAX_MGS_PER_CTX 8 166 167 struct irdma_mcast_grp_ctx_entry_info { 168 u32 qp_id; 169 bool valid_entry; 170 u16 dest_port; 171 u32 use_cnt; 172 }; 173 174 struct irdma_mcast_grp_info { 175 u8 dest_mac_addr[ETH_ALEN]; 176 u16 vlan_id; 177 u8 hmc_fcn_id; 178 bool ipv4_valid:1; 179 bool vlan_valid:1; 180 u16 mg_id; 181 u32 no_of_mgs; 182 u32 dest_ip_addr[4]; 183 u16 qs_handle; 184 struct irdma_dma_mem dma_mem_mc; 185 struct irdma_mcast_grp_ctx_entry_info mg_ctx_info[IRDMA_MAX_MGS_PER_CTX]; 186 }; 187 188 enum irdma_vers { 189 IRDMA_GEN_RSVD, 190 IRDMA_GEN_1, 191 IRDMA_GEN_2, 192 }; 193 194 struct irdma_uk_attrs { 195 u64 feature_flags; 196 u32 max_hw_wq_frags; 197 u32 max_hw_read_sges; 198 u32 max_hw_inline; 199 u32 max_hw_rq_quanta; 200 u32 max_hw_wq_quanta; 201 u32 min_hw_cq_size; 202 u32 max_hw_cq_size; 203 u16 max_hw_sq_chunk; 204 u16 max_hw_wq_size; 205 u16 min_sw_wq_size; 206 u8 hw_rev; 207 }; 208 209 struct irdma_hw_attrs { 210 struct irdma_uk_attrs uk_attrs; 211 u64 max_hw_outbound_msg_size; 212 u64 max_hw_inbound_msg_size; 213 u64 max_mr_size; 214 u32 min_hw_qp_id; 215 u32 min_hw_aeq_size; 216 u32 max_hw_aeq_size; 217 u32 min_hw_ceq_size; 218 u32 max_hw_ceq_size; 219 u32 max_hw_device_pages; 220 u32 max_hw_vf_fpm_id; 221 u32 first_hw_vf_fpm_id; 222 u32 max_hw_ird; 223 u32 max_hw_ord; 224 u32 max_hw_wqes; 225 u32 max_hw_pds; 226 u32 max_hw_ena_vf_count; 227 u32 max_qp_wr; 228 u32 max_pe_ready_count; 229 u32 max_done_count; 230 u32 max_sleep_count; 231 u32 max_cqp_compl_wait_time_ms; 232 u16 max_stat_inst; 233 u16 max_stat_idx; 234 }; 235 236 void icrdma_init_hw(struct irdma_sc_dev *dev); 237 void irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp); 238 #endif /* IRDMA_H*/ 239